KR880009487A

KR880009487A - Channel Data Decoding Circuit of Time Switch Circuit Using Speech Memory in Delta Modulation Exchange System

Info

Publication number: KR880009487A
Application number: KR870000417A
Authority: KR
Inventors: 송덕영
Original assignee: 강진구; 삼성반도체통신 주식회사
Priority date: 1987-01-20
Filing date: 1987-01-20
Publication date: 1988-09-15

Abstract

내용 없음.No content.

Description

Channel Data Decoding Circuit of Time Switch Circuit Using Speech Memory in Delta Modulation Exchange System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제 1 도는 펄스 부호 변조시스템 교환회로의 타임스위치 회로.1 is a time switch circuit of a pulse code modulation system exchange circuit.

제 2 도는 통화로 형성도 .Second degree is formed by currency.

제 3 도는 본 발명에 따른 구체회로도.3 is a detailed circuit diagram according to the present invention.

Claims

In the delta modulation switching system, a predetermined signal is generated by a clock generator 50 generating a predetermined clock, a control logic unit 60 outputting a predetermined control signal, and a clock of the clock generator 50. A first counter 20, a second counter 70, a third counter 100, and a subscriber modulated data of a delta modulation method, which are counted, and which are selectively output by the output of the first counter 20. A second multiplexer 80 for selecting and outputting a signal of an address bus to a tight address and a signal of a second counter 70 to a read address by a signal of the multiplexer 10 and the control logic unit 60; Control memory 90 for inputting control information data of the control logic unit 60 to write / read data of the selected output address of the first multiplexer 80 to the signal of the control logic unit 60, and the signal of the control logic unit 60; Output the third counter by A third multiplexer 110 for selectively outputting the output of the control memory 90 to a read address at a second address, a speech memory 30 for reading and writing subscriber data to an output address of the third multiplexer 110; And a demultiplexer 40 demultiplexing the output of the speech memory 30 to select the delta modulated subscriber's voice data channel by the first counter 20 at the first multiplexer 10. Outputs the sequential write to the speech memory 30 by the output of the third counter 100 and the written data by the read address signal of the control memory 90 under the control of the central processing unit. A channel data decoding circuit of a time switch using speech memory in a delta exchange system that reads the data of < RTI ID = 0.0 >) and demultiplexes in a demultiplexer 40. < / RTI >

※ Note: The disclosure is based on the initial application.