JPH04212200A - Voice synthesizer - Google Patents

Abstract

PURPOSE:To decrease the unnaturality of a silent part at the joint of voice data to be sensed when the synthesized tones of a message are listened. CONSTITUTION:A 1st memory means which stores the voice data is provided. A 2nd memory means which stores the address of the voice data is provided. A 3rd memory means having the memory function to store the arranging sequence of the voice data and the silent time to be inserted between the sets of the voice data is provided. An address assigning means 25 which assigns the address of the 2nd memory means by a message selection signal to select the messages is provided. A voice synthesizing means 21 which reads out the voice data and synthesizes the voices by the arranging sequence stored in the 3rd memory means.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a speech synthesizer, and more particularly to a speech synthesizer for generating message voices for guide devices, voice clocks, and the like.

0002

[Background Art] In recent years, with the development of digital signal processing theory,
Speech synthesis LSIs have become popular due to advances in IC miniaturization technology. The speech synthesis LSI performs speech synthesis in one chip by decoding and D/A converting the speech signal stored as a digital code in a read-only storage circuit. However, at present, the time required for synthesis using a read-only memory circuit built into one chip is generally about several seconds to one minute. Therefore, in order to increase the apparent synthesis time, messages are shared.

FIG. 7 is an explanatory diagram showing an example of message sharing. When storing the three messages "Today is sunny", "Today is cloudy", and "Today is candy" in the voice data memory, "Kyo wa" and "Desu" are stored as a shared part. different parts within each message, i.e. "swell", "cloudy",
By storing only the "candy" separately, it is possible to significantly reduce memory capacity compared to storing each message separately.

[0004] This is called an editing/synthesizing method, and the means for implementing it is generally known, for example, by a speech synthesizing device described in Patent Application No. 1983-309761. The general idea is that the order of audio data in units shorter than sentences corresponding to a message in sentence units is stored in advance, and the audio data is combined in accordance with that order to synthesize a message.

FIG. 6 is a block diagram showing an example of a conventional speech synthesis device.

[0006] In FIG. 6, the conventional speech synthesis device includes an external control section 1 and a speech synthesis section 3.

The speech synthesis section 3 includes a synthesis control section 21, a message output order decoding table 32, a message output order control section 33, a message start address decoding table 24, an address control section 25, and an audio data memory 26. , a decoding section 27, and a D/A converting section 28.

[0008] FIG. 8 shows each message and message output order when three messages "Today is sunny", "Today is cloudy", and "Today is candy" are synthesized using the circuit diagram shown in FIG. The contents of the decode table 32 (
a) Message start address decoding table 24
FIG. 4B is a diagram showing the relationship between the audio data memory 26 and the audio data memory 26, respectively.

The operation of a conventional speech synthesizer will be explained with reference to FIGS. 6 and 8.

First, a synthesis start signal E and a message selection code S are input from the external control section 1 to the speech synthesis section 2. Message selection code S (S0~S
2) is supplied, the message output order control unit 33 uses the message output order decoding table 32 to convert the message select code S into message numbers M0 to M4 to be actually output, and stores the output order. .

Next, the address control unit 25 refers to the message start address decoding table 24 according to the stored message number, converts it into an address of the audio data memory 26, and converts the address of the audio data memory 26 to the address of the audio data memory 26. Synthesized speech O is formed from the data using the decoding section 27 and the D/A converting section 28.

For example, message numbers M0, M1, and M4 are selected based on the message select code S0, and "Today is sunny" is output based on the message numbers M0, M1, and M4 output from the message output order control section 33. That is what it is.

[0013]

[Problems to be Solved by the Invention] The conventional speech synthesis device described above lacks silence information between consecutive speech data, so when listening to the synthesized speech of a message, depending on the arrangement of the speech data, the silence at the joint may be lost. This has the disadvantage that the spacing between the two feels unnatural.

[0014]

[Means for Solving the Problems] A speech synthesis device of the present invention includes a first storage means for storing a voice message as a unit of voice data shorter than the message, and an address of the voice data constituting the message. a second storage means for storing, a third storage means for storing the arrangement order of the audio data, and an addressing means for specifying the address of the second storage means by a message selection signal for selecting the message; In the speech synthesis device, the third storage means reads out the audio data in the arrangement order stored in the third storage means and synthesizes speech. It is configured to have a storage function for storing silent time information indicating the silent time to be inserted in between.

[0015]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the speech synthesis apparatus of the present invention.

The speech synthesis apparatus of this embodiment is composed of an external control section 1 and a speech synthesis section 2, as shown in FIG.

The speech synthesis section 2 includes a synthesis control section 21, a message output decoding table 22, a message output control section 23, a message start address decoding table 24, an address control section 25, and an audio data memory 26.
, a decoding section 27 , and a D/A converting section 28 .

It should be noted that the blocks in FIG. 1 having the same numbers as those in FIG. 6 are the same parts as those explained in the example of the prior art mentioned above, and the explanation will be redundant, so the explanation will be omitted here.

FIG. 2 is a block diagram showing details of the message output control section 23. As shown in FIG.

In FIG. 2, the message output control section 23
is a switch 231, an output order register 232, an audio data output control section 233, and a wait time register 23.
4 and a wait circuit 235.

The switch 231 is a switch that divides the data read from the message output decoding table 22 into audio data and wait time.

The output order register 232 stores the output order of audio data.

The audio data output control section 233 uses the output order register 232 to output the message number to be output next.

The wait time register 234 stores the wait time, which is the time of the silent portion between each piece of audio data.

The wait circuit 235 controls the audio data output control section 233 according to the output of the wait time register 234.
Apply weight to.

FIG. 3 shows the contents of the message output decoding table 22 in (a) and the corresponding output message in (b).
) are shown respectively.

As shown in FIG. 3, the message output decoding table 22 stores silent time information indicating the silent time between each audio data number.

Next, the operation of this embodiment will be explained.

First, the external control section 1 sends a synthesis start signal E and a message selection code S to the speech synthesis section 2.
Enter. Message selection code S (S0~S2
) is supplied, the message output control unit 23 uses the message output decoding table 22 to actually output the message select code S. Voice data numbers M0 to M
4 and the silent times t1 to t6 between each audio data.

Next, the switch 231 is used to alternately store the audio data number string in the output order register 232 and the silent time string between the audio data in the wait time register 234.

Next, the address control unit 25 refers to the message start address decoding table 24 according to the stored message number and converts it into an address of the audio data memory 26.

Furthermore, the message output control section 23 synthesizes messages by waiting for the time (t1 to t6) stored in the wait time register 234 each time each message output is completed, and then entering the next message output operation.

Next, a second embodiment of the present invention will be explained.

FIG. 4 is a block diagram showing a second embodiment of the speech synthesis apparatus of the present invention.

In FIG. 4, the speech synthesis device 4 of this embodiment
, a message output control section 41, a data memory 42 storing synthesis order and silence information, an address control section 43, END code detection circuits 44, 45, a silence code detection circuit 45, a counter 47, An audio data memory 26 and a decoding circuit 27 common to the first embodiment described above,
It is configured to include a D/A conversion circuit 28.

The difference between this embodiment and the first embodiment is that the message output decode table 22 and the message start address decode table 24 are stored in a single data memory 4.
In place of EN2, it also has an END code indicating the end of the message, and that the message output control section 41 and the address control section 43 have an address counter.
D code detection circuits 44 and 45 and silent code detection circuit 45
and a counter 47 are added.

FIG. 5(a) is a diagram showing the contents of the data memory 42 in FIG. 4, and FIG. 5(b) is a diagram showing the contents of the audio data memory 26.

In FIG. 5(b), A0 is "Kyoha"
A1 is the start address of the area that stores the phrase-based audio data of ``Kino wa'', A2 is the start address of the area that stores the phrase-based audio data of ``Kino wa'', and A2 is . ．． ．．
It is.

In addition, M0 in FIG. 5(a) is the start address of the area in which the order information of the audio data constituting the message "Today is sunny" and the silence code to be inserted between them is written, and M1 is " It’s sunny and cloudy today.”
M2 is the start address of the area that stores the order information of the audio data that makes up the message and the silence code inserted between them. ．． ．． It is.

The silence code numbers (0) to (5) indicate the length of silence; for example, (5) is 50 mS.

Here, M0, M1, M2. ．． ．． is the message select code S when viewed from the outside of this device.

[0043] Further, the leading address such as A0 or A1 stored in the data memory 42 and the silence code are distinguished by, for example, 0/1 of the uppermost bit. Next, the operation of this embodiment will be explained using the message "Today is sunny" as an example.

M0 as a message select code S is stored in the message output control section 41 from the external control section.

A0 is read out from the data memory 42 in response to the message output control section 41, and the address control section 43 reads out A0 from the data memory 42.
is stored in

[0046] The audio data of "Kyouha" is read word by word from the audio data memory 26 in accordance with the address control section 43, and is converted into an analog audio signal by the decoding section 27 and the D/A conversion circuit 28. .

At this time, the END code added at the end of the voice data of "Kyouha" is detected by the END code detection circuit 4.
The address control unit 43 adds 1 to the content until the number 5 is detected, and the audio data is continuously read out.

When the END code detection circuit 45 detects the END code, the contents of the message output control section 41 are changed to 1.
is added, and the silence code (5) is read out.

The silent code (5) is detected by the silent code detection circuit 4.
6, and the counter 47 counts, for example, 50 milliseconds.

During that time, the output of the audio data memory 26 is ignored and the outputs of the decoding section 27 and the D/A conversion circuit 28 are stopped.

When the counter 47 finishes counting, 1 is added to the contents of the message output control section 41 and A2 is read out from the data memory 42 to the address control section 43.

By repeating the above operations, the message "Today is sunny" is synthesized.

[0053] Furthermore, a message ``Today is sunny and cloudy'' is similarly synthesized according to an instruction from the external control device.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments and can be modified in various ways.

For example, in this embodiment, the message output decoding table, the message start address decoding table, and the voice data memory are each independent components, but a single data memory etc. that combines the above functions may be used. Of course, it is also possible to use the component as a component as long as it does not depart from the gist of the present invention.

[0056]

Effects of the Invention As explained above, the present invention is equipped with a means for storing silence time information between consecutive voice data, so that the silent portions at the joints of voice data that are felt when listening to the synthesized voice of a message can be suppressed. This has the effect of reducing unnaturalness.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a speech synthesis device of the present invention.

FIG. 2 is a block diagram showing details of the message output control section shown in FIG. 1;

FIG. 3 is a diagram showing the contents of the message output decoding table shown in FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of the speech synthesis device of the present invention.

FIG. 5 is a diagram showing the contents of the data memory shown in FIG. 4;

FIG. 6 is a block diagram showing an example of a conventional speech synthesis device.

FIG. 7 is a diagram illustrating an example of message sharing.

8 is a diagram for explaining the contents of a message output order table, a message start address table, and a voice data memory shown in FIG. 6; FIG.

[Explanation of symbols]

1 External control section 2, 3, 4 Speech synthesis section 21 Synthesis control section 22 Message output decoding table 23, 4
1 Message output control section 24 Message start address table 25, 43 Address control section 26 Audio data memory 27 Decoding section 28 D/A conversion section 32 Message output order table 33 Message output order control section 42 Data memory 44, 45 END code detection circuit 46
Silence code detection circuit 47 Counter 231 Switch 232 Output order register 233 Audio data output control section 234 Wait time register 235 Wait circuit

Claims (2)

[Claims] 1. A first storage means for storing a voice message as a unit of voice data shorter than the message, a second storage means for storing an address of the voice data constituting the message, and a first storage means for storing the voice data in units shorter than the message; a third storage means for storing an arrangement order of the messages, an addressing means for specifying an address of the second storage means by a message selection signal for selecting the message, and an arrangement order stored in the third storage means; In the speech synthesis device, the third storage means stores silence time information indicating the arrangement order of the audio data and silence time information to be inserted between the audio data. A speech synthesis device characterized by having a memory function. 2. The second storage means has a function of storing the arrangement order of the audio data and the silence time information, which are the functions of the third storage means, and the speech synthesis means generates a silence signal from the silence information. 2. The speech synthesis apparatus according to claim 1, further comprising a silence synthesis means for synthesizing the speech.