JP3064376B2 - Speech synthesizer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voice synthesizer, and more particularly to a voice synthesizer of a voice editing / synthesizing method suitable for generating a message voice such as a guide device or a voice clock.

[Prior Art] In recent years, with the development of digital signal processing technology and the advancement of miniaturization technology of semiconductor integrated circuits, LSIs for speech synthesis have become widespread.

However, at present, the time of a message that can be synthesized using a read-only storage circuit (ROM) built in one chip is generally about several seconds to one minute.

Therefore, as one method of extending the apparent speech synthesis time, speech editing and synthesis are performed.

Speech editing / synthesis is a sentence (message) to be synthesized
Divided into parts (phrases, words, syllables, etc.)
This is a method of compiling by editing them and returning them to sentences again.

In other words, by omitting a common part for each sentence, the storage capacity is increased.

For example, of the two sentences "Kyohashi Hare." And "Kyohaku Cloudy.", The two sentences "Kyohwa" and "is" are common. Therefore,
Effective use of the ROM by storing the voice data of the four phrases "Kyowa", "Hare", "Cloudy" and "Is" and omitting one of the two common phrases Can be.

FIG. 7 is a block diagram showing an example of a conventional speech synthesizer.

In FIG. 7, the conventional speech synthesizer includes a phrase output order table ROM 10, a phrase address table ROM 2, a voice data ROM 3, a phrase output order control circuit 14, an address control circuit 5, a speech synthesis circuit 6, And a speaker 7.

FIG. 8 is a diagram showing the contents of the phrase output order table ROM10.

As shown in FIG. 8, the phrase output order table ROM 10 stores the output order information of the phrases constituting the corresponding nine sentences (messages) in nine memory areas R1 to R9, respectively. ing.

Fig. 9 shows the phrase address table ROM2 and audio data
FIG. 4 is a diagram showing a relationship with ROM3.

As shown in FIG. 9, the voice data ROM 3 has six memory areas P1 to P6, each of which stores voice data of six types of phrases constituting a message.

Also, the phrase address table ROM2 stores the audio data ROM3
Of the six memory areas P1 to P6 are stored in the six memory areas Q1 to Q6, respectively.

 Next, the operation of the conventional speech synthesizer will be described.

Here, an example of synthesizing a sentence “Today is the day after day” will be described.

In this case, it is assumed that the speech data of the phrases stored in the six memory areas P1 to P6 of the speech data ROM 3 are "Kyowa"... "Is" as shown in FIG. .

First, a phrase output order control circuit from the host controller of the speech synthesizer or an external device such as an operation keyboard.
A sentence selection signal S for selecting the memory area R4 of the phrase output order table ROM 10 is input to 14.

The phrase output order control circuit 14 has a phrase output order table ROM10.
The address Q1 of the phrase address table ROM2 for selecting the memory area R4 of the above is read. The audio data indicated by the address Q1
The start address of the P1 area of the ROM 3 is read out to the address control circuit 5.

The address control circuit 5 sequentially reads out the voice data of “Kyowa” from the P1 area of the voice data ROM 3 to the voice synthesis circuit 6.

The voice synthesis circuit 6 converts the read voice data into analog voice and sends it to the speaker 7.

When an end code added to the end of the voice data is detected, the voice synthesis circuit 6 outputs a next phrase selection instruction signal N instructing selection of the next phrase to the phrase output order control circuit 14.

When receiving the next clause selection instruction signal N, the clause output order control circuit 14 reads the next address Q2 of the clause address table ROM2 for selecting the memory area R4 of the clause output order table ROM10. The head address of the P2 area of the audio data ROM 3 indicated by the address Q2 is read out to the address control circuit 5.

The address control circuit 5 sequentially reads out the voice data of “Hare” from the P2 area of the voice data ROM 3 to the voice synthesis circuit 6.

The voice synthesis circuit 6 converts the read voice data into analog voice and sends it to the speaker 7.

Hereinafter, similarly, the addresses Q5, Q3, and Q6 of the phrase address table ROM2 for selecting the memory area R4 of the phrase output order table ROM10 are sequentially read, and the voices of P5, P3, and P6 of the voice data ROM3 corresponding to the respective addresses are read. The data is sequentially read out to the voice synthesizing circuit 6 and converted into an analog voice.
To send to.

Finally, the end code E is output from the memory area R4 of the phrase output order table ROM10, and the above processing ends.

[Problems to be solved by the invention]

In the above-described conventional speech synthesizer, the phrase output order table has a structure in which the phrases constituting the sentences are arranged in the output order for each target sentence. Therefore, the memory capacity of the phrase output order table is the number of sentences. And the number of words obtained by multiplying the number of phrases of the longest sentence by a bit length capable of distinguishing the number of types of codes is required.

For example, in the example shown in the conventional example, the number of sentences is 9 and the number of segments of the longest sentence is 6 (including the end code E).
Requires 54 words. Further, since there are seven types of codes Q1 to Q6 and end codes, three bits are required for one word, so that the required memory capacity of the clause output order table is 162 bits.

[Means for solving the problem]

The voice synthesizing device of the present invention includes: a first storage circuit that stores a plurality of voice messages having a common part and a common utterance order as the common part as voice data in a unit shorter than the message; A second storage circuit that stores an address; an address control circuit that controls an address of the first storage circuit based on the head address output by the second storage circuit; and the audio data that is controlled by the address control circuit. And a voice synthesis circuit that synthesizes voice, output order information of the head address corresponding to the common utterance order of all the voice data forming the message, and an output order information of each of the messages. An output code for instructing the output of the head address of the utterance part and an output prohibition for inhibiting the output of the head address of the non-speech part A third storage circuit for storing a stop code; and a head address output order control circuit for controlling writing, reading and output of the third storage circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the speech synthesizer of the present invention.

As shown in FIG. 1, the speech synthesizer of the present invention comprises a phrase output order table ROM1, a phrase address table ROM2.
And a voice data ROM 3, a phrase output order control circuit 4, an address control circuit 5, a voice synthesis circuit 6, and a speaker 7.

FIG. 2 is a diagram showing the contents of the phrase output order table ROM1.

In FIG. 2, the phrase output order table ROM1 is composed of an address table unit 11 and a phrase selection table unit 12.

The address table unit 11 corresponds to a common utterance order of all voice data constituting all the target sentences.
The head address output order information stored in the phrase address table ROM2 is stored.

The phrase selection table unit 12 stores, for each of the sentences to be processed in S1 to S9, a phrase selection flag for designating a phrase to be uttered as "1" and a phrase not to be uttered as "0" in the head address output order information. Things.

FIG. 3 is a block diagram showing a configuration of the phrase output order control circuit 4.

3, the clause output order control circuit 4 includes an address counter 41, registers 42 and 46, a selector 43, an OR circuit 44, and a NOT circuit 45.

The components other than the phrase output order table ROM1 and the phrase output order control circuit 4 are common parts to those shown in the above-described example of the prior art, and are not redundant except those directly related to the present invention. Description is omitted.

 Next, the operation of this embodiment will be described.

As in the above-described conventional example, an example of synthesizing a sentence “Today is the day” will be described.

In this case, similarly, the speech data of the phrase stored in the six memory areas P1 to P6 of the speech data ROM3 is the ninth data.
It is assumed that there are six “Today”... “Is” as shown in the figure.

First, a sentence selection signal S for selecting the memory area S4 of the phrase output order table ROM1 and the sentence selection signal S to be written to the phrase output order control circuit 4 from the host control device of the speech synthesizer or an external device such as an operation keyboard. Write signal W
Is input.

The sentence selection signal S is stored in the register 42 of the phrase output order control circuit 4 by the write signal W.

On the other hand, the write signal W resets the address counter 41 to 0.

Next, the content of the phrase output order table ROM1 indicated by the address counter 41, that is, S4 is output.

The output of the phrase selection table section 12 of the phrase output order table ROM1 is selected by the selector 43 according to the contents of the register 42, that is, S4.

In this case, since the selected phrase selection flag is “1”, the address Q1 of the phrase address table ROM2 output from the address table unit 11 is stored in the register 46 at the same time.

The register 46 stores the audio data ROM3 specified by the address Q1.
Of the memory area P1 is read out and transferred to the address control circuit 5.

The address control circuit 5 sequentially reads out the voice data of “Kyowa” from the P1 area of the voice data ROM 3 to the voice synthesis circuit 6.

The voice synthesis circuit 6 converts the read voice data into analog voice and sends it to the speaker 7.

When an end code added to the end of the voice data is detected, the voice synthesis circuit 6 outputs a next phrase selection instruction signal N instructing selection of the next phrase to the phrase output control circuit 14.

The next clause selection instruction signal N increments (+1) the contents of the address counter 41 of the clause output order control circuit 4.

Next, the same processing as described above is performed, and the speech data of the next phrase, “Hare”, is sequentially read out to the speech synthesis circuit 6 and uttered.

The above processing is repeated. At this time, if the selection flag of the selected phrase selection table section 12 is '0', the signal passes through the NOT circuit 45 and the OR circuit 44 and the content of the address counter 41 is changed. Increment (+1).

As a result, the contents of the phrase output order table ROM1 are output, and the same processing is repeated until the selected phrase selection flag becomes “1”.

By repeating the above series of processes until the address counter 41 reaches 9, a message "Today is a day" can be uttered.

 Next, a second embodiment of the present invention will be described.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

In FIG. 4, the speech synthesizing apparatus of the present embodiment includes a phrase output order address table ROM 8, a phrase output order address control circuit 9 for controlling the same, a speech data ROM 3 similar to that of the first embodiment, It comprises a circuit 6 and a speaker 7.

The difference from the first embodiment is that the clause output order table RO
Instead of the M1, the phrase address table ROM2, the phrase output order control circuit 4, and the address control circuit 5, a phrase output order address table ROM8 and a phrase output order address control circuit 9 are provided.

FIG. 5 is a diagram showing the contents of the phrase output order address table ROM8.

In FIG. 5, the clause output order address table ROM8
Is composed of an address table section 81 and a phrase selection table section 12.

The address table section 81 stores the output order information of the audio data ROM3 instead of the head address stored in the phrase address table ROM2 in the first embodiment.

The phrase selection table section 12 is the same as that of the phrase output order table ROM1 of the first embodiment.

FIG. 6 is a block diagram showing a configuration of the clause output order address control circuit 9.

In FIG. 6, the clause output order address control circuit 9
Is composed of address counters 91 and 96, a register 92, a selector 93, an OR circuit 94, and a NOT circuit 95.

The difference from the phrase output order control circuit 4 in the first embodiment is that an address counter 96 is used instead of the register 46.

The difference between the operation of the present embodiment and the first embodiment is that
In the first embodiment, the audio data stored in the audio data ROM 3 is directly read instead of the head address stored in the phrase address table ROM 2.

This embodiment has a simple configuration, and has a voice data ROM.
When the bit length of the address is small, there is an advantage that the capacity of the phrase output order table ROM can be reduced.

〔The invention's effect〕

As described above, the speech synthesizing apparatus of the present invention has an effect that the capacity of the storage circuit for designating the output order of the clauses constituting the message can be reduced.

For example, in the example shown in the conventional example, when the number of sentences is 9 and the number of segments of the longest sentence is 6 (including the end code E), the code types are Q1 to Q6 and 7 types of end codes as in the conventional example. Therefore, three bits are required for one word, and the required capacity of the address output order information is 9 × 3 =
The required capacity of the 27-bit address storage portion for storing the address output and output prohibition code is 9 × 9 = 81 bits, for a total of 108 bits.
This is an effect that the number of bits can be reduced by 54 bits as compared with the conventional example.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the contents of a phrase output order table ROM of FIG. 1, and FIG. 3 is a diagram showing the configuration of a phrase output order control circuit of FIG. FIG. 4 is a block diagram showing a second embodiment of the present invention, and FIG. 5 is a clause output order address table RO of FIG.
FIG. 6 is a block diagram showing the structure of the phrase output order address control circuit shown in FIG. 4, FIG. 7 is a block diagram showing an example of a conventional speech synthesizer, and FIG. FIG. 9 is a diagram showing the contents of the phrase output order table ROM, and FIG. 9 is a diagram showing the relationship between the phrase address table ROM and the voice data ROM. 1 ... Phrase output order table ROM, 2 ... Phrase address table ROM, 3 ... Speech data ROM, 4 ... Phrase output order control circuit, 5 ... Address control circuit, 6 ... Speech synthesis circuit, 7 ... Speakers 7, 8 ... Phrase output order address table ROM, 9 ... Phrase output order address control circuit, 1
0 ... Phrase output order table ROM, 11,81 ... Address table section, 12 ... Phrase selection table section, 14 ... Phrase output order control circuit, 41,91,96 ... Address counter, 42,46,92 …
... Register, 43,93 ... Selector, 44,94 ... OR circuit, 45,95 ... Negation circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-303399 (JP, A) JP-A-1-123873 (JP, U) Patent 2513012 (JP, B2) JP 2-37639 (JP, A) B2) Japanese Patent Publication No. 2-10959 (JP, B2) Japanese Patent Publication No. 62-39751 (JP, B2) Japanese Patent Publication No. 59-50999 (JP, B2) Japanese Patent Publication No. 59-48398 (JP, B2) (58) Survey Fields (Int.Cl. ⁷ , DB name) G10L 11/00-13/08 G10L 19/00-21/06

Claims (2)

(57) [Claims] 1. A first storage circuit for storing a plurality of voice messages having a common part and a common utterance order as the common part as voice data in a unit shorter than the message, and storing a head address of the voice data. A second storage circuit, an address control circuit that controls the address of the first storage circuit by the head address output by the second storage circuit, and reading the audio data under the control of the address control circuit; A voice synthesis circuit for synthesizing voice, output order information of the head address corresponding to the common utterance order of all of the voice data constituting the message, and a utterance part in each of the messages of the output order information. An output code for instructing the output of the head address and an output prohibition code for prohibiting the output of the head address of the non-vocal portion are described. A speech synthesizer comprising: a third storage circuit for storing; and a head address output order control circuit for controlling writing, reading and output of the third storage circuit. 2. The voice according to claim 1, wherein said second storage circuit stores said head address and output order information of said head address, and is part of said third storage circuit. Synthesizer.