TW326529B - Memory device and its control method - Google Patents

Abstract

A memory device includes: 1) a discriminate circuit - receiving a read address input signal and a write address input signal, and generating a discriminate signal to have a voltage difference between read address signal and write address signal; 2) a determinate circuit - receiving a discriminate signal from the discriminate circuit, and generating a determinate signal to represent the discriminate signal range; if the discriminate output signal being within the range of the first preset value, the determinate output signal being set the first value; otherwise, the determinate output signal being set the second value; 3) an address generate circuit - receiving the input signal of a read address signal,a write address signal, and the related determinate signal simultaneously, and generating a converted read address signal and a converted write address signal; the difference value of the converted read address signal and converted write address signal at least larger than the preset value, nevertheless the difference value of the read address signal and the write address signal; 4) a write address decoder to decode the converted write address signal; 5) a read address decoder to decode the converted read address signal; 6) a memory unit - to store input information at the defined output address of the write address decoder, and to read stored information from the defined output address of the read address decoder.