KR20240135830A - 압전층 전사를 위한 도너 기판의 제조 공정 및 압전층을 지지 기판 상으로 전사하는 공정 - Google Patents

압전층 전사를 위한 도너 기판의 제조 공정 및 압전층을 지지 기판 상으로 전사하는 공정 Download PDF

Info

Publication number
KR20240135830A
KR20240135830A KR1020247027493A KR20247027493A KR20240135830A KR 20240135830 A KR20240135830 A KR 20240135830A KR 1020247027493 A KR1020247027493 A KR 1020247027493A KR 20247027493 A KR20247027493 A KR 20247027493A KR 20240135830 A KR20240135830 A KR 20240135830A
Authority
KR
South Korea
Prior art keywords
substrate
piezoelectric
layer
donor
donor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247027493A
Other languages
English (en)
Korean (ko)
Inventor
마르셀 브뢰카르트
세드리크 찰스-알프레드
루시아나 카펠로
모르간 로지오우
티에리 바르지
Original Assignee
소이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 소이텍 filed Critical 소이텍
Publication of KR20240135830A publication Critical patent/KR20240135830A/ko
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H01L21/02002—
    • H01L21/76254—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
    • H10N30/085—Shaping or machining of piezoelectric or electrostrictive bodies by machining
    • H10N30/086—Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/50—Piezoelectric or electrostrictive devices having a stacked or multilayer structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Laminated Bodies (AREA)
KR1020247027493A 2022-01-17 2023-01-11 압전층 전사를 위한 도너 기판의 제조 공정 및 압전층을 지지 기판 상으로 전사하는 공정 Pending KR20240135830A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FRFR2200380 2022-01-17
FR2200380A FR3131979B1 (fr) 2022-01-17 2022-01-17 Procédé de fabrication d’un substrat donneur pour le transfert d’une couche piézoélectrique et procédé de transfert d’une couche piézoélectrique sur un substrat support
PCT/EP2023/050571 WO2023135181A1 (fr) 2022-01-17 2023-01-11 Procédé de fabrication d'un substrat donneur pour le transfert d'une couche piézoélectrique et procédé de transfert d'une couche piézoélectrique sur un substrat support

Publications (1)

Publication Number Publication Date
KR20240135830A true KR20240135830A (ko) 2024-09-12

Family

ID=81328055

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247027493A Pending KR20240135830A (ko) 2022-01-17 2023-01-11 압전층 전사를 위한 도너 기판의 제조 공정 및 압전층을 지지 기판 상으로 전사하는 공정

Country Status (8)

Country Link
US (1) US20250176430A1 (https=)
EP (1) EP4466729A1 (https=)
JP (1) JP2025500549A (https=)
KR (1) KR20240135830A (https=)
CN (1) CN118525353A (https=)
FR (1) FR3131979B1 (https=)
TW (1) TW202336927A (https=)
WO (1) WO2023135181A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3140474B1 (fr) * 2022-09-30 2024-11-01 Soitec Silicon On Insulator Substrat donneur et Procédé de fabrication d’un substrat donneur pour être utilisé dans un procédé de transfert de couche mince piézoélectrique.

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3079346B1 (fr) 2018-03-26 2020-05-29 Soitec Procede de fabrication d'un substrat donneur pour le transfert d'une couche piezoelectrique, et procede de transfert d'une telle couche piezoelectrique
FR3079345B1 (fr) * 2018-03-26 2020-02-21 Soitec Procede de fabrication d'un substrat pour dispositif radiofrequence

Also Published As

Publication number Publication date
FR3131979A1 (fr) 2023-07-21
TW202336927A (zh) 2023-09-16
EP4466729A1 (fr) 2024-11-27
WO2023135181A1 (fr) 2023-07-20
JP2025500549A (ja) 2025-01-09
FR3131979B1 (fr) 2025-03-21
US20250176430A1 (en) 2025-05-29
CN118525353A (zh) 2024-08-20

Similar Documents

Publication Publication Date Title
JP7256204B2 (ja) 圧電層を支持基板上に転写する方法
KR101180497B1 (ko) 중간층 및 지지층을 갖는 웨이퍼 및 웨이퍼를 처리하기위한 방법 및 장치
FR2922359A1 (fr) Procede de fabrication d'une structure micro-electronique impliquant un collage moleculaire
EP1651560B1 (fr) Structure empilée et procédé pour la fabriquer
KR20240135830A (ko) 압전층 전사를 위한 도너 기판의 제조 공정 및 압전층을 지지 기판 상으로 전사하는 공정
JP2024509614A (ja) ヘテロ構造から層を転写するための方法
KR20240135826A (ko) 압전층 전사를 위한 도너 기판의 제조 방법 및 압전층을 지지 기판 상으로 전사하는 방법
FR3134650A1 (fr) Procede d’assemblage de deux substrats par adhesion moleculaire, et structure obtenue par un tel procede
US20250255187A1 (en) Piezoelectric-on-insulator (poi) substrate and method for producing a piezoelectric-on-insulator (poi) substrate
US20110214806A1 (en) Ingot formed from basic ingots, wafer made from said ingot and associated method
EP1692716B1 (fr) Collage moleculaire de composants microelectroniques sur un film polymere
KR20250060268A (ko) 압전 박막 전사 방법에 사용하기 위한 도너 기판의 제조 방법
TW202027289A (zh) 發光元件用半導體基板之製造方法及發光元件之製造方法
FR2915624A1 (fr) Procedes de collage et de fabrication d'un substrat du type a couche enterree tres fine.
TW202441580A (zh) 絕緣體上壓電（ｐｏｉ）底材及用於製作絕緣體上壓電（ｐｏｉ）底材之方法
TW202519102A (zh) 用於將壓電層移轉到載體底材上之供體底材製造方法

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000