JP2025500549A - 圧電層の移転のためのドナー基板の製造のためのプロセス及び支持基板への圧電層の移転のためのプロセス - Google Patents

圧電層の移転のためのドナー基板の製造のためのプロセス及び支持基板への圧電層の移転のためのプロセス Download PDF

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Publication number
JP2025500549A
JP2025500549A JP2024539002A JP2024539002A JP2025500549A JP 2025500549 A JP2025500549 A JP 2025500549A JP 2024539002 A JP2024539002 A JP 2024539002A JP 2024539002 A JP2024539002 A JP 2024539002A JP 2025500549 A JP2025500549 A JP 2025500549A
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Japan
Prior art keywords
substrate
piezoelectric
layer
donor
donor substrate
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Pending
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JP2024539002A
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Japanese (ja)
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JP2025500549A5 (https=
Inventor
マルセル ブローカート，
セドリック チャールズ‐アルフレッド，
ルシアナ カペッロ，
モルゲン ロギオウ，
ティエリー バルジュ，
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Soitec SA
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Soitec SA
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Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2025500549A publication Critical patent/JP2025500549A/ja
Publication of JP2025500549A5 publication Critical patent/JP2025500549A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/08—Shaping or machining of piezoelectric or electrostrictive bodies
    • H10N30/085—Shaping or machining of piezoelectric or electrostrictive bodies by machining
    • H10N30/086—Shaping or machining of piezoelectric or electrostrictive bodies by machining by polishing or grinding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/50—Piezoelectric or electrostrictive devices having a stacked or multilayer structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Laminated Bodies (AREA)
JP2024539002A 2022-01-17 2023-01-11 圧電層の移転のためのドナー基板の製造のためのプロセス及び支持基板への圧電層の移転のためのプロセス Pending JP2025500549A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2200380 2022-01-17
FR2200380A FR3131979B1 (fr) 2022-01-17 2022-01-17 Procédé de fabrication d’un substrat donneur pour le transfert d’une couche piézoélectrique et procédé de transfert d’une couche piézoélectrique sur un substrat support
PCT/EP2023/050571 WO2023135181A1 (fr) 2022-01-17 2023-01-11 Procédé de fabrication d'un substrat donneur pour le transfert d'une couche piézoélectrique et procédé de transfert d'une couche piézoélectrique sur un substrat support

Publications (2)

Publication Number Publication Date
JP2025500549A true JP2025500549A (ja) 2025-01-09
JP2025500549A5 JP2025500549A5 (https=) 2025-12-25

Family

ID=81328055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024539002A Pending JP2025500549A (ja) 2022-01-17 2023-01-11 圧電層の移転のためのドナー基板の製造のためのプロセス及び支持基板への圧電層の移転のためのプロセス

Country Status (8)

Country Link
US (1) US20250176430A1 (https=)
EP (1) EP4466729A1 (https=)
JP (1) JP2025500549A (https=)
KR (1) KR20240135830A (https=)
CN (1) CN118525353A (https=)
FR (1) FR3131979B1 (https=)
TW (1) TW202336927A (https=)
WO (1) WO2023135181A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3140474B1 (fr) * 2022-09-30 2024-11-01 Soitec Silicon On Insulator Substrat donneur et Procédé de fabrication d’un substrat donneur pour être utilisé dans un procédé de transfert de couche mince piézoélectrique.

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3079346B1 (fr) 2018-03-26 2020-05-29 Soitec Procede de fabrication d'un substrat donneur pour le transfert d'une couche piezoelectrique, et procede de transfert d'une telle couche piezoelectrique
FR3079345B1 (fr) * 2018-03-26 2020-02-21 Soitec Procede de fabrication d'un substrat pour dispositif radiofrequence

Also Published As

Publication number Publication date
FR3131979A1 (fr) 2023-07-21
TW202336927A (zh) 2023-09-16
EP4466729A1 (fr) 2024-11-27
KR20240135830A (ko) 2024-09-12
WO2023135181A1 (fr) 2023-07-20
FR3131979B1 (fr) 2025-03-21
US20250176430A1 (en) 2025-05-29
CN118525353A (zh) 2024-08-20

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