KR20230134324A - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

A power semiconductor device and a method of manufacturing the same are disclosed. A power semiconductor device according to an aspect of the present invention is formed by recessing a semiconductor layer by a predetermined depth from the surface of an epitaxial layer deposited on the semiconductor layer, at least one trench extending in one direction, and the at least one trench. a well region formed on the epitaxial layer inside the trench, a floating region (Buried Layer) formed on the semiconductor layer below the at least one trench, a gate insulating layer formed on at least a sidewall of the at least one trench, the at least at least one gate electrode layer formed on the gate insulating layer to fill one trench, an emitter region formed in the well region, an insulating layer formed outside the at least one trench and on the floating region, and the well region, and and an emitter electrode layer formed on the insulating layer to be connected to the emitter region.

Description

Power semiconductor device and method of fabricating the same}

The present invention relates to a power semiconductor device and a method of manufacturing the same, and more specifically, to a power semiconductor device that can improve the trade-off performance of the power semiconductor device without large-scale equipment investment to improve semiconductor manufacturing process capabilities, and It's about the manufacturing method.

Power semiconductor devices are semiconductor devices that operate in high voltage and high current environments. These power semiconductor devices are used in fields that require high-power switching, such as power conversion, power converters, and inverters. For example, power semiconductor devices include an insulated gate bipolar transistor (IGBT) and a power MOSFET (metal oxide semiconductor field effect transistor). These power semiconductor devices basically require withstand voltage characteristics against high voltages, and recently, additionally require high-speed switching operations.

Recently, the insulated gate bipolar transistor (IGBT) has been attracting attention as a power semiconductor device that combines the high-speed switching characteristics of a high-power MOSFET and the high-power characteristics of a BJT (Bipolar Junction Transistor). IGBT performance has three trade-off characteristics: breakdown voltage, collector-emitter saturation voltage (Vcesat), and robustness. Manufacturers around the world are making efforts to improve this trade-off performance.

In order to significantly improve the trade-off line, it is necessary to improve the performance of the parasitic capacitance forming the IGBT. This has a very significant effect in significantly improving robustness performance, and the key is to reduce the absolute size of the capacitance between Gate and Collector. To achieve this, conventional methods had the disadvantage of requiring large-scale equipment investment to significantly improve unit process capabilities such as etching, photo, and polishing.

Accordingly, there is a need for technology development that can improve the trade-off that determines the performance of power semiconductor devices with only excellent design capabilities without large-scale equipment investment.

The background technology of the present invention is disclosed in Republic of Korea Patent Publication No. 10-2070959 (2020.01.30 notice, Power device and manufacturing method thereof).

According to one aspect of the present invention, the present invention was created to solve the above problems, so as to improve the trade-off performance of power semiconductor devices without large-scale equipment investment to improve semiconductor manufacturing process capabilities. The purpose is to provide a power semiconductor device and a manufacturing method thereof.

Another object of the present invention is to provide a power semiconductor device and a manufacturing method thereof that can minimize non-ideal operations (eg, negative gate charging phenomenon, etc.) that may occur due to structural characteristics of the power semiconductor device.

The problem to be solved by the present invention is not limited to the problem(s) mentioned above, and other problem(s) not mentioned will be clearly understood by those skilled in the art from the description below.

A power semiconductor device according to an aspect of the present invention is formed by recessing a semiconductor layer by a predetermined depth from the surface of an epitaxial layer deposited on the semiconductor layer, at least one trench extending in one direction, and the at least one trench. a well region formed on the epitaxial layer inside the trench, a floating region (Buried Layer) formed on the semiconductor layer below the at least one trench, a gate insulating layer formed on at least a sidewall of the at least one trench, the at least at least one gate electrode layer formed on the gate insulating layer to fill one trench, an emitter region formed in the well region, an insulating layer formed outside the at least one trench and on the floating region, and the well region, and and an emitter electrode layer formed on the insulating layer to be connected to the emitter region.

In the present invention, the gate insulating layer includes a first portion between the bottom of the at least one trench and the gate electrode layer, and a second portion between the well region and the gate electrode layer, and the thickness of the first portion is It may be thicker than the thickness of the second portion.

In the present invention, the first part may have a W-shaped thickness with a convex center.

In the present invention, the semiconductor layer and the emitter region may be doped with an impurity of a first conductivity type, and the well region and the floating region may be doped with an impurity of a second conductivity type opposite to the first conductivity type.

A method of manufacturing a power semiconductor device according to another aspect of the present invention includes depositing an epitaxial layer on a semiconductor layer, forming a recess by a predetermined depth from the surface of the deposited epitaxial layer, and extending in one direction. forming at least one trench, forming a well region in the epitaxial layer inside the at least one trench, forming a floating region in the semiconductor layer outside the at least one trench, forming a gate insulating layer on at least a sidewall of the one trench, forming at least one gate electrode layer on the gate insulating layer inside the at least one trench, outside the at least one trench and the floating and forming an insulating layer on the area.

The present invention may further include forming an emitter region in the well region, and forming an emitter electrode layer on the insulating layer to be connected to the well region and the emitter region.

In the present invention, in the step of forming the gate insulating layer, the gate insulating layer includes a first portion between the bottom of the at least one trench and the gate electrode layer, and a second portion between the well region and the gate electrode layer. Including, the thickness of the first part may be thicker than the thickness of the second part.

In the present invention, the first part may have a W-shaped thickness with a convex center.

In the present invention, the semiconductor layer and the emitter region may be doped with an impurity of a first conductivity type, and the well region and the floating region may be doped with an impurity of a second conductivity type opposite to the first conductivity type.

The power semiconductor device and its manufacturing method according to one aspect of the present invention can control the maximum electric field position by forming a floating region in the semiconductor layer, thereby improving breakdown voltage performance and improving V _CESAT characteristics. You can.

The power semiconductor device and its manufacturing method according to another aspect of the present invention use a method of depositing a silicon epitaxial layer (EPI layer) on the top layer rather than investing in large-scale equipment such as etching, photo, and polishing in the case of forming a floating region. By doing so, it is possible to form a junction to a depth that is difficult to form with general implant equipment.

The power semiconductor device and its manufacturing method according to another aspect of the present invention significantly reduce the feedback influence of uncontrollable areas by forming a side wall structure composed of an insulating layer and a trench on the semiconductor layer, and additional gates are created through self-alignment. Cost savings are possible by not using poly masks.

The power semiconductor device and its manufacturing method according to another aspect of the present invention can secure an oxide safety margin against electric fields by forming a thick lower part of the trench, which is vulnerable to electric fields.

Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within the range apparent to those skilled in the art from the contents described below.

1 is a cross-sectional view illustrating a power semiconductor device according to an embodiment of the present invention.
Figure 2 is an enlarged view of area A in the power semiconductor device of Figure 1.
Figure 3 is a plan view cut off the VV plane of the power semiconductor device of Figure 1.
4 to 8 are cross-sectional views showing a method of manufacturing a power semiconductor device according to an embodiment of the present invention.
9 and 10 are diagrams for explaining the electric field of a power semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. The examples below make the disclosure of the present invention complete, and provide those of ordinary skill in the art with the scope of the invention. It is provided to provide complete information. Additionally, for convenience of explanation, the size of at least some components may be exaggerated or reduced in the drawings. In the drawings, like symbols refer to like elements.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by a person of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for illustrative purposes and thus serve to illustrate the general structures of the present invention. Identical reference signs indicate identical elements. It will be understood that when one component, such as a layer, region, or substrate, is referred to as being on another component, it may be directly on top of the other component, or other intervening components may also be present. On the other hand, when one designation is referred to as being “directly on” another, it is understood that there are no intervening structures.

1 is a cross-sectional view for explaining a power semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged view of area A in the power semiconductor device of FIG. 1, and FIG. 3 is a V-V plane in the power semiconductor device of FIG. 1. This is a cut floor plan.

1 to 3, the power semiconductor device according to an embodiment of the present invention may include a semiconductor layer 105, an insulating layer 130, and an emitter electrode layer 145. For example, the power semiconductor device 100 may have an insulated gate bipolar transistor (IGBT) or power MOSFET structure.

The semiconductor layer 105 may refer to one or more semiconductor material layers, for example, a portion of a semiconductor substrate and/or one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 may refer to one or multiple epitaxial layers on a semiconductor substrate.

For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide. Silicon carbide (SiC) has a wider bandgap than silicon, so it can maintain stability even at higher temperatures than silicon. Furthermore, silicon carbide has a much higher insulating wave field than silicon, so it can operate stably even at high voltages. Therefore, the power semiconductor device 100 using silicon carbide as the semiconductor layer 105 has a higher breakdown voltage compared to the case using silicon, has excellent heat dissipation characteristics, and can exhibit stable operating characteristics even at high temperatures.

More specifically, the semiconductor layer 105 may include a drift region (107). The drift region 107 may have a first conductivity type and may be formed by injecting an impurity of the first conductivity type into a portion of the semiconductor layer 105. For example, the drift region 107 may be formed by doping an impurity of the first conductivity type into the first epitaxial layer of silicon carbide.

A second epitaxial layer (not shown) is deposited on the first epitaxial layer (not shown) of the semiconductor layer 105, a well region (110) is formed in the second epitaxial layer, and the well region (110) is deposited on the first epitaxial layer (not shown) of the semiconductor layer 105. An emitter area 112 may be formed within (110). At this time, the first epitaxial layer and the second epitaxial layer may be provided as SiC epitaxial layers. The well region 110 may be formed by doping an impurity of a second conductivity type into the second epitaxial layer, and the emitter region 112 may be formed by doping an impurity of a first conductivity type into the well region 110. .

The well region 110 is formed in the semiconductor layer 105 to be in contact with the drift region 107 and may have a second conductivity type. For example, the well region 110 may be formed by doping the drift region 107 with an impurity of a second conductivity type that is opposite to the first conductivity type. The well region 110 may be formed by implanting (IMP) the top of the drift region 107 and then additionally depositing impurities of the second conductivity type. The well area 110 may be formed to surround at least a portion of the drift area 107 .

The emitter region 112 is formed in the well region 110 and may have a first conductivity type. For example, the emitter region 112 may be formed by doping the well region 110 with an impurity of the first conductivity type. The emitter region 112 may be formed by doping a higher concentration of impurities of the first conductivity type than the drift region 107 . The emitter region 112 may also be called a source region.

The semiconductor layer 105 may further include a floating area 125 in a portion extending between the gate electrode layers 120 and below the gate electrode layer 120 . The floating area 125 may be formed deeper than the bottom of the gate electrode layer 120. The floating region 125 may be formed in the semiconductor layer 105 opposite the well region 110 between two adjacent power semiconductor transistors PT. Accordingly, when viewed in cross section, well regions 110 and floating regions 125 may be formed alternately between the gate electrodes 120 .

For example, the drift region 107 and the emitter region 112 may have a first conductivity type, and the well region 110 and the floating region 125 may have a second conductivity type. The first conductivity type and the second conductivity type have opposite conductivity types and may be either n-type or p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

The drift region 107 may be provided as an epitaxial layer of a first conductivity type, and the well region 110 may be provided by doping impurities of a second conductivity type into this epitaxial layer or doping the epitaxial layer with an epitaxial layer of a second conductivity type. can be formed. The emitter region 112 may be formed by doping impurities of the first conductivity type into the well region 110 or by additionally forming an epitaxial layer of the first conductivity type.

Furthermore, when the power semiconductor device 100 is an IGBT, a collector region (not shown) is formed below the drift region 107, and a collector electrode layer (not shown) may be provided below the collector region to be connected to the collector region. . For example, the collector region may be provided with an epitaxial layer having a second conductivity type beneath the drift region 107 .

At least one trench 116 may be formed by recessing a predetermined depth from the surface of the second epitaxial layer 104. For example, the trench 116 may be formed to contact the semiconductor layer 105 along one direction. The trenches 116 may extend in one direction and may be arranged side by side and spaced apart in a direction perpendicular to one direction. The trench 116 may form a closed loop when viewed in plan. The loop may have various shapes, such as a donut shape or a square shape.

The number of trenches 116 may be appropriately selected depending on the performance of the power semiconductor device 100 and does not limit the scope of this embodiment.

According to this structure, the well region 110 may be formed in the second epitaxial layer inside the trench 116, and the floating region 125 may be formed in the semiconductor layer 105 below the trench 116.

Gate insulating layer 118 may be formed on the sidewall of at least one trench 116 . For example, the gate insulating layer 118 may be formed on the inner surface of the trench 116.

Gate insulating layer 118 may be formed on the bottom and inner wall of trench 116. For example, the gate insulating layer 118 includes a first portion 118a formed to a first thickness from the bottom of the trench 116 and a second portion 118b formed to a second thickness on the inner wall of the trench 116. It can be included.

For example, the first portion 118a may be formed to partially fill the trench 116 from the bottom of the trench 116 to a first thickness. At this time, the first part 118a may have a W-shaped thickness with a convex center. The second portion 118b may be formed substantially on the first portion 118a and may be formed on the sidewalls of the trench 116 . Accordingly, the second thickness of the second part 118b may be smaller than the first thickness of the first part 118a. For example, the second thickness may range from 1/5 to 1/30 of the first thickness.

The gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, or aluminum oxide, or may include a stacked structure thereof.

In this way, by forming the first part 118a of the gate insulating layer 118 at the bottom of the trench 116 to be thicker than the second part 118b, the trench 116 is formed when the power semiconductor device 100 is operated. Concentration of electric fields at the bottom can be alleviated.

The gate electrode layer 120 may be formed on the gate insulating layer 118 to fill at least one trench formed in the second epitaxial layer. In this way, a plurality of gate electrode layers 120 may be formed on the gate insulating layer 118 to fill the inside of the trench 116. Accordingly, the gate electrode layer 120 may be formed in the second epitaxial layer as a trench type, and may be arranged to extend parallel to one direction like the trenches 116 .

The insulating layer 130 may be formed outside of at least one trench and on the floating area 125. For example, the insulating layer 130 may include an appropriate insulating material, such as an oxide layer, a nitride layer, or a stacked structure thereof.

The emitter electrode layer 145 may be formed on the well region 110 and the insulating layer 130 and connected to the emitter region 112 and the well region 110. An insulating layer 130 may be interposed between the semiconductor layer 105 and the emitter electrode layer 145.

The emitter electrode layer 145 may be formed on the insulating layer 130 and connected to the emitter region 112 . For example, the emitter electrode layer 145 may be formed of an appropriate conductive material, metal, etc. That is, the emitter electrode layer 145 can be formed by forming a conductive layer, for example, a metal layer, on the insulating layer 130 and then patterning it.

According to an embodiment of the present invention, the peak of the E field is formed at the bottom of the epitaxial layer due to the floating area 125, thereby protecting the gate electrode layer 120 from the electric field concentrated at the bottom. Additionally, higher threshold voltage performance can be achieved at the same epitaxial layer length through charge sharing of the floating region 125.

In addition, the parasitic capacitance ratio C _GE /C _GC constituting the power semiconductor device must be high for the power semiconductor device to operate more stably. Accordingly, in the present invention, an insulating layer 130 is formed between the semiconductor layer 105 and the emitter electrode layer 145, and the first part 118a of the gate insulating layer 118 has a W-shaped thickness with a convex center. Therefore, the gate-collector capacitance (C _GC ) can be minimized. Additionally, the gate insulating layer 118 having a W-shaped thickness with a convex center in the first portion 118a can protect the gate insulation from destruction due to a high electric field.

In addition, the power semiconductor device according to the present invention can minimize the impact of negative gate charging (NGC) due to voltage changes between CEs during switching operations. For example, there is an effect as I _Displacement = C _GC *(dv _ce /dt), but in the case of the power semiconductor device according to the present invention, the thickness of the part forming C _GC in the lower region of the trench is thicker than the conventional structure, so NGC is affected. can be reduced.

In an embodiment of the present invention, the number of trenches 116, gate electrode layer 120, and emitter electrode layer 145 may be appropriately selected according to the operating specifications of the power semiconductor device 100 and does not limit the scope of this embodiment. I never do that.

The above descriptions were made assuming that the power semiconductor device is an IGBT, but can also be applied to a power MOSFET. For example, in a power MOSFET, there is no collector region and a drain electrode may be placed instead of the collector electrode.

Figures 4 to 8 are cross-sectional views showing a method of manufacturing a power semiconductor device according to an embodiment of the present invention, and Figures 9 and 10 are diagrams for explaining the electric field of the power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 4, a drift region 107 having a first conductivity type may be formed in the semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107 may be formed on a collector region (not shown) having a first conductivity type. In some embodiments, the collector region (not shown) is provided with a substrate of a first conductivity type, and the drift region 107 may be formed with one or more epitaxial layers on this substrate.

Next, as shown in FIG. 5, a second epitaxial layer may be formed on the first epitaxial layer, and diffusion heat treatment may be performed. A second epitaxial layer may be formed on the first epitaxial layer. For example, the first epitaxial layer and the second epitaxial layer may be provided as SiC epitaxial layers. Next, a well region 110 may be formed in the second epitaxial layer, and an emitter region 112 may be formed in the well region 110. For example, the well region 110 is formed by doping impurities of a second conductivity type into the second epitaxial layer, and the emitter region 112 is formed by doping impurities of a first conductivity type into the well region 110. can be formed.

For example, when the first conductivity type is n-type and the second conductivity type is p-type, the first epitaxial layer and the second epitaxial layer have a No doping level, and the well region 110 has a Po doping level. and the emitter region 112 may have an N+ doping level.

Subsequently, at least one trench 116 is formed to be recessed by a predetermined depth from the surface of the second epitaxial layer to the inside of the second epitaxial layer, and a well region (well region) is formed in the second epitaxial layer on one side of the trench 116. 110), and the floating area 125 may be defined in the semiconductor layer 105 on the other side of the trench 116. Emitter region 112 may be defined within well region 110 .

That is, a photoresist pattern can be formed on the second epitaxial layer. For example, a photoresist pattern can be formed using photolithography technology. Next, using the photoresist pattern as an etch protection film, a second epitaxial layer can be formed to a predetermined depth to form a trench having a second width. At this time, the trench 116 has a closed loop shape, the well region 110 is formed in the second epitaxial layer inside the trench 116, and the floating region 125 is formed in the semiconductor layer outside the trench 116. It can be formed at (105).

For example, the trench 116 forms a photoresist pattern using photolithography technology on the second epitaxial layer in which the well region 110 is formed, and uses this photoresist pattern as an etch protection film to form the second epitaxial layer. It can be formed by etching.

In this embodiment, it has been described that the trench 116 is formed after forming the well region 110, but the well region 110 may also be formed after forming the trench 116.

Next, as shown in FIG. 6, a gate insulating layer 118 filling the inside of the trench is formed on at least the sidewalls of the trench 116, and a trench is formed on the gate insulating layer 118 inside the trench 116. The gate electrode layer 120 may be formed to bury the gate electrode layer 120. The gate electrode layer 120 is formed as a trench type in the second epitaxial layer, and, like the trenches 116, may be arranged to extend parallel to one direction. The gate electrode layer 120 may include metal or doped polysilicon.

Next, an insulating layer 130 is formed as shown in FIG. 7, and an emitter electrode layer 145 is formed on the insulating layer 130 to be connected to the emitter region 112 as shown in FIG. 8. You can. At this time, the insulating layer 130 may be formed outside the trench and on the floating area 125. The insulating layer 130 can be formed by depositing and then patterning dielectric oxide for insulation. The emitter electrode layer 145 may be formed on the insulating layer 130 to be connected to the emitter region 112 and the well region 110. At this time, the emitter electrode layer 145 can be formed by forming a conductive layer, for example, a metal layer, on the insulating layer 130 and then patterning it.

According to an embodiment of the present invention, as shown in FIGS. 9 and 10, the peak of the E Field is formed at the bottom of the epitaxial layer due to the floating area 125 to protect from the electric field concentrated at the bottom of the gate electrode layer 120. can do. In addition, through charge sharing of the floating area 125, B of the present invention can achieve higher threshold voltage performance than A of the related art at the same epitaxial length, as shown in FIG. 10.

As such, the power semiconductor device and its manufacturing method according to an aspect of the present invention can control the maximum electric field position by forming the floating region 125 in the semiconductor layer 105, thereby improving breakdown voltage performance. This can improve V _CESAT characteristics.

The power semiconductor device and its manufacturing method according to another aspect of the present invention include depositing a silicon epitaxial layer (EPI layer) on the top layer rather than investing in large-scale equipment such as etching, photo, and polishing in the case of forming the floating region 125. By using the method, it is possible to form a junction to a depth that is difficult to form with general implant equipment.

The power semiconductor device and its manufacturing method according to another aspect of the present invention significantly reduce the feedback influence of uncontrollable areas by forming a side wall structure composed of an insulating layer 130 and a trench on the semiconductor layer and enable self-alignment. It is possible to reduce costs by not using additional Gate Poly masks.

The power semiconductor device and its manufacturing method according to another aspect of the present invention can secure an oxide safety margin against electric fields by forming a thick lower part of the trench, which is vulnerable to electric fields.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely illustrative, and those skilled in the art will recognize that various modifications and other equivalent embodiments can be made therefrom. You will understand. Therefore, the true technical protection scope of the present invention should be determined by the scope of the patent claims below.

105: semiconductor layer
107: Drift area
110: well area
112: Emitter area
118: Gate insulation layer
120: Gate electrode layer
125: floating area
130: insulation layer
145: Emitter electrode layer

Claims (9)

semiconductor layer;
at least one trench formed by recessing a predetermined depth from the surface of the epitaxial layer deposited on the semiconductor layer and extending in one direction;
a well region formed in the epitaxial layer inside the at least one trench;
a floating region (Buried Layer) formed in the semiconductor layer below the at least one trench;
a gate insulating layer formed on at least a sidewall of the at least one trench;
at least one gate electrode layer formed on the gate insulating layer to fill the at least one trench;
an emitter region formed within the well region;
an insulating layer formed outside the at least one trench and on the floating area; and
an emitter electrode layer formed on the insulating layer to be connected to the well region and the emitter region;
A power semiconductor device containing a.
According to paragraph 1,
The gate insulating layer is,
a first portion between the bottom of the at least one trench and the gate electrode layer, and a second portion between the well region and the gate electrode layer,
A power semiconductor device, characterized in that the thickness of the first portion is thicker than the thickness of the second portion.
According to paragraph 2,
The first part is,
A power semiconductor device characterized by having a W-shaped thickness with a convex center.
According to paragraph 1,
The semiconductor layer and the emitter region are doped with an impurity of a first conductivity type,
A power semiconductor device, wherein the well region and the floating region are doped with an impurity of a second conductivity type that is opposite to the first conductivity type.
After depositing an epitaxial layer on a semiconductor layer, forming at least one trench that is recessed by a predetermined depth from the surface of the deposited epitaxial layer and extends in one direction;
forming a well region in the epitaxial layer inside the at least one trench;
forming a floating area in the semiconductor layer outside the at least one trench;
forming a gate insulating layer on at least a sidewall of the at least one trench;
forming at least one gate electrode layer on the gate insulating layer inside the at least one trench; and
forming an insulating layer outside the at least one trench and on the floating area.
A method of manufacturing a power semiconductor comprising a.
According to clause 5,
forming an emitter region within the well region; and
A method of manufacturing a power semiconductor, further comprising forming an emitter electrode layer on the insulating layer to be connected to the well region and the emitter region.
According to clause 5,
In forming the gate insulating layer,
The gate insulating layer includes a first portion between the bottom of the at least one trench and the gate electrode layer, and a second portion between the well region and the gate electrode layer,
A method of manufacturing a power semiconductor, characterized in that the thickness of the first portion is thicker than the thickness of the second portion.
In clause 7,
The first part is,
A method of manufacturing a power semiconductor, characterized in that it has a W-shaped thickness with a convex center.
According to clause 6,
The semiconductor layer and the emitter region are doped with an impurity of a first conductivity type,
The method of manufacturing a power semiconductor, characterized in that the well region and the floating region are doped with an impurity of a second conductivity type that is opposite to the first conductivity type.