KR102417146B1 - Power semiconductor device - Google Patents

Abstract

A power semiconductor device according to an aspect of the present invention includes a semiconductor layer of silicon carbide (SiC), a first well region formed of a plurality of lines extending in one direction in a first region of the semiconductor layer, and the semiconductor layer. a second well region formed in a second region to be connected to the first well region, a well region having a second conductivity type, a first source region formed in the semiconductor layer on the first well region, and the second well region a second source region formed in the semiconductor layer on the well region to be connected to the first source region, the first source region having a first conductivity type; a drift region formed in the semiconductor layer to extend between the plurality of lines of a well region and having a first conductivity type; at least one trench formed to be recessed; a gate insulating layer formed on an inner wall of the at least one trench and the first region of the semiconductor layer; and a gate insulating layer formed on the gate insulating layer and filling the at least one trench and a gate electrode layer including a first portion and a second portion on the first region.

Description

Power semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power delivery.

A power semiconductor device is a semiconductor device that operates in a high voltage and high current environment. Such power semiconductor devices are used in fields requiring high power switching, for example, power conversion, power converters, inverters, and the like. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the like. Such a power semiconductor device is basically required to withstand high voltage, and recently, a high-speed switching operation is additionally required.

Accordingly, a power semiconductor device using silicon carbide (SiC) instead of conventional silicon (Si) is being studied. Silicon carbide (SiC) is a wide-gap semiconductor material having a higher bandgap than silicon, and can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Therefore, silicon carbide has a higher breakdown voltage than silicon, and exhibits excellent heat dissipation, so that it can be operated at a high temperature.

In the case of a power semiconductor device using such silicon carbide, the band gap on the surface of the silicon carbide rises upward due to the influence of negative charges due to the formation of carbon clusters in the gate insulating layer, so there is a problem in that the threshold voltage is increased and the channel resistance is increased. In addition, since the source contact structure is disposed between the gate electrodes, it is difficult to narrow the gap between the gate electrodes, so there is a limit in increasing the channel density. Furthermore, it is necessary to increase channel mobility while increasing the channel density.

Republic of Korea Publication No. 2011-0049249 (published on May 11, 2011)

An object of the present invention is to provide a silicon carbide power semiconductor device capable of increasing channel mobility while increasing a channel density as to solve the above problems. However, these problems are exemplary, and the scope of the present invention is not limited thereto.

In a power semiconductor device according to an aspect of the present invention for solving the above problems, a semiconductor layer of silicon carbide (SiC) and a first well formed by a plurality of lines extending in one direction in a first region of the semiconductor layer a second well region formed in a region and a second region of the semiconductor layer to be connected to the first well region, a well region having a second conductivity type, and a first formed in the semiconductor layer on the first well region a source region and a second source region formed on the semiconductor layer on the second well region to be connected to the first source region, the well to provide a source region having a first conductivity type and a vertical movement path of charges a drift region formed in the semiconductor layer extending between the plurality of lines of the first well region from below a region and having a first conductivity type; at least one trench formed to be recessed into the semiconductor layer; a gate insulating layer formed on an inner wall of the at least one trench and the first region of the semiconductor layer; and a gate electrode layer including a first portion filling one trench and a second portion on the first region of the semiconductor layer.

According to the power semiconductor device, the drift region includes a plurality of protruding portions extending between the plurality of lines of the first well region, and the at least one trench is formed by etching a part of the plurality of protruding portions. It may include a plurality of trenches formed.

According to the power semiconductor device, a first channel region formed along the at least one trench in the semiconductor layer between the drift region and the first source region, under the first portion of the gate electrode layer, and the gate electrode layer; and a second channel region formed in the semiconductor layer between the drift region and the first source region under the second portion of .

According to the power semiconductor device, the first channel region and the second channel region have a second conductivity type such that an inversion channel is formed, and the first channel region and the second channel region are a part of the first well region can

According to the power semiconductor device, the first channel region may have a second conductivity type to form an inversion channel, and the second channel region may have a first conductivity type to form an accumulation channel.

According to the power semiconductor device, the first well region may be symmetrically formed on both sides with respect to the second well region, and the first source region may be symmetrically formed on both sides with respect to the second source region. can

The power semiconductor device may include a well contact region extending from the second well region through the second source region in the second source region and having a second conductivity type, the second source region and the well contact region. It may further include a connected source electrode layer.

The power semiconductor device includes at least one groove passing through the second source region to expose the second well region, and a bottom surface of the at least one groove in contact with the second well region and having a second conductivity type. It may further include a well contact region having a , and a source electrode layer formed to fill the at least one groove and connected to the second source region and the well contact region.

The power semiconductor device may further include a drain region having a first conductivity type in the semiconductor layer under the drift region, and the drift region may be formed as an epitaxial layer on the drain region.

According to the power semiconductor device and the manufacturing method thereof according to an embodiment of the present invention made as described above, it is possible to increase the channel density to increase the degree of integration and increase the channel mobility.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a schematic schematic perspective view showing a power semiconductor device according to an embodiment of the present invention.
FIG. 2 is a plan view showing the power semiconductor device taken along line II-II of FIG. 1 .
3 is a cross-sectional view illustrating a power semiconductor device taken along line III-III of FIG. 2 .
4 is a cross-sectional view illustrating a power semiconductor device taken along line IV-IV of FIG. 2 .
FIG. 5 is a cross-sectional view showing the power semiconductor device taken along line VV of FIG. 2 .
6 and 7 are cross-sectional views illustrating power semiconductor devices according to other embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in a variety of different forms. It is provided to fully inform In addition, in the drawings for convenience of description, the size of at least some of the components may be exaggerated or reduced. In the drawings, like numbers refer to like elements.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for the purpose of explanation, and thus are provided to explain the general structures of the present invention.

Like reference signs indicate like elements. When referring to one component as being on another component, such as a layer, region, or substrate, it will be understood that other intervening components may also be present, either directly on top of the other component or in between. On the other hand, when referring to one configuration as being “directly on” of another, it is understood that intervening configurations do not exist.

1 is a schematic schematic perspective view showing a power semiconductor device 100 according to an embodiment of the present invention, FIG. 2 is a plan view showing the power semiconductor device 100 taken along line II-II of FIG. 1, 3 is a cross-sectional view showing the power semiconductor device 100 taken along line III-III of FIG. 2, FIG. 4 is a cross-sectional view showing the power semiconductor device 100 taken along line IV-IV of FIG. 2, and FIG. is a cross-sectional view showing the power semiconductor device 100 taken along line V-V of FIG. 2 .

1 to 5 , the power semiconductor device 100 may include at least a semiconductor layer 105 , a gate insulating layer 118 , and a gate electrode layer 120 . For example, the power semiconductor device 100 may have a power MOSFET structure.

The semiconductor layer 105 may refer to one or more semiconductor material layers, for example, one or multiple epitaxial layers. Furthermore, the semiconductor layer 105 may refer to one or multiple epitaxial layers on a semiconductor substrate.

For example, the semiconductor layer 105 may be made of silicon carbide (SiC). More specifically, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

Silicon carbide (SiC) has a wider bandgap than silicon, so it can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high insulating wave field compared to silicon, so it can operate stably even at a high voltage. Accordingly, the power semiconductor device 100 using silicon carbide as the semiconductor layer 105 has a high breakdown voltage and excellent heat dissipation characteristics compared to the case where silicon is used, and may exhibit stable operating characteristics even at high temperatures.

More specifically, the semiconductor layer 105 may include a drift region 107 . The drift region 107 may have the first conductivity type, and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105 . For example, the drift region 107 may be formed by doping an impurity of the first conductivity type into an epitaxial layer of silicon carbide.

The drift region 107 may provide a vertical movement path for electric charges. Furthermore, the drift region 107 may include at least one protruding portion 107a disposed under the gate electrode layer 120 . The protruding portion 107a may extend substantially onto the surface of the semiconductor layer 105 .

The well region 110 may be formed to contact at least a portion of the drift region 107 in the semiconductor layer 105 and may have a second conductivity type. For example, the well region 110 may be formed by doping impurities of a second conductivity type opposite to the first conductivity type into the semiconductor layer 105 or the drift region 107 .

For example, the well region 110 is formed in a first well region 110a formed of a plurality of lines extending in one direction in the first region of the semiconductor layer 105 and in the second region of the semiconductor layer 105 . It may include a second well region 110b formed to be connected to the first well region 110a.

More specifically, the first well region 110a may be formed in the first region of the semiconductor layer 105 under the gate electrode layer 120 and may be formed in contact with the protruding portion 107a of the drift region 107 . The second well region 110b may be formed in the second region of the semiconductor layer 105 outside the gate electrode layer 120 . The first well region 110a and the second well region 110b may be connected to each other. Substantially, a lower portion of the protruding portion 107a of the drift region 107 may be defined by the first well region 110a, and more specifically, may be in contact with a sidewall of the first well region 110a.

The drift region 107 may be formed in the semiconductor layer 105 to extend between the lines of the first well region 110a from below the well region 110 . For example, the drift region 107 may include a plurality of protruding portions 107a extending between lines of the first well region 110a.

A source region 112 may be formed on or in the well region 110 and may have a first conductivity type. For example, the source region 112 may be formed by doping the semiconductor layer 105 or the well region 110 with impurities of the first conductivity type. The source region 112 may be formed by doping a higher concentration of impurities of the first conductivity type than the drift region 107 .

For example, the source region 112 may be formed on or within the first well region 110a or within the first source region 112a and the second well region 110b or within the second well region. A second source region 112b formed on 110b may be included. The first source region 112a and the second source region 112b may be connected to each other. The first source region 112a may be disposed under the gate electrode layer 120 , and the second source region 112b may be disposed outside the gate electrode layer 120 .

Furthermore, like the first well region 110a , the first source region 112a may include a plurality of lines extending in one direction. The first source region 112a may extend symmetrically to both sides of the second source region 112b.

The second source region 112b may include a source contact region 112b1 connected to the source electrode layer 140 outside the gate electrode layers 120 . For example, the source contact region 112b1 is a part of the second source region 112b and may refer to a portion to which the source electrode layer 140 is connected.

The well contact region 114 may be formed in the second source region 112b, more specifically, in the source contact region 112b1. For example, the well contact region 114 may extend from the second well region 110b through the second source region 112b and may have the second conductivity type. One or a plurality of well contact regions 114 may be formed in the source contact region 112b1.

The well contact region 114 may be connected to the source electrode layer 140 , and may be doped with an impurity of the second conductivity type at a higher concentration than the well region 110 to reduce contact resistance when connected to the source electrode layer 140 . .

Additionally, the drain region 102 may be formed in the semiconductor layer 105 under the drift region 107 and may have a first conductivity type. For example, the drain region 102 may be doped at a higher concentration than the drift region 107 .

In some embodiments, the drain region 102 may be provided as a substrate of silicon carbide having a first conductivity type. In this case, the drain region 102 may be understood as a part of the semiconductor layer 105 or as a substrate separate from the semiconductor layer 105 . Further, in some embodiments, the drain region 102 is provided as a silicon carbide substrate of a first conductivity type, and the drift region 107 may be formed on one or more epitaxial layers on this drain region 102 . have.

In some embodiments, the drift region 107 may include a plurality of protruding portions 107a formed side by side in one direction. For example, the first well region 110a may be formed in a stripe pattern extending in one direction, and the protruding portions 107a may also be formed in a stripe pattern. Also, the first source region 112a may be formed in a stripe pattern on the first well region 110a.

The at least one trench 116 may be formed to be recessed by a predetermined depth from the surface of the semiconductor layer 105 into the semiconductor layer 105 . For example, the trench 116 may be formed to be recessed into at least a portion of the semiconductor layer 105 between the plurality of lines of the first well region 110a from the surface of the semiconductor layer 105 . More specifically, the trench 116 may be formed to contact the first source region 112a by etching the protruding portion 107a of the drift region 107 and a portion of the first well region 110a adjacent thereto. .

The trench 116 may extend in one direction in the semiconductor layer 105 . One direction refers to a length direction rather than a depth direction of the trench 116 , and may refer to a line IV-IV or a line V-V in FIG. 2 .

In some embodiments, more specifically, the trench 116 may include a plurality of trenches 116 formed by etching a portion of the protruding portions 107a of the drift region 107 . The plurality of trenches 116 may be formed between any one of adjacent two of the plurality of lines of the first well region 110a. For example, when viewed along line III-III of FIG. 2 , trenches 116 may be formed one by one between adjacent two of the plurality of lines of the first well region 110a .

The gate insulating layer 118 may be formed on inner walls of the trenches 116 and at least a portion of the semiconductor layer 105 . For example, the gate insulating layer 118 may be formed on inner walls of the trenches 116 and on the first region of the semiconductor layer 105 .

For example, the gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, aluminum oxide, or a stacked structure thereof.

The gate electrode layer 120 may be formed on the gate insulating layer 118 . For example, the gate electrode layer 120 may include a first portion 120a filling the at least one trench 116 and a second portion 120b on the first region of the semiconductor layer 105 . For example, the first portion 120a of the gate electrode layer 120 may have a trench type gate structure, and the second portion 120b may have a planar type gate structure. Accordingly, the gate electrode layer 120 may have a hybrid-type structure including both a trench-type gate structure and a planar-type gate structure.

More specifically, the gate electrode layer 120 may be formed on the first source region 112a , the channel region 110c , and the protruding portions 107a of the drift region 107 . The second well region 110b , the second source region 112b , and the well contact region 114 may be disposed outside the gate electrode layer 120 and may be exposed from the gate electrode layer 120 .

For example, the gate electrode layer 120 may include a suitable conductive material, such as polysilicon, metal, metal nitride, metal silicide, or the like, or may include a stacked structure thereof.

The depth of the first well region 110a may be formed at a position deeper than that of the trench 116 and the gate electrode layer 120 . Accordingly, the trench bottom edge of the first portion 120a of the gate electrode layer 120 may be surrounded by the first well region 110a. Such a structure may alleviate a portion where an electric field is concentrated at the bottom edge of the trench in the trench-type gate structure. Furthermore, since the height of the protruding portion 107a of the drift region 107 under the first portion 120a is lower than the height of the protruding portion 107a of the drift region 107 under the second portion 120b, the first It is possible to reduce the junction resistance under the portion 120a.

The interlayer insulating layer 130 may be formed on the gate electrode layer 120 . For example, the interlayer insulating layer 130 may include a suitable insulating material, such as an oxide layer, a nitride layer, or a laminate structure thereof.

The source electrode layer 140 may be formed on the interlayer insulating layer 130 , and may be connected to the source region 112 , more specifically, the second source region 112b or the source contact region 112b1 . Furthermore, the source electrode layer 140 may be commonly connected to the second source region 112b and the well contact region 114 . For example, the source electrode layer 140 may be formed of an appropriate conductive material, metal, or the like.

The first channel region C1 is at least one trench 116 in the semiconductor layer 105 between the drift region 107 and the first source region 112a under the first portion 120a of the gate electrode layer 120 . ) can be formed. For example, the first channel region C1 may be formed between the protruding portion 107a of the drift region 107 and the first source region 112a. The first channel region C1 may have a trench-type channel structure.

The second channel region C2 may be formed in the semiconductor layer 105 between the drift region 107 and the first source region 112 under the second portion 120b of the gate electrode layer 120 . The second channel region C2 may have a planar channel structure.

For example, the first channel region C1 and the second channel region C2 may have the second conductivity type to form an inversion channel. Since the first channel region C1 and the second channel region C2 have doping types opposite to those of the source region 112 and the drift region 107 , the first channel region C1 and the second channel region C2 ) may form a diode junction junction with the source region 112 and the drift region 107 .

Accordingly, although the first channel region C1 and the second channel region C2 do not allow the movement of charges under normal circumstances, when an operating voltage is applied to the gate electrode layer 120 , an inversion channel is formed therein. to allow the transfer of charges.

For example, the first channel region C1 and the second channel region C2 may be part of the well region 110 , for example, the first well region 110a. More specifically, the first channel region C1 is a part of the first well region 110a adjacent to the lower portion of the first portion 120a of the gate electrode layer 120, and the second channel region C2 is the gate electrode layer ( It may be a portion of the first well region 110a adjacent to the lower portion of the second portion 120b of 120 .

In this case, the first channel region C1 and the second channel region C2 may be integrally or continuously connected to the well region 110 . The doping concentrations of the impurities of the second conductivity type in the first channel region C1 and the second channel region C2 may be the same as in other portions of the well region 110 or may be different for controlling the threshold voltage.

In some embodiments, the protruding portion 107a of the drift region 107 , the first well region 110a , the channel region 110c , and/or the first source region 112a may extend in one direction.

In some embodiments, the first well region 110a and the first source region 112a may be formed symmetrically with respect to the protruding portion 107a of the drift region 107 . For example, the first well region 110a and the first source region 112a may be respectively formed in the semiconductor layer 105 on both sides of the protruding portion 107a of the drift region 107 .

In some embodiments, the first well region 110a is symmetrically formed with respect to the second well region 110b, and the first source region 112a is symmetrically formed with respect to the second source region 112b. can be formed. In this case, the protruding portions 107a of the drift region 107 may include a plurality of protruding portions 107a symmetrically formed with respect to the second well region 110b or the second source region 112b. have.

Furthermore, the first well region 110a and the second well region 110b may be repeatedly formed alternately in one direction. In this case, the first source region 112a and the second source region 112b may also be repeatedly formed.

In the above-described power semiconductor device 100 , the first conductivity type and the second conductivity type may have opposite conductivity types, but may be either n-type or p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

More specifically, when the power semiconductor device 100 is an N-type MOSFET, the drift region 107 is an N- region, the source region 112 and the drain region 102 are N+ regions, and the well region 110, The first channel region C1 and the second channel region C2 may be a P− region, and the well contact region 114 may be a P+ region.

In operation of the power semiconductor device 100 , a current flows from the drain region 102 along the protruding portions 107a of the drift region 107 in a generally vertical direction, followed by the first channel region C1 and the second channel. It may flow to the source region 112 through the region C2 .

In the power semiconductor device 100 , the source contact region 112b1 and the well contact region 114 may be separately disposed outside the gate electrode layer 120 . Accordingly, the first well region 110a and the first source region 112a may be formed such that the protruding portions 107a of the drift region 107 are densely disposed, and accordingly, the first channel region C1 and The second channel region C2 may be densely formed under the gate electrode layer 120 . Accordingly, the power semiconductor device 100 may have a high degree of integration.

The power semiconductor device 100 may have a hybrid structure including both a trench-type structure and a planar structure. Accordingly, it is possible to increase channel mobility while maintaining the degree of integration by adding the trench-type structure compared to the case of having only the planar structure. Accordingly, it is possible to reduce the increase in junction resistance while the separation distance of the first well region 110a is shortened.

6 is a cross-sectional view showing a power semiconductor device 100a according to another embodiment of the present invention. The power semiconductor device 100a is a variation of some configuration from the power semiconductor device 100 of FIGS. 1 to 5 , and may be referenced to each other, and overlapping descriptions will be omitted.

Referring to FIG. 6 , in the power semiconductor device 100a , the second channel region C2a may be formed in the semiconductor layer 105 between the drift region 107 and the source region 112 . For example, the second channel region C2a may be formed in the semiconductor layer 105 between the protruding portion 107a of the drift region 107 and the first source region 112a. The second channel region C2a may have the first conductivity type to form an accumulation channel.

For example, the second channel region C2a may have the same doping type as the source region 112 and the drift region 107 . In this case, the source region 112 , the second channel region C2a , and the drift region 107 have a structure in which they can be normally electrically connected. However, in the structure of the semiconductor layer 105 of silicon carbide, the band of the second channel region C2a is bent upward due to the influence of a negative charge generated while carbon clusters are formed in the gate insulating layer 118 . A potential barrier is formed. Accordingly, when an operating voltage is applied to the gate electrode layer 120 , an accumulation channel allowing the flow of charges or currents may be formed in the second channel region C2a.

Therefore, the threshold voltage that must be applied to the gate electrode layer 120 to form the accumulation channel in the second channel region C2a is significantly lower than the threshold voltage that must be applied to the gate electrode layer 120 to form a conventional inversion channel. can

In some embodiments, the second channel region C2a may be a part of the drift region 107 . More specifically, the second channel region C2a may be a part of the protruding portion 107a of the drift region 107 . For example, the second channel region C2a may be integrally formed with the drift region 107 .

For example, the doping concentration of the impurity of the first conductivity type in the second channel region C2a may be the same as that of other portions of the drift region 107 or may be different for controlling the threshold voltage.

In this embodiment, in a portion adjacent to the second channel region C2a, ends of the first well region 110a and the first source region 112a may be positioned on the same line. In this case, the first source region 112a may be in contact with the protruding portion 107a of the drift region 107 , and the channel region 107b may be defined in the contacting portion of the protruding portion 107a .

In some embodiments, the first well region 110a may be formed below the first source region 112a to protrude in the direction of the protruding portion 107a of the drift region 107 than the first source region 112a. In this case, the second channel region C2a may be formed in the semiconductor layer 105 on the protruding portion of the first well region 110a. For example, the protruding portion 107a of the drift region 107 may further extend into a groove portion between the first well region 110a and the gate electrode layer 120 , and the second channel region C2a is this portion. can be formed in This structure may allow the second channel region C2a to be defined between the gate electrode layer 120 and the well region 110 .

7 is a cross-sectional view showing a power semiconductor device 100b according to another embodiment of the present invention. The power semiconductor device 100b is a variation of some configuration from the power semiconductor device 100 of FIGS. 1 to 5 , and may be referenced to each other, and overlapping descriptions will be omitted.

Referring to FIG. 7 , the power semiconductor device 100b may include at least one groove 138 penetrating through the second source region 112b and exposing the second well region 110b. The groove 138 may be formed to expose the surface of the second well region 110b or to be recessed to a predetermined depth of the second well region 110b. A well contact region 114a may be formed on at least a bottom surface of the groove 138 to be in contact with the second well region 110b.

The source electrode layer 140 may be formed to fill the groove 138 and may be connected to the well contact region 114a, the second well region 110b, and/or the second source region 112b. Such a structure may help to reduce a contact resistance between the source electrode layer 140 and the second well region 110b and the second source region 112b by increasing the contact area therebetween.

In some embodiments, the well contact region 114a may be entirely formed on the surface of the second well region 110b exposed by the groove 138 . Accordingly, the well contact region 114a may be formed on the second well region 110b exposed from the bottom and sidewalls of the groove 138 . The structure of the well contact region 114a may serve to further reduce the contact resistance between the source electrode layer 140 and the second well region 110b.

Although the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: power semiconductor device
102: drain region
105: semiconductor layer
107: drift zone
110: well area
112: source area
118: gate insulating layer
120: gate electrode layer
130: interlayer insulating layer
140: source electrode layer

Claims (9)

a semiconductor layer of silicon carbide (SiC);
a first well region formed of a plurality of lines extending in one direction in a first region of the semiconductor layer and a second well region formed in a second region of the semiconductor layer to be connected to the first well region; a well region having a second conductivity type;
a source having a first conductivity type, comprising: a first source region formed in the semiconductor layer on the first well region; and a second source region formed in the semiconductor layer on the second well region to be connected to the first source region; area;
a drift region formed in the semiconductor layer and having a first conductivity type extending from below the well region to between the plurality of lines in the first well region to provide a vertical movement path of charge;
at least one trench formed to be recessed into at least a portion of the semiconductor layer between the plurality of lines from the surface of the semiconductor layer;
a gate insulating layer formed on an inner wall of the at least one trench and the first region of the semiconductor layer; and
a gate electrode layer formed on the gate insulating layer and comprising a first portion filling the at least one trench and a second portion on the first region of the semiconductor layer;
The first portion is formed above the first protrusion portion of the drift region disposed on the first side of the first well region, and the second protrusion portion of the drift region disposed on the second side of the first well region The second part is formed on the upper part,
a height of the first protruding portion of the drift region disposed below the first portion is lower than a height of the second protruding portion of the drift region disposed below the second portion;
power semiconductor devices. The method of claim 1,
the drift region comprises a plurality of protruding portions extending between the plurality of lines of the first well region;
wherein the at least one trench includes a plurality of trenches formed by etching some of the plurality of protruding portions;
power semiconductor devices. 3. The method of claim 2,
a first channel region formed along the at least one trench in the semiconductor layer between the drift region and the first source region under the first portion of the gate electrode layer; and
a second channel region formed in the semiconductor layer between the drift region and the first source region under the second portion of the gate electrode layer;
power semiconductor devices. 4. The method of claim 3,
the first channel region and the second channel region have a second conductivity type such that an inversion channel is formed;
wherein the first channel region and the second channel region are part of the first well region.
power semiconductor devices. 4. The method of claim 3,
the first channel region has a second conductivity type such that an inversion channel is formed;
the second channel region has a first conductivity type such that an accumulation channel is formed;
the first channel region is a part of the first well region;
wherein the second channel region is part of a drift region;
power semiconductor devices. The method of claim 1,
The first well region is formed symmetrically on both sides with respect to the second well region,
The first source region is formed symmetrically on both sides with respect to the second source region,
power semiconductor devices. The method of claim 1,
a well contact region extending from the second well region through the second source region in the second source region and having a second conductivity type; and
and a source electrode layer connected to the second source region and the well contact region.
power semiconductor devices. The method of claim 1,
at least one groove passing through the second source region to expose the second well region;
a well contact region formed in contact with the second well region on a bottom surface of the at least one groove and having a second conductivity type; and
and a source electrode layer formed to fill the at least one groove and connected to the second source region and the well contact region.
power semiconductor devices. The method of claim 1,
a drain region having a first conductivity type in the semiconductor layer under the drift region;
wherein the drift region is formed as an epitaxial layer on the drain region;
power semiconductor devices.

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