KR102572223B1 - Power semiconductor device and method of fabricating the same - Google Patents

Abstract

A power semiconductor device according to an embodiment of the present invention includes a semiconductor layer of silicon carbide (SiC), a vertical drift region extending in a vertical direction in the semiconductor layer and having a first conductivity type, and a vertical drift region in the semiconductor layer. a well region positioned on at least one side of the vertical drift region to be in contact with the drift region and having a second conductivity type opposite to the first conductivity type, extending from a surface of the semiconductor layer into the inside of the semiconductor layer in a first direction; A plurality of recess gate electrodes buried in the vertical drift region and the well region to span the vertical drift region and the well region, positioned in the well region between the plurality of recess gate electrodes, and the first conductivity type and a plurality of insulating layer protection regions having the second conductivity type and surrounding a lower portion of each of the plurality of recess gate electrodes in the vertical drift region. there is.

Description

Power semiconductor device and method of manufacturing the same {Power semiconductor device and method of fabricating the same}

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power delivery and a manufacturing method thereof.

A power semiconductor device is a semiconductor device operating in a high voltage and high current environment. These power semiconductor devices are used in fields requiring high power switching, such as power conversion, power converters, and inverters. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), and the like. These power semiconductor devices are basically required to have withstand voltage characteristics for high voltages, and recently additional high-speed switching operations are required.

Accordingly, research on power semiconductor devices using silicon carbide (SiC) instead of conventional silicon (Si) has been conducted. Silicon carbide (SiC) is a wide-gap semiconductor material with a higher band gap than silicon, and can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high dielectric breakdown field compared to silicon, so it can operate stably even at high voltage. Therefore, silicon carbide has a higher breakdown voltage than silicon, but exhibits excellent heat dissipation and thus exhibits characteristics capable of operating at high temperatures.

In order to increase the channel density of a power semiconductor device using such silicon carbide, a trench type gate structure having a vertical channel structure has been studied. In such a trench-type gate structure, there is a problem in that an electric field is concentrated at the edge of the trench.

Embodiments of the present invention are intended to provide a silicon carbide power semiconductor device capable of increasing channel density and reducing channel resistance while alleviating electric field concentration and a manufacturing method thereof. However, these tasks are illustrative, and the scope of the present invention is not limited thereby.

A power semiconductor device according to an embodiment of the present invention includes a semiconductor layer of silicon carbide (SiC), a vertical drift region extending in a vertical direction in the semiconductor layer and having a first conductivity type, and a vertical drift region in the semiconductor layer. a well region positioned on at least one side of the vertical drift region to be in contact with the drift region and having a second conductivity type opposite to the first conductivity type, extending from a surface of the semiconductor layer into the inside of the semiconductor layer in a first direction; A plurality of recess gate electrodes buried in the vertical drift region and the well region to span the vertical drift region and the well region, positioned in the well region between the plurality of recess gate electrodes, and the first conductivity type and a plurality of insulating layer protection regions positioned at least below each of the plurality of recess gate electrodes in the vertical drift region and having the second conductivity type.

Preferably, the insulating layer protection regions may have a shape surrounding lower portions of the recess gate electrodes.

Preferably, the power semiconductor device may further include a pillar region having the second conductivity type and positioned under the well region to contact the vertical drift region and the well region in the semiconductor layer.

Preferably, in the vertical drift region, a width of a region contacting the pillar region may be greater than a width of a region contacting the well region.

Preferably, the power semiconductor device may further include a horizontal drift region connected to the vertical drift region and positioned below the pillar region to contact the pillar region.

Preferably, the well region and the source region may be symmetrically positioned on both sides of the vertical drift region with respect to the vertical drift region.

Preferably, the power semiconductor device may further include a source contact region connected in common to the source regions outside the recess gate electrodes.

Preferably, the power semiconductor device may further include a well contact region positioned within the source contact region and connected to the well region.

Preferably, the power semiconductor device may further include a source electrode layer connected to the source contact region and the well contact region.

Preferably, the plurality of recess gate electrodes are positioned to extend to a partial area of the well area while penetrating the vertical drift area in the first direction, and are spaced apart from each other in a second direction crossing the first direction. It can be.

Preferably, the plurality of insulating layer protection regions may be positioned to entirely span the vertical drift region in the first direction, and may be spaced apart from each other in the second direction.

Preferably, the power semiconductor device may further include a plate gate electrode positioned on the semiconductor layer while connecting the plurality of recess gate electrodes to each other.

Preferably, the plate gate electrode may be positioned on the semiconductor layer to cover the vertical drift region and the plurality of source regions.

Preferably, the plurality of source regions may be spaced apart from the vertical drift region by a predetermined distance.

Preferably, the plurality of source regions may be positioned to contact the vertical drift region.

A method of manufacturing a power semiconductor device according to an embodiment of the present invention includes forming a drift region by implanting impurities of a first conductivity type into a semiconductor layer of silicon carbide (SiC), and forming a drift region with the first conductivity type and the first conductivity type in the drift region. forming a vertical drift region and a well region on at least one side of the vertical drift region by implanting impurities of a second conductivity type that are opposite to each other; forming a source region by implanting impurities of the first conductivity type into the well region; , forming a plurality of trenches by etching the vertical drift region and the well region by a predetermined depth to span the vertical drift region and the well region in a first direction, wherein the vertical drift region is formed in the plurality of trenches The method may include forming a plurality of insulating layer protection regions positioned under at least each of the trenches by implanting impurities of the second conductivity type into the region, and forming a gate electrode layer to fill the trenches. .

Preferably, the method of manufacturing the power semiconductor device may further include forming a pillar region in contact with the well region by injecting impurities of the second conductivity type under the well region.

Preferably, the forming of the pillar area may include forming a horizontal drift area in which the drift area remains at a constant thickness under the pillar area.

Preferably, the forming of the plurality of trenches extends to a partial area of the well region while penetrating the vertical drift region in the first direction, and is spaced apart in a second direction crossing the first direction. can be formed.

Preferably, the forming of the plurality of insulating layer protection regions may cover the entirety of the vertical drift region in the first direction, and may be spaced apart from each other in the second direction.

Preferably, in the forming of the plurality of trenches, the plurality of trenches may be formed to a depth lower than that of the well region.

According to the power semiconductor device and method of manufacturing the same according to an embodiment of the present invention, concentration of an electric field at a corner of a gate layer can be reduced while channel resistance is reduced and channel density is increased to increase integration.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a perspective view schematically showing the structure of a power semiconductor device according to an embodiment of the present invention;
FIG. 2 is a horizontal cross-sectional view showing a structure cut along the line AA′ in FIG. 1 as an example;
3 is a vertical cross-sectional view exemplarily showing a structure cut along a BB′ cutting line in FIG. 2;
4 is a vertical cross-sectional view illustrating a structure cut along a CC′ cut line in FIG. 2 as an example;
5 is a vertical cross-sectional view exemplarily showing a structure cut along a DD′ cut line in FIG. 2;
6 is a graph showing a change in electric field according to the depth of a power semiconductor device.
7 is a perspective view schematically showing the structure of a power semiconductor device according to another embodiment of the present invention;
8 is a perspective view schematically showing the structure of a power semiconductor device according to another embodiment of the present invention;
9 is a horizontal cross-sectional view exemplarily showing a structure cut along the EE′ cut line in FIG. 8;
10 is a vertical cross-sectional view exemplarily showing a structure cut along the FF′ cut line in FIG. 8;
11 is a vertical cross-sectional view exemplarily showing a structure cut along a GG′ cut line in FIG. 8;
12 to 16 are perspective views schematically illustrating a method of manufacturing the power semiconductor device of FIG. 1 .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. It is provided to fully inform you. Also, for convenience of explanation, the size of at least some components may be exaggerated or reduced in the drawings. Like symbols in the drawings refer to like elements.

Unless defined otherwise, all terms used herein are used with the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for illustrative purposes and are therefore provided to illustrate the general structures of the present invention.

Like reference numerals denote like elements. It will be understood that when one element, such as a layer, region, or substrate, is referred to as being on another element, it may be directly on top of or intervening elements may also exist. On the other hand, when referring to a component being “directly on” another component, it is understood that there are no intervening components present.

FIG. 1 is a perspective view schematically showing a structure of a power semiconductor device according to an exemplary embodiment of the present invention, and FIG. 2 is a horizontal cross-sectional view exemplarily showing a structure taken along a line A-A′ in FIG. 1 . And, FIGS. 3 to 5 are vertical cross-sectional views showing structures cut along the lines B-B', C-C', and D-D' in FIG. 2, respectively.

1 to 5, the power semiconductor device 100 may include a semiconductor layer 105, a gate insulating layer 118, a gate electrode layer 120, an interlayer insulating layer 130, and a source electrode layer 140. can For example, the power semiconductor device 100 may have a power MOSFET structure.

The semiconductor layer 105 may include one or a plurality of semiconductor material layers. For example, the semiconductor layer 105 may include one or multiple epitaxial layers. Alternatively, the semiconductor layer 105 may include one or multiple epitaxial layers on a semiconductor substrate. For example, the semiconductor layer 105 may include silicon carbide (SiC). Alternatively, the semiconductor layer 105 may include at least one epitaxial layer of silicon carbide.

Silicon carbide (SiC) has a wider band gap than silicon, so it can maintain stability even at high temperatures compared to silicon. Furthermore, silicon carbide has a very high dielectric breakdown field compared to silicon, so it can operate stably even at high voltage. Therefore, the power semiconductor device 100 using silicon carbide as the semiconductor layer 105 has excellent heat dissipation characteristics while having a higher breakdown voltage than when silicon is used, and can exhibit stable operating characteristics even at high temperatures.

The semiconductor layer 105 may include a drift region 107 . The drift region 107 may be formed of a first conductivity type (N type), and may be formed by implanting impurities of the first conductivity type into a portion of the semiconductor layer 105 . For example, the drift region 107 may be formed by implanting impurities of the first conductivity type into an epitaxial layer of silicon carbide.

The drift region 107 may provide a current movement path during operation of the power semiconductor device 100 . The drift region 107 is formed to extend in a horizontal direction from the lower portion of the semiconductor layer 105 to provide a horizontal movement path for current, and a horizontal portion 107a within the semiconductor layer 105. It may include a vertical portion 107b connected to the portion 107a and extending in a vertical direction (Z direction) to provide a vertical movement path for current. For example, in the drift region 107, the horizontal portion 107a may correspond to an area located below the pillar region 111, and the vertical portion 107b may correspond to the horizontal portion 107a and the well region 110. ) and an area positioned in contact with the side surface of the pillar area 111 may correspond.

In this case, the vertical portion 107b may include regions divided into a plurality of regions by the recess gate electrodes 120R. In the power semiconductor device of this embodiment, each of the divided vertical portions 107b may be used as a vertical movement path of current.

The well region 110 may be formed to contact the drift region 107 in the semiconductor layer 105 and may include impurities of the second conductivity type. For example, the well region 110 may be formed by implanting impurities of a second conductivity type (P type) opposite to the first conductivity type into an epitaxial layer of silicon carbide.

The well region 110 may be formed to surround at least a portion of the drift region 107 . For example, the well region 110 may be formed to surround an upper portion of the vertical portion 107b in the drift region 107 . In FIG. 1, the state in which the well region 110 is divided into two regions separated by a predetermined distance in the Y direction by the vertical portion 107b is illustrated as an example, but other various modifications may be made. For example, the well region 110 may be formed to entirely surround side surfaces of the vertical portion 107b in an all-around shape.

A pillar region 111 may be formed in the semiconductor layer 105 under the well region 110 to be connected to the well region 110 . The pillar region 111 may be formed to contact the drift region 107 to form a super junction with the drift region 107 . For example, the top surface of the pillar area 111 is in contact with the well area 110, and the side surface and bottom surface of the pillar area 111 are in contact with the vertical portion 107b and the horizontal portion 107a of the drift area 107, respectively. ) can be placed below.

The pillar region 111 may be formed in the semiconductor layer 105 to have a conductivity type opposite to that of the drift region 107 so as to form a super junction with the drift region 107 . For example, the pillar region 111 may include impurities of the same second conductivity type as the well region 110 while being opposite to the drift region 107 . For example, a doping concentration of impurities of the second conductivity type in the pillar region 111 may be equal to or less than a doping concentration of impurities of the second conductivity type in the well region 110 .

In some embodiments, the pillar region 111 may be formed to have a width narrower than that of the well region 110 in one direction (Y direction). For example, when the well region 110 and the pillar region 111 are spaced apart from each other on both sides of the vertical portion 107b, the distance between the spaced pillar regions 111 (distance in the Y direction) is It may be larger than the distance between the well regions 110 (distance in the Y direction). To this end, in the vertical portion 107b of the drift region 107, the Y-direction length (width) of the portion in contact with the well region 110 is smaller than the Y-direction length of the portion in contact with the pillar region 111. can

In some embodiments, a plurality of pillar regions 111 and drift regions 107 may be alternately arranged so that side surfaces thereof contact each other to form a super junction structure. Furthermore, a plurality of pillar regions 111 and drift regions 107 may be alternately disposed under one well region 110 .

Source regions 112 may be formed in the well region 110 and have a first conductivity type. For example, the source regions 112 may be formed between the recess gate electrodes 120R in the well region 110, and first conductivity type impurities are implanted into some regions of the well region 110. can be formed by The source regions 112 may be formed by implanting impurities of the first conductivity type at a higher concentration than the drift region 107 .

The channel regions 110a may be formed between the vertical portion 107b of the drift region 107 and the source regions 112 . The channel regions 110a may include impurities of the second conductivity type. Since the channel regions 110a include impurities of a second conductivity type opposite to those of the source regions 112 and the drift region 107, a diode junction is formed between the source regions 112 and the drift region 107. can form Accordingly, the channel regions 110a do not allow charge to move when the power semiconductor device 100 is not operating, thereby electrically isolating the vertical portion 107b of the drift region 107 and the source regions 112. can make it On the other hand, in the channel regions 110a, when an operating voltage is applied to the gate electrode layer 120, an inversion channel is formed therein to allow charge to move, thereby allowing the vertical portion of the drift region 107 ( 107b) and the source regions 112 may be electrically connected.

Although the channel regions 110a are shown separately from the well region 110 in FIG. 1 , the channel regions 110a may be part of the well region 110 . For example, the channel regions 110a may correspond to regions between the source region 112 and the vertical portion 107b of the drift region 107 in the well region 110 . The doping concentration of impurities of the second conductivity type of the channel regions 110a may be the same as that of the well region 110 or may be different for adjusting the threshold voltage.

In some embodiments, the well region 110, the pillar region 111, the channel regions 110a, and the source regions 112 are symmetrical in the Y direction with respect to the vertical portion 107b of the drift region 107. can be formed For example, the well region 110, the pillar region 111, the channel regions 110a, and the source regions 112 are each located on both sides of the vertical portion 107b of the drift region 107 in the Y direction. part and a second part. Each of the well region 110, the pillar region 111, and the source region 112 may be separated from each other by a vertical portion 107b of the drift region 107, or a vertical portion 107b of the drift region 107. ) may be connected to each other so as to surround.

Additionally, the drain region 102 may be formed in the semiconductor layer 105 under the drift region 107 and may include impurities of the first conductivity type. For example, the drain region 102 may include impurities of the first conductivity type injected at a higher concentration than the drift region 107 .

In some embodiments, the drain region 102 may be provided as a substrate of silicon carbide having a first conductivity type. In this case, the drain region 102 may be formed as a part of the semiconductor layer 105 or may be formed as a substrate separate from the semiconductor layer 105 .

At least one trench 116 may be formed by etching the semiconductor layer 105 by a predetermined depth from a surface (upper surface) of the semiconductor layer 105 into the inside of the semiconductor layer 105 . The at least one trench 116 may include a plurality of trenches formed to be spaced apart at regular intervals along the X direction. The trenches 116 may extend in parallel in the Y direction to pass through the vertical portion 107b of the drift region 107 and the channel region 110a in the semiconductor layer 105 .

The channel regions 110a may be located between the trenches 116, and regions in contact with the well region 110 in the vertical portion 107b of the drift region 107 are a plurality of regions by the trenches 116. can be divided into In one embodiment, between the trenches 116, the vertical portions 107b of the drift region 107 may be formed in the form of barrier ribs, respectively on both sides (both sides in the Y direction) of the vertical portions 107b in the form of barrier ribs. A channel region 110a may be located. Further, source regions 112 may be positioned on one side opposite to the channel regions 110a in the Y direction.

The gate insulating layer 118 may be formed on at least inner surfaces of the trenches 116 . For example, the gate insulating layer 118 may be formed on inner surfaces of the trenches 116 and on the semiconductor layer 105 outside the trenches 116 . The thickness of the gate insulating layer 118 may be uniform, or a portion formed on the bottom surface of the trench 116 may be thicker than a portion formed on the side surface in order to lower the electric field of the bottom portion of the trench 116 .

The gate insulating layer 118 may include an insulating material such as silicon oxide, silicon carbide oxide, silicon nitride, hafnium oxide, zirconium oxide, and aluminum oxide, or may include a stacked structure thereof.

The gate electrode layer 120 may be formed on the gate insulating layer 118 to fill the trench 116 . In addition, the gate electrode layer 120 may be formed on the gate insulating layer 118 over the semiconductor layer 105 so as to cover at least the channel region 110a. For example, the gate electrode layer 120 may include a plurality of recess gate electrodes 120R formed to be buried in the trench 116 while spaced at regular intervals along the X direction. In addition, the gate electrode layer 120 may include a plate gate electrode 120P formed in a flat plate shape on the semiconductor layer 105 to cover the channel regions 110a while connecting the plurality of recess gate electrodes 120R. can

In the power semiconductor device 100 according to the present embodiment, a source region 112 and a channel region 110a are formed along the Y direction between the plurality of recess gate electrodes 120R under the plate gate electrode 120P. And structures in which the vertical portion 107b is connected may be formed. For example, between the plurality of recess gate electrodes 120R, the channel region 110a and the source region 112 may be connected to both side walls of the vertical portion 107b in the Y direction. The vertical portion 107b of the drift region 107 connected in this way, the channel region 110a, and the source region 112 may become a current movement path when the power semiconductor device 100 operates.

As described above, in the power semiconductor device 100 according to the present embodiment, the vertical portion 107b of the drift region 107, the channel region 110a, and the source region 112 are formed between the plurality of recess gate electrodes 120R, respectively. By including a multi-lateral channel structure in which connected current movement paths are formed, more charges can move simultaneously. In addition, in each movement path, the gate electrode layer 120 is formed to surround three surfaces (both sides and top in the X direction) of the vertical portion 107b, the channel region 110a, and the source region 112, so that more It allows charges to move. The gate electrode layer 120 may include a conductive material such as polysilicon, metal, metal nitride, metal silicide, or the like, or may include a stacked structure thereof.

The well region 110 may be formed deeper than the recess gate electrodes 120R to surround side surfaces and a bottom surface of the recess gate electrodes 120R.

The interlayer insulating layer 130 may be formed on the gate electrode layer 120 . The interlayer insulating layer 130 may include an insulating material for electrical insulation between the gate electrode layer 120 and the source electrode layer 140, for example, an oxide layer, a nitride layer, or a stacked structure thereof.

The source electrode layer 140 may be formed on the interlayer insulating layer 130 and may be electrically connected to the source regions 112 . The source electrode layer 140 may include a conductive material such as metal.

In the above-described embodiment, the first conductivity type and the second conductivity type are N-type and P-type, respectively, but the opposite may also be true. For example, when the power semiconductor device 100 is an N-type MOSFET, the drift region 107 is an N- region, the source region 112 and the drain region 102 are N+ regions, the well region 110, The pillar region 111 and the channel region 110a may be P-regions.

During operation of the power semiconductor device 100, current flows in a vertical direction from the drain region 102 along the vertical portions 107b of the drift region 107, and then through the channel region 110a to the source region 112. can flow to

In the power semiconductor device 100 described above, the recess gate electrodes 120R in the trench 116 may be densely arranged in parallel in a stripe type or a line type, and the channel regions 110a may be recessed Channel density may be increased by being disposed between the gate electrodes 120R.

In addition, in the power semiconductor device 100 according to the present embodiment, the well region 110 is formed to surround the lower portion of the trench 116, so that the electric field is generated at the lower corner portion of the gate electrode layer 120. Concentration can be alleviated. Furthermore, the power semiconductor device 100 according to the present embodiment includes insulating layer protection regions surrounding the lower portion of each of the recess gate electrodes 120R in the vertical portion 107b of the drift region 107. (115) may be included. The insulating layer protection regions 115 may include impurities of the second conductivity type.

When an operating voltage is applied to the gate electrode layer 120, an electric field may be concentrated on the lower corner portion of the recess gate electrodes 120R, and when the electric field is concentrated, the gate insulating layer 118 in the corresponding region is A dielectric breakdown of the gate insulating layer 118 may occur due to severe stress. Therefore, in the present embodiment, in the recess gate electrodes 120R, the portions formed in the well region 110 have their lower regions surrounded by the P-type well region 110, and in addition, the recess gate electrode The portions formed in the vertical portion 107b of the drift region 107 in fields 120R are corner portions of the gate insulating layer 118 by making their lower regions surrounded by P-type insulating layer protection regions 115. It is possible to prevent dielectric breakdown of the gate insulating layer 118 due to concentration of an electric field in the field.

In the power semiconductor device 100 according to the present embodiment, since current flows through the vertical portions 107b of the drift region 107, when the insulating layer protection region 115 is formed, the current movement path is narrowed and resistance is reduced. (JFET resistance) may increase. However, in the power semiconductor device 100 according to the present embodiment, the JFET resistance can be reduced by using the drift region 107 and the pillar region 111 forming a super junction. For example, in this embodiment, as shown in FIG. 6 described later, the JFET resistance may be reduced by adjusting the amount of charge in the pillar region 111 and the amount of charge in the drift region 107 .

6 is a graph showing a change in electric field according to the depth of a power semiconductor device.

Referring to FIG. 6 , when the charge amount Qp of the pillar region 111 is greater than the charge amount Qn of the drift region 107, the maximum electric field during operation of the power semiconductor device 100 is in the pillar region 111. The breakdown voltage can be increased by generating the drift region 107 on the same line as the bottom surface. In FIG. 6 , the gradient of the electric field strength between the A position and the B position can be controlled by adjusting the charge quantity Qp of the pillar region 111 .

For example, by making the doping concentration of impurities of the second conductivity type of the pillar region 111 higher than the doping concentration of impurities of the first conductivity type of the drift region 107, the amount of charge Qp of the pillar region 111 is reduced. By setting the charge amount Qn of the drift region 107 to be greater than that of the drift region 107 , the withstand voltage characteristic of the power semiconductor device 100 can be improved and the JFET resistance can be reduced.

7 is a perspective view schematically showing the structure of a power semiconductor device according to another embodiment of the present invention.

In the power semiconductor device 100a according to the present embodiment, a partial structure of the power semiconductor device 100 of FIGS. 1 to 5 is modified, and a description of the redundant structure is omitted.

Referring to FIG. 7 , in the power semiconductor device 100a of this embodiment, source regions 112' may be formed to contact vertical portions 107b of the drift region 107. The source regions 112' may include first conductivity type impurities in the same manner as the source regions 112.

In the semiconductor layer 105 structure of silicon carbide, a potential barrier is formed in a current movement path due to negative charges generated when carbon clusters are formed on the gate insulating layer 118, thereby blocking current movement. Accordingly, as in the present embodiment, even if the source regions 112' are formed to contact the vertical portions 107b of the drift region 107, current flows only when an operating voltage is applied to the gate electrode layer 120. An accumulation channel may be formed that allows In this case, the operating voltage may be significantly lower than the operating voltage for forming the inversion channel in the channel region 110a in FIG. 1 .

8 is a schematic perspective view showing the structure of a power semiconductor device according to another embodiment of the present invention, and FIG. 9 is a horizontal cross-sectional view exemplarily showing the structure cut along the line E-E′ in FIG. 8 . And, FIGS. 10 and 11 are vertical cross-sectional views showing structures cut along F-F' and G-G' cut lines in FIG. 9, respectively.

The power semiconductor device 100b according to the present embodiment uses or partially modifies the power semiconductor device 100 of FIG. 1 , and thus redundant descriptions are omitted.

Referring to FIGS. 8 to 11 , the power semiconductor device 100b may include at least one gate region GR1 and GR2 and a contact region CR.

The gate regions GR1 and GR2 are regions including the gate electrode layer 120 and may include the structure of FIG. 1 or FIG. 7 described above. FIG. 8 illustrates an embodiment in which the gate regions GR1 and GR2 include the structure of FIG. 1 . Therefore, a detailed description of the gate regions GR1 and GR2 will be omitted.

The contact region CR is a region for connecting the source regions 112 of the gate regions GR1 and GR2 to the source electrode layer 140, and may be located on one side of the gate regions SR1 and SR2. The contact region CR may include a drift region 107a, a well region 110, a pillar region 111, a source contact region 112a, a well contact region 114, and a source electrode layer 140.

The drift region 107a, the well region 110, and the pillar region 111 of the contact region CR may be the drift region 107a, the well region 110, and the pillar region 111 of the gate regions GR1 and GR2, respectively. ) and may be integrally formed. That is, for convenience of explanation, the gate regions GR1 and GR2 and the drift region 107a, the well region 110, and the pillar region 111 of the contact region CR are distinguished, but they are each integrally formed. can be formed into regions.

The source contact region 112a is a region for connecting the source regions 112 to the source electrode layer 140 . The source contact region 112a may be positioned on one side of the gate regions GR1 and GR2 in the Y direction and may be integrally formed with the source regions 112 . For example, the source regions 112 may extend to the contact region CR, and the extended source regions 112 may be integrally connected to the outside of the recess gate electrodes 120R in common. In this case, a region in the contact region CR among the integrally commonly connected regions may be the source contact region 112a. Accordingly, the source contact region 112a may be part of the source regions 112, and the source regions 112 may be electrically connected to the source electrode layer 140 through the source contact region 112a.

A well contact region 114 may be formed in the source contact region 112a. For example, the well contact region 114 may extend from the well region 110 to pass through the source contact region 112 . One or more well contact regions 114 may be formed in the source contact region 112a.

The well contact region 114 may include impurities of the second conductivity type. The well contact region 114 may be implanted with impurities of the second conductivity type at a higher concentration than the well region 110 in order to lower contact resistance when connected to the source electrode layer 140 . For example, the well contact region 114 may be a P+ region.

The source electrode layer 140 of the contact region CR may be integrally connected to the source electrode layer 140 of the gate regions GR1 and GR2 . The source electrode layer 140 may be connected to the source contact region 112a and the well contact region 114 in common.

The plate gate electrode 120P of the gate regions GR1 and GR2 may be formed to extend to a boundary region between the gate regions GR1 and GR2 and the contact region CR in the Y direction. For example, as shown in FIG. 10 , the plate gate electrode 120P may extend longer in the Y direction than the recess gate electrodes 120R and may be formed closer to the contact region CR. The recess gate electrodes 120R may be formed to extend to a partial area of the well region 110 while penetrating the vertical portion 107b of the drift region 107 in the Y direction.

The source regions 112 formed between the recess gate electrodes 120R may be connected in common to the source contact region 112a. Insulation layer protection regions 115 surrounding lower portions of each of the recess gate electrodes 120R may be formed in the vertical portion 107b of the drift region 107 .

8 to 11 show that the source contact region 112a and the well contact region 114 are formed on only one side of the vertical portions 107b of the drift region 107, but the source region 112 and the well region 110 ) is divided into a plurality of regions, the source contact region 112a and the well contact region 114 may be formed in each region. For example, when the source regions 112 and the well regions 110 on both sides of the vertical portion 107b are electrically connected to each other, as shown in FIG. 8 , the contact region CR is the vertical portion. It can be formed only on one side of (107b). On the other hand, when the source regions 112 and the well regions 110 on both sides of the vertical portion 107b are electrically separated from each other, the contact region CR is formed on both sides of the vertical portion 107b. can be formed in each.

The power semiconductor device 100b in FIG. 8 includes two gate regions GR1 and GR2 and one contact region CR formed between the gate regions GR1 and GR2, thereby forming one contact region CR. The two gate regions GR1 and GR2 are connected in common. However, the power semiconductor device 100b may include one gate region GR1 or GR2 and one contact region CR formed on one side thereof. In this case, the contact region CR may be formed on one side of the gate region GR1 or GR2 in the Y direction or the X direction.

Also, the power semiconductor device 100b may include a plurality of gate regions and a plurality of contact regions positioned between the gate regions. For example, the power semiconductor device 100b may include three or more gate regions spaced apart from each other along the Y direction and a plurality of contact regions formed one by one between adjacent gate regions. In this case, structures of adjacent gate regions and a contact region formed therebetween may be the same as those of FIGS. 8 to 11 described above.

12 to 16 are perspective views schematically illustrating a method of manufacturing the power semiconductor device of FIG. 1 .

Referring to FIG. 12 , a drift region 107' having a first conductivity type may be formed in the semiconductor layer 105 of silicon carbide (SiC). For example, the drift region 107' may be formed over the drain region 102 having the first conductivity type. In some embodiments, the drain region 102 is provided with a substrate of a first conductivity type, and the drift region 107' may be formed of one or more epitaxial layers on such a substrate. The first conductivity type may be N type.

Next, referring to FIG. 13 , the well region 110 and the pillar region 111 may be formed by implanting impurities of the second conductivity type into the drift region 107'. For example, after forming a mask pattern (photoresist pattern) to open a region where the well region 110 is to be formed on the drift region 107', impurities of the second conductivity type are added to the drift region 107' by a predetermined depth. By implanting them, the vertical portion 107b and the well region 110 may be formed.

The well region 110 may be formed on at least one side of the vertical portion 107b. For example, the well region 110 may be formed on both sides of the vertical portion 107b in the Y direction or may be formed to surround the vertical portion 107b.

Next, the pillar region 111 may be formed by implanting impurities of the second conductivity type into the drift region 107' below the well region 110 . For example, after removing the mask pattern used to form the well region 110 and forming the mask pattern defining the pillar region 111 over the drift region 107', a second conductive layer is formed below the well region 110. The pillar region 111 may be formed by implanting impurities of this type. In this case, the pillar region 111 may be formed such that a drift region 107a having a certain thickness exists below it. As such, a super junction may be formed by forming the second conductive type pillar region 111 so that the lower surface and the side surface are in contact with the horizontal portion 107a and the vertical portion 107b of the drift region 107 , respectively. The top surface of the pillar region 111 may be formed to contact the well region 110 . The second conductivity type may be a P type opposite to the first conductivity type.

In the above-described embodiment, the case where the well region 110 is formed first and the pillar region 111 is formed thereunder has been described. may be

Subsequently, a source region 112 ″ having a first conductivity type may be formed in the well region 110 . For example, the source region 112″ may be formed by implanting impurities of the first conductivity type into the well region 110 . The source region 112 ″ may be substantially formed at a predetermined depth from the surface of the semiconductor layer 105 and may be formed in a bar shape elongated in the X direction. The source region 112” may be spaced apart from the vertical portion 107b by a predetermined distance. In this case, a region between the source region 112″ and the vertical portion 107b in the well region 110 may become the channel region 110a′. Alternatively, as shown in FIG. 7 , the source region 112” may be formed to contact the vertical portion 107b.

Optionally, a heat treatment step for activating or diffusing the impurities may be performed after implanting the impurities.

Next, referring to FIG. 14 , after a mask pattern defining the trench 116 region is formed on the semiconductor layer 105, the semiconductor layer 105 is etched by a certain depth using the mask pattern as an etching mask at regular intervals in the X direction. Trenches 116 spaced apart from each other may be formed. The trenches 116 may be formed to extend in the Y direction to a length capable of crossing the vertical portion 107b and the channel region 110a' and the source region 112" on both sides of the vertical portion 107b. there is.

A plurality of channel regions 110a and a plurality of source regions 112 may be formed by dividing the channel region 110a' and the source region 112" into a plurality of regions by the trenches 116. there is. In addition, the vertical portion 107b may also be divided into a plurality of regions by the trenches 116 . Each partition-shaped vertical portion 107b divided by the trenches 116 and the channel region 110a and the source region 112 connected to the vertical portion 107b may serve as a current movement path. That is, the power semiconductor device according to the present embodiment includes a plurality of current movement paths connected in parallel, so that more current can flow at one time.

The trenches 116 may be formed to be shallower than the well region 110 such that lower portions of the trenches 116 are covered by the well region 110 .

Referring next to FIG. 15, by implanting second conductivity type (P-type) impurities into the region where the vertical portion 107b of the drift region 107 is located in the trenches 116, as shown in FIG. 4, the trenches Insulating layer protection regions 115 surrounding a lower portion of 116 may be formed in the vertical portion 107b. For example, after forming a mask pattern on the semiconductor layer 105 such that the vertical portion 107b of the drift region 107 is exposed in the trenches 116 , P-type impurities may be implanted into the exposed region. In this case, the P-type impurity region 115 may be formed in the vertical portion 107b to surround the lower region of the trenches 116 by adjusting the ion implantation angle. The insulating layer protection regions 115 may be formed to entirely span the vertical portion 107b in the Y direction, and may be spaced apart from each other in the X direction. If the lower regions of some of the trenches 116 are not rounded, the P-type impurity regions 115 do not completely cover the lower regions of the trenches 116 and are positioned below the trenches 116 . It could be.

Referring next to FIG. 16 , a gate insulating layer 118 may be formed on bottom and side surfaces of the trenches 116 . The gate insulating layer 118 may also be formed on the semiconductor layer 105 outside the trenches 116 . The gate insulating layer 118 may be formed of an oxide obtained by oxidizing the semiconductor layer 105 or by depositing an insulating material such as oxide or nitride on the semiconductor layer 105 .

Subsequently, gate electrode layers 120R and 120P may be formed on the gate insulating layer 118 to fill the trenches 116 . For example, the gate electrode layers 120R and 120P cover the channel regions 110a while connecting the recess gate electrodes 120R formed to be buried in the trenches 116 and the recess gate electrodes 120R. A plate gate electrode 120P formed in a flat shape on the semiconductor layer 105 may be included. Accordingly, the plate gate electrode 120P and the recess gate electrode 120R have three surfaces of the vertical portions 107b of the drift region, the source regions 112, and the channel regions 110a in a “∩” shape. It can be a structure that surrounds (top surface and both sides). The gate electrode layer 120 may be formed by implanting impurities into polysilicon or may include a conductive metal or metal silicide.

The lower portion of the recess gate electrodes 120R is formed to be surrounded by the well region 110 of the second conductivity type and the insulating layer protection region 115, thereby forming a corner portion of the gate insulating layer 118. It is possible to prevent dielectric breakdown of the gate insulating layer 118 due to concentration of the electric field.

Next, an interlayer insulating layer 130 may be formed on the plate gate electrode 120P, and a source electrode layer 140 may be formed on the interlayer insulating layer 130 . For example, the source electrode layer 140 may include a conductive layer, such as a metal layer.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100, 100a, 100b: power semiconductor device
102: drain area
105: semiconductor layer
107: drift area
110: well area
111: pillar area
112: source area
115: insulating layer protection area
118: gate insulating layer
120: gate electrode layer
130: interlayer insulating layer
140: source electrode layer

Claims (20)

a semiconductor layer of silicon carbide (SiC);
a vertical drift region extending in a vertical direction within the semiconductor layer and having a first conductivity type;
a well region located on at least one side of the vertical drift region in the semiconductor layer to be in contact with the vertical drift region and having a second conductivity type opposite to the first conductivity type;
a plurality of recess gate electrodes extending from a surface of the semiconductor layer into the inside of the semiconductor layer and buried in the well region;
a plurality of source regions positioned in the well region between the plurality of recess gate electrodes and having the first conductivity type; and
a plurality of insulating layer protection regions positioned at least below each of the plurality of recess gate electrodes in the vertical drift region and having the second conductivity type;
The power semiconductor device of claim 1 , wherein the recess gate electrodes, the well region, and the vertical drift region overlap each other in a horizontal direction. The method according to claim 1, wherein the insulating layer protection regions
The power semiconductor device, characterized in that surrounding the lower portion (lower portion) of the recess gate electrodes. The method of claim 1,
The power semiconductor device of claim 1 , further comprising a pillar region having the second conductivity type and located under the well region to contact the vertical drift region and the well region in the semiconductor layer. The method according to claim 3, wherein the vertical drift region
The power semiconductor device of claim 1 , wherein a width of a region in contact with the pillar region is greater than a width of a region in contact with the well region. The method of claim 3,
The power semiconductor device further comprises a horizontal drift region connected to the vertical drift region and positioned below the pillar region to contact the pillar region. The method according to claim 1, wherein the well region and the source region
The power semiconductor device, characterized in that located on both sides of the vertical drift region symmetrically relative to the vertical drift region. The method of claim 1,
The power semiconductor device of claim 1 , further comprising a source contact region connected in common to the source regions outside the recess gate electrodes. The method of claim 7,
The power semiconductor device of claim 1, further comprising a well contact region formed in the source contact region and connected to the well region. The method of claim 8,
The power semiconductor device further comprises a source electrode layer connected to the source contact region and the well contact region. The method according to claim 1, wherein the plurality of recess gate electrodes
The power semiconductor device characterized in that it is positioned to extend to a partial area of the well region while penetrating the vertical drift region in a first direction, and is spaced apart from each other in a second direction crossing the first direction. The method according to claim 10, wherein the plurality of insulating layer protection regions
The power semiconductor device, characterized in that positioned to entirely span the vertical drift region in the first direction, and spaced apart from each other in the second direction. The method of claim 1,
The power semiconductor device further comprises a plate gate electrode positioned on the semiconductor layer while connecting the plurality of recess gate electrodes to each other. 13. The method of claim 12, wherein the plate gate electrode
The power semiconductor device, characterized in that located on the semiconductor layer to cover the vertical drift region and the plurality of source regions. The method according to claim 1, wherein the plurality of source regions
A power semiconductor device, characterized in that located at a predetermined distance from the vertical drift region. The method according to claim 1, wherein the plurality of source regions
A power semiconductor device, characterized in that located in contact with the vertical drift region. forming a drift region by implanting impurities of a first conductivity type into a semiconductor layer of silicon carbide (SiC);
forming a vertical drift region and a well region on at least one side of the vertical drift region by injecting impurities of a second conductivity type opposite to the first conductivity type into the drift region;
forming a source region by injecting impurities of the first conductivity type into the well region;
forming a plurality of trenches by etching the vertical drift region and the well region by a predetermined depth;
forming a plurality of insulating layer protection regions located at least below each of the trenches by injecting impurities of the second conductivity type into the region where the vertical drift region is formed in the plurality of trenches; and
Forming a gate electrode layer to fill the trenches;
The method of manufacturing a power semiconductor device in which the gate electrode layer, the well region, and the vertical drift region are positioned to overlap each other in a horizontal direction. The method of claim 16
and forming a pillar region in contact with the well region by injecting impurities of the second conductivity type under the well region. 17. The method of claim 16, wherein forming the plurality of trenches
A method of manufacturing a power semiconductor device, characterized in that trenches are formed extending to a partial area of the well region while penetrating the vertical drift region in a first direction, and spaced apart in a second direction crossing the first direction. The method according to claim 18, wherein forming the plurality of insulating layer protection regions
The method of manufacturing a power semiconductor device, characterized in that formed across the entire vertical drift region in the first direction, and spaced apart from each other in the second direction. 17. The method of claim 16, wherein forming the plurality of trenches
The method of manufacturing a power semiconductor device, characterized in that the plurality of trenches are formed to a depth lower than the well region.