KR20220154868A - Three dimensional flash memory including connection unit and manufacturing method thereof - Google Patents

Abstract

Disclosed are a three-dimensional flash memory comprising a connection unit, and a manufacturing method thereof. According to one embodiment, the three-dimensional flash memory comprises: stack structures stacked in a vertical direction and including interlayer insulating films and gate electrodes extending in a horizontal direction and alternately stacked in the vertical direction, and vertical channel structures extending in the vertical direction passing through the interlayer insulating films and the gate electrodes, wherein each of the vertical channel structures includes a data storage pattern extending in the vertical direction and a vertical channel pattern covering an inner wall of the data storage pattern and extending in the vertical direction; and a buffer layer including connecting units disposed between the stack structures and connecting the vertical channel patterns of each of the stack structures to each other. Each of the connecting units has a curved corner while protruding in the horizontal direction more than each of the vertical channel patterns. The three-dimensional flash memory according to embodiments may achieve an effect of solving a problem of deterioration of channel current characteristics due to vertical channel pattern misalignment in a stack stacking process.

Description

Three-dimensional flash memory including a connection unit and a method for manufacturing the same

The following embodiments relate to a 3D flash memory, and more specifically, a technology for a 3D flash memory manufactured through a stack stacking process.

A flash memory device is an electrically erasable programmable read only memory (EEPROM) by electrically controlling input and output of data by Fowler-Nordheimtunneling or hot electron injection. , can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, and the like.

In such a flash memory device, a three-dimensional structure in which memory cell transistors are arranged in a vertical direction to form a cell string has been proposed to increase the degree of integration in order to meet the excellent performance and low price demanded by consumers.

The 3D flash memory has recently become more sophisticated and integrated, and as a manufacturing process, a process in which a plurality of stack structures are stacked in a vertical direction is used to realize a more sophisticated and integrated structure.

However, in the case of a stack stacking process, the vertical channel patterns VCP of each of the stack structures may be misaligned, resulting in deterioration of channel current characteristics.

Accordingly, the embodiments below seek to propose techniques that solve the described problems.

In one embodiment, in order to solve the problem of deterioration of channel current characteristics due to misalignment of vertical channel patterns in a stack stacking process, a three-dimensional flash memory having a structure including connecting parts connecting vertical channel patterns of each of stack structures, A manufacturing method and an electronic system including the same are proposed.

In particular, one embodiment proposes a 2D flash memory having a structure in which each of the connection parts protrudes more horizontally than each of the vertical channel patterns and has a curved corner shape, a manufacturing method thereof, and an electronic system including the same.

However, the technical problems to be solved by the present invention are not limited to the above problems, and can be variously expanded without departing from the technical spirit and scope of the present invention.

According to an exemplary embodiment, the 3D flash memory includes interlayer insulating films and gate electrodes that extend in a horizontal direction and are alternately stacked in a vertical direction, and extend in the vertical direction while penetrating the interlayer insulating films and the gate electrodes. Formed vertical channel structures, each of which includes a data storage pattern extending in the vertical direction and a vertical channel pattern extending in the vertical direction covering an inner wall of the data storage pattern stack structures each including: the stack structures are stacked in the vertical direction; and a buffer layer disposed between the stack structures and including connection parts connecting vertical channel patterns of each of the stack structures to each other. Each of the connection parts may have a curved corner while protruding in the horizontal direction more than each of the vertical channel patterns.

According to one aspect, each of the connection parts may be formed on a sidewall on which wet etching is performed for a portion of the buffer layer in the horizontal direction, and may have a curved corner.

According to another aspect, the buffer layer may be formed of a material capable of performing the wet etching.

According to another aspect, the material forming the buffer layer may include at least one of silicon oxide and metal oxide.

According to another aspect, in each of the connection parts, as the buffer layer is formed by stacking a plurality of layers having different etching ratios in the vertical direction, etching is performed on a portion of the buffer layer in the horizontal direction. It may be formed on the sidewall and characterized in that the corner has a curved shape.

According to another aspect, a layer located at the center in the vertical direction among the plurality of layers may have a higher etching rate than layers located at edges in the vertical direction among the plurality of layers.

According to another aspect, when each of the vertical channel patterns includes a back gate extending in the vertical direction while at least partially surrounded by each of the vertical channel patterns, each of the connection parts may include the back gate. The gate may include an inner hole extending in the vertical direction.

According to another aspect, each of the connection parts may include a part formed of the same material as the vertical channel patterns.

According to another aspect, each of the connection parts may be formed at a size and position to accommodate each of the vertical channel patterns on a plane.

According to an embodiment, a method of manufacturing a 3D flash memory includes interlayer insulating films and gate electrodes that extend in a horizontal direction and are alternately stacked in a vertical direction, and the interlayer insulating films and the gate electrodes are formed in the vertical direction. preparing a lower stack structure including channel holes therethrough; forming a buffer layer on top of the lower stack structure; The interlayer insulating films and the gate electrodes, which extend in the horizontal direction and are alternately stacked in the vertical direction, on the upper part of the lower stack structure on which the buffer layer is formed, and the interlayer insulating films and the gate electrodes are formed in the vertical direction. forming an upper stack structure including channel holes passing through; forming channel connection holes penetrating the buffer layer in the vertical direction based on positions of the channel holes; performing wet etching on a portion of the buffer layer in the horizontal direction through the channel holes and the channel connection holes so that a remaining portion has an undercut shape; and forming vertical channel structures each including a data storage pattern and a vertical channel pattern extending in the vertical direction on inner walls of the channel holes and sidewalls where the buffer layer has been etched, wherein the vertical channel structures are formed. In the step of extending in the vertical direction, the vertical channel patterns extending from the upper stack structure and the vertical channel patterns extending from the lower stack structure are connected to each other and protrude in the horizontal direction more than each of the vertical channel patterns. It may be characterized in that it comprises the step of forming connection parts having a curved corner shape.

According to one aspect, the step of forming the buffer layer may be characterized in that the step of forming the buffer layer with a material capable of performing the wet etching.

According to an embodiment, a method of manufacturing a three-dimensional flash memory, interlayer insulating films and gate electrodes extending in a horizontal direction and alternately stacked in a vertical direction, and penetrating the interlayer insulating films and the gate electrodes in the vertical direction. preparing a lower stack structure including channel holes to forming a buffer layer on top of the lower stack structure in which a plurality of layers having different etching ratios are stacked in the vertical direction; The interlayer insulating films and the gate electrodes, which extend in the horizontal direction and are alternately stacked in the vertical direction, on the upper part of the lower stack structure on which the buffer layer is formed, and the interlayer insulating films and the gate electrodes are formed in the vertical direction. forming an upper stack structure including channel holes passing through; forming channel connection holes penetrating the buffer layer in the vertical direction based on positions of the channel holes; etching a portion of the buffer layer in the horizontal direction through the channel holes and the channel connection holes so that a remaining portion has an undercut shape; and forming vertical channel structures each including a data storage pattern and a vertical channel pattern extending in the vertical direction on inner walls of the channel holes and sidewalls where the buffer layer has been etched, wherein the vertical channel structures are formed. In the step of extending in the vertical direction, the vertical channel patterns extending from the upper stack structure and the vertical channel patterns extending from the lower stack structure are connected to each other and protrude in the horizontal direction more than each of the vertical channel patterns. It may be characterized in that it comprises the step of forming connection parts having a curved corner shape.

According to one aspect, in the forming of the buffer layer, a layer positioned at the center in the vertical direction among the plurality of layers is made of a material having a higher etching ratio than layers positioned at the edges in the vertical direction among the plurality of layers. It may be characterized in that it includes the step of forming.

Embodiments may suggest a 3D flash memory having a structure including interconnections connecting vertical channel patterns of each of the stack structures, a manufacturing method thereof, and an electronic system including the same.

In particular, one embodiment may suggest a dimensional flash memory having a structure in which each of the connection parts protrudes more horizontally than each of the vertical channel patterns and has curved corners, a manufacturing method thereof, and an electronic system including the same.

Accordingly, the 3D flash memory according to the exemplary embodiments may achieve an effect of solving a problem of deterioration of channel current characteristics due to vertical channel pattern misalignment in a stack stacking process.

However, the effects of the present invention are not limited to the above effects, and can be variously extended without departing from the technical spirit and scope of the present invention.

1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to one embodiment.
2 is a plan view illustrating the structure of a 3D flash memory according to an exemplary embodiment.
FIG. 3 is a cross-sectional view showing the structure of a 3D flash memory according to an exemplary embodiment, and corresponds to a cross-section of FIG. 2 taken along line A-A'.
FIG. 4 is a cross-sectional view illustrating another implementation example of connection parts and a buffer layer included in the 3D flash memory shown in FIG. 3 , and corresponds to a cross-section of FIG. 2 taken along line A-A'.
FIG. 5 is a cross-sectional view showing the structure of a 3D flash memory according to another embodiment, corresponding to a cross-section of FIG. 2 taken along line A-A'.
FIG. 6 is a cross-sectional view for explaining another implementation example of connection parts and a buffer layer included in the 3D flash memory shown in FIG. 5 , and corresponds to a cross-section of FIG.
FIG. 7 is a flow chart illustrating a method of manufacturing a 3D flash memory having the structure shown in FIGS. 3 and 5 .
8A to 8F are cross-sectional views illustrating a 3D flash memory to explain the manufacturing method shown in FIG. 7 .
FIG. 9 is a flow chart illustrating a method of manufacturing a 3D flash memory having the structure shown in FIGS. 4 and 6 .
10A to 10F are cross-sectional views illustrating a 3D flash memory to explain the manufacturing method shown in FIG. 9 .
11 is a perspective view schematically illustrating an electronic system including a 3D flash memory according to embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, terms used in this specification (terminology) are terms used to appropriately express preferred embodiments of the present invention, which may vary according to the intention of a viewer or operator or customs in the field to which the present invention belongs. Therefore, definitions of these terms will have to be made based on the content throughout this specification. For example, in this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. Also, as used herein, "comprises" and/or "comprising" means that a referenced component, step, operation, and/or element is one or more other components, steps, operations, and/or elements. The presence or addition of elements is not excluded. In addition, although terms such as first and second are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish one area, direction or shape from another area, direction or shape. Accordingly, a portion referred to as a first portion in one embodiment may be referred to as a second portion in another embodiment.

Also, it should be understood that the various embodiments of the present invention are different from each other but are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in one embodiment in another embodiment without departing from the spirit and scope of the present invention. In addition, it should be understood that the location, arrangement, or configuration of individual components in the scope of each embodiment presented may be changed without departing from the spirit and scope of the present invention.

Hereinafter, a 3D flash memory according to embodiments, an operating method thereof, and an electronic system including the same will be described in detail with reference to the drawings.

1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to one embodiment.

Referring to FIG. 1 , a three-dimensional flash memory array according to an embodiment includes a common source line CSL, a plurality of bit lines BL0, BL1, and BL2, and the common source line CSL and bit lines BL0. , BL1, and BL2) may include a plurality of cell strings CSTR.

The bit lines BL0 , BL1 , and BL2 may be two-dimensionally arranged while being spaced apart from each other along the first direction D1 while extending in the second direction D2 . Here, each of the first direction D1 , the second direction D2 , and the third direction D3 are orthogonal to each other and may form a rectangular coordinate system defined by X, Y, and Z axes.

A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0 , BL1 , and BL2 . The cell strings CSTR may be connected in common to the common source line CSL while being provided between the bit lines BL0 , BL1 , and BL2 and one common source line CSL. In this case, a plurality of common source lines CSL may be provided, and the plurality of common source lines CSL are spaced apart from each other along the second direction D2 while extending in the first direction D1 and have a two-dimensional can be arranged sequentially. The same voltage may be electrically applied to the plurality of common source lines CSL, but different voltages may be applied as each of the plurality of common source lines CSL is electrically independently controlled without being limited or limited thereto. have.

The cell strings CSTR may be spaced apart from each other along the second direction D2 for each bit line while extending in the third direction D3 and may be arranged. According to an embodiment, each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL and first and second strings connected in series to bit lines BL0, BL1, and BL2. Select transistors SST1 and SST2, memory cell transistors MCT connected in series while being disposed between the ground select transistor GST and the first and second string select transistors SST1 and SST2, and an erase control transistor ECT ) can be configured. Also, each of the memory cell transistors MCT may include a data storage element.

For example, each of the cell strings CSTR may include first and second string select transistors SST1 and SST2 connected in series, and the second string select transistor SST2 may include bit lines BL0 and BL1 , BL2). However, without being limited thereto, each of the cell strings CSTR may include one string select transistor. As another example, the ground select transistor GST in each of the cell strings CSTR may be composed of a plurality of MOS transistors connected in series similarly to the first and second string select transistors SST1 and SST2. .

One cell string CSTR may include a plurality of memory cell transistors MCT having different distances from the common source lines CSL. That is, the memory cell transistors MCT may be connected in series while being disposed along the third direction D3 between the first string select transistor SST1 and the ground select transistor GST. The erase control transistor ECT may be connected between the ground select transistor GST and the common source lines CSL. Each of the cell strings CSTR is formed between the first string select transistor SST1 and the uppermost one of the memory cell transistors MCT and between the ground select transistor GST and the lowermost one of the memory cell transistors MCT. Dummy cell transistors DMC connected to each other may be further included.

According to an embodiment, the first string select transistor SST1 may be controlled by the first string select lines SSL1-1, SSL1-2, and SSL1-3, and the second string select transistor SST2 may be It can be controlled by 2 string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors MCT may be respectively controlled by a plurality of word lines WL0 - WLn, and the dummy cell transistors DMC may be respectively controlled by a dummy word line DWL. The ground select transistor GST may be controlled by the ground select lines GSL0 , GSL1 , and GSL2 , and the erase control transistor ECT may be controlled by the erase control line ECL. A plurality of erasure control transistors ECT may be provided. Common source lines CSL may be commonly connected to sources of erase control transistors ECT.

Gate electrodes of the memory cell transistors MCT, which are provided at substantially the same distance from the common source lines CSL, may be connected in common to one of the word lines WL0 - WLn and DWL to be in an equipotential state. . However, without being limited thereto, even if the gate electrodes of the memory cell transistors MCT are provided at substantially the same level from the common source lines CSL, the gate electrodes provided in different rows or columns may be independently controlled. have.

Ground select lines (GSL0, GSL1, GSL2), first string select lines (SSL1-1, SSL1-2, SSL1-3) and second string select lines (SSL2-1, SSL2-2, SSL2-3) ) may extend along the first direction D1, be spaced apart from each other in the second direction D2, and be two-dimensionally arranged. ground selection lines GSL0, GSL1, and GSL2 provided at substantially the same level from the common source lines CSL, first string selection lines SSL1-1, SSL1-2, SSL1-3, and a second string The selection lines SSL2-1, SSL2-2, and SSL2-3 may be electrically separated from each other. Also, erase control transistors ECT of different cell strings CSTR may be controlled by a common erase control line ECL. The erase control transistors ECT may generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines BL0 , BL1 , and BL2 and/or the common source lines CSL during an erase operation of the memory cell array, and the string select transistor SST and/or Alternatively, gate induced leakage current may be generated in the erasure control transistors ECT.

The above-described string selection line SSL may be expressed as an upper selection line USL, and the ground selection line GSL may be expressed as a lower selection line.

2 is a plan view illustrating the structure of a 3D flash memory according to an exemplary embodiment. FIG. 3 is a cross-sectional view showing the structure of a 3D flash memory according to an exemplary embodiment, and corresponds to a cross-section of FIG. 2 taken along line A-A'.

Referring to FIGS. 2 and 3 , the substrate SUB may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. . The substrate SUB may be doped with first conductivity-type impurities (eg, P-type impurities).

Stacked structures ST may be disposed on the substrate SUB. The stacked structures ST may be two-dimensionally disposed along the second direction D2 while extending in the first direction D1. In addition, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1 , EL2 , and EL3 alternately stacked in a vertical direction perpendicular to the upper surface of the substrate SUB (eg, in the third direction D3 ), and interlayer insulating films ILD. can include The stacked structures ST may have substantially flat upper surfaces. That is, top surfaces of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or a direction opposite to the third direction D3.

Referring back to FIG. 1 , each of the gate electrodes EL1 , EL2 , and EL3 includes an erase control line ECL, ground select lines GSL0 , GSL1 , and GSL2 sequentially stacked on the substrate SUB, and a word line. (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) can be

Each of the gate electrodes EL1 , EL2 , and EL3 may have substantially the same thickness in the third direction D3 while extending in the first direction D1 . Hereinafter, the thickness means the thickness in the third direction D3. Each of the gate electrodes EL1 , EL2 , and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1 , EL2 , EL3 may be a doped semiconductor (ex, doped silicon, etc.), a metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1 , EL2 , and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal material described above.

More specifically, the gate electrodes EL1 , EL2 , and EL3 include a lowermost first gate electrode EL1 , an uppermost third gate electrode EL3 , and the first and third gate electrodes EL1 and EL3 . A plurality of second gate electrodes EL2 may be included therebetween. Although each of the first gate electrode EL1 and the third gate electrode EL3 is shown and described in the singular number, this is exemplary and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0 , GSL1 , and GLS2 shown in FIG. 1 . The second gate electrode EL2 may correspond to one of the word lines WL0 - WLn and DWL shown in FIG. 1 . The third gate electrode EL3 includes any one of the first string select lines SSL1-1, SSL1-2 and SSL1-3 of FIG. 1 shown in FIG. 1 or the second string select lines SSL2-1 and SSL2-1. SSL2-2, SSL2-3) may correspond to any one.

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the lengths of the gate electrodes EL1 , EL2 , and EL3 of the stack structures ST in the first direction D1 may decrease as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the largest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the longest length in the first direction D1 and the shortest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures ST may decrease as the distance from the outermost one of the vertical channel structures VS described later increases, and the gate electrodes EL1, Sidewalls of EL2 and EL3 may be spaced apart at regular intervals along the first direction D1 when viewed in plan.

Each of the interlayer insulating layers ILD may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers ILD may have a smaller thickness than other interlayer insulating layers ILD. However, this is illustrative and not limited thereto, and the thickness of each of the interlayer insulating layers ILD may be different from each other according to the characteristics of the semiconductor device or all may be set to be the same. The interlayer insulating layers ILD may be formed of an insulating material to insulate between the gate electrodes EL1 , EL2 , and EL3 . For example, the interlayer insulating layers ILD may be formed of silicon oxide.

A plurality of channel holes CH penetrating portions of the stacked structures ST and the substrate SUB may be provided. Vertical channel structures VS may be provided in the channel holes CH. The vertical channel structures VS are the plurality of cell strings CSTR shown in FIG. 1 , and may extend in the third direction D3 while being connected to the substrate SUB. The connection of the vertical channel structures VS with the substrate SUB may be achieved by partially burying a portion of each of the vertical channel structures VS in the substrate SUB, but is not limited thereto, and the vertical channel structures VS are not limited thereto. The lower surface of (VS) may be made by contacting the upper surface of the substrate (SUB). When portions of each of the vertical channel structures VS are buried in the substrate SUB, lower surfaces of the vertical channel structures VS may be positioned at a lower level than the upper surface of the substrate SUB.

A plurality of columns of vertical channel structures VS passing through any one of the stacked structures ST may be provided. For example, as shown in FIG. 2 , columns of two vertical channel structures VS may pass through one of the stacked structures ST. However, without being limited thereto, three or more columns of vertical channel structures VS may pass through one of the stacked structures ST. In a pair of adjacent columns, the vertical channel structures VS corresponding to one column may be shifted in the first direction D1 from the vertical channel structures VS corresponding to the other adjacent column. have. When viewed from a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited thereto, the vertical channel structures VS may form an array arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures VS is shown as having a column shape having the same width at the top and bottom, but is not limited thereto, and is not limited thereto. It may have a shape in which the width to (D2) is increased. This is due to the limitation that, when the channel holes CH are etched, the widths in the first direction D1 and the second direction D2 decrease toward the opposite direction of the third direction D3. The upper surface of each of the vertical channel structures VS may have a circular shape, an elliptical shape, a rectangular shape, or a bar shape.

Each of the vertical channel structures VS may include a data storage pattern DSP, a vertical channel pattern VCP, a vertical semiconductor pattern VSP, and a conductive pad PAD. In each of the vertical channel structures VS, the data storage pattern DSP may have a pipe shape or macaroni shape with an open bottom, and the vertical channel pattern VCP may have a pipe shape or macaroni shape with a closed bottom. can have a shape. The vertical semiconductor pattern VSP may fill a space surrounded by the vertical channel pattern VCP and the conductive pad PAD.

The data storage pattern DSP covers the inner walls of each of the channel holes CH and contacts the vertical channel pattern VCP inwardly and contacts the sidewalls of the gate electrodes EL1 , EL2 , and EL3 outwardly. can Accordingly, the regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP are the second gate electrodes along with the regions corresponding to the second gate electrodes EL2 of the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through EL2 may be configured. The memory cells correspond to the memory cell transistors MCT shown in FIG. 1 . That is, the data storage pattern DSP traps charges or holes by a voltage applied through the second gate electrodes EL2 or maintains a state of charges (eg, a polarization state of charges) in a 3D flash memory. It can act as a data repository. For example, an ONO (tunnel oxide-charge storage layer (Nitride)-blocking oxide layer) layer or a ferroelectric layer may be used as the data storage pattern DSP. Such a data storage pattern DSP may represent binary data values or multi-valued data values with changes in trapped charges or holes, or represent binary data values or multi-valued data values with changes in states of charges.

The vertical channel pattern VCP may cover an inner wall of the data storage pattern DSP. The vertical channel pattern VCP may include a first portion VCP1 and a second portion VCP2 on the first portion VCP1.

The first portion VCP1 of the vertical channel pattern VCP may be provided under each of the channel holes CH and may contact the substrate SUB. The first portion VCP1 of the vertical channel pattern VCP may be used to block, suppress, or minimize leakage current in each of the vertical channel structures VS and/or to form an epitaxial pattern. A thickness of the first portion VCP1 of the vertical channel pattern VCP may be greater than, for example, a thickness of the first gate electrode EL1. A sidewall of the first part VCP1 of the vertical channel pattern VCP may be surrounded by the data storage pattern DSP. A top surface of the first portion VCP1 of the vertical channel pattern VCP may be positioned at a higher level than a top surface of the first gate electrode EL1. More specifically, the top surface of the first part VCP1 of the vertical channel pattern VCP may be positioned between the top surface of the first gate electrode EL1 and the bottom surface of the lowermost one of the second gate electrodes EL2. A lower surface of the first portion VCP1 of the vertical channel pattern VCP may be positioned at a lower level than an uppermost surface of the substrate SUB (ie, a lower surface of a lowermost one of the interlayer insulating layers ILD). A portion of the first portion VCP1 of the vertical channel pattern VCP may overlap the first gate electrode EL1 in a horizontal direction. Hereinafter, the horizontal direction refers to an arbitrary direction extending on a plane parallel to the first and second directions D1 and D2.

The second portion VCP2 of the vertical channel pattern VCP may extend in the third direction D3 from the upper surface of the first portion VCP1. The second portion VCP2 of the vertical channel pattern VCP may be provided between the data storage pattern DSP and the vertical semiconductor pattern VSP, and may correspond to the second gate electrodes EL2. Accordingly, the second portion VCP2 of the vertical channel pattern VCP may form memory cells together with regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP, as described above. .

A top surface of the second part VCP2 of the vertical channel pattern VCP may be substantially coplanar with a top surface of the vertical semiconductor pattern VSP. A top surface of the second part VCP2 of the vertical channel pattern VCP may be positioned at a level higher than a top surface of an uppermost one of the second gate electrodes EL2 . More specifically, the upper surface of the second portion VCP2 of the vertical channel pattern VCP may be positioned between the upper and lower surfaces of the third gate electrode EL3 .

The vertical channel pattern VCP is a component that transfers charges or holes to the data storage pattern DSP, and may be formed of monocrystalline silicon or polysilicon to form a channel or to be boosted by an applied voltage. However, without being limited thereto, the vertical channel pattern VCP may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing leakage current. For example, the vertical channel pattern VCP may be formed of an oxide semiconductor material including at least one of In, Zn, and Ga having excellent leakage current characteristics, or a Group 4 semiconductor material. The vertical channel pattern VCP may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern VCP may block, suppress, or minimize leakage current to the gate electrodes EL1 , EL2 , and EL3 or the substrate SUB, and at least one of the gate electrodes EL1 , EL2 , and EL3 Any one transistor characteristic (eg, threshold voltage distribution and program/read speed) may be improved, and consequently, electrical characteristics of the 3D flash memory may be improved.

The vertical semiconductor pattern VSP may be surrounded by the second portion VCP2 of the vertical channel pattern VCP. An upper surface of the vertical semiconductor pattern VSP may contact the conductive pad PAD, and a lower surface of the vertical semiconductor pattern VSP may contact the first portion VCP1 of the vertical channel pattern VCP. The vertical semiconductor pattern VSP may be spaced apart from the substrate SUB in the third direction D3. In other words, the vertical semiconductor pattern VSP may be electrically floated from the substrate SUB.

The vertical semiconductor pattern VSP may be formed of a material that helps diffusion of charges or holes in the vertical channel pattern VCP. More specifically, the vertical semiconductor pattern VSP may be formed of a material having excellent charge and hole mobility. For example, the vertical semiconductor pattern VSP may be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. For a more specific example, the vertical semiconductor pattern VSP may be formed of polysilicon doped with impurities of the same first conductivity type as the substrate SUB (eg, P-type impurities). That is, the vertical semiconductor pattern VSP can improve the electrical characteristics of the 3D flash memory to increase the speed of memory operation.

Referring back to FIG. 1 , the vertical channel structures VS include an erase control transistor ECT, first and second string select transistors SST1 and SST2 , a ground select transistor GST, and memory cell transistors MCT. ) may correspond to channels of

Conductive pads PAD may be provided on top surfaces of the second portion VCP2 of the vertical channel pattern VCP and on top surfaces of the vertical semiconductor pattern VSP. The conductive pad PAD may be connected to an upper portion of the vertical channel pattern VCP and an upper portion of the vertical semiconductor pattern VSP. A sidewall of the conductive pad PAD may be surrounded by the data storage pattern DSP. A top surface of the conductive pad PAD may be substantially coplanar with a top surface of each of the stack structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). A lower surface of the conductive pad PAD may be positioned at a lower level than an upper surface of the third gate electrode EL3 . More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3 . That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in a horizontal direction.

The conductive pad PAD may be formed of a semiconductor doped with impurities or a conductive material. For example, the conductive pad PAD is doped with an impurity different from that of the vertical semiconductor pattern VSP (more precisely, an impurity of a second conductivity type (eg, N-type) different from the first conductivity type (eg, P-type)). It may be formed of a semiconductor material.

The conductive pad PAD may reduce contact resistance between the bit line BL and the vertical channel pattern VCP (or vertical semiconductor pattern VSP), which will be described later.

Although the vertical channel structures VS have been described as having a structure including the conductive pad PAD, it is not limited thereto and may have a structure in which the conductive pad PAD is omitted. In this case, as the conductive pad PAD is omitted from the vertical channel structures VS, the upper surfaces of each of the vertical channel pattern VCP and the vertical semiconductor pattern VSP are the upper surfaces of each of the stacked structures ST (ie, Each of the vertical channel pattern VCP and the vertical semiconductor pattern VSP may extend in the third direction D3 so as to be substantially coplanar with the top surface of the uppermost one of the interlayer insulating layers ILD. Also, in this case, the bit line contact plug BLPG, which will be described later, directly contacts the vertical channel pattern VCP instead of being indirectly electrically connected to the vertical channel pattern VCP through the conductive pad PAD. can be electrically connected.

Also, although it has been described that the vertical channel structures VS include the vertical semiconductor pattern VSP, the vertical semiconductor pattern VSP may be omitted without being limited or limited thereto.

In addition, although the vertical channel pattern VCP has been described as having a structure including the first part VCP1 and the second part VCP2, it is not limited thereto and may have a structure excluding the first part VCP1. can For example, the vertical channel pattern VCP is provided between the vertical semiconductor pattern VSP and the data storage pattern DSP and extends to the substrate SUB to contact the substrate SUB. can In this case, the lower surface of the vertical channel pattern VCP may be positioned at a lower level than the uppermost surface of the substrate SUB (the lower surface of the lowermost one of the interlayer insulating films ILD), and the upper surface of the vertical channel pattern VCP may be located at a level lower than that of the upper surface of the substrate SUB. A top surface of the pattern VSP may be substantially coplanar.

An isolation trench TR extending in the first direction D1 may be provided between the stacked structures ST adjacent to each other. The common source region CSR may be provided inside the substrate SUB exposed by the isolation trench TR. The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with impurities of the second conductivity type (eg, N-type impurities). The common source region CSR may correspond to the common source line CSL of FIG. 1 .

A common source plug CSP may be provided in the isolation trench TR. The common source plug CSP may be connected to the common source region CSR. A top surface of the common source plug CSP may be substantially coplanar with a top surface of each of the stacked structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). The common source plug CSP may have a plate shape extending in the first and third directions D1 and D3. In this case, the common source plug CSP may have a shape in which a width in the second direction D2 increases toward the third direction D3.

Insulation spacers SP may be interposed between the common source plug CSP and the stacked structures ST. Insulation spacers SP may be provided to face each other between adjacent stacked structures ST. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A capping insulating layer CAP may be provided on the stacked structures ST, the vertical channel structures VS, and the common source plug CSP. The capping insulating layer CAP may cover the top surface of the uppermost one of the interlayer insulating layers ILD, the top surface of the conductive pad PAD, and the top surface of the common source plug CSP. The capping insulating layer CAP may be formed of an insulating material different from that of the interlayer insulating layers ILD. A bit line contact plug BLPG electrically connected to the conductive pad PAD may be provided inside the capping insulating layer CAP. The bit line contact plug BLPG may have a shape in which widths in the first and second directions D1 and D2 increase in the third direction D3.

A bit line BL may be provided on the capping insulating layer CAP and the bit line contact plug BLPG. The bit line BL corresponds to any one of the plurality of bit lines BL0 , BL1 , and BL2 shown in FIG. 1 , and may be formed of a conductive material to extend along the second direction D2 . The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1 , EL2 , and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through the bit line contact plug BLPG. Here, that the bit line BL is connected to the vertical channel structures VS may mean that it is connected to the vertical channel pattern VCP included in the vertical channel structures VS.

The three-dimensional flash memory having such a structure includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string selection line SSL, a voltage applied to each of the word lines WL0-WLn, and a ground selection line. A program operation, a read operation, and an erase operation may be performed based on the voltage applied to the GSL and the voltage applied to the common source line CSL. For example, the 3D flash memory includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string select line SSL, a voltage applied to each of the word lines WL0 to WLn, and a ground select line GSL. ) and the voltage applied to the common source line (CSL), a channel is formed in the vertical channel pattern (VCP) to transfer charges or holes to the data storage pattern (DSP) of the target memory cell, thereby program operation. can be performed.

In addition, the 3D flash memory according to an embodiment is not limited or not limited to the structure described above, and may include a vertical channel pattern (VCP), a data storage pattern (DSP), and gate electrodes EL1, EL2, and EL3 according to implementation examples. , a bit line (BL), and a common source line (CSL) may be implemented in various structures.

As the 3D flash memory having such a structure is manufactured through a stack stacking process, each of the stack structures ST may include an upper stack structure USS and a lower stack structure LSS. The lower stack structure LSS is disposed on the substrate SUB and may include gate electrodes EL1 and parts of EL2 alternately stacked in a vertical direction, and interlayer insulating layers ILD. The upper stack structure USS is stacked on the lower stack structure LSS and may include gate electrodes (part of EL2, EL3) and an interlayer insulating layer ILD that are alternately stacked in a vertical direction.

When the lower stack structure LSS and the upper stack structure USS are stacked, the vertical channel structures VS included in the lower stack structure LSS and the vertical channel structures VS included in the upper stack structure USS This misalignment problem may occur. For example, when the vertical channel patterns VCP of the lower stack structure LSS and the vertical channel patterns VCP of the upper stack structure USS are misaligned, a problem of deteriorating channel current characteristics may occur. Therefore, each of the stacked structures ST of the 3D flash memory is disposed between the upper stack structure USS and the lower stack structure LSS, and vertical channel patterns of each of the stack structures USS and LSS ( It may include connection units (CU) connecting VCP) to each other. The connection units CU are formed by portions of the buffer layer BU positioned between the upper stack structure USS and the lower stack structure LSS in the horizontal direction (first direction D1 and second direction D2). Since it is formed in the etched spaces, it can be accommodated by the buffer layer BU.

In addition, the connection portions CU formed on the inner walls of the spaces in which portions of the buffer layer BU in the horizontal direction are etched include channel holes CH of the upper stack structures USS and lower stack structures LSS, respectively. Since they are collectively formed through the same process as the vertical channel structures VS formed therein, each of the connection units CU includes a first connection unit CU1 formed of the same material as the data storage pattern DSP, A second connection portion CU2 formed of the same material as the channel pattern VCP and a third connection portion CU3 formed of the same material as the vertical semiconductor pattern VSP may be included.

In particular, each of the connection units CU may have a shape in which a corner is curved while protruding in a horizontal direction more than each of the vertical channel patterns VCP. More specifically, each of the connection units CU may have a shape protruding in a horizontal direction more than each of the vertical channel patterns VCP by being formed to a size accommodating each of the vertical channel patterns VCP on a plane. In addition, the connection units CU may be formed at positions accommodating the vertical channel patterns VCP of the upper and lower stack structures USS and LSS to connect the vertical channel patterns VCP to each other.

As such, each of the connection units CU protrudes and has a curved corner, so that each of the connection units CU is formed on the sidewall of the remaining portion having an undercut shape after a portion of the buffer layer BU is etched. because it becomes That is, the sidewall on which wet etching has been performed on a portion of the buffer layer BU in the horizontal direction (the sidewall of the remaining portion after wet etching is performed) has an undercut shape, and each of the connection units CU has As it is formed on the sidewall of the remaining portion after wet etching is performed, it may have a curved corner while protruding in a horizontal direction.

To this end, the buffer layer BU may be formed of a material capable of performing wet etching. Here, the material on which wet etching may be performed may include at least one of silicon oxide or metal oxide (eg, silicon nitride, silicon oxide, silicon carbide, or silicon oxynitride).

As described above, the 3D flash memory includes the connection units CU to connect the vertical channel patterns VCP of each of the stack structures USS and LSS to each other, thereby solving a problem of deterioration of channel current characteristics.

The three-dimensional flash memory is manufactured through a stack lamination process and is described as including an upper stack structure (USS) and a lower stack structure (LSS). It may include stack structures (eg, upper stack structures USS, middle stack structures MSS, and lower stack structures LSS). In this case, the connecting units CU may be arranged in a connection portion of the stack structures with groups arranged in the horizontal direction (first direction D1 and second direction D2) spaced apart in the third direction D3. A plurality of buffer layers BU may be provided and spaced apart from each other in the third direction D3 to surround groups of the connecting units CU that are spaced apart from each other in the third direction D3.

FIG. 4 is a cross-sectional view illustrating another implementation example of connection parts and a buffer layer included in the 3D flash memory shown in FIG. 3 , and corresponds to a cross-section of FIG. 2 taken along line A-A'.

The 3D flash memory described below with reference to FIG. 4 has all components identical to the 3D flash memory described above with reference to FIG. 3, but is characterized in that only the structure of the buffer layer BU is different. Accordingly, only the buffer layer BU having a different structure will be described below.

Each of the connection units CU shown in FIG. 4 may also have a shape with curved corners while protruding in a horizontal direction than each of the vertical channel patterns VCP. In this way, each of the connection parts CU has a curved corner while protruding, as described with reference to FIG. 3, each of the connection parts CU is undercut after a portion of the buffer layer BU is etched ( This is because it is formed on the sidewall of the remaining part having an undercut shape.

However, the buffer layer BU shown in FIG. 4 is etched through not only wet etching but also dry etching as a plurality of layers L1, L2, and L3 having different etching ratios are vertically stacked and formed. It is different from the buffer layer BU shown in FIG. 3 in that the sidewall having this effect has an undercut shape. That is, the buffer layer BU is formed by vertically stacking a plurality of layers L1 , L2 , and L3 having different etching ratios, so that a portion of the buffer layer BU in the horizontal direction is etched. The sidewall (the sidewall of the remaining portion after etching) has an undercut shape, and each of the connection units CU is formed on the sidewall of the remaining portion after etching, protruding in the horizontal direction and having curved corners. can have a shape.

Regarding the fact that the buffer layer BU is formed by stacking a plurality of layers L1, L2, and L3 having different etching ratios in a vertical direction, the plurality of layers L1 to have an undercut shape on the etched sidewall. , L2, and L3), the layer L2 located at the center in the vertical direction may have a higher etching rate than the layers L1 and L3 located at the edge.

Although the buffer layer BU has been described as being composed of three layers (L1, L2, and L3), it may be composed of four or more layers without being limited or limited thereto. In this case, each of the four or more layers may have a higher etching rate closer to the center in the vertical direction and a lower etching rate closer to the edge.

FIG. 5 is a cross-sectional view showing the structure of a 3D flash memory according to another embodiment, corresponding to a cross-section of FIG. 2 taken along line A-A'.

Referring to FIG. 5 , the substrate SUB may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. The substrate SUB may be doped with first conductivity-type impurities (eg, P-type impurities).

Stacked structures ST may be disposed on the substrate SUB. The stacked structures ST may be two-dimensionally disposed along the second direction D2 while extending in the first direction D1. In addition, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1 , EL2 , and EL3 alternately stacked in a vertical direction perpendicular to the upper surface of the substrate SUB (eg, in the third direction D3 ), and interlayer insulating films ILD. can include The stacked structures ST may have substantially flat upper surfaces. That is, top surfaces of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or a direction opposite to the third direction D3.

Referring back to FIG. 1 , each of the gate electrodes EL1 , EL2 , and EL3 includes an erase control line ECL, ground select lines GSL0 , GSL1 , and GSL2 sequentially stacked on the substrate SUB, and a word line. (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) can be

Each of the gate electrodes EL1 , EL2 , and EL3 may have substantially the same thickness in the third direction D3 while extending in the first direction D1 . Hereinafter, the thickness means the thickness in the third direction D3. Each of the gate electrodes EL1 , EL2 , and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1 , EL2 , EL3 may be a doped semiconductor (ex, doped silicon, etc.), a metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1 , EL2 , and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal material described above.

More specifically, the gate electrodes EL1 , EL2 , and EL3 include a lowermost first gate electrode EL1 , an uppermost third gate electrode EL3 , and the first and third gate electrodes EL1 and EL3 . A plurality of second gate electrodes EL2 may be included therebetween. Although each of the first gate electrode EL1 and the third gate electrode EL3 is shown and described in the singular number, this is exemplary and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0 , GSL1 , and GLS2 shown in FIG. 1 . The second gate electrode EL2 may correspond to one of the word lines WL0 - WLn and DWL shown in FIG. 1 . The third gate electrode EL3 includes any one of the first string select lines SSL1-1, SSL1-2 and SSL1-3 of FIG. 1 shown in FIG. 1 or the second string select lines SSL2-1 and SSL2-1. SSL2-2, SSL2-3) may correspond to any one.

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the lengths of the gate electrodes EL1 , EL2 , and EL3 of the stack structures ST in the first direction D1 may decrease as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the largest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the longest length in the first direction D1 and the shortest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures ST may decrease as the distance from the outermost one of the vertical channel structures VS described later increases, and the gate electrodes EL1, Sidewalls of EL2 and EL3 may be spaced apart at regular intervals along the first direction D1 when viewed in plan.

Each of the interlayer insulating layers ILD may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers ILD may have a smaller thickness than other interlayer insulating layers ILD. However, this is illustrative and not limited thereto, and the thickness of each of the interlayer insulating layers ILD may be different from each other according to the characteristics of the semiconductor device or all may be set to be the same. The interlayer insulating layers ILD may be formed of an insulating material to insulate between the gate electrodes EL1 , EL2 , and EL3 . For example, the interlayer insulating layers ILD may be formed of silicon oxide.

A plurality of channel holes CH penetrating portions of the stacked structures ST and the substrate SUB may be provided. Vertical channel structures VS may be provided in the channel holes CH. The vertical channel structures VS are the plurality of cell strings CSTR shown in FIG. 1 , and may extend in the third direction D3 while being connected to the substrate SUB. The connection of the vertical channel structures VS with the substrate SUB may be achieved by partially burying a portion of each of the vertical channel structures VS in the substrate SUB, but is not limited thereto, and the vertical channel structures VS are not limited thereto. The lower surface of (VS) may be made by contacting the upper surface of the substrate (SUB). When portions of each of the vertical channel structures VS are buried in the substrate SUB, lower surfaces of the vertical channel structures VS may be positioned at a lower level than the upper surface of the substrate SUB.

A plurality of columns of vertical channel structures VS passing through any one of the stacked structures ST may be provided. For example, as shown in FIG. 2 , columns of two vertical channel structures VS may pass through one of the stacked structures ST. However, without being limited thereto, three or more columns of vertical channel structures VS may pass through one of the stacked structures ST. In a pair of adjacent columns, the vertical channel structures VS corresponding to one column may be shifted in the first direction D1 from the vertical channel structures VS corresponding to the other adjacent column. have. When viewed from a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited thereto, the vertical channel structures VS may form an array arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures VS is shown as having a column shape having the same width at the top and bottom, but is not limited thereto, and is not limited thereto. It may have a shape in which the width to (D2) is increased. This is due to the limitation that, when the channel holes CH are etched, the widths in the first direction D1 and the second direction D2 decrease toward the opposite direction of the third direction D3. The upper surface of each of the vertical channel structures VS may have a circular shape, an elliptical shape, a rectangular shape, or a bar shape.

Each of the vertical channel structures VS may include a data storage pattern DSP, a vertical channel pattern VCP, a back gate BG, and a conductive pad PAD. In each of the vertical channel structures VS, the data storage pattern DSP may have a pipe shape or macaroni shape with an open bottom, and the vertical channel pattern VCP may have a pipe shape or macaroni shape with a closed bottom. can have a shape. The back gate BG may be formed to apply a voltage to the vertical channel pattern VCP while at least a portion of the back gate BG is surrounded by the vertical channel pattern VCP. Hereinafter, that the back gate BG is included in the vertical channel pattern VCP may mean a state in which at least a portion of the back gate BF is covered by the vertical channel pattern VCP, as described above.

The data storage pattern DSP covers the inner walls of each of the channel holes CH and contacts the vertical channel pattern VCP inwardly and contacts the sidewalls of the gate electrodes EL1 , EL2 , and EL3 outwardly. can Accordingly, the regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP are the second gate electrodes along with the regions corresponding to the second gate electrodes EL2 of the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through EL2 may be configured. The memory cells correspond to the memory cell transistors MCT shown in FIG. 1 . That is, the data storage pattern DSP traps charges or holes by a voltage applied through the second gate electrodes EL2 or maintains a state of charges (eg, a polarization state of charges) in a 3D flash memory. It can act as a data repository. For example, an ONO (tunnel oxide-charge storage layer (Nitride)-blocking oxide layer) layer or a ferroelectric layer may be used as the data storage pattern DSP. Such a data storage pattern DSP may represent binary data values or multi-valued data values with changes in trapped charges or holes, or represent binary data values or multi-valued data values with changes in states of charges.

The vertical channel pattern VCP may cover an inner wall of the data storage pattern DSP and may extend in the third direction D3. The vertical channel pattern VCP may be provided between the data storage pattern DSP and the back gate BG, and may correspond to the second gate electrodes EL2. Accordingly, as described above, the vertical channel pattern VCP may constitute memory cells together with regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP.

A top surface of the vertical channel pattern VCP may be positioned at a level higher than a top surface of an uppermost one of the second gate electrodes EL2 . More specifically, the upper surface of the vertical channel pattern VCP may be positioned between the upper and lower surfaces of the third gate electrode EL3 .

The vertical channel pattern VCP is a component that transfers charges or holes to the data storage pattern DSP, and may be formed of monocrystalline silicon or polysilicon to form a channel or to be boosted by an applied voltage. However, without being limited thereto, the vertical channel pattern VCP may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing leakage current. For example, the vertical channel pattern VCP may be formed of an oxide semiconductor material including at least one of In, Zn, and Ga having excellent leakage current characteristics, or a Group 4 semiconductor material. The vertical channel pattern VCP may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern VCP may block, suppress, or minimize leakage current to the gate electrodes EL1 , EL2 , and EL3 or the substrate SUB, and at least one of the gate electrodes EL1 , EL2 , and EL3 Any one transistor characteristic (eg, threshold voltage distribution and program/read speed) may be improved, and consequently, electrical characteristics of the 3D flash memory may be improved.

At least a portion of the back gate BG is surrounded by and contacts the vertical channel pattern VCP, and may be formed to apply a voltage to the vertical channel pattern VCP for a memory operation. To this end, the back gate BG is a doped semiconductor (ex, doped silicon, etc.), a metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), It may be formed of a conductive material including at least one selected from Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (eg, titanium nitride, tantalum nitride, etc.). In addition to the metal material described above, the back gate BG may include at least one of all metal materials that can be formed by ALD.

In this case, the back gate BG extends along the third direction D3 from a level corresponding to the first gate electrode EL1 to a level corresponding to the second gate electrode EL2 within the vertical channel pattern VCP. can be formed That is, the upper surface of the back gate BG may be positioned at a level higher than that of the uppermost one of the second gate electrodes EL2 . However, without being limited thereto, the back gate BG may extend along the third direction D3 to a level corresponding to the third gate electrode EL3 within the vertical channel pattern VCP.

Although the lower substrate contacting the lower portion of the back gate BG is omitted in the drawing, a lower substrate contacting the lower surface of the back gate BG may be included according to an implementation example. Also, according to an implementation example, the back gate BG may be formed from inside the substrate SUB or from an upper portion of the substrate SUB.

The back gate BG is included in the vertical channel pattern VCP of each of the cell strings CSTR, and the back gate BG included in the vertical channel pattern VCP of each of the cell strings CSTR is The back gate BG may be electrically connected to all of the planes formed by the first direction D1 and the second direction D2. That is, the back gate BG may be commonly connected to the cell strings CSTR. In this case, the back gate BG of each of the cell strings CSTR may be collectively controlled so that the same voltage may be applied to all of them.

However, without being limited thereto, the back gates BG included in the vertical channel patterns VCP of each of the cell strings CSTR may be electrically connected to each other along the first direction D1 of FIG. 1 . In this case, each of the back gates BG of the cell strings CSTR arranged along the second direction D2 is electrically independently controlled so that different voltages can be applied. The same voltage may be applied to the back gates BG of each of the cell strings CSTR arranged along D1 by being collectively controlled.

Also, the back gates BG included in the vertical channel patterns VCP of each of the cell strings CSTR may be electrically connected to each other along the second direction D2 of FIG. 1 . In this case, each of the back gates BG of the cell strings CSTR arranged along the first direction D1 may be electrically independently controlled so that different voltages may be applied. The same voltage may be applied to the back gates BG of each of the cell strings CSTR arranged along D2 by being collectively controlled.

Since the insulating layer INS is disposed between the back gate BG and the vertical channel pattern VCP, direct contact between the back gate BG and the vertical channel pattern VCP may be prevented. Like the interlayer insulating layers ILD, the insulating layer ILD may be formed of an insulating material such as silicon oxide.

In the above, it has been described that the back gate BG is formed in an inner hole of the vertical channel pattern VCP and is formed while being surrounded by the vertical channel pattern VCP without gaps, but is not limited or limited thereto, and the vertical channel pattern ( It may also be formed in a structure in which at least a portion is wrapped by the VCP). For example, a structure in which the back gate BG and the insulating layer INS are included in at least a portion of the vertical channel pattern VCP or a structure penetrating the vertical channel pattern VCP may be implemented.

Referring back to FIG. 1 , the vertical channel structures VS include an erase control transistor ECT, first and second string select transistors SST1 and SST2 , a ground select transistor GST, and memory cell transistors MCT. ) may correspond to channels of

A conductive pad PAD may be provided on a top surface of the vertical channel pattern VCP. The conductive pad PAD may be connected to an upper portion of the vertical channel pattern VCP. A sidewall of the conductive pad PAD may be surrounded by the data storage pattern DSP. A top surface of the conductive pad PAD may be substantially coplanar with a top surface of each of the stack structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). A lower surface of the conductive pad PAD may be positioned at a lower level than an upper surface of the third gate electrode EL3 . More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3 . That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in a horizontal direction.

The conductive pad PAD may be formed of a semiconductor doped with impurities or a conductive material. For example, the conductive pad PAD is a semiconductor material doped with impurities different from those of the substrate SUB (more precisely, impurities of a second conductivity type (eg, N-type) different from the first conductivity type (eg, P-type)). can be formed as

The conductive pad PAD may reduce contact resistance between the bit line BL and the vertical channel pattern VCP, which will be described later.

An isolation trench TR extending in the first direction D1 may be provided between the stacked structures ST adjacent to each other. The common source region CSR may be provided inside the substrate SUB exposed by the isolation trench TR. The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with impurities of the second conductivity type (eg, N-type impurities). The common source region CSR may correspond to the common source line CSL of FIG. 1 .

A common source plug CSP may be provided in the isolation trench TR. The common source plug CSP may be connected to the common source region CSR. A top surface of the common source plug CSP may be substantially coplanar with a top surface of each of the stacked structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). The common source plug CSP may have a plate shape extending in the first and third directions D1 and D3. In this case, the common source plug CSP may have a shape in which a width in the second direction D2 increases toward the third direction D3.

Insulation spacers SP may be interposed between the common source plug CSP and the stacked structures ST. Insulation spacers SP may be provided to face each other between adjacent stacked structures ST. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A capping insulating layer CAP may be provided on the stacked structures ST, the vertical channel structures VS, and the common source plug CSP. The capping insulating layer CAP may cover the top surface of the uppermost one of the interlayer insulating layers ILD, the top surface of the conductive pad PAD, and the top surface of the common source plug CSP. The capping insulating layer CAP may be formed of an insulating material different from that of the interlayer insulating layers ILD. A bit line contact plug BLPG electrically connected to the conductive pad PAD may be provided inside the capping insulating layer CAP. The bit line contact plug BLPG may have a shape in which widths in the first and second directions D1 and D2 increase in the third direction D3.

A bit line BL may be provided on the capping insulating layer CAP and the bit line contact plug BLPG. The bit line BL corresponds to any one of the plurality of bit lines BL0 , BL1 , and BL2 shown in FIG. 1 , and may be formed of a conductive material to extend along the second direction D2 . The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1 , EL2 , and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through the bit line contact plug BLPG. Here, that the bit line BL is connected to the vertical channel structures VS may mean that it is connected to the vertical channel pattern VCP included in the vertical channel structures VS.

The three-dimensional flash memory having such a structure includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string selection line SSL, a voltage applied to each of the word lines WL0-WLn, and a ground selection line. A program operation, a read operation, and an erase operation may be performed based on the voltage applied to the GSL, the voltage applied to the common source line CSL, and the voltage applied to the back gate BG. For example, the 3D flash memory includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string select line SSL, a voltage applied to each of the word lines WL0 to WLn, and a ground select line GSL. ), a voltage applied to the common source line (CSL), and a voltage applied to the back gate (BG), a channel is formed in the vertical channel pattern (VCP) to transfer charges or holes to the data of the target memory cell. A program operation can be performed by transferring to a stored pattern (DSP).

In addition, the 3D flash memory according to another embodiment is not limited or not limited to the described structure, and according to an implementation example, a vertical channel pattern (VCP), a data storage pattern (DSP), a back gate (BG), and gate electrodes ( EL1, EL2, EL3), a bit line BL, and a common source line CSL may be implemented in various structures.

As the 3D flash memory having such a structure is manufactured through a stack stacking process, each of the stack structures ST may include an upper stack structure USS and a lower stack structure LSS. The lower stack structure LSS is disposed on the substrate SUB and may include gate electrodes EL1 and parts of EL2 alternately stacked in a vertical direction, and interlayer insulating layers ILD. The upper stack structure USS is stacked on the lower stack structure LSS and may include gate electrodes (part of EL2, EL3) and an interlayer insulating layer ILD that are alternately stacked in a vertical direction.

When the lower stack structure LSS and the upper stack structure USS are stacked, the vertical channel structures VS included in the lower stack structure LSS and the vertical channel structures VS included in the upper stack structure USS This misalignment problem may occur. For example, when the vertical channel patterns VCP of the lower stack structure LSS and the vertical channel patterns VCP of the upper stack structure USS are misaligned, a problem of deteriorating channel current characteristics may occur. Therefore, each of the stacked structures ST of the 3D flash memory is disposed between the upper stack structure USS and the lower stack structure LSS, and vertical channel patterns of each of the stack structures USS and LSS ( It may include connection units (CU) connecting VCP) to each other. The connection units CU are formed by portions of the buffer layer BU positioned between the upper stack structure USS and the lower stack structure LSS in the horizontal direction (first direction D1 and second direction D2). Since it is formed in the etched spaces, it can be accommodated by the buffer layer BU.

In addition, the connection portions CU formed on the inner walls of the spaces in which portions of the buffer layer BU in the horizontal direction are etched include channel holes CH of the upper stack structures USS and lower stack structures LSS, respectively. Since they are collectively formed through the same process as the vertical channel structures VS formed therein, each of the connection units CU includes a first connection unit CU1 formed of the same material as the data storage pattern DSP, A second connector CU2 formed of the same material as the channel pattern VCP and a third connector CU3 formed of the same material as the back gate BG may be included. In this case, when it is understood that the back gates BG of the upper and lower stack structures USS and LSS extend in the vertical direction, the third connection portion CU3 is an inner hole (where one back gate BG is extended). hole). That is, each of the connection units CU may include an inner hole through which the back gate BG extends in the vertical direction.

In particular, each of the connection units CU may have a shape in which a corner is curved while protruding in a horizontal direction more than each of the vertical channel patterns VCP. More specifically, each of the connection units CU may have a shape protruding in a horizontal direction more than each of the vertical channel patterns VCP by being formed to a size accommodating each of the vertical channel patterns VCP on a plane. In addition, the connection units CU may be formed at positions accommodating the vertical channel patterns VCP of the upper and lower stack structures USS and LSS to connect the vertical channel patterns VCP to each other.

As such, each of the connection units CU protrudes and has a curved corner, so that each of the connection units CU is formed on the sidewall of the remaining portion having an undercut shape after a portion of the buffer layer BU is etched. because it becomes That is, the sidewall on which wet etching has been performed on a portion of the buffer layer BU in the horizontal direction (the sidewall of the remaining portion after wet etching is performed) has an undercut shape, and each of the connection units CU has As it is formed on the sidewall of the remaining portion after wet etching is performed, it may have a curved corner while protruding in a horizontal direction.

To this end, the buffer layer BU may be formed of a material capable of performing wet etching. Here, the material on which wet etching may be performed may include at least one of silicon oxide or metal oxide (eg, silicon nitride, silicon oxide, silicon carbide, or silicon oxynitride).

As described above, the 3D flash memory includes the connection units CU to connect the vertical channel patterns VCP of each of the stack structures USS and LSS to each other, thereby solving a problem of deterioration of channel current characteristics.

The three-dimensional flash memory is manufactured through a stack lamination process and is described as including an upper stack structure (USS) and a lower stack structure (LSS). It may include stack structures (eg, upper stack structures USS, middle stack structures MSS, and lower stack structures LSS). In this case, the connecting units CU may be arranged in a connection portion of the stack structures with groups arranged in the horizontal direction (first direction D1 and second direction D2) spaced apart in the third direction D3. A plurality of buffer layers BU may be provided and spaced apart from each other in the third direction D3 to surround groups of the connecting units CU that are spaced apart from each other in the third direction D3.

FIG. 6 is a cross-sectional view for explaining another implementation example of connection parts and a buffer layer included in the 3D flash memory shown in FIG. 5 , and corresponds to a cross-section of FIG.

The 3D flash memory described below with reference to FIG. 6 has all components identical to the 3D flash memory described above with reference to FIG. 5 , but is characterized in that only the structure of the buffer layer BU is different. Accordingly, only the buffer layer BU having a different structure will be described below.

Each of the connection units CU shown in FIG. 6 may also have a shape with curved corners while protruding in a horizontal direction than each of the vertical channel patterns VCP. In this way, each of the connection parts CU has a curved corner while protruding, as described with reference to FIG. 5, each of the connection parts CU is undercut after a portion of the buffer layer BU is etched ( This is because it is formed on the sidewall of the remaining part having an undercut shape.

However, the buffer layer BU shown in FIG. 6 is etched through dry etching as well as wet etching as a plurality of layers L1, L2, and L3 having different etching ratios are vertically stacked and formed. It is different from the buffer layer BU shown in FIG. 5 in that the sidewall having this effect has an undercut shape. That is, the buffer layer BU is formed by vertically stacking a plurality of layers L1 , L2 , and L3 having different etching ratios, so that a portion of the buffer layer BU in the horizontal direction is etched. The sidewall (the sidewall of the remaining portion after etching) has an undercut shape, and each of the connection units CU is formed on the sidewall of the remaining portion after etching, protruding in the horizontal direction and having curved corners. can have a shape.

Regarding the fact that the buffer layer BU is formed by stacking a plurality of layers L1, L2, and L3 having different etching ratios in a vertical direction, the plurality of layers L1 to have an undercut shape on the etched sidewall. , L2, and L3), the layer L2 located at the center in the vertical direction may have a higher etching rate than the layers L1 and L3 located at the edge.

Although the buffer layer BU has been described as being composed of three layers (L1, L2, and L3), it may be composed of four or more layers without being limited or limited thereto. In this case, each of the four or more layers may have a higher etching rate closer to the center in the vertical direction and a lower etching rate closer to the edge.

7 is a flow chart showing a method of manufacturing a 3D flash memory having the structure shown in FIGS. 3 and 5, and FIGS. 8A to 8F are cross-sectional views illustrating the 3D flash memory to explain the method of manufacturing the 3D flash memory shown in FIG. 7. .

Referring to FIG. 7 , a method of manufacturing a 3D flash memory according to an embodiment is for manufacturing the 3D flash memory described with reference to FIGS. 3 and 5 and is performed by an automated and mechanized manufacturing system, Interlayer insulating films (ILD) and gate electrodes (parts of EL1 and EL2) extending in the horizontal direction and stacked alternately in the vertical direction, and interlayer insulating films (ILD) and gate electrodes (parts of EL1 and EL2) are formed. preparing a lower stack structure (LSS) including channel holes (CH) penetrating in the vertical direction (S710); forming a buffer layer BU on the lower stack structure LSS (S720); On top of the lower stack structure LSS on which the buffer layer BU is formed, interlayer insulating films ILD extending in the horizontal direction and alternately stacked in the vertical direction, a portion of the gate electrode EL2 and EL3, and interlayer insulating films forming an upper stack structure (USS) including channel holes (CH) penetrating the (ILD) and the gate electrodes (part of EL2, EL3) in a vertical direction (S730); forming channel connection holes (CCH) penetrating the buffer layer (BU) in a vertical direction based on the positions of the channel holes (CH) (S740); Performing wet etching on a portion of the buffer layer BU in the horizontal direction through the channel holes CH and the channel connection holes CCH so that the remaining portion has an undercut shape (S750) ; and vertical channel structures VS including a data storage pattern DSP and a vertical channel pattern VCP, respectively, on inner walls of the channel holes CH and sidewalls where the buffer layer BU is etched, in a vertical direction. It may include a step of extending and forming (S760). In particular, operation S760 connects the vertical channel patterns VCP extending from the upper stack structure USS and the vertical channel patterns VCP formed from the lower stack structure LSS to each other, and connecting the vertical channel patterns VCP to each other. ) forming connection units CU having curved corners while protruding more horizontally than each other.

Hereinafter, each step (S710 to S760) of FIG. 7 will be described in detail with reference to FIGS. 8A to 8F.

Referring to FIG. 8A , in step S710, the manufacturing system extends in the horizontal direction (eg, the first direction D1 and the second direction D2) on the substrate SUB and extends in the vertical direction (eg, the third direction ( D3)) through the alternately stacked interlayer insulating films ILD and gate electrodes EL1 and EL2, and through the interlayer insulating films ILD and part of gate electrodes EL1 and EL2 in the vertical direction. A lower stack structure LSS including channel holes CH may be prepared.

Although not described and illustrated as separate steps and drawings, in the manufacturing system before the step of preparing the lower stack structure LSS (S710), the interlayer insulating films ILD and the sacrificial layers SAC alternate in the vertical direction. Channel holes CH are formed in the stacked structure, the sacrificial layers SAC are selectively removed through the channel holes CH, and the gate regions GR are spaces from which the sacrificial layers SAC are removed. A step of forming gate electrodes (parts of EL1 and EL2) may be performed. That is, the manufacturing system performs the WL replacement process before step S710, and in step S710, the lower part including the interlayer insulating films ILD and gate electrodes EL1 and EL2 and the channel holes CH. A stack structure (LSS) can be prepared. Here, the selective removal of the sacrificial layers SAC may be performed not only through the channel holes CH but also through the isolation trench TR. In this case, a step of forming an isolation trench TR may precede step S710 .

In addition, it has been described that the WL replacement process is performed before the above step (S710) to prepare the lower stack structure (LSS) on which the gate electrodes (EL, part of EL2) are formed, but it is not limited or limited thereto, and the gate first (Gate The lower stack structure LSS on which the gate electrodes EL1 and EL2 are formed may be prepared through a first) process.

Since the buffer layer BU needs to be formed on the lower stack structure LSS in step S720 to be described later, the channel holes CH of the lower stack structure LSS may be filled with filling layers FL. The filling layers FL may be removed when channel connection holes are formed in step S740 to be described later.

Referring to FIG. 8B , in step S720, the manufacturing system may form a buffer layer BU on the lower stack structure LSS. In more detail, since wet etching of the buffer layer BU must be performed through step S750, the manufacturing system uses a material (at least one of silicon oxide and metal oxide) on which wet etching can be performed in step S720. The buffer layer BU may be formed of (eg, silicon nitride, silicon oxide, silicon carbide, or silicon oxynitride).

Referring to FIG. 8C , in step S730, the manufacturing system moves the upper part of the lower stack structure LSS on which the buffer layer BU is formed in a horizontal direction (eg, in the first direction D1 and the second direction D2). Interlayer insulating films (ILD) and gate electrodes (part of EL2, EL3) alternately stacked along the vertical direction (eg, the third direction D3) while being extended, and the interlayer insulating films (ILD) and gate electrodes ( An upper stack structure USS including channel holes CH penetrating a portion of EL2 and EL3 in a vertical direction may be formed.

Although not described and illustrated as separate steps and drawings, in the manufacturing system before the step of preparing the upper stack structure USS (S730), the interlayer insulating films ILD and the sacrificial layers SAC alternate in the vertical direction. Channel holes CH are formed in the stacked structure, the sacrificial layers SAC are selectively removed through the channel holes CH, and the gate regions GR are spaces from which the sacrificial layers SAC are removed. A step of forming the gate electrodes (part of EL2, EL3) may be performed. That is, the manufacturing system performs the WL replacement process between steps S720 and S730, thereby interlayer insulating films ILD and gate electrodes EL2 and part of EL3 and channel holes CH in step S730. ) It is possible to form an upper stack structure (USS) including. Here, the selective removal of the sacrificial layers SAC may be performed not only through the channel holes CH but also through the isolation trench TR. In this case, a step of forming an isolation trench TR may be preceded between steps S720 and S730 .

In addition, it has been described that the WL replacement process is performed before the above step (S730) to prepare the upper stack structure (USS) in which the gate electrodes (part of EL2, EL3) are formed, but it is not limited or limited thereto, and the gate first (Gate Through a first) process, an upper stack structure USS having gate electrodes EL2 and EL3 may be formed.

Referring to FIG. 8D , in step S740, the manufacturing system may form channel connection holes CCH penetrating the buffer layer BU in the vertical direction based on the positions of the channel holes CH. More specifically, the manufacturing system has upper and lower parts so that the channel holes CH included in the lower stack structure LSS and the channel holes CH included in the upper stack structure USS can be connected to each other through the channel connection holes CCH. Channel connection holes CCH may be formed based on positions of channel holes CH of each of the stack structures USS and LSS.

In the step of forming the channel connection holes (CCH) (S740), an anisotropic etching method using a mask pattern as an etch mask may be used. However, this is merely an example and various etching processes may be used in step S740.

Referring to FIG. 8E , in step S750, the manufacturing system wet-etches the portion 810 in the horizontal direction from the buffer layer BU through the channel holes CH and the channel connection holes CCH. ) can be performed. Due to wet etching, the remaining portion after etching may have an undercut shape 820 .

Referring to FIG. 8F, in step S760, the manufacturing system forms data storage patterns (DSP) and vertical channel patterns (VCP) on inner walls of the channel holes (CH) and sidewalls on which the buffer layer (BU) is etched. Each of the vertical channel structures VS may be formed to extend in the vertical direction. At this time, the sidewall on which the etching of the buffer layer BU is performed exists at a position extending in a horizontal direction from the inner walls of the channel holes CH, so that the data formed on the sidewall on which the etching of the buffer layer BU is performed. Both the storage pattern (DSP) and the vertical channel pattern (VCP) extend in the horizontal direction than the data storage pattern (DSP) and the vertical channel pattern (VCP) formed on the inner walls of the channel holes (CH) and have a protruding structure. can

In addition, since the remaining portion after etching the buffer layer BU has an undercut shape 820, both the data storage pattern DSP and the vertical channel pattern VCP formed on the sidewall where the buffer layer BU is etched. may have a shape with curved corners.

Therefore, in operation S760, the vertical channel patterns VCP extending from the upper stack structure USS and the vertical channel patterns VCP formed from the lower stack structure LSS are connected to each other, and the vertical channel patterns ( VCP) may include forming connection units (CU) 830 having curved corners while protruding in a horizontal direction than each other.

In the drawing, each of the vertical channel structures VS is shown as the structure shown in FIG. 3 including the vertical semiconductor pattern VSP, but is not limited thereto, and is not limited thereto, and the structure shown in FIG. 5 including the back gate BG. may be a rescue.

First, detailed steps of step 760 will be described on the assumption that each of the vertical channel structures VS includes a vertical semiconductor pattern VSP.

In step S760, the formation of the connection parts CU 830 has been described with an emphasis on forming the vertical channel structures VS in the extension, but step S760 is performed on the inner wall and the buffer layer of each of the channel holes CH. a first step of extending and forming the data storage pattern DSP in a vertical direction (eg, a third direction D3) to cover the sidewall on which the BU has been etched; a second step of extending and forming the vertical channel pattern VCP covering a portion of the sidewall of the data storage pattern DSP in a vertical direction (eg, a third direction D3); a third step of forming a vertical semiconductor pattern (VSP) filling a space surrounded by the vertical channel pattern (VCP); and a fourth step of forming a conductive pad PAD filling a space surrounded by a portion of a sidewall of the data storage pattern DSP, an upper surface of the vertical channel pattern VCP, and an upper surface of the vertical semiconductor pattern VSP. .

In more detail, the second step of extending and forming the vertical channel pattern VCP includes forming the first portion VCP1 covering the lower sidewall of the data storage pattern DSP and contacting the substrate SUB. step; and a 2-2 step of forming a second portion VCP2 covering the upper sidewall of the data storage pattern DSP on the first portion VCP1.

Since materials forming each of the data storage pattern DSP, vertical channel pattern VCP, vertical semiconductor pattern VSP, and conductive pad PAD have been described with reference to FIGS. 3 and 5, a detailed description thereof will be omitted. do.

In the first step of extending and forming the data storage pattern DSP, the second step of extending and forming the vertical channel pattern VCP, and the third step of forming the vertical semiconductor pattern VSP, the data storage pattern DSP, Each of the channel pattern VCP and the vertical semiconductor pattern VSP may be formed by a chemical vapor deposition method or an atomic layer deposition method.

The manufacturing system includes the 4th step of forming the conductive pad PAD, the 4-1 step of recessing the top of the vertical channel pattern VCP and the top of the vertical semiconductor pattern VSP, and the doped semiconductor in the recessed region. It may be subdivided into a 4-2 step of filling a material or a conductive material.

When each of the vertical channel structures VS has a structure including a back gate BG instead of the vertical semiconductor pattern VSP, step 760 is performed on the inner wall of each of the channel holes CH and the buffer layer BU. A first step of extending and forming the data storage pattern DSP in a vertical direction (eg, a third direction D3) to cover the etched sidewall; a second step of extending and forming the vertical channel pattern VCP covering a portion of the sidewall of the data storage pattern DSP in a vertical direction (eg, a third direction D3); a third step of extending and forming the insulating film INS in the vertical direction (eg, in the third direction D3) in the inner hole of the vertical channel pattern VCP; a fourth step of forming a back gate BG extending in a vertical direction (eg, in a third direction D3 ) in an inner hole of the insulating film INS; and a fifth step of forming conductive pads PAD filling a space surrounded by a portion of a sidewall of the data storage pattern DSP and an upper surface of the vertical channel pattern VCP.

Since the materials forming the data storage pattern DSP, the vertical channel pattern VCP, the back gate BG, and the conductive pad PAD have been described with reference to FIGS. 3 and 5, a detailed description thereof will be omitted. .

In the first step of extending and forming the data storage pattern DSP, the second step of extending and forming the vertical channel pattern VCP, and the third step of forming the insulating film INT, the data storage pattern DSP and the vertical channel pattern Each of the (VCP) and the insulating film (INS) may be formed by a chemical vapor deposition method or an atomic layer deposition method.

The manufacturing system includes the fifth step of forming the conductive pad PAD, the 5-1 step of recessing the top of the vertical channel pattern VCP, and the 5-1 step of filling the recessed region with a doped semiconductor material or conductive material. It can be subdivided into two stages.

In addition, although not described as a separate step, the manufacturing system includes, in addition to steps S710 to S760, forming an isolation trench TR and performing a WL replacement process through the isolation trench TR (WL It can be omitted if the replacement process is performed through the channel holes (CH), a step of forming a common source region (CSR) in the substrate (SUB) exposed through the isolation trench (TR), and a sidewall of the isolation trench (TR). Forming a common source plug (CSP) filling an inner space of the covering insulating spacer (SP) and the isolation trench (TR) surrounded by the insulating spacer (SP), on the vertical channel structures (VS) and the common source plug (CSP) forming a capping insulating film (CAP); forming a bit line contact plug (BLPG) passing through the capping insulating film (CAP) and electrically connected to the conductive pad (PAD); and forming a bit line on the capping insulating film (CAP). A step of extending and forming the bit line BL electrically connected to the contact plug BLPG along the second direction D2 may be further included.

9 is a flow chart illustrating a method of manufacturing a 3D flash memory having the structure shown in FIGS. 4 and 6, and FIGS. 10A to 10F are cross-sectional views illustrating the 3D flash memory to explain the manufacturing method shown in FIG. 9. .

Referring to FIG. 9 , a method of manufacturing a 3D flash memory according to another embodiment is for manufacturing the 3D flash memory described with reference to FIGS. 4 and 6 and is performed by an automated and mechanized manufacturing system, Interlayer insulating films (ILD) and gate electrodes (parts of EL1 and EL2) extending in the horizontal direction and stacked alternately in the vertical direction, and interlayer insulating films (ILD) and gate electrodes (parts of EL1 and EL2) are formed. Preparing a lower stack structure (LSS) including channel holes (CH) penetrating in the vertical direction (S910); forming a buffer layer BU in which a plurality of layers L1, L2, and L3 having different etching ratios are stacked in a vertical direction on top of the lower stack structure LSS (S920); On top of the lower stack structure LSS on which the buffer layer BU is formed, interlayer insulating films ILD extending in the horizontal direction and alternately stacked in the vertical direction, a portion of the gate electrode EL2 and EL3, and interlayer insulating films forming an upper stack structure (USS) including channel holes (CH) penetrating the (ILD) and the gate electrodes (part of EL2, EL3) in a vertical direction (S930); forming channel connection holes (CCH) penetrating the buffer layer (BU) in a vertical direction based on the positions of the channel holes (CH) (S940); Etching a portion of the buffer layer BU in a horizontal direction through the channel holes CH and the channel connection holes CCH so that the remaining portion has an undercut shape (S950); and vertical channel structures VS including a data storage pattern DSP and a vertical channel pattern VCP, respectively, on inner walls of the channel holes CH and sidewalls where the buffer layer BU is etched, in a vertical direction. It may include a step of extending and forming (S960). Particularly, in operation S960 , the vertical channel patterns VCP extending from the upper stack structure USS and the vertical channel patterns VCP formed from the lower stack structure LSS are connected to each other to form the vertical channel patterns VCP. ) forming connection units CU having curved corners while protruding more horizontally than each other.

Hereinafter, each step (S910 to S960) of FIG. 9 will be described in detail with reference to FIGS. 10A to 10F.

Referring to FIG. 10A , in step S910, the manufacturing system extends in the horizontal direction (eg, the first direction D1 and the second direction D2) on the substrate SUB and extends in the vertical direction (eg, the third direction ( D3)) through the alternately stacked interlayer insulating films ILD and gate electrodes EL1 and EL2, and through the interlayer insulating films ILD and part of gate electrodes EL1 and EL2 in the vertical direction. A lower stack structure LSS including channel holes CH may be prepared.

Although not described and illustrated as separate steps and drawings, in the manufacturing system before the step of preparing the lower stack structure LSS (S910), the interlayer insulating films ILD and the sacrificial layers SAC alternate in the vertical direction. Channel holes CH are formed in the stacked structure, the sacrificial layers SAC are selectively removed through the channel holes CH, and the gate regions GR are spaces from which the sacrificial layers SAC are removed. A step of forming gate electrodes (parts of EL1 and EL2) may be performed. That is, the manufacturing system performs the WL replacement process before step S910, and in step S910, the lower part including the interlayer insulating films ILD and gate electrodes EL1 and EL2 and the channel holes CH. A stack structure (LSS) can be prepared. Here, the selective removal of the sacrificial layers SAC may be performed not only through the channel holes CH but also through the isolation trench TR. In this case, a step of forming an isolation trench TR may precede step S710 .

In addition, it has been described that the WL replacement process is performed prior to the above step (S910) to prepare the lower stack structure (LSS) on which the gate electrodes (EL, part of EL2) are formed, but it is not limited or limited thereto, and the gate first (Gate The lower stack structure LSS on which the gate electrodes EL1 and EL2 are formed may be prepared through a first) process.

Since the buffer layer BU must be formed on the lower stack structure LSS in step S920 to be described later, the channel holes CH of the lower stack structure LSS may be filled with filling layers FL. The filling layers FL may be removed when channel connection holes are formed in step S940 to be described later.

Referring to FIG. 10B , in step S920, the manufacturing system includes a buffer layer BU in which a plurality of layers L1, L2, and L3 having different etching ratios are vertically stacked on top of the lower stack structure LSS. can form In more detail, as a result of etching the buffer layer BU through step S950, since the sidewall of the remaining portion must have an undercut shape, in step S920, the manufacturing system includes a plurality of layers L1, L2, and L3. The layer L2 located at the center in the vertical direction may be formed of a material having a higher etching rate than the layers L1 and L3 located at the edges.

When the buffer layer BU is composed of four or more layers, the manufacturing system has a buffer layer BU so that each of the four or more layers has a higher etch rate closer to the center in the vertical direction and a lower etch rate closer to the edge. can form

Referring to FIG. 10C , in step S930, the manufacturing system moves the upper part of the lower stack structure LSS on which the buffer layer BU is formed in a horizontal direction (eg, in the first direction D1 and the second direction D2). Interlayer insulating films (ILD) and gate electrodes (part of EL2, EL3) alternately stacked along the vertical direction (eg, the third direction D3) while being extended, and the interlayer insulating films (ILD) and gate electrodes ( An upper stack structure USS including channel holes CH penetrating a portion of EL2 and EL3 in a vertical direction may be formed.

Although not described and illustrated as separate steps and drawings, in the manufacturing system before the step of preparing the upper stack structure USS (S930), the interlayer insulating films ILD and the sacrificial layers SAC alternate in the vertical direction. Channel holes CH are formed in the stacked structure, the sacrificial layers SAC are selectively removed through the channel holes CH, and the gate regions GR are spaces from which the sacrificial layers SAC are removed. A step of forming the gate electrodes (part of EL2, EL3) may be performed. That is, the manufacturing system performs the WL replacement process between steps S920 and S930, thereby interlayer insulating films ILD and gate electrodes EL2 and part of EL3 and channel holes CH in step S930. ) It is possible to form an upper stack structure (USS) including. Here, the selective removal of the sacrificial layers SAC may be performed not only through the channel holes CH but also through the isolation trench TR. In this case, a step of forming an isolation trench TR may be preceded between steps S920 and S930 .

In addition, it has been described that the WL replacement process is performed before the above step (S930) to prepare the upper stack structure (USS) on which the gate electrodes (part of EL2, EL3) are formed, but it is not limited or limited thereto, and the gate first (Gate Through a first) process, an upper stack structure USS having gate electrodes EL2 and EL3 may be formed.

Referring to FIG. 10D , in step S940, the manufacturing system may form channel connection holes CCH penetrating the buffer layer BU in the vertical direction based on the positions of the channel holes CH. More specifically, the manufacturing system has upper and lower parts so that the channel holes CH included in the lower stack structure LSS and the channel holes CH included in the upper stack structure USS can be connected to each other through the channel connection holes CCH. Channel connection holes CCH may be formed based on positions of channel holes CH of each of the stack structures USS and LSS.

In the step of forming the channel connection holes (CCH) (S940), an anisotropic etching method using a mask pattern as an etch mask may be used. However, this is merely an example and various etching processes may be used in step S940.

Referring to FIG. 10E, in step S950, the manufacturing system performs etching on the portion 1010 in the horizontal direction from the buffer layer BU through the channel holes CH and the channel connection holes CCH. can be done As described above, since the buffer layer BU is formed by vertically stacking a plurality of layers L1, L2, and L3 having different etching ratios, dry etching as well as wet etching is used as an etching method. Even if it is, the remaining portion after etching may have an undercut shape 1020 .

Referring to FIG. 10F, in step S960, the manufacturing system forms data storage patterns (DSP) and vertical channel patterns (VCP) on inner walls of the channel holes (CH) and sidewalls on which the buffer layer (BU) is etched. Each of the vertical channel structures VS may be formed to extend in the vertical direction. At this time, the sidewall on which the etching of the buffer layer BU is performed exists at a position extending in a horizontal direction from the inner walls of the channel holes CH, so that the data formed on the sidewall on which the etching of the buffer layer BU is performed. Both the storage pattern (DSP) and the vertical channel pattern (VCP) extend in the horizontal direction than the data storage pattern (DSP) and the vertical channel pattern (VCP) formed on the inner walls of the channel holes (CH) and have a protruding structure. can

In addition, since the remaining portion after etching the buffer layer BU has an undercut shape 1020, both the data storage pattern DSP and the vertical channel pattern VCP formed on the sidewall on which the buffer layer BU is etched. may have a shape with curved corners.

Accordingly, in operation S960, the vertical channel patterns VCP extending from the upper stack structure USS and the vertical channel patterns VCP extending from the lower stack structure LSS are connected to each other, and the vertical channel patterns ( VCP) may include forming connection units (CU) 1030 having curved corners while protruding in a horizontal direction than each other.

In the drawing, each of the vertical channel structures VS is shown as having the structure shown in FIG. 5 including a back gate BG, but is not limited thereto and is shown in FIG. 3 including a vertical semiconductor pattern VSP. may be a rescue.

First, detailed steps of step 960 will be described on the assumption that each of the vertical channel structures VS includes a back gate BG.

In step S960, forming the vertical channel structures VS has been described with an emphasis on forming the connection parts CU 1030, but step S960 is performed on the inner wall and the buffer layer of each of the channel holes CH. a first step of extending and forming the data storage pattern DSP in a vertical direction (eg, a third direction D3) to cover the sidewall on which the BU has been etched; a second step of extending and forming the vertical channel pattern VCP covering a portion of the sidewall of the data storage pattern DSP in a vertical direction (eg, a third direction D3); a third step of extending and forming the insulating film INS in the vertical direction (eg, in the third direction D3) in the inner hole of the vertical channel pattern VCP; a fourth step of forming a back gate BG extending in a vertical direction (eg, in a third direction D3 ) in an inner hole of the insulating film INS; and a fifth step of forming conductive pads PAD filling a space surrounded by a portion of a sidewall of the data storage pattern DSP and an upper surface of the vertical channel pattern VCP.

Since the materials forming the data storage pattern DSP, the vertical channel pattern VCP, the back gate BG, and the conductive pad PAD have been described with reference to FIGS. 3 and 5, a detailed description thereof will be omitted. .

In the first step of extending and forming the data storage pattern DSP, the second step of extending and forming the vertical channel pattern VCP, and the third step of forming the insulating film INT, the data storage pattern DSP and the vertical channel pattern Each of the (VCP) and the insulating film (INS) may be formed by a chemical vapor deposition method or an atomic layer deposition method.

The manufacturing system includes the fifth step of forming the conductive pad PAD, the 5-1 step of recessing the top of the vertical channel pattern VCP, and the 5-1 step of filling the recessed region with a doped semiconductor material or conductive material. It can be subdivided into two stages.

When each of the vertical channel structures VS has a structure including a vertical semiconductor pattern VSP instead of a back gate BG, step S960 is performed on the inner wall of each of the channel holes CH and the buffer layer BU. A first step of extending and forming the data storage pattern DSP in a vertical direction (eg, a third direction D3) to cover the etched sidewall; a second step of extending and forming the vertical channel pattern VCP covering a portion of the sidewall of the data storage pattern DSP in a vertical direction (eg, a third direction D3); a third step of forming a vertical semiconductor pattern (VSP) filling a space surrounded by the vertical channel pattern (VCP); and a fourth step of forming a conductive pad PAD filling a space surrounded by a portion of a sidewall of the data storage pattern DSP, an upper surface of the vertical channel pattern VCP, and an upper surface of the vertical semiconductor pattern VSP. .

In more detail, the second step of extending and forming the vertical channel pattern VCP includes forming the first portion VCP1 covering the lower sidewall of the data storage pattern DSP and contacting the substrate SUB. step; and a 2-2 step of forming a second portion VCP2 covering the upper sidewall of the data storage pattern DSP on the first portion VCP1.

Since materials forming each of the data storage pattern DSP, vertical channel pattern VCP, vertical semiconductor pattern VSP, and conductive pad PAD have been described with reference to FIGS. 3 and 5, a detailed description thereof will be omitted. do.

In the first step of extending and forming the data storage pattern DSP, the second step of extending and forming the vertical channel pattern VCP, and the third step of forming the vertical semiconductor pattern VSP, the data storage pattern DSP, Each of the channel pattern VCP and the vertical semiconductor pattern VSP may be formed by a chemical vapor deposition method or an atomic layer deposition method.

The manufacturing system includes the 4th step of forming the conductive pad PAD, the 4-1 step of recessing the top of the vertical channel pattern VCP and the top of the vertical semiconductor pattern VSP, and the doped semiconductor in the recessed region. It may be subdivided into a 4-2 step of filling a material or a conductive material.

In addition, although not described as a separate step, the manufacturing system includes, in addition to steps S910 to S960, forming an isolation trench TR and performing a WL replacement process through the isolation trench TR (WL It can be omitted if the replacement process is performed through the channel holes (CH), a step of forming a common source region (CSR) in the substrate (SUB) exposed through the isolation trench (TR), and a sidewall of the isolation trench (TR). Forming a common source plug (CSP) filling an inner space of the covering insulating spacer (SP) and the isolation trench (TR) surrounded by the insulating spacer (SP), on the vertical channel structures (VS) and the common source plug (CSP) forming a capping insulating film (CAP); forming a bit line contact plug (BLPG) passing through the capping insulating film (CAP) and electrically connected to the conductive pad (PAD); and forming a bit line on the capping insulating film (CAP). A step of extending and forming the bit line BL electrically connected to the contact plug BLPG along the second direction D2 may be further included.

11 is a perspective view schematically illustrating an electronic system including a 3D flash memory according to embodiments.

Referring to FIG. 11 , an electronic system 1100 including a 3D flash memory according to embodiments includes a main board 1101, a controller 1102 mounted on the main board 1101, and one or more semiconductor packages 1103. ) and DRAM 1104.

The semiconductor package 1103 and the DRAM 1104 may be connected to the controller 1102 through wiring patterns 1105 provided on the main board 1101 .

The main board 1101 may include a connector 1106 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 1106 may vary depending on the communication interface between the electronic system 1100 and an external host.

The electronic system 1100 may, for example, use any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIExpress), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). Depending on one, you can communicate with external hosts. The electronic system 1100 may operate by power supplied from an external host through, for example, a connector 1106 . The electronic system 1100 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to the controller 1102 and the semiconductor package 1103 .

The controller 1102 can write data to the semiconductor package 1103 or read data from the semiconductor package 1103 and can improve the operating speed of the electronic system 1100 .

The DRAM 1104 may be a buffer memory for mitigating a speed difference between the semiconductor package 1103, which is a data storage space, and an external host. The DRAM 1104 included in the electronic system 1100 may also operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 1103 . When the electronic system 1100 includes the DRAM 1104 , the controller 1102 may further include a DRAM controller for controlling the DRAM 1104 in addition to the NAND controller for controlling the semiconductor package 1103 .

The semiconductor package 1103 may include first and second semiconductor packages 1103a and 1103b spaced apart from each other. Each of the first and second semiconductor packages 1103a and 1103b may be a semiconductor package including a plurality of semiconductor chips 1120 . Each of the first and second semiconductor packages 1103a and 1103b includes a package substrate 1110 , semiconductor chips 1120 on the package substrate 1110 , and adhesive layers 1130 disposed on a lower surface of each of the semiconductor chips 1120 . ), connection structures 1140 electrically connecting the semiconductor chips 1120 and the package substrate 1110 and a molding layer 1150 covering the semiconductor chips 1120 and the connection structures 1140 on the package substrate 1110 can include

The package substrate 1110 may be a printed circuit board including package upper pads 1111 . Each of the semiconductor chips 1120 may include input/output pads 1121 . Each of the semiconductor chips 1120 may include the 3D flash memory described above with reference to FIGS. 3 to 6 . More specifically, each of the semiconductor chips 1120 may include gate stack structures 1122 and memory channel structures 1123 . The gate stack structures 1122 may correspond to the above-described stack structures ST, and the memory channel structures 1123 may correspond to the above-described vertical channel structures VS.

The connection structures 1140 may be, for example, bonding wires electrically connecting the input/output pads 1121 and the package upper pads 1111 . Accordingly, in each of the first and second semiconductor packages 1103a and 1103b, the semiconductor chips 1120 may be electrically connected to each other using a bonding wire method, and the package upper pads 1111 of the package substrate 1110 and can be electrically connected. According to example embodiments, in each of the first and second semiconductor packages 1103a and 1103b, the semiconductor chips 1120 are connected to the through electrode (Through Silicon Via) instead of the bonding wire type connection structures 1140. may be electrically connected to each other.

Unlike shown, the controller 1102 and the semiconductor chips 1120 may be included in one package. The controller 1102 and the semiconductor chips 1120 may be mounted on a separate interposer substrate different from the main substrate 1101, and the controller 1102 and the semiconductor chips 1120 may be connected to each other by wiring provided on the interposer substrate. have.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

Claims (13)

Interlayer insulating films and gate electrodes extending in the horizontal direction and alternately stacked in the vertical direction, and vertical channel structures penetrating the interlayer insulating films and the gate electrodes and extending in the vertical direction-the vertical channel structures Each of the stack structures including a data storage pattern extending in the vertical direction and a vertical channel pattern covering an inner wall of the data storage pattern and extending in the vertical direction - the stack structures include: stacked in the vertical direction; and
A buffer layer including connecting parts disposed between the stack structures and connecting vertical channel patterns of each of the stack structures to each other.
Including.
Each of the connection parts,
The three-dimensional flash memory, characterized in that the corner of the three-dimensional flash memory has a curved shape while protruding in the horizontal direction than each of the vertical channel patterns. According to claim 1,
Each of the connection parts,
The three-dimensional flash memory is formed on a sidewall on which wet etching has been performed on a portion of the buffer layer in the horizontal direction and has a curved corner. According to claim 2,
The buffer layer,
A three-dimensional flash memory, characterized in that formed of a material capable of performing the wet etching. According to claim 3,
The material forming the buffer layer,
A three-dimensional flash memory comprising at least one of silicon oxide and metal oxide. According to claim 1,
Each of the connection parts,
As the buffer layer is formed by stacking a plurality of layers having different etching ratios in the vertical direction, a portion of the buffer layer in the horizontal direction is formed on the sidewall on which etching has been performed, so that the corner has a curved shape. Characterized by a three-dimensional flash memory. According to claim 5,
Among the plurality of layers, the layer located in the center in the vertical direction,
The three-dimensional flash memory, characterized in that it has a higher etching rate than the layers positioned at the edge in the vertical direction among the plurality of layers. According to claim 1,
When each of the vertical channel patterns includes a back gate extending in the vertical direction while at least partially surrounded by each of the vertical channel patterns, each of the connection parts,
The three-dimensional flash memory, characterized in that the back gate comprises an inner hole extending in the vertical direction. According to claim 1,
Each of the connection parts,
The three-dimensional flash memory comprising a portion formed of the same material as the vertical channel patterns. According to claim 1,
Each of the connection parts,
A three-dimensional flash memory characterized in that it is formed in a size and position to accommodate each of the vertical channel patterns on a plane. preparing a lower stack structure including interlayer insulating films and gate electrodes extending in a horizontal direction and alternately stacked in a vertical direction, and channel holes penetrating the interlayer insulating films and the gate electrodes in the vertical direction;
forming a buffer layer on top of the lower stack structure;
The interlayer insulating films and the gate electrodes, which extend in the horizontal direction and are alternately stacked in the vertical direction, on the upper part of the lower stack structure on which the buffer layer is formed, and the interlayer insulating films and the gate electrodes are formed in the vertical direction. forming an upper stack structure including channel holes passing through;
forming channel connection holes penetrating the buffer layer in the vertical direction based on positions of the channel holes;
performing wet etching on a portion of the buffer layer in the horizontal direction through the channel holes and the channel connection holes so that a remaining portion has an undercut shape; and
forming vertical channel structures each including a data storage pattern and a vertical channel pattern extending in the vertical direction on inner walls of the channel holes and sidewalls where the buffer layer has been etched;
including,
Forming the vertical channel structures extending in the vertical direction,
Connecting the vertical channel patterns extending from the upper stack structure and the vertical channel patterns extending from the lower stack structure to each other, forming connection parts having curved corners while protruding in the horizontal direction from each of the vertical channel patterns. A method of manufacturing a three-dimensional flash memory, comprising the steps of: According to claim 1,
Forming the buffer layer,
The method of manufacturing a three-dimensional flash memory, characterized in that the step of forming the buffer layer with a material capable of performing the wet etching. preparing a lower stack structure including interlayer insulating films and gate electrodes extending in a horizontal direction and alternately stacked in a vertical direction, and channel holes penetrating the interlayer insulating films and the gate electrodes in the vertical direction;
forming a buffer layer on top of the lower stack structure in which a plurality of layers having different etching ratios are stacked in the vertical direction;
The interlayer insulating films and the gate electrodes, which extend in the horizontal direction and are alternately stacked in the vertical direction, on the upper part of the lower stack structure on which the buffer layer is formed, and the interlayer insulating films and the gate electrodes are formed in the vertical direction. forming an upper stack structure including channel holes passing through;
forming channel connection holes penetrating the buffer layer in the vertical direction based on positions of the channel holes;
etching a portion of the buffer layer in the horizontal direction through the channel holes and the channel connection holes so that a remaining portion has an undercut shape; and
forming vertical channel structures each including a data storage pattern and a vertical channel pattern extending in the vertical direction on inner walls of the channel holes and sidewalls where the buffer layer has been etched;
including,
Forming the vertical channel structures extending in the vertical direction,
Connecting the vertical channel patterns extending from the upper stack structure and the vertical channel patterns extending from the lower stack structure to each other, forming connection parts having curved corners while protruding in the horizontal direction from each of the vertical channel patterns. A method of manufacturing a three-dimensional flash memory, comprising the steps of: According to claim 12,
Forming the buffer layer,
Forming a layer positioned at the center of the plurality of layers in the vertical direction with a material having a higher etching ratio than layers positioned at the edges in the vertical direction among the plurality of layers.
Method for manufacturing a three-dimensional flash memory comprising a.

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