KR102624193B1 - Improved program operation method of three dimensional flash memory - Google Patents

Abstract

An improved program operation method for 3D flash memory is disclosed. According to one embodiment, word lines extend in the horizontal direction on the substrate and are arranged to be spaced apart in the vertical direction; and cell strings extending in the vertical direction and passing through the word lines - each of the cell strings covers a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern and extending in the vertical direction. A method of programming a three-dimensional flash memory, including a vertical channel pattern formed, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines, include: applying a negative voltage to a bit line of a selected cell string corresponding to a target memory cell that is the target of the program operation; applying a program voltage to a selected word line corresponding to the target memory cell among the word lines; and in response to applying the negative voltage to the bit line of the selected cell string and applying the program voltage to the selected word line, forming a channel in the vertical channel pattern included in the selected cell string to obtain the object. It may include performing the program operation on a memory cell.

Description

Improved program operation method of 3D flash memory {IMPROVED PROGRAM OPERATION METHOD OF THREE DIMENSIONAL FLASH MEMORY}

The following embodiments relate to 3D flash memory, and more specifically, to a technology for an improved program operation method of 3D flash memory.

Flash memory devices are electrically erasable programmable read only memory (EEPROM) that can be electrically programmed and erased by electrically controlling the input and output of data by Fowler-Nordheimtunneling (Fowler-Nordheimtunneling) or hot electron injection. , can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

In these flash memory devices, it is required to increase the degree of integration to meet the excellent performance and low price demanded by consumers, and a three-dimensional structure in which memory cell transistors are arranged vertically to form a cell string has been proposed.

3D flash memory has recently become increasingly advanced and integrated, and problems such as a decrease in program operation speed and a decrease in cell current are emerging due to the increased level and integration. Accordingly, in order to solve the above shortcomings, a method of applying the program voltage (Vpgm) to a higher value than the existing one has been proposed, but this method has the problem of placing a burden on the circuit of the 3D flash memory and adversely affecting memory reliability. .

Accordingly, the following embodiments are intended to propose techniques for solving the problems described.

One embodiment includes a three-dimensional flash memory that uses a relatively low program voltage by applying a negative voltage to the bit line of a selected cell string to solve problems caused by a high program voltage, a method of programming the same, and the same. We propose an electronic system that

Additionally, embodiments propose a three-dimensional flash memory that applies a positive voltage to a back gate included in a vertical channel pattern to improve cell current, a read operation method therefor, and an electronic system including the same.

However, the technical problems to be solved by the present invention are not limited to the above problems, and may be expanded in various ways without departing from the technical spirit and scope of the present invention.

According to one embodiment, word lines extend in the horizontal direction on the substrate and are arranged to be spaced apart in the vertical direction; and cell strings extending in the vertical direction and passing through the word lines - each of the cell strings covers a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern and extending in the vertical direction. A method of programming a three-dimensional flash memory, including a vertical channel pattern formed, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines, include: applying a negative voltage to a bit line of a selected cell string corresponding to a target memory cell that is the target of the program operation; applying a program voltage to a selected word line corresponding to the target memory cell among the word lines; and in response to applying the negative voltage to the bit line of the selected cell string and applying the program voltage to the selected word line, forming a channel in the vertical channel pattern included in the selected cell string to obtain the object. It may include performing the program operation on a memory cell.

According to one aspect, the step of applying a negative value voltage to the bit line of the selected cell string includes the vertical channel pattern included in the selected cell string where the voltage between the selected word line and the bit line of the selected cell string is It may be characterized as a step of applying a negative voltage to the bit line of the selected cell string so that it is directly transmitted to.

According to another aspect, the step of applying a negative voltage to the bit line of the selected cell string includes applying a negative voltage used when the 3D flash memory performs an operation other than the program operation. It may be characterized as a step of applying the negative voltage generated from the generating circuit to the bit line of the selected cell string.

According to another aspect, applying a program voltage to the selected word line includes applying a pass voltage to each of the unselected word lines other than the selected word line. You can do this.

According to another aspect, when the vertical channel pattern includes a back gate extending in the vertical direction with at least a portion surrounded by the vertical channel pattern, applying a program voltage to the selected word line includes , floating each of the remaining unselected word lines except for the selected word line; and applying a pass voltage to the back gate.

According to another aspect, the step of floating each of the unselected word lines may cause disturbance due to the pass voltage being applied to the unselected word lines as each of the unselected word lines is floated. It can be characterized by preventing the phenomenon.

According to another aspect, when the vertical channel pattern includes a back gate extending in the vertical direction with at least a portion surrounded by the vertical channel pattern, applying a program voltage to the selected word line includes , applying a ground voltage to each of the unselected word lines, excluding the selected word line; and applying a pass voltage to the back gate.

According to another aspect, the step of floating each of the unselected word lines is performed by applying the pass voltage to the unselected word lines as the ground voltage is applied to each of the unselected word lines. It may be characterized by preventing interference.

According to one embodiment, a three-dimensional flash memory includes word lines that extend in the horizontal direction on a substrate and are spaced apart in the vertical direction; and cell strings extending in the vertical direction and passing through the word lines - each of the cell strings covers a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern and extending in the vertical direction. and a vertical channel pattern formed, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines, and during a program operation, a target of the program operation among the cell strings It may be configured to apply a negative voltage to the bit line of the selected cell string corresponding to the target memory cell.

According to one embodiment, word lines extend in the horizontal direction on the substrate and are arranged to be spaced apart in the vertical direction; and cell strings extending in the vertical direction and passing through the word lines - each of the cell strings covers a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern and extending in the vertical direction. A vertical channel pattern is formed, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines, and the vertical channel pattern is at least partially surrounded by the vertical channel pattern. A method of a read operation of a three-dimensional flash memory, including a back gate extending in a vertical direction, includes: a read operation method of a selected cell string corresponding to a target memory cell that is the target of the read operation among the cell strings; applying a first voltage higher than the ground voltage; applying a verification voltage to a selected word line corresponding to the target memory cell among the word lines; applying a read voltage to each of the unselected word lines other than the selected word line; applying a positive voltage to the back gate; and a first voltage is applied to the bit line of the selected cell string, the verification voltage is applied to the selected word line, a pass voltage is applied to each of the unselected word lines, and the positive voltage is applied to the back gate. In response to being applied, performing the read operation on the target memory cell.

According to one aspect, the step of applying a positive voltage to the back gate includes applying the positive voltage to the back gate to improve cell current in the three-dimensional flash memory. It can be characterized.

Embodiments may propose a three-dimensional flash memory that uses a relatively low program voltage by applying a negative voltage to the bit line of the selected cell string, a program operation method thereof, and an electronic system including the same.

Therefore, the 3D flash memory according to one embodiment can solve the problem caused by a high program voltage - a problem that places a burden on the circuit of the 3D flash memory - and can improve memory reliability.

Additionally, embodiments may propose a three-dimensional flash memory that applies a positive voltage to a back gate included in a vertical channel pattern, a read operation method thereof, and an electronic system including the same.

Accordingly, the 3D flash memory according to one embodiment can achieve the effect of improving cell current.

However, the effects of the present invention are not limited to the above effects, and may be expanded in various ways without departing from the technical spirit and scope of the present invention.

1 is a simplified circuit diagram showing an array of three-dimensional flash memory according to one embodiment.
Figure 2 is a plan view showing the structure of a three-dimensional flash memory according to an embodiment.
FIG. 3 is a cross-sectional view showing the structure of a three-dimensional flash memory according to an embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.
FIG. 4 is a cross-sectional view showing the structure of a three-dimensional flash memory according to another embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.
FIG. 5 is a flow chart showing a program operation method of the 3D flash memory shown in FIGS. 3 and 4.
FIG. 6 is a cross-sectional view showing the structure of the three-dimensional flash memory shown in FIG. 3 to explain the program operation method shown in FIG. 5.
FIG. 7 is a cross-sectional view showing the structure of the three-dimensional flash memory shown in FIG. 4 to explain the program operation method shown in FIG. 5.
FIG. 8 is a flow chart showing a read operation method of the 3D flash memory shown in FIG. 4.
FIG. 9 is a cross-sectional view showing the structure of the three-dimensional flash memory shown in FIG. 4 to explain the read operation method shown in FIG. 8.
FIGS. 10 and 11 are diagrams showing pulses of applied voltages in a program operation and a read operation performed by the three-dimensional flash memory shown in FIG. 4.
Figure 12 is a perspective view schematically showing an electronic system including a three-dimensional flash memory according to embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or limited by the examples. Additionally, the same reference numerals in each drawing indicate the same members.

Additionally, terminologies used in this specification are terms used to appropriately express preferred embodiments of the present invention, and may vary depending on the intention of the viewer, operator, or customs in the field to which the present invention belongs. Therefore, definitions of these terms should be made based on the content throughout this specification. For example, in this specification, singular forms also include plural forms unless specifically stated otherwise in the context. Additionally, as used herein, “comprises” and/or “comprising” refers to a referenced component, step, operation, and/or element that includes one or more other components, steps, operations, and/or elements. It does not exclude the presence or addition of elements. Additionally, although terms such as first and second are used in this specification to describe various areas, directions, and shapes, these areas, directions, and shapes should not be limited by these terms. These terms are merely used to distinguish one area, direction or shape from another area, direction or shape. Accordingly, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

Additionally, it should be understood that the various embodiments of the present invention are different from one another but are not necessarily mutually exclusive. For example, specific shapes, structures and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention with respect to one embodiment. Additionally, it should be understood that the location, arrangement, or configuration of individual components in each presented embodiment category may be changed without departing from the technical spirit and scope of the present invention.

Hereinafter, a three-dimensional flash memory according to embodiments, a method of operating the same, and an electronic system including the same will be described in detail with reference to the drawings.

1 is a simplified circuit diagram showing an array of three-dimensional flash memory according to one embodiment.

Referring to FIG. 1, an array of three-dimensional flash memory according to an embodiment includes a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a common source line (CSL) and bit lines (BL0). , BL1, and BL2) may include a plurality of cell strings (CSTR).

The bit lines BL0, BL1, and BL2 may extend in the second direction D2 and be spaced apart from each other in the first direction D1 and may be arranged two-dimensionally. Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and may form a rectangular coordinate system defined by the X, Y, and Z axes.

A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, and BL2). The cell strings CSTR may be provided between the bit lines BL0, BL1, and BL2 and one common source line CSL and may be commonly connected to the common source line CSL. At this time, a plurality of common source lines (CSL) may be provided, and the plurality of common source lines (CSL) may extend in the first direction (D1) and be spaced apart from each other along the second direction (D2), forming a two-dimensional can be arranged sequentially. The same electrical voltage may be applied to the plurality of common source lines (CSL), but this is not limited or limited, and each of the plurality of common source lines (CSL) is electrically independently controlled, so that different voltages may be applied. there is.

The cell strings CSTR may extend in the third direction D3 and be arranged to be spaced apart from each other along the second direction D2 for each bit line. According to the embodiment, each of the cell strings (CSTR) is connected to a ground selection transistor (GST) connected to the common source line (CSL), the bit lines (BL0, BL1, BL2), and the first and second strings connected in series. Memory cell transistors (MCT) and erase control transistor (ECT) arranged in series between the selection transistors (SST1, SST2), the ground selection transistor (GST) and the first and second string selection transistors (SST1, SST2) ) can be composed of. Additionally, each memory cell transistor (MCT) may include a data storage element.

As an example, each cell string CSTR may include first and second string selection transistors SST1 and SST2 connected in series, and the second string selection transistor SST2 may be connected to the bit lines BL0 and BL1. , BL2) can be connected to one of the following. However, without being limited or limited thereto, each cell string CSTR may include one string select transistor. As another example, the ground selection transistor GST in each cell string CSTR may be composed of a plurality of MOS transistors connected in series, similar to the first and second string selection transistors SST1 and SST2. .

One cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from the common source lines (CSL). That is, the memory cell transistors MCT may be connected in series while being arranged along the third direction D3 between the first string selection transistor SST1 and the ground selection transistor GST. The erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each of the cell strings (CSTR) is between the first string select transistor (SST1) and the highest one of the memory cell transistors (MCT) and between the ground select transistor (GST) and the lowest one of the memory cell transistors (MCT). It may further include dummy cell transistors (DMCs) each connected to each other.

According to an embodiment, the first string selection transistor SST1 may be controlled by the first string selection lines SSL1-1, SSL1-2, and SSL1-3, and the second string selection transistor SST2 may be controlled by the first string selection lines SSL1-1, SSL1-2, and SSL1-3. It can be controlled by 2 string selection lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may each be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may each be controlled by a dummy word line (DWL). The ground select transistor GST may be controlled by the ground select lines GSL0, GSL1, and GSL2, and the erase control transistor ECT may be controlled by the erase control line ECL. A plurality of erase control transistors (ECT) may be provided. Common source lines (CSL) may be commonly connected to sources of erase control transistors (ECT).

The gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and be in an equipotential state. . However, without being limited or limited thereto, even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be controlled independently. there is.

Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string selection lines (SSL2-1, SSL2-2, SSL2-3) ) extends along the first direction (D1), are spaced apart from each other in the second direction (D2), and may be arranged two-dimensionally. Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string provided at substantially the same level from the common source lines (CSL) The selection lines (SSL2-1, SSL2-2, and SSL2-3) may be electrically separated from each other. Additionally, the erase control transistors ECT of different cell strings CSTR may be controlled by a common erase control line ECL. Erase control transistors (ECT) may generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, during an erase operation of the memory cell array, an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and/or the common source lines (CSL), and the string select transistor (SST) and/or Alternatively, gate-induced leakage current may be generated in the erase control transistors (ECT).

The string selection line (SSL) described above may be expressed as an upper selection line (USL), and the ground selection line (GSL) may be expressed as a lower selection line.

Figure 2 is a plan view showing the structure of a three-dimensional flash memory according to an embodiment. FIG. 3 is a cross-sectional view showing the structure of a three-dimensional flash memory according to an embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.

2 and 3, the substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a monocrystalline silicon substrate. . The substrate SUB may be doped with a first conductivity type impurity (eg, a P-type impurity).

Stacked structures (ST) may be disposed on the substrate (SUB). The stacked structures ST may extend in the first direction D1 and be two-dimensionally arranged along the second direction D2. Additionally, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1, EL2, and EL3 and interlayer insulating films ILD that are alternately stacked in a vertical direction perpendicular to the top surface of the substrate SUB (for example, in the third direction D3). may include. The stacked structures ST may have a substantially flat top surface. That is, the top surface of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or the reverse direction of the third direction D3.

Referring again to FIG. 1, each of the gate electrodes EL1, EL2, and EL3 includes an erase control line (ECL), ground selection lines (GSL0, GSL1, GSL2), and a word line sequentially stacked on the substrate (SUB). (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) It can be.

Each of the gate electrodes EL1, EL2, and EL3 may extend in the first direction D1 and have substantially the same thickness in the third direction D3. Hereinafter, thickness refers to the thickness in the third direction (D3). Each of the gate electrodes EL1, EL2, and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1, EL2, and EL3 is made of a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1, EL2, and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal materials described.

More specifically, the gate electrodes EL1, EL2, and EL3 include the first gate electrode EL1 at the bottom, the third gate electrode EL3 at the top, and the first gate electrode EL1 and the third gate electrode EL3. It may include a plurality of second gate electrodes EL2 therebetween. The first gate electrode EL1 and the third gate electrode EL3 are each shown and described in singular form, but this is illustrative and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0, GSL1, and GLS2 shown in FIG. 1. The second gate electrode EL2 may correspond to one of the word lines WL0-WLn and DWL shown in FIG. 1. The third gate electrode EL3 is one of the first string selection lines SSL1-1, SSL1-2, and SSL1-3 shown in FIG. 1 or the second string selection lines SSL2-1 and SSL1-3. It may correspond to either SSL2-2 or SSL2-3).

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the length of the gate electrodes EL1, EL2, and EL3 of the stacked structures ST may decrease in the first direction D1 as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the greatest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the greatest length in the first direction D1 and the smallest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures (ST) may decrease as it moves away from the outer-most one of the vertical channel structures (VS), which will be described later, and the gate electrodes (EL1, The side walls of EL2 and EL3) may be spaced apart at regular intervals along the first direction D1 from a plan view.

Each of the interlayer dielectric layers (ILD) may have different thicknesses. For example, the lowest and uppermost of the interlayer insulating layers (ILD) may have a smaller thickness than the other interlayer insulating layers (ILD). However, this is an example and is not limited to this, and the thickness of each interlayer dielectric layer (ILD) may have a different thickness depending on the characteristics of the semiconductor device, or may all be set to be the same. The interlayer insulating films ILD may be formed of an insulating material to insulate the gate electrodes EL1, EL2, and EL3. As an example, the interlayer insulating films (ILD) may be formed of silicon oxide.

A plurality of channel holes CH may be provided penetrating a portion of the stacked structures ST and the substrate SUB. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures VS are a plurality of cell strings CSTR shown in FIG. 1 and may be connected to the substrate SUB and extend in the third direction D3. The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a portion of each of the vertical channel structures (VS) being buried inside the substrate (SUB), but is not limited or limited thereto and the vertical channel structures (VS) are connected to the substrate (SUB). This may be achieved by contacting the lower surface of (VS) with the upper surface of the substrate (SUB). When a portion of each of the vertical channel structures (VS) is buried inside the substrate (SUB), the lower surface of the vertical channel structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

A plurality of rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided. For example, as shown in FIG. 2 , rows of two vertical channel structures (VS) may penetrate one of the stacked structures (ST). However, without being limited or limited thereto, rows of three or more vertical channel structures (VS) may penetrate one of the stacked structures (ST). In a pair of adjacent columns, the vertical channel structures (VS) corresponding to one column may be shifted in the first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent column. there is. From a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited or restricted thereto, the vertical channel structures VS may be arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures (VS) is shown as having a pillar shape with the same width at the top and bottom, but it is not limited or limited thereto, and as it moves toward the third direction (D3), the first direction (D1) and the second direction (D2) may have a shape in which the width is increased. This is due to the limitation that when the channel holes CH are etched, their widths in the first direction D1 and the second direction D2 decrease as they go in the opposite direction of the third direction D3. The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a vertical semiconductor pattern (VSP), and a conductive pad (PAD). In each of the vertical channel structures (VS), the data storage pattern (DSP) may have a pipe shape with an open bottom or a macaroni shape, and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom. It can have a shape. The vertical semiconductor pattern (VSP) can fill the space surrounded by the vertical channel pattern (VCP) and the conductive pad (PAD).

The data storage pattern (DSP) covers the inner wall of each of the channel holes (CH) and contacts the vertical channel pattern (VCP) on the inside and the side walls of the gate electrodes (EL1, EL2, EL3) on the outside. You can. Accordingly, the areas corresponding to the second gate electrodes EL2 in the data storage pattern DSP are the second gate electrodes together with the areas corresponding to the second gate electrodes EL2 in the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by voltage applied through (EL2) can be configured. The memory cells correspond to memory cell transistors (MCT) shown in FIG. 1. That is, the data storage pattern DSP traps charges or holes by a voltage applied through the second gate electrodes EL2 or maintains the state of the charges (e.g., the polarization state of the charges) in the three-dimensional flash memory. It can act as a data storage. For example, an ONO (tunnel oxide (oxide)-charge storage layer (nitride)-blocking oxide) layer or a ferroelectric layer may be used as the data storage pattern (DSP). Such a data storage pattern (DSP) may represent a binary data value or a multi-valued data value by changing the state of trapped charges or holes, or it can represent a binary data value or a multi-valued data value by changing the state of the charges.

A vertical channel pattern (VCP) may cover the inner wall of the data storage pattern (DSP). The vertical channel pattern (VCP) may include a first part (VCP1) and a second part (VCP2) on the first part (VCP1).

The first portion (VCP1) of the vertical channel pattern (VCP) may be provided below each of the channel holes (CH) and may be in contact with the substrate (SUB). The first part (VCP1) of the vertical channel pattern (VCP) may be used to block, suppress, or minimize leakage current in each of the vertical channel structures (VS) and/or as an epitaxial pattern. For example, the thickness of the first portion (VCP1) of the vertical channel pattern (VCP) may be greater than the thickness of the first gate electrode (EL1). A sidewall of the first portion (VCP1) of the vertical channel pattern (VCP) may be surrounded by a data storage pattern (DSP). The top surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located at a higher level than the top surface of the first gate electrode (EL1). More specifically, the top surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located between the top surface of the first gate electrode (EL1) and the bottom surface of the lowest one of the second gate electrodes (EL2). The bottom surface of the first portion VCP1 of the vertical channel pattern VCP may be located at a lower level than the top surface of the substrate SUB (that is, the bottom surface of the lowest one of the interlayer insulating layers ILD). A portion of the first portion (VCP1) of the vertical channel pattern (VCP) may overlap the first gate electrode (EL1) in the horizontal direction. Hereinafter, the horizontal direction means any direction extending on a plane parallel to the first direction D1 and the second direction D2.

The second part (VCP2) of the vertical channel pattern (VCP) may extend from the top surface of the first part (VCP1) in the third direction (D3). The second portion (VCP2) of the vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the vertical semiconductor pattern (VSP) and may correspond to the second gate electrodes (EL2). Accordingly, the second part (VCP2) of the vertical channel pattern (VCP), together with the regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP), as described above, may form memory cells. .

The top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be substantially coplanar with the top surface of the vertical semiconductor pattern (VSP). The top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be located at a higher level than the top surface of the uppermost one of the second gate electrodes (EL2). More specifically, the top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be located between the top and bottom surfaces of the third gate electrode (EL3).

The vertical channel pattern (VCP) is a component that transfers charges or holes to the data storage pattern (DSP), and may be formed of single crystalline silicon or polysilicon to form a channel or be boosted by an applied voltage. However, without being limited or limited thereto, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material that can block, suppress, or minimize leakage current. For example, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material containing at least one of In, Zn, or Ga with excellent leakage current characteristics. The vertical channel pattern (VCP) may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern (VCP) can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and at least one of the gate electrodes (EL1, EL2, EL3) The characteristics of any one transistor (for example, threshold voltage distribution and speed of program/read operations) can be improved, and as a result, the electrical characteristics of the 3D flash memory can be improved.

The vertical semiconductor pattern (VSP) may be surrounded by the second portion (VCP2) of the vertical channel pattern (VCP). The upper surface of the vertical semiconductor pattern (VSP) may contact the conductive pad (PAD), and the lower surface of the vertical semiconductor pattern (VSP) may contact the first portion (VCP1) of the vertical channel pattern (VCP). The vertical semiconductor pattern VSP may be spaced apart from the substrate SUB in the third direction D3. In other words, the vertical semiconductor pattern VSP may be electrically floating from the substrate SUB.

The vertical semiconductor pattern (VSP) may be formed of a material that helps diffusion of charges or holes in the vertical channel pattern (VCP). More specifically, the vertical semiconductor pattern (VSP) can be formed of a material with excellent charge and hole mobility. For example, the vertical semiconductor pattern (VSP) may be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material that is not doped with an impurity, or a polycrystalline semiconductor material. For a more specific example, the vertical semiconductor pattern VSP may be formed of polysilicon doped with the same first conductivity type impurity (eg, P-type impurity) as the substrate SUB. In other words, the vertical semiconductor pattern (VSP) can improve the speed of memory operation by improving the electrical characteristics of 3D flash memory.

Referring again to FIG. 1, the vertical channel structures (VS) include an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT). ) may correspond to the channels.

A conductive pad (PAD) may be provided on the top surface of the second portion (VCP2) of the vertical channel pattern (VCP) and the top surface of the vertical semiconductor pattern (VSP). The conductive pad (PAD) may be connected to the top of the vertical channel pattern (VCP) and the top of the vertical semiconductor pattern (VSP). The sidewall of the conductive pad (PAD) may be surrounded by a data storage pattern (DSP). The top surface of the conductive pad PAD may be substantially coplanar with the top surface of each of the stacked structures ST (that is, the top surface of the uppermost one of the interlayer dielectric layers ILD). The lower surface of the conductive pad PAD may be located at a lower level than the upper surface of the third gate electrode EL3. More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3. That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in the horizontal direction.

The conductive pad (PAD) may be formed of a semiconductor or conductive material doped with impurities. For example, the conductive pad (PAD) is doped with impurities (more precisely, impurities of a second conductivity type (e.g., N-type) different from the first conductivity type (e.g., P-type)) than the vertical semiconductor pattern (VSP). It can be formed from a semiconductor material.

The conductive pad (PAD) can reduce contact resistance between the bit line (BL) and the vertical channel pattern (VCP) (or vertical semiconductor pattern (VSP)), which will be described later.

Above, the vertical channel structures VS have been described as having a structure including a conductive pad (PAD), but they are not limited or limited thereto and may have a structure omitting the conductive pad (PAD). In this case, as the conductive pad (PAD) is omitted from the vertical channel structures (VS), the upper surface of each of the vertical channel pattern (VCP) and the vertical semiconductor pattern (VSP) is the upper surface of each of the stacked structures (ST) (i.e. Each of the vertical channel pattern (VCP) and the vertical semiconductor pattern (VSP) may be formed to extend in the third direction (D3) so as to be substantially coplanar with the top surface of the uppermost one of the interlayer insulating layers (ILD). Additionally, in this case, the bit line contact plug (BLPG), which will be described later, directly contacts the vertical channel pattern (VCP) instead of being indirectly electrically connected to the vertical channel pattern (VCP) through the conductive pad (PAD). Can be electrically connected.

In addition, although it has been described that the vertical channel structures VS include the vertical semiconductor pattern VSP, the present invention is not limited or limited thereto and the vertical semiconductor pattern VSP may be omitted.

In addition, although the vertical channel pattern (VCP) has been described as having a structure including a first part (VCP1) and a second part (VCP2), it is not limited or limited thereto and may have a structure excluding the first part (VCP1). You can. For example, the vertical channel pattern (VCP) is provided between the vertical semiconductor pattern (VSP) and the data storage pattern (DSP) formed to extend to the substrate (SUB) and is formed to extend to the substrate (SUB) to contact the substrate (SUB). You can. In this case, the bottom surface of the vertical channel pattern (VCP) may be located at a lower level than the top surface of the substrate (SUB) (the bottom surface of the lowest one of the interlayer dielectric layers (ILD)), and the top surface of the vertical channel pattern (VCP) may be located at a lower level than the top surface of the substrate (SUB). It can be substantially coplanar with the top surface of the pattern (VSP).

A separation trench TR extending in the first direction D1 may be provided between adjacent stacked structures ST. The common source region (CSR) may be provided inside the substrate (SUB) exposed by the isolation trench (TR). The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with second conductivity type impurities (eg, N-type impurities). The common source region (CSR) may correspond to the common source line (CSL) in FIG. 1.

A common source plug (CSP) may be provided in the isolation trench (TR). The common source plug (CSP) may be connected to the common source region (CSR). The top surface of the common source plug (CSP) may be substantially coplanar with the top surface of each of the stacked structures (ST) (that is, the top surface of the uppermost one of the interlayer insulating layers (ILD)). The common source plug (CSP) may have a plate shape extending in the first direction (D1) and the third direction (D3). At this time, the common source plug CSP may have a shape whose width in the second direction D2 increases as it moves toward the third direction D3.

Insulating spacers (SP) may be interposed between the common source plug (CSP) and the stacked structures (ST). Insulating spacers SP may be provided between adjacent stacked structures ST to face each other. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material with a low dielectric constant.

A capping insulating layer (CAP) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating layer (CAP) may cover the top surface of the uppermost one of the interlayer insulating layers (ILD), the top surface of the conductive pad (PAD), and the top surface of the common source plug (CSP). The capping insulating film (CAP) may be formed of an insulating material different from the interlayer insulating films (ILD). A bit line contact plug (BLPG) electrically connected to the conductive pad (PAD) may be provided inside the capping insulating film (CAP). The bit line contact plug BLPG may have a shape whose width in the first direction D1 and the second direction D2 increases as it moves toward the third direction D3.

A bit line (BL) may be provided on the capping insulating film (CAP) and the bit line contact plug (BLPG). The bit line BL corresponds to one of the plurality of bit lines BL0, BL1, and BL2 shown in FIG. 1 and may be formed to extend along the second direction D2 using a conductive material. The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1, EL2, and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through a bit line contact plug (BLPG). Here, the fact that the bit line (BL) is connected to the vertical channel structures (VS) may mean that it is connected to the vertical channel pattern (VCP) included in the vertical channel structures (VS).

A three-dimensional flash memory with this structure includes a voltage applied to each of the cell strings (CSTR), a voltage applied to the string selection line (SSL), a voltage applied to each of the word lines (WL0-WLn), and a ground selection line. Based on the voltage applied to the (GSL) and the voltage applied to the common source line (CSL), a program operation, a read operation, and an erase operation can be performed. For example, the 3D flash memory includes a voltage applied to each of the cell strings (CSTR), a voltage applied to the string select line (SSL), a voltage applied to each of the word lines (WL0-WLn), and a ground select line (GSL). Based on the voltage applied to ) and the voltage applied to the common source line (CSL), a channel is formed in the vertical channel pattern (VCP) to transfer charges or holes to the data storage pattern (DSP) of the target memory cell to operate the program. can be performed. A detailed description of this will be described with reference to FIGS. 5 and 6.

In addition, the three-dimensional flash memory according to one embodiment is not limited or limited to the described structure, and may include a vertical channel pattern (VCP), a data storage pattern (DSP), and gate electrodes (EL1, EL2, and EL3) depending on the implementation example. , it can be implemented in various structures provided that it includes a bit line (BL) and a common source line (CSL).

FIG. 4 is a cross-sectional view showing the structure of a three-dimensional flash memory according to another embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.

Referring to FIG. 4, the substrate SUB may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate SUB may be doped with a first conductivity type impurity (eg, a P-type impurity).

Stacked structures (ST) may be disposed on the substrate (SUB). The stacked structures ST may extend in the first direction D1 and be two-dimensionally arranged along the second direction D2. Additionally, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1, EL2, and EL3 and interlayer insulating films ILD that are alternately stacked in a vertical direction perpendicular to the top surface of the substrate SUB (for example, in the third direction D3). may include. The stacked structures ST may have a substantially flat top surface. That is, the top surface of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or the reverse direction of the third direction D3.

Referring again to FIG. 1, each of the gate electrodes EL1, EL2, and EL3 includes an erase control line (ECL), ground selection lines (GSL0, GSL1, GSL2), and a word line sequentially stacked on the substrate (SUB). (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) It can be.

Each of the gate electrodes EL1, EL2, and EL3 may extend in the first direction D1 and have substantially the same thickness in the third direction D3. Hereinafter, thickness refers to the thickness in the third direction (D3). Each of the gate electrodes EL1, EL2, and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1, EL2, and EL3 is made of a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1, EL2, and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal materials described.

More specifically, the gate electrodes EL1, EL2, and EL3 include the first gate electrode EL1 at the bottom, the third gate electrode EL3 at the top, and the first gate electrode EL1 and the third gate electrode EL3. It may include a plurality of second gate electrodes EL2 therebetween. The first gate electrode EL1 and the third gate electrode EL3 are each shown and described in singular form, but this is illustrative and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0, GSL1, and GLS2 shown in FIG. 1. The second gate electrode EL2 may correspond to one of the word lines WL0-WLn and DWL shown in FIG. 1. The third gate electrode EL3 is one of the first string selection lines SSL1-1, SSL1-2, and SSL1-3 shown in FIG. 1 or the second string selection lines SSL2-1 and SSL1-3. It may correspond to either SSL2-2 or SSL2-3).

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the length of the gate electrodes EL1, EL2, and EL3 of the stacked structures ST may decrease in the first direction D1 as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the greatest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the greatest length in the first direction D1 and the smallest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures (ST) may decrease as it moves away from the outer-most one of the vertical channel structures (VS), which will be described later, and the gate electrodes (EL1, The side walls of EL2 and EL3) may be spaced apart at regular intervals along the first direction D1 from a plan view.

Each of the interlayer dielectric layers (ILD) may have different thicknesses. For example, the lowest and uppermost of the interlayer insulating layers (ILD) may have a smaller thickness than the other interlayer insulating layers (ILD). However, this is an example and is not limited to this, and the thickness of each interlayer dielectric layer (ILD) may have a different thickness depending on the characteristics of the semiconductor device, or may all be set to be the same. The interlayer insulating films ILD may be formed of an insulating material to insulate the gate electrodes EL1, EL2, and EL3. As an example, the interlayer insulating films (ILD) may be formed of silicon oxide.

A plurality of channel holes CH may be provided penetrating a portion of the stacked structures ST and the substrate SUB. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures VS are a plurality of cell strings CSTR shown in FIG. 1 and may be connected to the substrate SUB and extend in the third direction D3. The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a portion of each of the vertical channel structures (VS) being buried inside the substrate (SUB), but is not limited or limited thereto and the vertical channel structures (VS) are connected to the substrate (SUB). This may be achieved by contacting the lower surface of (VS) with the upper surface of the substrate (SUB). When a portion of each of the vertical channel structures (VS) is buried inside the substrate (SUB), the lower surface of the vertical channel structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

A plurality of rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided. For example, as shown in FIG. 2 , rows of two vertical channel structures (VS) may penetrate one of the stacked structures (ST). However, without being limited or limited thereto, rows of three or more vertical channel structures (VS) may penetrate one of the stacked structures (ST). In a pair of adjacent columns, the vertical channel structures (VS) corresponding to one column may be shifted in the first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent column. there is. From a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited or restricted thereto, the vertical channel structures VS may be arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures (VS) is shown as having a pillar shape with the same width at the top and bottom, but it is not limited or limited thereto, and as it moves toward the third direction (D3), the first direction (D1) and the second direction (D2) may have a shape in which the width is increased. This is due to the limitation that when the channel holes CH are etched, their widths in the first direction D1 and the second direction D2 decrease as they go in the opposite direction of the third direction D3. The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a back gate (BG), and a conductive pad (PAD). In each of the vertical channel structures (VS), the data storage pattern (DSP) may have a pipe shape with an open bottom or a macaroni shape, and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom. It can have a shape. The back gate (BG) may be formed to apply a voltage to the vertical channel pattern (VCP) while being at least partially surrounded by the vertical channel pattern (VCP). Hereinafter, the fact that the back gate (BG) is included in the vertical channel pattern (VCP) may mean that the back gate (BG) is at least partially surrounded by the vertical channel pattern (VCP), as described.

The data storage pattern (DSP) covers the inner wall of each of the channel holes (CH) and contacts the vertical channel pattern (VCP) on the inside and the side walls of the gate electrodes (EL1, EL2, EL3) on the outside. You can. Accordingly, the areas corresponding to the second gate electrodes EL2 in the data storage pattern DSP are the second gate electrodes together with the areas corresponding to the second gate electrodes EL2 in the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by voltage applied through (EL2) can be configured. The memory cells correspond to memory cell transistors (MCT) shown in FIG. 1. That is, the data storage pattern DSP traps charges or holes by a voltage applied through the second gate electrodes EL2 or maintains the state of the charges (e.g., the polarization state of the charges) in the three-dimensional flash memory. It can act as a data storage. For example, an ONO (tunnel oxide (oxide)-charge storage layer (nitride)-blocking oxide) layer or a ferroelectric layer may be used as the data storage pattern (DSP). Such a data storage pattern (DSP) may represent a binary data value or a multi-valued data value by changing the state of trapped charges or holes, or it can represent a binary data value or a multi-valued data value by changing the state of the charges.

The vertical channel pattern (VCP) may cover the inner wall of the data storage pattern (DSP) and may extend in the third direction (D3). The vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the back gate (BG) and may correspond to the second gate electrodes (EL2). Accordingly, as described above, the vertical channel pattern VCP may form memory cells together with regions corresponding to the second gate electrodes EL2 in the data storage pattern DSP.

The top surface of the vertical channel pattern VCP may be located at a higher level than the top surface of the uppermost one of the second gate electrodes EL2. More specifically, the top surface of the vertical channel pattern VCP may be located between the top and bottom surfaces of the third gate electrode EL3.

The vertical channel pattern (VCP) is a component that transfers charges or holes to the data storage pattern (DSP), and may be formed of single crystalline silicon or polysilicon to form a channel or be boosted by an applied voltage. However, without being limited or limited thereto, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material that can block, suppress, or minimize leakage current. For example, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material containing at least one of In, Zn, or Ga with excellent leakage current characteristics. The vertical channel pattern (VCP) may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern (VCP) can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and at least one of the gate electrodes (EL1, EL2, EL3) The characteristics of any one transistor (for example, threshold voltage distribution and speed of program/read operations) can be improved, and as a result, the electrical characteristics of the 3D flash memory can be improved.

The back gate (BG) is at least partially surrounded and contacted by the vertical channel pattern (VCP) and may be formed to apply a voltage to the vertical channel pattern (VCP) for a memory operation. For this purpose, the back gate (BG) is a doped semiconductor (ex, doped silicon, etc.), metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), It may be formed of a conductive material containing at least one selected from Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.). The back gate (BG) may include at least one of all metal materials that can be formed by ALD in addition to the metal materials described.

At this time, the back gate BG extends along the third direction D3 from the level corresponding to the first gate electrode EL1 to the level corresponding to the second gate electrode EL2 within the vertical channel pattern VCP. can be formed. That is, the top surface of the back gate BG may be located at a higher level than the top surface of the uppermost one of the second gate electrodes EL2. However, without being limited or restricted thereto, the back gate BG may be formed to extend along the third direction D3 within the vertical channel pattern VCP to a level corresponding to the third gate electrode EL3.

Although the lower substrate in contact with the lower surface of the back gate (BG) is omitted in the drawing, the lower substrate in contact with the lower surface of the back gate (BG) may be included depending on the implementation example. Additionally, depending on the implementation example, the back gate BG may be formed from inside the substrate SUB or may be formed from the top of the substrate SUB.

This back gate (BG) is included in the vertical channel pattern (VCP) of each cell string (CSTR), and the back gate (BG) included in the vertical channel pattern (VCP) of each cell string (CSTR) is The back gate BG may be electrically connected to all planes formed by the first direction D1 and the second direction D2. That is, the back gate (BG) may be commonly connected to the cell strings (CSTR). In this case, the back gates (BG) of each of the cell strings (CSTR) are collectively controlled so that the same voltage can be applied to all of them.

However, without being limited or limited thereto, the back gates BG included in the vertical channel pattern VCP of each of the cell strings CSTR may be electrically connected to each other along the first direction D1 of FIG. 1 . In this case, each back gate (BG) of the cell strings (CSTR) arranged along the second direction (D2) is electrically independently controlled, so that different voltages can be applied, and in the first direction of FIG. 1 The back gates (BG) of each of the cell strings (CSTR) arranged along (D1) are collectively controlled so that the same voltage can be applied.

Additionally, the back gates BG included in the vertical channel pattern VCP of each of the cell strings CSTR may be electrically connected to each other along the second direction D2 of FIG. 1 . In this case, the back gates BG of each of the cell strings CSTR arranged along the first direction D1 are electrically independently controlled, so that different voltages can be applied, and in the second direction of FIG. 1 The back gates (BG) of each of the cell strings (CSTR) arranged along (D2) are collectively controlled so that the same voltage can be applied.

An insulating film (INS) is disposed between the back gate (BG) and the vertical channel pattern (VCP), thereby preventing the back gate (BG) from directly contacting the vertical channel pattern (VCP). The insulating layer (ILD), like the interlayer insulating layers (ILD), may be formed of an insulating material such as silicon oxide.

Above, it has been described as a structure in which the back gate (BG) is formed in the inner hole of the vertical channel pattern (VCP) and is tightly surrounded by the vertical channel pattern (VCP), but is not limited or limited thereto and is not limited to the vertical channel pattern (VCP). It may be formed in a structure in which at least part of the structure is surrounded by VCP). For example, a structure in which the back gate (BG) and the insulating layer (INS) are included in at least a portion of the vertical channel pattern (VCP) or a structure that penetrates the vertical channel pattern (VCP) may be implemented.

Referring again to FIG. 1, the vertical channel structures (VS) include an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT). ) may correspond to the channels.

A conductive pad (PAD) may be provided on the upper surface of the vertical channel pattern (VCP). The conductive pad (PAD) may be connected to the top of the vertical channel pattern (VCP). The sidewall of the conductive pad (PAD) may be surrounded by a data storage pattern (DSP). The top surface of the conductive pad PAD may be substantially coplanar with the top surface of each of the stacked structures ST (that is, the top surface of the uppermost one of the interlayer dielectric layers ILD). The lower surface of the conductive pad PAD may be located at a lower level than the upper surface of the third gate electrode EL3. More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3. That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in the horizontal direction.

The conductive pad (PAD) may be formed of a semiconductor or conductive material doped with impurities. For example, the conductive pad (PAD) is a semiconductor material doped with impurities different from the substrate SUB (more precisely, impurities of a second conductivity type (e.g., N-type) different from the first conductivity type (e.g., P-type)). It can be formed as

The conductive pad (PAD) can reduce contact resistance between the bit line (BL) and the vertical channel pattern (VCP), which will be described later.

A separation trench TR extending in the first direction D1 may be provided between adjacent stacked structures ST. The common source region (CSR) may be provided inside the substrate (SUB) exposed by the isolation trench (TR). The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with second conductivity type impurities (eg, N-type impurities). The common source region (CSR) may correspond to the common source line (CSL) in FIG. 1.

A common source plug (CSP) may be provided in the isolation trench (TR). The common source plug (CSP) may be connected to the common source region (CSR). The top surface of the common source plug (CSP) may be substantially coplanar with the top surface of each of the stacked structures (ST) (that is, the top surface of the uppermost one of the interlayer insulating layers (ILD)). The common source plug (CSP) may have a plate shape extending in the first direction (D1) and the third direction (D3). At this time, the common source plug CSP may have a shape whose width in the second direction D2 increases as it moves toward the third direction D3.

Insulating spacers (SP) may be interposed between the common source plug (CSP) and the stacked structures (ST). Insulating spacers SP may be provided between adjacent stacked structures ST to face each other. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material with a low dielectric constant.

A capping insulating layer (CAP) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating layer (CAP) may cover the top surface of the uppermost one of the interlayer insulating layers (ILD), the top surface of the conductive pad (PAD), and the top surface of the common source plug (CSP). The capping insulating film (CAP) may be formed of an insulating material different from the interlayer insulating films (ILD). A bit line contact plug (BLPG) electrically connected to the conductive pad (PAD) may be provided inside the capping insulating film (CAP). The bit line contact plug BLPG may have a shape whose width in the first direction D1 and the second direction D2 increases as it moves toward the third direction D3.

A bit line (BL) may be provided on the capping insulating film (CAP) and the bit line contact plug (BLPG). The bit line BL corresponds to one of the plurality of bit lines BL0, BL1, and BL2 shown in FIG. 1 and may be formed to extend along the second direction D2 using a conductive material. The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1, EL2, and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through a bit line contact plug (BLPG). Here, the fact that the bit line (BL) is connected to the vertical channel structures (VS) may mean that it is connected to the vertical channel pattern (VCP) included in the vertical channel structures (VS).

A three-dimensional flash memory with this structure includes a voltage applied to each of the cell strings (CSTR), a voltage applied to the string selection line (SSL), a voltage applied to each of the word lines (WL0-WLn), and a ground selection line. Program operations, read operations, and erase operations can be performed based on the voltage applied to the (GSL), the voltage applied to the common source line (CSL), and the voltage applied to the back gate (BG). For example, the 3D flash memory includes a voltage applied to each of the cell strings (CSTR), a voltage applied to the string select line (SSL), a voltage applied to each of the word lines (WL0-WLn), and a ground select line (GSL). ) Based on the voltage applied to the common source line (CSL) and the voltage applied to the back gate (BG), a channel is formed in the vertical channel pattern (VCP) to transfer charges or holes to the data of the target memory cell. Program operations can be performed by passing it to a stored pattern (DSP). A detailed description of this will be described with reference to FIGS. 5 and 7.

In addition, the three-dimensional flash memory according to another embodiment is not limited or limited to the described structure, and may include a vertical channel pattern (VCP), a data storage pattern (DSP), a back gate (BG), and a gate electrode ( EL1, EL2, EL3), a bit line (BL), and a common source line (CSL).

FIG. 5 is a flow chart showing a program operation method of the three-dimensional flash memory shown in FIGS. 3 and 4, and FIG. 6 is a flow chart of the three-dimensional flash memory shown in FIG. 3 to explain the program operation method shown in FIG. 5. It is a cross-sectional view showing the structure, and FIG. 7 is a cross-sectional view showing the structure of the three-dimensional flash memory shown in FIG. 4 to explain the program operation method shown in FIG. 5. Hereinafter, the program operation method described is assumed to be performed in a three-dimensional flash memory with the structure described with reference to FIGS. 1 to 4. In addition, hereinafter, "selected cell string (sel CSTR)" refers to a cell string including a target memory cell that is the target of a program operation among cell strings (CSTR), and "unselected cell string (unsel) “CSTR)” refers to a cell string that does not include a target memory cell among the cell strings (CSTR). Likewise, “selected word line (sel WL)” refers to the word line corresponding to the target memory cell among the word lines (WL0-WLn), and “unselected word line (unsel WL)” refers to the word line (WL0-WLn) corresponding to the target memory cell. WLn) refers to word lines that do not correspond to the target memory cell (word lines other than the selected word line). Here, the word lines (WL0-WLn) correspond to the second gate electrode (EL2) shown in FIGS. 1 to 4, and the string select line (SSL) corresponds to the third gate electrode (EL3) shown in FIGS. 1 to 4. may apply.

Referring to the drawing, in step S510, the three-dimensional flash memory is connected to the bit line (sel BL0) of the selected cell string (sel CSTR) corresponding to the target memory cell that is the target of the program operation among the cell strings (CSTR). A negative voltage can be applied. At this time, the negative voltage is the selected word line (sel WL), which will be described later, such that the potential difference between the selected word line (sel WL) and the bit line (sel BL0) of the selected cell string (sel CSTR) is 20 V or more. It can be appropriately determined based on the value of the program voltage (Vpgm) applied to. For example, if the program voltage (Vpgm) is 20V, the negative value voltage may be -2V.

Although not shown in a separate drawing, the three-dimensional flash memory may be configured so that a negative voltage is applied to the bit line (sel BL0) of the cell string (sel CSTR) selected in step S510 during the program operation. You can. For example, the three-dimensional flash memory, in addition to the structure described with reference to FIGS. 1 to 4, includes a circuit capable of generating a negative voltage, and the circuit is connected to the bit line BL of the cell strings CSTR. ) may have a structure electrically connected to.

Additionally, a negative voltage can be generated using an existing circuit, instead of being generated through a circuit provided only for program operation. In more detail, the negative voltage applied to the bit line (sel BL0) of the cell string (sel CSTR) selected in step S510 means that the three-dimensional flash memory performs an operation other than a program operation (for example, a read operation). It can be generated from a circuit that generates a negative value voltage that is used when performing the operation. That is, in step S510, the three-dimensional flash memory transmits a negative voltage generated from a circuit that generates a negative voltage used when performing operations other than the program operation to the selected cell string (sel CSTR). It can be applied to the bit line (sel BL0).

In step S520, the 3D flash memory may apply a program voltage (Vpgm; for example, 20V) to the selected word line (sel WL) corresponding to the target memory cell among the word lines.

The method of the present invention in which a negative voltage is applied to the bit line (sel BL0) of the selected cell string (sel CSTR) in this way is to apply a ground voltage to the bit line (sel BL0) of the existing selected cell string (sel CSTR). Program speed can be improved further than the authorized method. This is the method of the present invention (applying a negative voltage of -2V to the bit line (sel BL0) of the selected cell string (sel CSTR) and applying a program voltage of 20V to the selected word line (sel WL) and the existing method. Method (applying a ground voltage of 0V to the bit line (sel BL0) of the selected cell string (sel CSTR) and applying a program voltage of 22V to the selected word line (sel WL)), the selected word line (sel WL) and Even if the potential difference between the bit lines (sel BL0) of the selected cell string (sel CSTR) is the same, in the method of the present invention, the potential difference (selected word line (sel WL) and the bit line (sel BL0) of the selected cell string (sel CSTR) is transmitted directly to the vertical channel pattern (VCP), whereas in the conventional method, the potential difference (voltage between the selected word line (sel WL) and the bit line (sel BL0) of the selected cell string (sel CSTR) is transmitted directly to the vertical channel pattern (VCP). This is because it is indirectly transmitted to the vertical channel pattern (VCP) through the data storage pattern (DSP).

Accordingly, the existing 22V voltage between the selected word line (sel WL) and the bit line (sel BL0) of the selected cell string (sel CSTR) is indirectly transmitted to the vertical channel pattern (VCP) through the data storage pattern (DSP). The method may slow down the program speed due to coupling, and 22V, which is the voltage between the selected word line (sel WL) and the bit line (sel BL0) of the selected cell string (sel CSTR), is used as a vertical channel pattern (VCP). The method of the present invention, which is directly transmitted, can improve program speed by preventing coupling.

Accordingly, in step S510, the voltage between the selected word line (sel WL) and the bit line (sel BL0) of the selected cell string (sel CSTR) is applied to the vertical channel pattern (VCP) included in the selected cell string (sel CSTR). A negative voltage may be applied to the bit line (sel BL0) of the cell string (sel CSTR) selected to be directly transmitted.

In step S530, the three-dimensional flash memory responds to a negative voltage being applied to the bit line (sel BL0) of the selected cell string (sel CSTR) and a program voltage being applied to the selected word line (sel WL), A program operation for a target memory cell can be performed by forming a channel in the vertical channel pattern (VCP) included in the selected cell string (sel CSTR).

Meanwhile, 3D flash memory can prevent program operations in memory cells included in the unselected cell string (unsel CSTR) by boosting the unselected cell string (unsel CSTR). there is. Specifically, the 3D flash memory applies the power supply voltage (Vcc) to the bit line (unsel BL1) of the unselected cell string (unsel CSTR), so that the unselected cell string (unsel CSTR) is applied to the bit line (unsel BL1). It is possible to have a boosted potential by the supplied power voltage and the program voltage applied to the selected word line (sel WL). Accordingly, memory cells included in the unselected cell string (unsel CSTR) can be prevented from being programmed.

Hereinafter, the program operation method including steps S510 to S530 will be described separately into the case of being performed on a 3D flash memory having the structure of FIG. 3 and the case of being performed on a 3D flash memory having the structure of FIG. 4. .

Referring to FIG. 6, after performing step S510, the 3D flash memory performs step S520 and simultaneously selects the remaining unselected word lines (unsel WL) among the word lines except for the selected word line (sel WL). ) A pass voltage (Vpass; hereinafter, the pass voltage refers to a voltage higher than the threshold voltage of the memory transistor in the program state and lower than the program voltage (Vpgm), for example, 9V) may be applied to each. At this time, the 3D flash memory has a power supply voltage (Vcc; hereinafter, the power supply voltage is higher than the threshold voltage of the string selection line (SSL) and a program voltage (Vpgm) applied to the selected word line (sel WL). ; meaning a voltage lower than 20V, for example) can be applied, a ground voltage (GND; for example, 0V) can be applied to the ground selection line (GSL), and the common source line (CSL) can be floated.

Therefore, since there is almost no potential difference between the selected cell string (sel CSTR) and the unselected word lines (unsel WL), the unselected word lines (unsel WL) among the memory cells included in the selected cell string (sel CSTR) ) is not programmed, and only the target memory cell can be programmed as in step S530.

Referring to FIG. 7 showing a structure including a back gate, the 3D flash memory performs step S510 and then step S520, and at the same time performs step S520, excluding the selected word line (sel WL) among the word lines. Each of the remaining unselected word lines (unsel WL) is floated, and the pass voltage (Vpass; hereinafter, the pass voltage is higher than the threshold voltage of the memory transistor in the program state and the program voltage (Vpgm) is applied to the back gate (BG). A lower voltage, for example 9V, can be applied. Instead of floating each of the unselected word lines (unsel WL), the 3D flash memory may apply a ground voltage (GND; for example, 0V) to each of the unselected word lines (unsel WL). At this time, the 3D flash memory has a power supply voltage (Vcc; hereinafter, the power supply voltage is higher than the threshold voltage of the string selection line (SSL) and a program voltage (Vpgm) applied to the selected word line (sel WL). ; meaning a voltage lower than 20V, for example) can be applied, a ground voltage (GND; for example, 0V) can be applied to the ground selection line (GSL), and the common source line (CSL) can be floated.

Therefore, since there is almost no potential difference between the selected cell string (sel CSTR) and the unselected word lines (unsel WL), the unselected word lines (unsel WL) among the memory cells included in the selected cell string (sel CSTR) ) is not programmed, and only the target memory cell can be programmed as in step S530.

As shown in FIG. 7, a three-dimensional flash memory with a structure including a back gate (BG), instead of applying a pass voltage to each of the unselected word lines (unsel WL) during a program operation, By floating each (unsel WL) or applying a ground voltage to each of the unselected word lines (unsel WL), the disturbance caused by the pass voltage being applied to each of the unselected word lines (unsel WL) is prevented. can do.

Since the program operation method described above uses a relatively low program voltage (Vpgm) compared to the existing method, it can reduce the burden on the circuit and improve memory reliability.

FIG. 8 is a flow chart showing the read operation method of the three-dimensional flash memory shown in FIG. 4, and FIG. 9 shows the structure of the three-dimensional flash memory shown in FIG. 4 to explain the read operation method shown in FIG. This is a cross-sectional view.

Hereinafter, the program operation method described is assumed to be performed in a three-dimensional flash memory having the structure described with reference to FIG. 4 (a structure including a back gate (BG)). In addition, hereinafter, "selected cell string (sel CSTR)" refers to a cell string including a target memory cell that is the target of a read operation among cell strings (CSTR), and "unselected cell string (unsel) “CSTR)” refers to a cell string that does not include a target memory cell among the cell strings (CSTR). Likewise, “selected word line (sel WL)” refers to the word line corresponding to the target memory cell among the word lines (WL0-WLn), and “unselected word line (unsel WL)” refers to the word line (WL0-WLn) corresponding to the target memory cell. WLn) refers to word lines that do not correspond to the target memory cell (word lines other than the selected word line). Here, the word lines (WL0-WLn) correspond to the second gate electrode (EL2) shown in FIGS. 1 to 4, and the string select line (SSL) corresponds to the third gate electrode (EL3) shown in FIGS. 1 to 4. may apply.

Referring to the drawing, in step S810, the three-dimensional flash memory is connected to the bit line (sel BL0) of the selected cell string (sel CSTR) corresponding to the target memory cell that is the target of the read operation among the cell strings (CSTR). A first voltage (V1; for example, 1V) higher than the ground voltage (GND; for example, 0V) may be applied.

In step S820, the 3D flash memory may apply a verification voltage (Vverify; for example, 20V) to the selected word line (sel WL) corresponding to the target memory cell among the word lines.

In step S830, the three-dimensional flash memory applies a read voltage (Vread) to each of the unselected word lines (unsel WL) except for the selected word line (sel WL) among the word lines; the read voltage is applied to the ground and string selection transistors. A threshold voltage of (GST, SST), which is higher than the threshold voltage of the memory transistor in the program state and lower than the program voltage (Vpgm), may be the above-described pass voltage (Vpass), for example, 6V).

In step S840, the 3D flash memory may apply a positive voltage (eg, 2V) to the back gate (BG). The reason why a positive voltage is applied to the back gate (BG) is to improve cell current in the 3D flash memory.

Accordingly, in step S850, the 3D flash memory applies a first voltage to the bit line (sel BL0) of the selected cell string (sel CSTR), a verification voltage is applied to the selected word line (sel WL), and the unselected word In response to a read voltage being applied to each of the lines and a positive voltage being applied to the back gate (BG), a read operation may be performed on the target memory cell.

The read operation method described above is performed by applying a positive voltage to the back gate (BG) when reading after a program operation, thereby achieving the effect of improving cell current compared to the existing method.

FIGS. 10 and 11 are diagrams showing pulses of applied voltages in a program operation and a read operation performed by the three-dimensional flash memory shown in FIG. 4.

The pulses of applied voltages in the program operation and read operation performed by the three-dimensional flash memory with a structure including a back gate (BG), described above with reference to FIGS. 7 and 8, are as shown in FIG. 10 or 11.

Figure 12 is a perspective view schematically showing an electronic system including a three-dimensional flash memory according to embodiments.

Referring to FIG. 12, an electronic system 1200 including a three-dimensional flash memory according to embodiments includes a main board 1201, a controller 1202 mounted on the main board 1201, and one or more semiconductor packages 1203. ) and DRAM 1204.

The semiconductor package 1203 and the DRAM 1204 may be connected to the controller 1202 through wiring patterns 1205 provided on the main board 1201.

The main board 1201 may include a connector 1206 including a plurality of pins coupled to an external host. The number and arrangement of a plurality of pins in the connector 1206 may vary depending on the communication interface between the electronic system 1200 and an external host.

For example, the electronic system 1200 may use any of the interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIExpress), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). Depending on one, you can communicate with an external host. The electronic system 1200 may operate by, for example, power supplied from an external host through the connector 1206. The electronic system 1200 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to the controller 1202 and the semiconductor package 1203.

The controller 1202 can write data to or read data from the semiconductor package 1203 and improve the operating speed of the electronic system 1200.

The DRAM 1204 may be a buffer memory to alleviate the speed difference between the semiconductor package 1203, which is a data storage space, and an external host. The DRAM 1204 included in the electronic system 1200 may operate as a type of cache memory and may provide space for temporarily storing data during control operations for the semiconductor package 1203. When the electronic system 1200 includes the DRAM 1204, the controller 1202 may further include a DRAM controller for controlling the DRAM 1204 in addition to a NAND controller for controlling the semiconductor package 1203.

The semiconductor package 1203 may include first and second semiconductor packages 1203a and 1203b that are spaced apart from each other. The first and second semiconductor packages 1203a and 1203b may each include a plurality of semiconductor chips 1220. Each of the first and second semiconductor packages 1203a and 1203b includes a package substrate 1210, semiconductor chips 1220 on the package substrate 1210, and adhesive layers 1230 disposed on the lower surfaces of each of the semiconductor chips 1220. ), connection structures 1240 that electrically connect the semiconductor chips 1220 and the package substrate 1210, and a molding layer 1250 that covers the semiconductor chips 1220 and the connection structures 1240 on the package substrate 1210. may include.

The package substrate 1210 may be a printed circuit board including upper package pads 1211. Each semiconductor chip 1220 may include input/output pads 1221. Each of the semiconductor chips 1220 may include the three-dimensional flash memory described above with reference to FIG. 3 or 4. More specifically, each of the semiconductor chips 1220 may include gate stacked structures 1222 and memory channel structures 1223. The gate stacked structures 1222 may correspond to the above-described stacked structures (ST), and the memory channel structures 1223 may correspond to the above-described vertical channel structures (VS). Accordingly, the above-described improved program operation can be performed on each of the semiconductor chips 1220.

The connection structures 1240 may be, for example, bonding wires that electrically connect the input/output pads 1221 and the top pads of the package 1211. Accordingly, in each of the first and second semiconductor packages 1203a and 1203b, the semiconductor chips 1220 may be electrically connected to each other using a bonding wire method, and may be electrically connected to the package upper pads 1211 of the package substrate 1210. Can be electrically connected. According to embodiments, in each of the first and second semiconductor packages 1203a and 1203b, the semiconductor chips 1220 are connected to a through electrode (Through Silicon Via) instead of the bonding wire-type connection structures 1240. They may be electrically connected to each other.

Unlike shown, the controller 1202 and the semiconductor chips 1220 may be included in one package. The controller 1202 and the semiconductor chips 1220 may be mounted on a separate interposer board different from the main board 1201, and the controller 1202 and the semiconductor chips 1220 may be connected to each other by wiring provided on the interposer board. there is.

As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims (11)

delete delete delete delete word lines extending in the horizontal direction on the substrate and arranged to be spaced apart in the vertical direction; and cell strings extending in the vertical direction and passing through the word lines - each of the cell strings covers a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern and extending in the vertical direction. A program operation method for a three-dimensional flash memory comprising a vertical channel pattern formed, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines,
applying a negative voltage to a bit line of a selected cell string corresponding to a target memory cell that is the target of the program operation among the cell strings;
applying a program voltage to a selected word line corresponding to the target memory cell among the word lines; and
In response to applying the negative voltage to the bit line of the selected cell string and applying the program voltage to the selected word line, the target memory is formed by forming a channel in the vertical channel pattern included in the selected cell string. performing the program operation on the cell
Including,
When the vertical channel pattern includes a back gate extending in the vertical direction with at least a portion surrounded by the vertical channel pattern, applying a program voltage to the selected word line includes:
floating each of the remaining unselected word lines, excluding the selected word line; and
Applying a pass voltage to the back gate
A program operation method of a three-dimensional flash memory comprising: According to clause 5,
The step of floating each of the unselected word lines is,
As each of the unselected word lines is floated, a disturbance phenomenon caused by the pass voltage being applied to the unselected word lines is prevented. word lines extending in the horizontal direction on the substrate and arranged to be spaced apart in the vertical direction; and cell strings extending in the vertical direction and passing through the word lines - each of the cell strings covers a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern and extending in the vertical direction. A program operation method for a three-dimensional flash memory comprising a vertical channel pattern formed, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines,
applying a negative voltage to a bit line of a selected cell string corresponding to a target memory cell that is the target of the program operation among the cell strings;
applying a program voltage to a selected word line corresponding to the target memory cell among the word lines; and
In response to applying the negative voltage to the bit line of the selected cell string and applying the program voltage to the selected word line, the target memory is formed by forming a channel in the vertical channel pattern included in the selected cell string. performing the program operation on the cell
Including,
When the vertical channel pattern includes a back gate extending in the vertical direction with at least a portion surrounded by the vertical channel pattern, applying a program voltage to the selected word line includes:
applying a ground voltage to each of the unselected word lines, excluding the selected word line; and
Applying a pass voltage to the back gate
A program operation method of a three-dimensional flash memory comprising: In clause 7,
The step of floating each of the unselected word lines is,
As the ground voltage is applied to each of the unselected word lines, an interference phenomenon caused by the pass voltage being applied to the unselected word lines is prevented. delete word lines extending in the horizontal direction on the substrate and arranged to be spaced apart in the vertical direction; and cell strings extending in the vertical direction and passing through the word lines - each of the cell strings covers a data storage pattern extending in the vertical direction and an inner wall of the data storage pattern and extending in the vertical direction. A vertical channel pattern is formed, wherein the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines, and the vertical channel pattern is at least partially surrounded by the vertical channel pattern. A read operation method of a three-dimensional flash memory comprising a back gate extending in a vertical direction, comprising:
applying a first voltage higher than the ground voltage to a bit line of a selected cell string corresponding to a target memory cell that is the target of the read operation among the cell strings;
applying a verification voltage to a selected word line corresponding to the target memory cell among the word lines;
applying a read voltage to each of the unselected word lines other than the selected word line;
applying a positive voltage to the back gate; and
A first voltage is applied to the bit line of the selected cell string, the verification voltage is applied to the selected word line, a pass voltage is applied to each of the unselected word lines, and the positive voltage is applied to the back gate. In response to being selected, performing the read operation on the target memory cell.
A method of reading a three-dimensional flash memory comprising: According to clause 10,
The step of applying a positive voltage to the back gate is,
A read operation method for a three-dimensional flash memory, characterized in that the step of applying the positive voltage to the back gate in order to improve cell current in the three-dimensional flash memory.