KR102627215B1 - Three dimensional flash memory including connection unit and manufacturing method thereof - Google Patents

Abstract

A three-dimensional flash memory including a connection portion and a method of manufacturing the same are disclosed. According to one embodiment, the three-dimensional flash memory is formed by extending in the horizontal direction and forming interlayer insulating films and gate electrodes alternately stacked in the vertical direction, penetrating the interlayer insulating films and the gate electrodes and extending in the vertical direction. Vertical channel structures - each of the vertical channel structures includes a data storage pattern extending in the vertical direction and a vertical channel pattern covering an inner wall of the data storage pattern and extending in the vertical direction. Stack structures comprising, the stack structures being stacked in the vertical direction; and connecting portions disposed between the stack structures and protruding in the horizontal direction from each of the vertical channel patterns to connect the vertical channel patterns of each of the stack structures to each other.

Description

3D flash memory including connection and manufacturing method thereof {THREE DIMENSIONAL FLASH MEMORY INCLUDING CONNECTION UNIT AND MANUFACTURING METHOD THEREOF}

The following embodiments relate to 3D flash memory, and more specifically, technology for 3D flash memory manufactured through a stack lamination process.

Flash memory devices are electrically erasable programmable read only memory (EEPROM) that can be electrically programmed and erased by electrically controlling the input and output of data by Fowler-Nordheimtunneling (Fowler-Nordheimtunneling) or hot electron injection. , can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, etc.

In these flash memory devices, it is required to increase the degree of integration to meet the excellent performance and low price demanded by consumers, and a three-dimensional structure in which memory cell transistors are arranged vertically to form a cell string has been proposed.

3D flash memory has recently become increasingly sophisticated and integrated, and a manufacturing process in which a plurality of stack structures are stacked vertically is being used to implement a highly sophisticated and integrated structure.

However, in the case of a stack lamination process, the vertical channel pattern (VCP) of each stack structure may be misaligned, resulting in a decrease in channel current characteristics.

Accordingly, the following embodiments are intended to propose techniques for solving the problems described.

One embodiment is to solve the problem of deterioration of channel current characteristics due to vertical channel pattern misalignment in the stack stacking process, a three-dimensional flash memory having a structure including connection parts connecting vertical channel patterns of each stack structure to each other, the same. A manufacturing method and an electronic system including the same are proposed.

In particular, embodiments propose a dimensional flash memory with a structure in which each of the connection parts protrudes in the horizontal direction beyond each of the vertical channel patterns, a method of manufacturing the same, and an electronic system including the same.

However, the technical problems to be solved by the present invention are not limited to the above problems, and may be expanded in various ways without departing from the technical spirit and scope of the present invention.

According to one embodiment, the three-dimensional flash memory includes interlayer insulating films and gate electrodes extending in the horizontal direction and alternately stacked in the vertical direction, penetrating the interlayer insulating films and the gate electrodes and extending in the vertical direction. Vertical channel structures formed - each of the vertical channel structures includes a data storage pattern extending in the vertical direction and a vertical channel pattern covering an inner wall of the data storage pattern and extending in the vertical direction. each comprising stack structures, wherein the stack structures are stacked in the vertical direction; and connecting portions disposed between the stack structures and protruding in the horizontal direction from each of the vertical channel patterns to connect the vertical channel patterns of each of the stack structures to each other.

According to one aspect, when each of the vertical channel patterns includes a back gate extending in the vertical direction with at least a portion surrounded by each of the vertical channel patterns, the back gate is formed in the vertical direction. The vertical semiconductor pattern is formed in a tube shape including an internal hole extending in the vertical direction, or is included in an upper stack structure among the stack structures when each of the vertical channel patterns includes a vertical semiconductor pattern. The vertical semiconductor pattern included in the lower stack structure may be formed in a pillar shape with a closed interior so that it is separated by each of the connection parts.

According to one embodiment, a method of manufacturing a three-dimensional flash memory includes forming interlayer insulating films and gate electrodes extending in the horizontal direction and alternately stacked in the vertical direction, and interlayer insulating films and gate electrodes in the vertical direction. preparing a lower stack structure including penetrating vertical channel structures; forming connections on the lower stack structure based on the positions of the vertical channel structures in the lower stack structure; and the interlayer insulating films and the gate electrodes extending in the horizontal direction and alternately stacked in the vertical direction on the upper part of the lower stack structure where the connection portions are formed, and the interlayer insulating films and the gate electrodes in the vertical direction. and forming an upper stack structure including the vertical channel structures penetrating in one direction.

According to one embodiment, a method of manufacturing a three-dimensional flash memory includes forming interlayer insulating films and gate electrodes extending in the horizontal direction and alternately stacked in the vertical direction, and interlayer insulating films and gate electrodes in the vertical direction. preparing a lower stack structure including penetrating vertical channel structures; forming connections on the lower stack structure based on the positions of the vertical channel structures in the lower stack structure; The interlayer insulating films and the gate electrodes are formed extending in the horizontal direction and alternately stacked in the vertical direction on the upper part of the lower stack structure where the connecting portions are formed, and the interlayer insulating films and the gate electrodes are formed in the vertical direction. forming an upper stack structure including channel holes penetrating; forming channel connection holes penetrating the connection parts in the vertical direction based on the positions of the channel holes; and forming the vertical channel structures on inner walls of the channel holes and inner walls of the channel connection holes, extending in the vertical direction.

According to one aspect, forming the connections on the lower stack structure includes etching an upper portion of the lower stack structure and forming the connections in the remaining spaces; Alternatively, it may be characterized in that it includes any one of the steps of forming the connection portions on the upper part of the lower stack structure.

Embodiments may propose a three-dimensional flash memory with a structure including connectors connecting vertical channel patterns of each of the stack structures, a manufacturing method thereof, and an electronic system including the same.

In particular, embodiments may propose a dimensional flash memory with a structure in which each of the connection parts protrudes in the horizontal direction beyond each of the vertical channel patterns, a manufacturing method thereof, and an electronic system including the same.

Therefore, the three-dimensional flash memory according to one embodiment can solve the problem of deterioration of channel current characteristics due to vertical channel pattern misalignment in the stack stacking process.

However, the effects of the present invention are not limited to the above effects, and may be expanded in various ways without departing from the technical spirit and scope of the present invention.

1 is a simplified circuit diagram showing an array of three-dimensional flash memory according to one embodiment.
Figure 2 is a plan view showing the structure of a three-dimensional flash memory according to an embodiment.
FIG. 3 is a cross-sectional view showing the structure of a three-dimensional flash memory according to an embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.
FIG. 4 is a cross-sectional view for explaining another example of implementation of connection parts included in the three-dimensional flash memory shown in FIG. 3, and corresponds to a cross-section taken along line A-A' of FIG. 2.
FIG. 5 is a cross-sectional view showing the structure of a three-dimensional flash memory according to another embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2.
FIG. 6 is a cross-sectional view for explaining another example of implementation of connection parts included in the three-dimensional flash memory shown in FIG. 5, and corresponds to a cross-section taken along line A-A' of FIG. 2.
FIG. 7 is a flow chart showing a method of manufacturing a three-dimensional flash memory having the structure shown in FIGS. 3 and 4.
Figures 8A to 8E are cross-sectional views showing a three-dimensional flash memory to explain the manufacturing method shown in Figure 7.
FIG. 9 is a flow chart showing a method of manufacturing a three-dimensional flash memory having the structure shown in FIGS. 5 and 6.
Figures 10a to 10g are cross-sectional views showing a three-dimensional flash memory to explain the manufacturing method shown in Figure 9.
Figure 11 is a perspective view schematically showing an electronic system including a three-dimensional flash memory according to embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or limited by the examples. Additionally, the same reference numerals in each drawing indicate the same members.

Additionally, terminologies used in this specification are terms used to appropriately express preferred embodiments of the present invention, and may vary depending on the intention of the viewer, operator, or customs in the field to which the present invention belongs. Therefore, definitions of these terms should be made based on the content throughout this specification. For example, in this specification, singular forms also include plural forms unless specifically stated otherwise in the context. Additionally, as used herein, “comprises” and/or “comprising” refers to a referenced component, step, operation, and/or element that includes one or more other components, steps, operations, and/or elements. It does not exclude the presence or addition of elements. Additionally, although terms such as first and second are used in this specification to describe various areas, directions, and shapes, these areas, directions, and shapes should not be limited by these terms. These terms are merely used to distinguish one area, direction or shape from another area, direction or shape. Accordingly, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

Additionally, it should be understood that the various embodiments of the present invention are different from one another but are not necessarily mutually exclusive. For example, specific shapes, structures and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention with respect to one embodiment. Additionally, it should be understood that the location, arrangement, or configuration of individual components in each presented embodiment category may be changed without departing from the technical spirit and scope of the present invention.

Hereinafter, a three-dimensional flash memory according to embodiments, a method of operating the same, and an electronic system including the same will be described in detail with reference to the drawings.

1 is a simplified circuit diagram showing an array of three-dimensional flash memory according to one embodiment.

Referring to FIG. 1, an array of three-dimensional flash memory according to an embodiment includes a common source line (CSL), a plurality of bit lines (BL0, BL1, BL2), and a common source line (CSL) and bit lines (BL0). , BL1, and BL2) may include a plurality of cell strings (CSTR).

The bit lines BL0, BL1, and BL2 may extend in the second direction D2 and be spaced apart from each other in the first direction D1 and may be arranged two-dimensionally. Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and may form a rectangular coordinate system defined by the X, Y, and Z axes.

A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0, BL1, and BL2). The cell strings CSTR may be provided between the bit lines BL0, BL1, and BL2 and one common source line CSL and may be commonly connected to the common source line CSL. At this time, a plurality of common source lines (CSL) may be provided, and the plurality of common source lines (CSL) may extend in the first direction (D1) and be spaced apart from each other along the second direction (D2), forming a two-dimensional can be arranged sequentially. The same electrical voltage may be applied to the plurality of common source lines (CSL), but this is not limited or limited, and each of the plurality of common source lines (CSL) is electrically independently controlled, so that different voltages may be applied. there is.

The cell strings CSTR may extend in the third direction D3 and be arranged to be spaced apart from each other along the second direction D2 for each bit line. According to the embodiment, each of the cell strings (CSTR) is connected to a ground selection transistor (GST) connected to the common source line (CSL), the bit lines (BL0, BL1, BL2), and the first and second strings connected in series. Memory cell transistors (MCT) and erase control transistor (ECT) arranged in series between the selection transistors (SST1, SST2), the ground selection transistor (GST) and the first and second string selection transistors (SST1, SST2) ) can be composed of. Additionally, each memory cell transistor (MCT) may include a data storage element.

As an example, each cell string CSTR may include first and second string selection transistors SST1 and SST2 connected in series, and the second string selection transistor SST2 may be connected to the bit lines BL0 and BL1. , BL2) can be connected to one of the following. However, without being limited or limited thereto, each cell string CSTR may include one string select transistor. As another example, the ground selection transistor GST in each cell string CSTR may be composed of a plurality of MOS transistors connected in series, similar to the first and second string selection transistors SST1 and SST2. .

One cell string (CSTR) may be composed of a plurality of memory cell transistors (MCT) having different distances from the common source lines (CSL). That is, the memory cell transistors MCT may be connected in series while being arranged along the third direction D3 between the first string selection transistor SST1 and the ground selection transistor GST. The erase control transistor (ECT) may be connected between the ground select transistor (GST) and the common source lines (CSL). Each of the cell strings (CSTR) is between the first string select transistor (SST1) and the highest one of the memory cell transistors (MCT) and between the ground select transistor (GST) and the lowest one of the memory cell transistors (MCT). It may further include dummy cell transistors (DMCs) each connected to each other.

According to an embodiment, the first string selection transistor SST1 may be controlled by the first string selection lines SSL1-1, SSL1-2, and SSL1-3, and the second string selection transistor SST2 may be controlled by the first string selection lines SSL1-1, SSL1-2, and SSL1-3. It can be controlled by 2 string selection lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors (MCT) may each be controlled by a plurality of word lines (WL0-WLn), and the dummy cell transistors (DMC) may each be controlled by a dummy word line (DWL). The ground select transistor GST may be controlled by the ground select lines GSL0, GSL1, and GSL2, and the erase control transistor ECT may be controlled by the erase control line ECL. A plurality of erase control transistors (ECT) may be provided. Common source lines (CSL) may be commonly connected to sources of erase control transistors (ECT).

The gate electrodes of the memory cell transistors (MCT), which are provided at substantially the same distance from the common source lines (CSL), may be commonly connected to one of the word lines (WL0-WLn, DWL) and be in an equipotential state. . However, without being limited or limited thereto, even if the gate electrodes of the memory cell transistors (MCT) are provided at substantially the same level from the common source lines (CSL), the gate electrodes provided in different rows or columns may be controlled independently. there is.

Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string selection lines (SSL2-1, SSL2-2, SSL2-3) ) extends along the first direction (D1), are spaced apart from each other in the second direction (D2), and may be arranged two-dimensionally. Ground selection lines (GSL0, GSL1, GSL2), first string selection lines (SSL1-1, SSL1-2, SSL1-3), and second string provided at substantially the same level from the common source lines (CSL) The selection lines (SSL2-1, SSL2-2, and SSL2-3) may be electrically separated from each other. Additionally, the erase control transistors ECT of different cell strings CSTR may be controlled by a common erase control line ECL. Erase control transistors (ECT) may generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, during an erase operation of the memory cell array, an erase voltage may be applied to the bit lines (BL0, BL1, BL2) and/or the common source lines (CSL), and the string select transistor (SST) and/or Alternatively, gate-induced leakage current may be generated in the erase control transistors (ECT).

The string selection line (SSL) described above may be expressed as an upper selection line (USL), and the ground selection line (GSL) may be expressed as a lower selection line.

Figure 2 is a plan view showing the structure of a three-dimensional flash memory according to an embodiment. FIG. 3 is a cross-sectional view showing the structure of a three-dimensional flash memory according to an embodiment, and corresponds to a cross-section taken along line A-A' of FIG. 2, and FIG. 4 is a cross-sectional view showing the structure of a three-dimensional flash memory shown in FIG. 3. This is a cross-sectional view to explain another example of implementation of the connection parts, and corresponds to a cross-section taken along line A-A' in Figure 2.

2 and 4, the substrate (SUB) may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a monocrystalline silicon substrate. . The substrate SUB may be doped with a first conductivity type impurity (eg, a P-type impurity).

Stacked structures (ST) may be disposed on the substrate (SUB). The stacked structures ST may extend in the first direction D1 and be two-dimensionally arranged along the second direction D2. Additionally, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1, EL2, and EL3 and interlayer insulating films ILD that are alternately stacked in a vertical direction perpendicular to the top surface of the substrate SUB (for example, in the third direction D3). may include. The stacked structures ST may have a substantially flat top surface. That is, the top surface of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or the reverse direction of the third direction D3.

Referring again to FIG. 1, each of the gate electrodes EL1, EL2, and EL3 includes an erase control line (ECL), ground selection lines (GSL0, GSL1, GSL2), and a word line sequentially stacked on the substrate (SUB). (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) It can be.

Each of the gate electrodes EL1, EL2, and EL3 may extend in the first direction D1 and have substantially the same thickness in the third direction D3. Hereinafter, thickness refers to the thickness in the third direction (D3). Each of the gate electrodes EL1, EL2, and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1, EL2, and EL3 is made of a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1, EL2, and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal materials described.

More specifically, the gate electrodes EL1, EL2, and EL3 include the first gate electrode EL1 at the bottom, the third gate electrode EL3 at the top, and the first gate electrode EL1 and the third gate electrode EL3. It may include a plurality of second gate electrodes EL2 therebetween. The first gate electrode EL1 and the third gate electrode EL3 are each shown and described in singular form, but this is illustrative and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0, GSL1, and GLS2 shown in FIG. 1. The second gate electrode EL2 may correspond to one of the word lines WL0-WLn and DWL shown in FIG. 1. The third gate electrode EL3 is one of the first string selection lines SSL1-1, SSL1-2, and SSL1-3 shown in FIG. 1 or the second string selection lines SSL2-1 and SSL1-3. It may correspond to either SSL2-2 or SSL2-3).

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the length of the gate electrodes EL1, EL2, and EL3 of the stacked structures ST may decrease in the first direction D1 as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the greatest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the greatest length in the first direction D1 and the smallest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures (ST) may decrease as it moves away from the outer-most one of the vertical channel structures (VS), which will be described later, and the gate electrodes (EL1, The side walls of EL2 and EL3) may be spaced apart at regular intervals along the first direction D1 from a plan view.

Each of the interlayer dielectric layers (ILD) may have different thicknesses. For example, the lowest and uppermost of the interlayer insulating layers (ILD) may have a smaller thickness than the other interlayer insulating layers (ILD). However, this is an example and is not limited to this, and the thickness of each interlayer dielectric layer (ILD) may have a different thickness depending on the characteristics of the semiconductor device, or may all be set to be the same. The interlayer insulating films ILD may be formed of an insulating material to insulate the gate electrodes EL1, EL2, and EL3. As an example, the interlayer insulating films (ILD) may be formed of silicon oxide.

A plurality of channel holes CH may be provided penetrating a portion of the stacked structures ST and the substrate SUB. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures VS are a plurality of cell strings CSTR shown in FIG. 1 and may be connected to the substrate SUB and extend in the third direction D3. The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a portion of each of the vertical channel structures (VS) being buried inside the substrate (SUB), but is not limited or limited thereto and the vertical channel structures (VS) are connected to the substrate (SUB). This may be achieved by contacting the lower surface of (VS) with the upper surface of the substrate (SUB). When a portion of each of the vertical channel structures (VS) is buried inside the substrate (SUB), the lower surface of the vertical channel structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

A plurality of rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided. For example, as shown in FIG. 2 , rows of two vertical channel structures (VS) may penetrate one of the stacked structures (ST). However, without being limited or limited thereto, rows of three or more vertical channel structures (VS) may penetrate one of the stacked structures (ST). In a pair of adjacent columns, the vertical channel structures (VS) corresponding to one column may be shifted in the first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent column. there is. From a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited or restricted thereto, the vertical channel structures VS may be arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures (VS) is shown as having a pillar shape with the same width at the top and bottom, but it is not limited or limited thereto, and as it moves toward the third direction (D3), the first direction (D1) and the second direction (D2) may have a shape in which the width is increased. This is due to the limitation that when the channel holes CH are etched, their widths in the first direction D1 and the second direction D2 decrease as they go in the opposite direction of the third direction D3. The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a vertical semiconductor pattern (VSP), and a conductive pad (PAD). In each of the vertical channel structures (VS), the data storage pattern (DSP) may have a pipe shape with an open bottom or a macaroni shape, and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom. It can have a shape. The vertical semiconductor pattern (VSP) can fill the space surrounded by the vertical channel pattern (VCP) and the conductive pad (PAD).

The data storage pattern (DSP) covers the inner wall of each of the channel holes (CH) and contacts the vertical channel pattern (VCP) on the inside and the side walls of the gate electrodes (EL1, EL2, EL3) on the outside. You can. Accordingly, the areas corresponding to the second gate electrodes EL2 in the data storage pattern DSP are the second gate electrodes together with the areas corresponding to the second gate electrodes EL2 in the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by voltage applied through (EL2) can be configured. The memory cells correspond to memory cell transistors (MCT) shown in FIG. 1. That is, the data storage pattern DSP traps charges or holes by a voltage applied through the second gate electrodes EL2 or maintains the state of the charges (e.g., the polarization state of the charges) in the three-dimensional flash memory. It can act as a data storage. For example, an ONO (tunnel oxide (oxide)-charge storage layer (nitride)-blocking oxide) layer or a ferroelectric layer may be used as the data storage pattern (DSP). Such a data storage pattern (DSP) may represent a binary data value or a multi-valued data value by changing the state of trapped charges or holes, or it can represent a binary data value or a multi-valued data value by changing the state of the charges.

A vertical channel pattern (VCP) may cover the inner wall of the data storage pattern (DSP). The vertical channel pattern (VCP) may include a first part (VCP1) and a second part (VCP2) on the first part (VCP1).

The first portion (VCP1) of the vertical channel pattern (VCP) may be provided below each of the channel holes (CH) and may be in contact with the substrate (SUB). The first part (VCP1) of the vertical channel pattern (VCP) may be used to block, suppress, or minimize leakage current in each of the vertical channel structures (VS) and/or as an epitaxial pattern. For example, the thickness of the first portion (VCP1) of the vertical channel pattern (VCP) may be greater than the thickness of the first gate electrode (EL1). A sidewall of the first portion (VCP1) of the vertical channel pattern (VCP) may be surrounded by a data storage pattern (DSP). The top surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located at a higher level than the top surface of the first gate electrode (EL1). More specifically, the top surface of the first portion (VCP1) of the vertical channel pattern (VCP) may be located between the top surface of the first gate electrode (EL1) and the bottom surface of the lowest one of the second gate electrodes (EL2). The bottom surface of the first portion VCP1 of the vertical channel pattern VCP may be located at a lower level than the top surface of the substrate SUB (that is, the bottom surface of the lowest one of the interlayer insulating layers ILD). A portion of the first portion (VCP1) of the vertical channel pattern (VCP) may overlap the first gate electrode (EL1) in the horizontal direction. Hereinafter, the horizontal direction means any direction extending on a plane parallel to the first direction D1 and the second direction D2.

The second part (VCP2) of the vertical channel pattern (VCP) may extend from the top surface of the first part (VCP1) in the third direction (D3). The second portion (VCP2) of the vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the vertical semiconductor pattern (VSP) and may correspond to the second gate electrodes (EL2). Accordingly, the second part (VCP2) of the vertical channel pattern (VCP), together with the regions corresponding to the second gate electrodes (EL2) of the data storage pattern (DSP), as described above, may form memory cells. .

The top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be substantially coplanar with the top surface of the vertical semiconductor pattern (VSP). The top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be located at a higher level than the top surface of the uppermost one of the second gate electrodes (EL2). More specifically, the top surface of the second portion (VCP2) of the vertical channel pattern (VCP) may be located between the top and bottom surfaces of the third gate electrode (EL3).

The vertical channel pattern (VCP) is a component that transfers charges or holes to the data storage pattern (DSP), and may be formed of single crystalline silicon or polysilicon to form a channel or be boosted by an applied voltage. However, without being limited or limited thereto, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material that can block, suppress, or minimize leakage current. For example, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material containing at least one of In, Zn, or Ga with excellent leakage current characteristics. The vertical channel pattern (VCP) may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern (VCP) can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and at least one of the gate electrodes (EL1, EL2, EL3) The characteristics of any one transistor (for example, threshold voltage distribution and speed of program/read operations) can be improved, and as a result, the electrical characteristics of the 3D flash memory can be improved.

The vertical semiconductor pattern (VSP) may be surrounded by the second portion (VCP2) of the vertical channel pattern (VCP). The upper surface of the vertical semiconductor pattern (VSP) may contact the conductive pad (PAD), and the lower surface of the vertical semiconductor pattern (VSP) may contact the first portion (VCP1) of the vertical channel pattern (VCP). The vertical semiconductor pattern VSP may be spaced apart from the substrate SUB in the third direction D3. In other words, the vertical semiconductor pattern VSP may be electrically floating from the substrate SUB.

The vertical semiconductor pattern (VSP) may be formed of a material that helps diffusion of charges or holes in the vertical channel pattern (VCP). More specifically, the vertical semiconductor pattern (VSP) can be formed of a material with excellent charge and hole mobility. For example, the vertical semiconductor pattern (VSP) may be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material that is not doped with an impurity, or a polycrystalline semiconductor material. For a more specific example, the vertical semiconductor pattern VSP may be formed of polysilicon doped with the same first conductivity type impurity (eg, P-type impurity) as the substrate SUB. In other words, the vertical semiconductor pattern (VSP) can improve the speed of memory operation by improving the electrical characteristics of 3D flash memory.

Referring again to FIG. 1, the vertical channel structures (VS) include an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT). ) may correspond to the channels.

A conductive pad (PAD) may be provided on the top surface of the second portion (VCP2) of the vertical channel pattern (VCP) and the top surface of the vertical semiconductor pattern (VSP). The conductive pad (PAD) may be connected to the top of the vertical channel pattern (VCP) and the top of the vertical semiconductor pattern (VSP). The sidewall of the conductive pad (PAD) may be surrounded by a data storage pattern (DSP). The top surface of the conductive pad PAD may be substantially coplanar with the top surface of each of the stacked structures ST (that is, the top surface of the uppermost one of the interlayer dielectric layers ILD). The lower surface of the conductive pad PAD may be located at a lower level than the upper surface of the third gate electrode EL3. More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3. That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in the horizontal direction.

The conductive pad (PAD) may be formed of a semiconductor or conductive material doped with impurities. For example, the conductive pad (PAD) is doped with impurities (more precisely, impurities of a second conductivity type (e.g., N-type) different from the first conductivity type (e.g., P-type)) than the vertical semiconductor pattern (VSP). It can be formed from a semiconductor material.

The conductive pad (PAD) can reduce contact resistance between the bit line (BL) and the vertical channel pattern (VCP) (or vertical semiconductor pattern (VSP)), which will be described later.

Above, the vertical channel structures VS have been described as having a structure including a conductive pad (PAD), but they are not limited or limited thereto and may have a structure omitting the conductive pad (PAD). In this case, as the conductive pad (PAD) is omitted from the vertical channel structures (VS), the upper surface of each of the vertical channel pattern (VCP) and the vertical semiconductor pattern (VSP) is the upper surface of each of the stacked structures (ST) (i.e. Each of the vertical channel pattern (VCP) and the vertical semiconductor pattern (VSP) may be formed to extend in the third direction (D3) so as to be substantially coplanar with the top surface of the uppermost one of the interlayer insulating layers (ILD). Additionally, in this case, the bit line contact plug (BLPG), which will be described later, directly contacts the vertical channel pattern (VCP) instead of being indirectly electrically connected to the vertical channel pattern (VCP) through the conductive pad (PAD). Can be electrically connected.

In addition, although it has been described that the vertical channel structures VS include the vertical semiconductor pattern VSP, the present invention is not limited or limited thereto and the vertical semiconductor pattern VSP may be omitted.

In addition, although the vertical channel pattern (VCP) has been described as having a structure including a first part (VCP1) and a second part (VCP2), it is not limited or limited thereto and may have a structure excluding the first part (VCP1). You can. For example, the vertical channel pattern (VCP) is provided between the vertical semiconductor pattern (VSP) and the data storage pattern (DSP) formed to extend to the substrate (SUB) and is formed to extend to the substrate (SUB) to contact the substrate (SUB). You can. In this case, the bottom surface of the vertical channel pattern (VCP) may be located at a lower level than the top surface of the substrate (SUB) (the bottom surface of the lowest one of the interlayer dielectric layers (ILD)), and the top surface of the vertical channel pattern (VCP) may be located at a lower level than the top surface of the substrate (SUB). It can be substantially coplanar with the top surface of the pattern (VSP).

A separation trench TR extending in the first direction D1 may be provided between adjacent stacked structures ST. The common source region (CSR) may be provided inside the substrate (SUB) exposed by the isolation trench (TR). The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with second conductivity type impurities (eg, N-type impurities). The common source region (CSR) may correspond to the common source line (CSL) in FIG. 1.

A common source plug (CSP) may be provided in the isolation trench (TR). The common source plug (CSP) may be connected to the common source region (CSR). The top surface of the common source plug (CSP) may be substantially coplanar with the top surface of each of the stacked structures (ST) (that is, the top surface of the uppermost one of the interlayer insulating layers (ILD)). The common source plug (CSP) may have a plate shape extending in the first direction (D1) and the third direction (D3). At this time, the common source plug CSP may have a shape whose width in the second direction D2 increases as it moves toward the third direction D3.

Insulating spacers (SP) may be interposed between the common source plug (CSP) and the stacked structures (ST). Insulating spacers SP may be provided between adjacent stacked structures ST to face each other. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material with a low dielectric constant.

A capping insulating layer (CAP) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating layer (CAP) may cover the top surface of the uppermost one of the interlayer insulating layers (ILD), the top surface of the conductive pad (PAD), and the top surface of the common source plug (CSP). The capping insulating film (CAP) may be formed of an insulating material different from the interlayer insulating films (ILD). A bit line contact plug (BLPG) electrically connected to the conductive pad (PAD) may be provided inside the capping insulating film (CAP). The bit line contact plug BLPG may have a shape whose width in the first direction D1 and the second direction D2 increases as it moves toward the third direction D3.

A bit line (BL) may be provided on the capping insulating film (CAP) and the bit line contact plug (BLPG). The bit line BL corresponds to one of the plurality of bit lines BL0, BL1, and BL2 shown in FIG. 1 and may be formed to extend along the second direction D2 using a conductive material. The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1, EL2, and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through a bit line contact plug (BLPG). Here, the fact that the bit line (BL) is connected to the vertical channel structures (VS) may mean that it is connected to the vertical channel pattern (VCP) included in the vertical channel structures (VS).

A three-dimensional flash memory with this structure includes a voltage applied to each of the cell strings (CSTR), a voltage applied to the string selection line (SSL), a voltage applied to each of the word lines (WL0-WLn), and a ground selection line. Based on the voltage applied to the (GSL) and the voltage applied to the common source line (CSL), a program operation, a read operation, and an erase operation can be performed. For example, the 3D flash memory includes a voltage applied to each of the cell strings (CSTR), a voltage applied to the string select line (SSL), a voltage applied to each of the word lines (WL0-WLn), and a ground select line (GSL). Based on the voltage applied to ) and the voltage applied to the common source line (CSL), a channel is formed in the vertical channel pattern (VCP) to transfer charges or holes to the data storage pattern (DSP) of the target memory cell to operate the program. can be performed.

In addition, the three-dimensional flash memory according to one embodiment is not limited or limited to the described structure, and may include a vertical channel pattern (VCP), a data storage pattern (DSP), and gate electrodes (EL1, EL2, and EL3) depending on the implementation example. , it can be implemented in various structures provided that it includes a bit line (BL) and a common source line (CSL).

As the 3D flash memory with this structure is manufactured through a stack stacking process, each of the stacked structures (ST) may include an upper stack structure (USS) and a lower stack structure (LSS). The lower stack structure (LSS) is disposed on the substrate (SUB) and may include gate electrodes (part of EL1 and EL2) and interlayer insulating layers (ILD) alternately stacked in the vertical direction. The upper stack structure (USS) is stacked on the lower stack structure (LSS) and may include gate electrodes (part of EL2, EL3) and an interlayer insulating layer (ILD) alternately stacked in the vertical direction.

When the lower stack structure (LSS) and the upper stack structure (USS) are stacked, the vertical channel structures (VS) included in the lower stack structure (LSS) and the vertical channel structures (VS) included in the upper stack structure (USS) This misalignment problem may occur. For example, if the vertical channel patterns (VCP) of the lower stack structure (LSS) and the vertical channel patterns (VCP) of the upper stack structure (USS) are misaligned, a problem of deterioration of channel current characteristics may occur. Accordingly, each of the stacked structures (ST) of the three-dimensional flash memory is disposed between the upper stack structure (USS) and the lower stack structure (LSS), and has vertical channel patterns ( It may include connecting units (CU) that connect VCPs to each other. These connection units (CU) may be formed in a pillar shape with a closed interior so that the vertical semiconductor pattern (VSP) included in the upper stack structure (USS) and the vertical semiconductor pattern (VSP) included in the lower stack structure (LSS) are separated. Depending on the manufacturing process, there is a recessed type that is recessed in the uppermost interlayer dielectric (ILD) included in the lower stack structure (LSS) as shown in FIG. 3, or a recessed type that is included in the lower stack structure (LSS) as shown in FIG. 4. It may be formed in a protruding shape located on top of the uppermost interlayer insulating layer (ILD). When the connection portions CU are formed in a protruding shape, the connection portions CU may be accommodated by additional interlayer insulating films ILD that are not included in the upper and lower stack structures USS and LSS.

In particular, each of the connection units CU may have a shape that protrudes in the horizontal direction more than each of the vertical channel patterns VCP. In more detail, each of the connection portions CU may be formed to a size that accommodates each of the vertical channel patterns VCP on a plane, and thus may have a shape that protrudes in the horizontal direction beyond each of the vertical channel patterns VCP. Additionally, the connection units CU may be formed at a location to accommodate the vertical channel patterns VCP of the upper and lower stack structures USS and LSS to connect the vertical channel patterns VCP to each other.

Additionally, each of the connection units CU may be formed of the same material as the vertical channel patterns VCP in order to connect the vertical channel patterns VCP of the upper and lower stack structures USS and LSS. For example, each of the connection units CU may be formed of single crystalline silicon or polysilicon constituting the vertical channel patterns VCP. However, without being limited or limited thereto, each of the connection units CU may be formed of various materials capable of connecting the vertical channel patterns VCP of the upper and lower stack structures USS and LSS.

As described, the 3D flash memory includes connection units (CU), thereby connecting the vertical channel patterns (VCP) of each of the stack structures (USS, LSS) to each other, thereby solving the problem of deteriorating channel current characteristics.

The three-dimensional flash memory is manufactured through a stack stacking process and is described as including an upper stack structure (USS) and a lower stack structure (LSS). However, the number of stack structures stacked in the stack stacking process is adjusted to produce three or more. It may also include stack structures (eg, top stack structures (USS), middle stack structures (MSS), and bottom stack structures (LSS). In this case, the connection units CU may be arranged in groups arranged in the horizontal direction (first direction D1 and second direction D2) and spaced apart in the third direction D3 and placed at connection portions of the stack structures. A plurality of buffer layers BU may be provided to surround groups of connection units CU arranged to be spaced apart in the third direction D3, and may be positioned to be spaced apart from each other in the third direction D3.

FIG. 5 is a cross-sectional view showing the structure of a three-dimensional flash memory according to another embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, and FIG. 6 is a structure included in the three-dimensional flash memory shown in FIG. 5. This is a cross-sectional view to explain another example of implementation of the connection parts, and corresponds to a cross-section taken along line A-A' in Figure 2.

5 to 6, referring to FIG. 5, the substrate (SUB) is a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystal epitaxial layer grown on a monocrystalline silicon substrate. It may be a semiconductor substrate. The substrate SUB may be doped with a first conductivity type impurity (eg, a P-type impurity).

Stacked structures (ST) may be disposed on the substrate (SUB). The stacked structures ST may extend in the first direction D1 and be two-dimensionally arranged along the second direction D2. Additionally, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1, EL2, and EL3 and interlayer insulating films ILD that are alternately stacked in a vertical direction perpendicular to the top surface of the substrate SUB (for example, in the third direction D3). may include. The stacked structures ST may have a substantially flat top surface. That is, the top surface of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or the reverse direction of the third direction D3.

Referring again to FIG. 1, each of the gate electrodes EL1, EL2, and EL3 includes an erase control line (ECL), ground selection lines (GSL0, GSL1, GSL2), and a word line sequentially stacked on the substrate (SUB). (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) It can be.

Each of the gate electrodes EL1, EL2, and EL3 may extend in the first direction D1 and have substantially the same thickness in the third direction D3. Hereinafter, thickness refers to the thickness in the third direction (D3). Each of the gate electrodes EL1, EL2, and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1, EL2, and EL3 is made of a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1, EL2, and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal materials described.

More specifically, the gate electrodes EL1, EL2, and EL3 include the first gate electrode EL1 at the bottom, the third gate electrode EL3 at the top, and the first gate electrode EL1 and the third gate electrode EL3. It may include a plurality of second gate electrodes EL2 therebetween. The first gate electrode EL1 and the third gate electrode EL3 are each shown and described in singular form, but this is illustrative and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0, GSL1, and GLS2 shown in FIG. 1. The second gate electrode EL2 may correspond to one of the word lines WL0-WLn and DWL shown in FIG. 1. The third gate electrode EL3 is one of the first string selection lines SSL1-1, SSL1-2, and SSL1-3 shown in FIG. 1 or the second string selection lines SSL2-1 and SSL1-3. It may correspond to either SSL2-2 or SSL2-3).

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the length of the gate electrodes EL1, EL2, and EL3 of the stacked structures ST may decrease in the first direction D1 as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the greatest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the greatest length in the first direction D1 and the smallest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures (ST) may decrease as it moves away from the outer-most one of the vertical channel structures (VS), which will be described later, and the gate electrodes (EL1, The side walls of EL2 and EL3) may be spaced apart at regular intervals along the first direction D1 from a plan view.

Each of the interlayer dielectric layers (ILD) may have different thicknesses. For example, the lowest and uppermost of the interlayer insulating layers (ILD) may have a smaller thickness than the other interlayer insulating layers (ILD). However, this is an example and is not limited to this, and the thickness of each interlayer dielectric layer (ILD) may have a different thickness depending on the characteristics of the semiconductor device, or may all be set to be the same. The interlayer insulating films ILD may be formed of an insulating material to insulate the gate electrodes EL1, EL2, and EL3. As an example, the interlayer insulating films (ILD) may be formed of silicon oxide.

A plurality of channel holes CH may be provided penetrating a portion of the stacked structures ST and the substrate SUB. Vertical channel structures (VS) may be provided within the channel holes (CH). The vertical channel structures VS are a plurality of cell strings CSTR shown in FIG. 1 and may be connected to the substrate SUB and extend in the third direction D3. The connection of the vertical channel structures (VS) to the substrate (SUB) may be achieved by a portion of each of the vertical channel structures (VS) being buried inside the substrate (SUB), but is not limited or limited thereto and the vertical channel structures (VS) are connected to the substrate (SUB). This may be achieved by contacting the lower surface of (VS) with the upper surface of the substrate (SUB). When a portion of each of the vertical channel structures (VS) is buried inside the substrate (SUB), the lower surface of the vertical channel structures (VS) may be located at a lower level than the upper surface of the substrate (SUB).

A plurality of rows of vertical channel structures (VS) penetrating one of the stacked structures (ST) may be provided. For example, as shown in FIG. 2 , rows of two vertical channel structures (VS) may penetrate one of the stacked structures (ST). However, without being limited or limited thereto, rows of three or more vertical channel structures (VS) may penetrate one of the stacked structures (ST). In a pair of adjacent columns, the vertical channel structures (VS) corresponding to one column may be shifted in the first direction (D1) from the vertical channel structures (VS) corresponding to the other adjacent column. there is. From a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited or restricted thereto, the vertical channel structures VS may be arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures (VS) is shown as having a pillar shape with the same width at the top and bottom, but it is not limited or limited thereto, and as it moves toward the third direction (D3), the first direction (D1) and the second direction (D2) may have a shape in which the width is increased. This is due to the limitation that when the channel holes CH are etched, their widths in the first direction D1 and the second direction D2 decrease as they go in the opposite direction of the third direction D3. The upper surface of each of the vertical channel structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

Each of the vertical channel structures (VS) may include a data storage pattern (DSP), a vertical channel pattern (VCP), a back gate (BG), and a conductive pad (PAD). In each of the vertical channel structures (VS), the data storage pattern (DSP) may have a pipe shape with an open bottom or a macaroni shape, and the vertical channel pattern (VCP) may have a pipe shape or a macaroni shape with a closed bottom. It can have a shape. The back gate (BG) may be formed to apply a voltage to the vertical channel pattern (VCP) while being at least partially surrounded by the vertical channel pattern (VCP). Hereinafter, the fact that the back gate (BG) is included in the vertical channel pattern (VCP) may mean that the back gate (BF) is at least partially surrounded by the vertical channel pattern (VCP), as described.

The data storage pattern (DSP) covers the inner wall of each of the channel holes (CH), contacts the vertical channel pattern (VCP) on the inside, and contacts the sidewalls of the gate electrodes (EL1, EL2, EL3) on the outside. You can. Accordingly, the areas corresponding to the second gate electrodes EL2 in the data storage pattern DSP are the second gate electrodes together with the areas corresponding to the second gate electrodes EL2 in the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by voltage applied through (EL2) can be configured. The memory cells correspond to memory cell transistors (MCT) shown in FIG. 1. That is, the data storage pattern DSP traps charges or holes by a voltage applied through the second gate electrodes EL2 or maintains the state of the charges (e.g., the polarization state of the charges) in the three-dimensional flash memory. It can act as a data storage. For example, an ONO (tunnel oxide (oxide)-charge storage layer (nitride)-blocking oxide) layer or a ferroelectric layer may be used as the data storage pattern (DSP). Such a data storage pattern (DSP) may represent a binary data value or a multi-valued data value by changing the trapped charges or holes, or it can represent a binary data value or a multi-valued data value by changing the state of the charges.

The vertical channel pattern (VCP) may cover the inner wall of the data storage pattern (DSP) and may extend in the third direction (D3). The vertical channel pattern (VCP) may be provided between the data storage pattern (DSP) and the back gate (BG) and may correspond to the second gate electrodes (EL2). Accordingly, as described above, the vertical channel pattern VCP may form memory cells together with regions corresponding to the second gate electrodes EL2 in the data storage pattern DSP.

The top surface of the vertical channel pattern VCP may be located at a higher level than the top surface of the uppermost one of the second gate electrodes EL2. More specifically, the top surface of the vertical channel pattern VCP may be located between the top and bottom surfaces of the third gate electrode EL3.

The vertical channel pattern (VCP) is a component that transfers charges or holes to the data storage pattern (DSP), and may be formed of single crystalline silicon or polysilicon to form a channel or be boosted by an applied voltage. However, without being limited or limited thereto, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material that can block, suppress, or minimize leakage current. For example, the vertical channel pattern (VCP) may be formed of an oxide semiconductor material or a group 4 semiconductor material containing at least one of In, Zn, or Ga with excellent leakage current characteristics. The vertical channel pattern (VCP) may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern (VCP) can block, suppress, or minimize leakage current to the gate electrodes (EL1, EL2, EL3) or the substrate (SUB), and at least one of the gate electrodes (EL1, EL2, EL3) The characteristics of any one transistor (for example, threshold voltage distribution and speed of program/read operations) can be improved, and as a result, the electrical characteristics of the 3D flash memory can be improved.

The back gate (BG) is at least partially surrounded and contacted by the vertical channel pattern (VCP) and may be formed to apply a voltage to the vertical channel pattern (VCP) for a memory operation. For this purpose, the back gate (BG) is a doped semiconductor (ex, doped silicon, etc.), metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), It may be formed of a conductive material containing at least one selected from Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.). The back gate (BG) may include at least one of all metal materials that can be formed by ALD in addition to the metal materials described.

At this time, the back gate BG extends along the third direction D3 from the level corresponding to the first gate electrode EL1 to the level corresponding to the second gate electrode EL2 within the vertical channel pattern VCP. can be formed. That is, the top surface of the back gate BG may be located at a higher level than the top surface of the uppermost one of the second gate electrodes EL2. However, without being limited or restricted thereto, the back gate BG may be formed to extend along the third direction D3 within the vertical channel pattern VCP to a level corresponding to the third gate electrode EL3.

Although the lower substrate in contact with the lower surface of the back gate (BG) is omitted in the drawing, the lower substrate in contact with the lower surface of the back gate (BG) may be included depending on the implementation example. Additionally, depending on the implementation example, the back gate BG may be formed from inside the substrate SUB or may be formed from the top of the substrate SUB.

This back gate (BG) is included in the vertical channel pattern (VCP) of each cell string (CSTR), and the back gate (BG) included in the vertical channel pattern (VCP) of each cell string (CSTR) is The back gate BG may be electrically connected to all planes formed by the first direction D1 and the second direction D2. That is, the back gate (BG) may be commonly connected to the cell strings (CSTR). In this case, the back gates (BG) of each of the cell strings (CSTR) are collectively controlled so that the same voltage can be applied to all of them.

However, without being limited or limited thereto, the back gates BG included in the vertical channel pattern VCP of each of the cell strings CSTR may be electrically connected to each other along the first direction D1 of FIG. 1 . In this case, each back gate (BG) of the cell strings (CSTR) arranged along the second direction (D2) is electrically independently controlled, so that different voltages can be applied, and in the first direction of FIG. 1 The back gates (BG) of each of the cell strings (CSTR) arranged along (D1) are collectively controlled so that the same voltage can be applied.

Additionally, the back gates BG included in the vertical channel pattern VCP of each of the cell strings CSTR may be electrically connected to each other along the second direction D2 of FIG. 1 . In this case, the back gates BG of each of the cell strings CSTR arranged along the first direction D1 are electrically independently controlled, so that different voltages can be applied, and in the second direction of FIG. 1 The back gates (BG) of each of the cell strings (CSTR) arranged along (D2) are collectively controlled so that the same voltage can be applied.

An insulating film (INS) is disposed between the back gate (BG) and the vertical channel pattern (VCP), thereby preventing the back gate (BG) from directly contacting the vertical channel pattern (VCP). The insulating layer (ILD), like the interlayer insulating layers (ILD), may be formed of an insulating material such as silicon oxide.

Above, it has been described as a structure in which the back gate (BG) is formed in the inner hole of the vertical channel pattern (VCP) and is tightly surrounded by the vertical channel pattern (VCP), but is not limited or limited thereto and is not limited to the vertical channel pattern (VCP). It may be formed in a structure in which at least part of the structure is surrounded by VCP). For example, a structure in which the back gate (BG) and the insulating layer (INS) are included in at least a portion of the vertical channel pattern (VCP) or a structure that penetrates the vertical channel pattern (VCP) may be implemented.

Referring again to FIG. 1, the vertical channel structures (VS) include an erase control transistor (ECT), first and second string select transistors (SST1, SST2), a ground select transistor (GST), and memory cell transistors (MCT). ) may correspond to the channels.

A conductive pad (PAD) may be provided on the upper surface of the vertical channel pattern (VCP). The conductive pad (PAD) may be connected to the top of the vertical channel pattern (VCP). The sidewall of the conductive pad (PAD) may be surrounded by a data storage pattern (DSP). The top surface of the conductive pad PAD may be substantially coplanar with the top surface of each of the stacked structures ST (that is, the top surface of the uppermost one of the interlayer dielectric layers ILD). The lower surface of the conductive pad PAD may be located at a lower level than the upper surface of the third gate electrode EL3. More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3. That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in the horizontal direction.

The conductive pad (PAD) may be formed of a semiconductor or conductive material doped with impurities. For example, the conductive pad (PAD) is a semiconductor material doped with impurities different from the substrate SUB (more precisely, impurities of a second conductivity type (e.g., N-type) different from the first conductivity type (e.g., P-type)). It can be formed as

The conductive pad (PAD) can reduce contact resistance between the bit line (BL) and the vertical channel pattern (VCP), which will be described later.

A separation trench TR extending in the first direction D1 may be provided between adjacent stacked structures ST. The common source region (CSR) may be provided inside the substrate (SUB) exposed by the isolation trench (TR). The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with second conductivity type impurities (eg, N-type impurities). The common source region (CSR) may correspond to the common source line (CSL) in FIG. 1.

A common source plug (CSP) may be provided in the isolation trench (TR). The common source plug (CSP) may be connected to the common source region (CSR). The top surface of the common source plug (CSP) may be substantially coplanar with the top surface of each of the stacked structures (ST) (that is, the top surface of the uppermost one of the interlayer insulating layers (ILD)). The common source plug (CSP) may have a plate shape extending in the first direction (D1) and the third direction (D3). At this time, the common source plug CSP may have a shape whose width in the second direction D2 increases as it moves toward the third direction D3.

Insulating spacers (SP) may be interposed between the common source plug (CSP) and the stacked structures (ST). Insulating spacers SP may be provided between adjacent stacked structures ST to face each other. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material with a low dielectric constant.

A capping insulating layer (CAP) may be provided on the stacked structures (ST), the vertical channel structures (VS), and the common source plug (CSP). The capping insulating layer (CAP) may cover the top surface of the uppermost one of the interlayer insulating layers (ILD), the top surface of the conductive pad (PAD), and the top surface of the common source plug (CSP). The capping insulating film (CAP) may be formed of an insulating material different from the interlayer insulating films (ILD). A bit line contact plug (BLPG) electrically connected to the conductive pad (PAD) may be provided inside the capping insulating film (CAP). The bit line contact plug BLPG may have a shape whose width in the first direction D1 and the second direction D2 increases as it moves toward the third direction D3.

A bit line (BL) may be provided on the capping insulating film (CAP) and the bit line contact plug (BLPG). The bit line BL corresponds to one of the plurality of bit lines BL0, BL1, and BL2 shown in FIG. 1 and may be formed to extend along the second direction D2 using a conductive material. The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1, EL2, and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through a bit line contact plug (BLPG). Here, the fact that the bit line (BL) is connected to the vertical channel structures (VS) may mean that it is connected to the vertical channel pattern (VCP) included in the vertical channel structures (VS).

A three-dimensional flash memory with this structure includes a voltage applied to each of the cell strings (CSTR), a voltage applied to the string selection line (SSL), a voltage applied to each of the word lines (WL0-WLn), and a ground selection line. Program operations, read operations, and erase operations can be performed based on the voltage applied to the (GSL), the voltage applied to the common source line (CSL), and the voltage applied to the back gate (BG). For example, the 3D flash memory includes a voltage applied to each of the cell strings (CSTR), a voltage applied to the string select line (SSL), a voltage applied to each of the word lines (WL0-WLn), and a ground select line (GSL). ) Based on the voltage applied to the common source line (CSL) and the voltage applied to the back gate (BG), a channel is formed in the vertical channel pattern (VCP) to transfer charges or holes to the data of the target memory cell. Program operations can be performed by passing it to a stored pattern (DSP).

In addition, the three-dimensional flash memory according to another embodiment is not limited or limited to the described structure, and may include a vertical channel pattern (VCP), a data storage pattern (DSP), a back gate (BG), and a gate electrode ( EL1, EL2, EL3), a bit line (BL), and a common source line (CSL).

As the 3D flash memory with this structure is manufactured through a stack stacking process, each of the stacked structures (ST) may include an upper stack structure (USS) and a lower stack structure (LSS). The lower stack structure (LSS) is disposed on the substrate (SUB) and may include gate electrodes (part of EL1 and EL2) and interlayer insulating layers (ILD) alternately stacked in the vertical direction. The upper stack structure (USS) is stacked on the lower stack structure (LSS) and may include gate electrodes (part of EL2, EL3) and an interlayer insulating layer (ILD) alternately stacked in the vertical direction.

When the lower stack structure (LSS) and the upper stack structure (USS) are stacked, the vertical channel structures (VS) included in the lower stack structure (LSS) and the vertical channel structures (VS) included in the upper stack structure (USS) This misalignment problem may occur. For example, if the vertical channel patterns (VCP) of the lower stack structure (LSS) and the vertical channel patterns (VCP) of the upper stack structure (USS) are misaligned, a problem of deterioration of channel current characteristics may occur. Accordingly, each of the stacked structures (ST) of the three-dimensional flash memory is disposed between the upper stack structure (USS) and the lower stack structure (LSS), and has vertical channel patterns ( It may include connection units (CU) that connect VCPs to each other. These connection units CU may be formed in a tube shape including an internal hole extending in the vertical direction (third direction D3) of the back gate BG, as shown in FIG. 5 according to the manufacturing process. As shown, it is recessed in the uppermost interlayer insulating film (ILD) included in the lower stack structure (LSS), or in the upper part of the uppermost interlayer insulating film (ILD) included in the lower stack structure (LSS) as shown in FIG. 6. It can be formed in a protruding shape. When the connection portions CU are formed in a protruding shape, the connection portions CU may be accommodated by additional interlayer insulating films ILD that are not included in the upper and lower stack structures USS and LSS. As the connection units (CU) are formed in a tube shape, the back gate (BG) and the insulating film (INS) extend from the lower stack structure (LSS) to the upper stack structure (USS) through the internal holes of each of the connection units (CU). can be formed.

In particular, each of the connection units CU may have a shape that protrudes in the horizontal direction more than each of the vertical channel patterns VCP. In more detail, each of the connection portions CU may be formed to a size that accommodates each of the vertical channel patterns VCP on a plane, and thus may have a shape that protrudes in the horizontal direction beyond each of the vertical channel patterns VCP. Additionally, the connection units CU may be formed at a location to accommodate the vertical channel patterns VCP of the upper and lower stack structures USS and LSS to connect the vertical channel patterns VCP to each other.

Additionally, each of the connection units CU may be formed of the same material as the vertical channel patterns VCP in order to connect the vertical channel patterns VCP of the upper and lower stack structures USS and LSS. For example, each of the connection units CU may be formed of single crystalline silicon or polysilicon constituting the vertical channel patterns VCP. However, without being limited or limited thereto, each of the connection units CU may be formed of various materials capable of connecting the vertical channel patterns VCP of the upper and lower stack structures USS and LSS.

As described, the 3D flash memory includes connection units (CU), thereby connecting the vertical channel patterns (VCP) of each of the stack structures (USS, LSS) to each other, thereby solving the problem of deteriorating channel current characteristics.

The three-dimensional flash memory is manufactured through a stack stacking process and is described as including an upper stack structure (USS) and a lower stack structure (LSS). However, the number of stack structures stacked in the stack stacking process is adjusted to produce three or more. It may also include stack structures (eg, top stack structures (USS), middle stack structures (MSS), and bottom stack structures (LSS). In this case, the connection units CU may be arranged in groups arranged in the horizontal direction (first direction D1 and second direction D2) and spaced apart in the third direction D3 and placed at connection portions of the stack structures. A plurality of buffer layers BU may be provided to surround groups of connection units CU arranged to be spaced apart in the third direction D3, and may be positioned to be spaced apart from each other in the third direction D3.

FIG. 7 is a flow chart showing a manufacturing method of a three-dimensional flash memory with the structure shown in FIGS. 3 and 5, and FIGS. 8A to 8E are cross-sectional views showing a three-dimensional flash memory to explain the manufacturing method shown in FIG. 7. .

Referring to FIG. 7, a method of manufacturing a three-dimensional flash memory according to an embodiment is for manufacturing the three-dimensional flash memory described with reference to FIGS. 3 and 4, provided that it is performed by an automated and mechanized manufacturing system. Interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) extending in the horizontal direction and stacked alternately in the vertical direction, and interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) Preparing a lower stack structure (LSS) including vertical channel structures (VS) penetrating in the vertical direction (S710); Forming connections (CU) on the lower stack structure (LSS) based on the positions of the vertical channel structures (VS) in the lower stack structure (LSS) (S720); and interlayer insulating films (ILD) and gate electrode (part of EL2, EL3) extending in the horizontal direction and alternately stacked in the vertical direction on the upper part of the lower stack structure (LSS) where the connection portions (CU) are formed, and interlayer It may include forming an upper stack structure (USS) including vertical channel structures (VS) penetrating insulating films (ILD) and gate electrodes (part of EL2, EL3) in the vertical direction (S730). .

In particular, step S720 may be characterized by forming connection portions CU that have a shape that protrudes in the horizontal direction from each of the vertical channel patterns (VCP) of the lower stack structure (LSS), and may be formed according to the manufacturing process. A recessed type that is recessed in the uppermost interlayer insulating layer (ILD) included in the lower stack structure (LSS) as shown in Figure 3, or a recessed type in the uppermost interlayer insulating layer (ILD) included in the lower stack structure (LSS) as shown in FIG. Connection units (CU) can be formed in a protruding form located at the top.

Hereinafter, with reference to FIGS. 8A to 8E, each step (S710 to S730) of FIG. 7 will be described in detail.

Referring to FIG. 8A, in step S710, the manufacturing system is formed to extend in the horizontal direction (e.g., the first direction D1 and the second direction D2) on the substrate SUB and is extended in the vertical direction (e.g., the third direction (e.g., Penetrating in the vertical direction through the interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) alternately stacked along D3)) and the interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) A lower stack structure (LSS) including vertical channel structures (VS) can be prepared. Here, the vertical channel structures (VS) are the structures described in FIGS. 3 and 4, and include parts of a data storage pattern (DSP), a vertical channel pattern (VCP), and a vertical semiconductor pattern (VSP) as shown in the drawings. can do.

Although not explained or shown in separate steps and drawings, before the step (S710) in which the lower stack structure (LSS) is prepared, the manufacturing system has interlayer dielectric layers (ILD) and sacrificial layers (SAC) alternating vertical directions. Channel holes (CH) are formed in the stacked structure, the sacrificial layers (SAC) are selectively removed through the channel holes (CH), and the gate regions (GR) are spaces where the sacrificial layers (SAC) are removed. Forming gate electrodes (part of EL1 and EL2) and forming vertical channel structures (VS) extending in the vertical direction in the channel holes (CH) may be performed. That is, the manufacturing system performs the WL replacement process and the vertical channel structure formation process before step S710, thereby forming the interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) and the vertical channel structure in step S710. A lower stack structure (LSS) containing VS can be prepared. Here, the sacrificial layers (SAC) may be selectively removed not only through the channel holes (CH) but also through the separation trench (TR). In this case, the step S710 may be preceded by the step of forming the isolation trench TR.

In addition, it has been explained that the WL Replacement process is performed before the above step (S710) to prepare the lower stack structure (LSS) in which the gate electrodes (EL, part of EL2) are formed, but it is not limited or limited thereto and the gate first (Gate first) process is performed before the above step (S710). A lower stack structure (LSS) in which gate electrodes (part of EL1 and EL2) are formed may be prepared through a first) process.

8B to 8D, in step S720, the manufacturing system connects the connections CU on the lower stack structure LSS based on the positions of the vertical channel structures VS in the lower stack structure LSS. ) can be formed. At this time, the manufacturing system connects the vertical channel patterns (VCP) included in the lower stack structure (LSS) and the vertical channel patterns (VCP) included in the upper stack structure (USS) to be formed in step S730, which will be described later. In order to connect, connection parts are formed on the upper part of the vertical channel patterns (VCP) included in the lower stack structure (LSS) made of the same material (e.g., single crystalline silicon or polysilicon) as the material constituting the vertical channel patterns (VCP). (CU) can form each.

For example, the manufacturing system may etch the top portion of the lower stack structure (LSS) (the top portion corresponding to the vertical channel structures (VS) in the lower stack structure (LSS)) 810 as shown in FIG. 8B. Later, as shown in FIG. 8C, connection units CU may be formed in the spaces 820 remaining after etching. The connection portions CU formed in this way may be recessed in the uppermost interlayer insulating layer ILD included in the lower stack structure LSS, as shown in FIG. 3 .

As another example, the manufacturing system may provide connections CU at the top of the lower stack structure (LSS) (the upper part corresponding to the vertical channel structures (VS) in the lower stack structure (LSS)) as shown in FIG. 8D. By forming, as shown in FIG. 4 , the connection portions CU can be formed in a protruding shape located on top of the uppermost interlayer insulating layer ILD included in the lower stack structure LSS. In this case, the manufacturing system can form an additional interlayer dielectric (ILD) that accommodates the connections (CU).

With reference to the drawings below, it will be explained that a three-dimensional flash memory having a structure including connection units (CU) formed in a protruding shape is manufactured.

Referring to FIG. 8E, in step S730, the manufacturing system extends in the horizontal direction on the upper part of the lower stack structure (LSS) where the connection portions (CU) are formed, and interlayer insulating films (ILD) are alternately stacked in the vertical direction. ) and a gate electrode (part of EL2, EL3), an upper stack structure ( USS) can be formed. Here, the vertical channel structures (VS) are the structures described in FIGS. 5 to 6, and the remaining portions of the data storage pattern (DSP), the vertical channel pattern (VCP), and the vertical semiconductor pattern (VSP) as shown in the figures ( Among the data storage pattern (DSP), vertical channel pattern (VCP), and vertical semiconductor pattern (VSP) shown in FIGS. 5 and 6, the data storage pattern (DSP), vertical channel pattern (VCP) included in the above-described lower stack structure (LSS) It may include the remaining portion excluding a portion of the VCP) and the vertical semiconductor pattern (VSP).

Although not explained or shown in separate steps and drawings, before the step (S730) in which the upper stack structure (USS) is prepared, the manufacturing system has interlayer dielectric layers (ILD) and sacrificial layers (SAC) alternating vertical directions. Channel holes (CH) are formed in the stacked structure, the sacrificial layers (SAC) are selectively removed through the channel holes (CH), and the gate regions (GR) are spaces where the sacrificial layers (SAC) are removed. Forming gate electrodes (part of EL2, EL3) and forming vertical channel structures VS in the channel holes CH extending in the vertical direction may be performed. That is, the manufacturing system performs the WL replacement process and the vertical channel structure formation process between steps S720 and S730, thereby forming the interlayer insulating films (ILD) and the gate electrodes (part of EL2, EL3) in step S730. ) and a top stack structure (USS) including vertical channel structures (VS). Here, the sacrificial layers (SAC) may be selectively removed not only through the channel holes (CH) but also through the separation trench (TR). In this case, the step of forming the separation trench TR may be preceded between steps S720 and S730.

In addition, it has been explained that the WL Replacement process is performed before the above step (S730) to prepare the upper stack structure (USS) on which the gate electrodes (part of EL2, EL3) are formed, but it is not limited or limited thereto and the gate first (Gate First) process is performed before the above step (S730). The upper stack structure (USS) in which the gate electrodes (part of EL2, EL3) are formed may be formed through the first) process.

Although not described as a separate step, the manufacturing system includes the steps of forming a separation trench (TR) and performing a WL replacement process through the separation trench (TR) in addition to the steps (S710 to S7630) (WL Replacement process) (can be omitted if made through channel holes (CH)), forming a common source region (CSR) in the substrate (SUB) exposed through the isolation trench (TR), insulation covering the sidewalls of the isolation trench (TR) forming a common source plug (CSP) filling the interior space of the isolation trench (TR) surrounded by spacers (SP) and insulating spacers (SP), capping the vertical channel structures (VS) and the common source plug (CSP); Forming an insulating film (CAP), forming a bit line contact plug (BLPG) that penetrates the capping insulating film (CAP) and electrically connected to the conductive pad (PAD), and forming a bit line contact plug on the capping insulating film (CAP). It may further include forming a bit line (BL) electrically connected to (BLPG) extending along the second direction (D2).

FIG. 9 is a flow chart showing a manufacturing method of a three-dimensional flash memory with the structure shown in FIGS. 5 and 6, and FIGS. 10A to 10G are cross-sectional views showing a three-dimensional flash memory to explain the manufacturing method shown in FIG. 9. .

Referring to FIG. 9, a method of manufacturing a three-dimensional flash memory according to another embodiment is for manufacturing the three-dimensional flash memory described with reference to FIGS. 5 and 6, provided that it is performed by an automated and mechanized manufacturing system. Interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) extending in the horizontal direction and stacked alternately in the vertical direction, and interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) Preparing a lower stack structure (LSS) including vertical channel structures (VS) penetrating in the vertical direction (S910); Forming connections (CU) on the lower stack structure (LSS) based on the positions of the vertical channel structures (VS) in the lower stack structure (LSS) (S920); On the upper part of the lower stack structure (LSS) where the connections (CU) are formed, interlayer insulating films (ILD) and gate electrodes (part of EL2, EL3) extending in the horizontal direction and stacked alternately in the vertical direction, and an interlayer insulating film Channel holes (CH) penetrating in the vertical direction through the ILD and the gate electrodes (part of EL2, EL3) (on the inner walls of each channel hole, there is a data storage pattern among the components of each of the vertical channel structures (VS) forming an upper stack structure (USS) including (DSP) and a vertical channel pattern (VCP) formed thereon (S930); Forming channel connection holes (CCH) in the vertical direction of the connection portions (CU) based on the positions of the channel holes (CH) (S940); and at least one component other than the data storage pattern (DSP) and the vertical channel pattern (VCP) among the vertical channel structures (VS) on the inner walls of the channel holes (CH) and the inner walls of the channel connection holes (CCH). It may include the step of extending in the vertical direction (S950).

In particular, step S920 may be characterized by forming connection portions CU that have a shape that protrudes in the horizontal direction from each of the vertical channel patterns (VCP) of the lower stack structure (LSS). Depending on the manufacturing process, A recessed type that is recessed in the uppermost interlayer insulating film (ILD) included in the lower stack structure (LSS) as shown in Figure 5, or a recessed type in the uppermost interlayer insulating film (ILD) included in the lower stack structure (LSS) as shown in FIG. Connection units (CU) can be formed in a protruding form located at the top.

Hereinafter, with reference to FIGS. 10A to 10G, each step (S910 to S950) of FIG. 9 will be described in detail.

Referring to FIG. 10A, in step S910, the manufacturing system is formed to extend in a horizontal direction (e.g., first direction D1 and second direction D2) on the substrate SUB and is extended in a vertical direction (e.g., third direction (e.g., third direction)). Penetrating in the vertical direction through the interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) alternately stacked along D3)) and the interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) A lower stack structure (LSS) including vertical channel structures (VS) can be prepared. Here, the vertical channel structures (VS) are the structures described in FIGS. 5 to 6 and include a data storage pattern (DSP), a vertical channel pattern (VCP), an insulating film (INS), and a back gate (BG) as shown in the figures. It may include part of .

Although not explained or shown in separate steps and drawings, before the step (S910) in which the lower stack structure (LSS) is prepared, the manufacturing system has interlayer dielectric layers (ILD) and sacrificial layers (SAC) alternating vertical directions. Channel holes (CH) are formed in the stacked structure, the sacrificial layers (SAC) are selectively removed through the channel holes (CH), and the gate regions (GR) are spaces where the sacrificial layers (SAC) are removed. Forming gate electrodes (part of EL1 and EL2) and forming vertical channel structures (VS) extending in the vertical direction in the channel holes (CH) may be performed. That is, the manufacturing system performs the WL replacement process and the vertical channel structure formation process before step S910, thereby forming the interlayer insulating films (ILD) and gate electrodes (part of EL1 and EL2) and the vertical channel structure in step S910. A lower stack structure (LSS) including VS can be prepared. Here, the sacrificial layers (SAC) may be selectively removed not only through the channel holes (CH) but also through the separation trench (TR). In this case, the step S710 may be preceded by the step of forming the isolation trench TR.

In addition, it has been explained that the WL Replacement process is performed before the above step (S910) to prepare the lower stack structure (LSS) in which the gate electrodes (EL, part of EL2) are formed, but it is not limited or limited thereto and the gate first (Gate first) process is performed before the above step (S910). A lower stack structure (LSS) in which gate electrodes (part of EL1 and EL2) are formed may be prepared through a first) process.

10B to 10D, in step S920, the manufacturing system connects the connections CU on the lower stack structure LSS based on the positions of the vertical channel structures VS in the lower stack structure LSS. ) can be formed. At this time, the manufacturing system uses vertical channel patterns (VCP) included in the lower stack structure (LSS) and vertical channel patterns (VCP) included in the upper stack structure (USS) to each other. Each of the connection portions (CU) may be formed on the upper part of the vertical channel patterns (VCP) included in the lower stack structure (LSS) using the same material (e.g., single crystalline silicon or polysilicon) as the material constituting the VCP. .

For example, the manufacturing system may etch the top portion of the lower stack structure (LSS) (the top portion corresponding to the vertical channel structures (VS) in the lower stack structure (LSS)) 1010 as shown in FIG. 10B. Later, as shown in FIG. 10C, connection units CU may be formed in the spaces 1020 remaining after etching. The connection portions CU formed in this way may be recessed in the uppermost interlayer insulating layer ILD included in the lower stack structure LSS, as shown in FIG. 5 .

As another example, the manufacturing system may provide connections CU at the top of the lower stack structure (LSS) (the upper part corresponding to the vertical channel structures (VS) in the lower stack structure (LSS)) as shown in FIG. 10D. By forming, as shown in FIG. 6 , the connection portions CU can be formed in a protruding shape located on top of the uppermost interlayer insulating layer ILD included in the lower stack structure LSS. In this case, the manufacturing system can form an additional interlayer dielectric (ILD) that accommodates the connections (CU).

With reference to the drawings below, it will be explained that a three-dimensional flash memory having a structure including connection units (CU) formed in a protruding shape is manufactured.

Referring to FIG. 10E, in step S930, the manufacturing system is installed on the upper part of the lower stack structure (LSS) where the connection portions (CU) are formed, in a horizontal direction (e.g., in the first direction (D1) and the second direction (D2)). Interlayer insulating films (ILD) and gate electrodes (part of EL2, EL3) and interlayer insulating films (ILD) and gate electrodes that are alternately stacked along a vertical direction (e.g., third direction D3) and extend to Channel holes (CH) penetrating (part of EL2, EL3) in the vertical direction (on the inner wall of each channel hole are vertical channel structures (VS), a data storage pattern (DSP) and a vertical channel pattern ( It is possible to form an upper stack structure (USS) including (VCP) is formed.

At this time, an upper stack structure (USS) in which some components (e.g., data storage pattern (DSP) and vertical channel pattern (VCP)) of each of the vertical channel structures (VS) are formed in each of the channel holes (CH). It can be. This is to ensure that the vertical channel patterns (VCP) of the upper and lower stack structures (USS, LSS) are connected by the connection units (CU).

Although not explained or shown in separate steps and drawings, before the step (S930) in which the upper stack structure (USS) is prepared, the manufacturing system is such that the interlayer dielectric layers (ILD) and sacrificial layers (SAC) alternate in vertical directions. Channel holes (CH) are formed in the stacked structure, the sacrificial layers (SAC) are selectively removed through the channel holes (CH), and the gate regions (GR) are spaces where the sacrificial layers (SAC) are removed. Forming gate electrodes (part of EL2, EL3) and forming a data storage pattern (DSP) and a vertical channel pattern (VCP) among the vertical channel structures (VS) may be performed. That is, the manufacturing system performs a WL replacement process and a data storage pattern (DSP)/vertical channel pattern (VCP) formation process between steps S920 and S930, thereby forming interlayer dielectric layers (ILD) in step S930. ) and an upper stack structure (USS) including gate electrodes (part of EL2, EL3) and channel holes (CH) (channel holes (CH) in which a data storage pattern (DSP) and a vertical channel pattern (VCP) are formed. can be formed. Here, the sacrificial layers (SAC) may be selectively removed not only through the channel holes (CH) but also through the separation trench (TR). In this case, the step of forming the separation trench TR may be preceded between steps S920 and S930.

In addition, it has been explained that the WL Replacement process is performed before the above step (S930) to prepare the upper stack structure (USS) on which the gate electrodes (part of EL2, EL3) are formed, but it is not limited or limited thereto and the gate first (Gate First) process is performed before the above step (S930). The upper stack structure (USS) in which the gate electrodes (part of EL2, EL3) are formed may be formed through the first) process.

Referring to FIG. 10F , in step S940, the manufacturing system may form channel connection holes (CCH) that vertically penetrate the connection portions (CU) based on the positions of the channel holes (CH). More specifically, the manufacturing system allows vertical channel structures (VS) included in the lower stack structure (LSS) and channel holes (CH) included in the upper stack structure (USS) to be connected to each other through channel connection holes (CCH). Channel connection holes (CCH) may be formed based on the positions of the channel holes (CH) of the upper stack structures (USS) and the positions of the vertical channel structures (VS) of the lower stack structures (LSS).

In the step S940 of forming the channel connection holes (CCH), an anisotropic etching method using a mask pattern as an etch mask may be used. However, this is only an example, and various etching processes may be used in step S940.

Referring to FIG. 10g, in step S950, the manufacturing system stores a data storage pattern (DSP) and a data storage pattern (DSP) among the vertical channel structures (VS) on the inner walls of the channel holes (CH) and the inner walls of the channel connection holes (CCH). At least one component other than the vertical channel pattern (VCP) may be formed to extend in the vertical direction.

As described above, in step S930, some of the components (eg, data storage pattern (DSP) and vertical channel pattern (VCP)) of the vertical channel structures (VS) are installed in the channel holes (CH). When the upper stack structure (USS) is formed, in step S950, the remaining components (e.g., insulating layer (INS) and back gate (BG)) among the components of each of the vertical channel structures (VS) are can be formed.

Here, the vertical channel structures (VS) are the structures described in FIGS. 5 to 6 and include a data storage pattern (DSP), a vertical channel pattern (VCP), an insulating film (INS), and a back gate (BG) as shown in the figures. The remaining portion (data storage pattern included in the aforementioned lower stack structure (LSS) among the data storage pattern (DSP), vertical channel pattern (VCP), insulating layer (INS), and back gate (BG) shown in FIGS. 5 and 6 (DSP), vertical channel pattern (VCP), insulating layer (INS), and the remaining portion excluding a portion of the back gate (BG)).

In addition, although not described as a separate step, the manufacturing system includes, in addition to steps S910 to S950, forming a separation trench (TR) and performing a WL replacement process through the separation trench (TR) (WL (can be omitted if the replacement process is performed through channel holes (CH)), forming a common source region (CSR) in the substrate (SUB) exposed through the isolation trench (TR), forming the sidewalls of the isolation trench (TR) forming a covering insulating spacer (SP) and a common source plug (CSP) filling the interior space of the isolation trench (TR) surrounded by the insulating spacer (SP), on the vertical channel structures (VS) and on the common source plug (CSP). forming a capping insulating film (CAP) on the capping insulating film (CAP), forming a bit line contact plug (BLPG) that penetrates the capping insulating film (CAP) and is electrically connected to the conductive pad (PAD), and forming a bit line contact plug (BLPG) on the capping insulating film (CAP). The step of extending the bit line BL electrically connected to the contact plug BLPG along the second direction D2 may be further included.

Figure 11 is a perspective view schematically showing an electronic system including a three-dimensional flash memory according to embodiments.

Referring to FIG. 11, an electronic system 1100 including a three-dimensional flash memory according to embodiments includes a main board 1101, a controller 1102 mounted on the main board 1101, and one or more semiconductor packages 1103. ) and DRAM 1104.

The semiconductor package 1103 and the DRAM 1104 may be connected to the controller 1102 through wiring patterns 1105 provided on the main board 1101.

The main board 1101 may include a connector 1106 including a plurality of pins coupled to an external host. The number and arrangement of a plurality of pins in the connector 1106 may vary depending on the communication interface between the electronic system 1100 and an external host.

For example, the electronic system 1100 may use any of the interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIExpress), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). Depending on one, you can communicate with an external host. The electronic system 1100 may operate by, for example, power supplied from an external host through the connector 1106. The electronic system 1100 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to the controller 1102 and the semiconductor package 1103.

The controller 1102 can write data to or read data from the semiconductor package 1103 and improve the operating speed of the electronic system 1100.

The DRAM 1104 may be a buffer memory to alleviate the speed difference between the semiconductor package 1103, which is a data storage space, and an external host. The DRAM 1104 included in the electronic system 1100 may operate as a type of cache memory and may provide space for temporarily storing data during control operations for the semiconductor package 1103. When the electronic system 1100 includes the DRAM 1104, the controller 1102 may further include a DRAM controller for controlling the DRAM 1104 in addition to a NAND controller for controlling the semiconductor package 1103.

The semiconductor package 1103 may include first and second semiconductor packages 1103a and 1103b that are spaced apart from each other. The first and second semiconductor packages 1103a and 1103b may each include a plurality of semiconductor chips 1120. Each of the first and second semiconductor packages 1103a and 1103b includes a package substrate 1110, semiconductor chips 1120 on the package substrate 1110, and adhesive layers 1130 disposed on the lower surfaces of each of the semiconductor chips 1120. ), connection structures 1140 that electrically connect the semiconductor chips 1120 and the package substrate 1110, and a molding layer 1150 that covers the semiconductor chips 1120 and the connection structures 1140 on the package substrate 1110. may include.

The package substrate 1110 may be a printed circuit board including upper package pads 1111. Each semiconductor chip 1120 may include input/output pads 1121 . Each of the semiconductor chips 1120 may include the three-dimensional flash memory described above with reference to FIGS. 3 to 6 . More specifically, each of the semiconductor chips 1120 may include gate stacked structures 1122 and memory channel structures 1123. The gate stacked structures 1122 may correspond to the above-described stacked structures (ST), and the memory channel structures 1123 may correspond to the above-described vertical channel structures (VS).

The connection structures 1140 may be, for example, bonding wires that electrically connect the input/output pads 1121 and the upper package pads 1111. Accordingly, in each of the first and second semiconductor packages 1103a and 1103b, the semiconductor chips 1120 may be electrically connected to each other using a bonding wire method, and may be electrically connected to the package upper pads 1111 of the package substrate 1110. Can be electrically connected. According to embodiments, in each of the first and second semiconductor packages 1103a and 1103b, the semiconductor chips 1120 are connected to a through electrode (Through Silicon Via) instead of the bonding wire-type connection structures 1140. They may be electrically connected to each other.

Unlike shown, the controller 1102 and the semiconductor chips 1120 may be included in one package. The controller 1102 and the semiconductor chips 1120 may be mounted on a separate interposer board different from the main board 1101, and the controller 1102 and the semiconductor chips 1120 may be connected to each other by wiring provided on the interposer board. there is.

As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent.

Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

Claims (5)

Interlayer insulating films and gate electrodes extending in the horizontal direction and alternately stacked in the vertical direction, and vertical channel structures penetrating the interlayer insulating films and the gate electrodes and extending in the vertical direction - the vertical channel structures Stack structures each including a data storage pattern extending in the vertical direction and a vertical channel pattern covering an inner wall of the data storage pattern and extending in the vertical direction. Stacked vertically -; and
Connection parts disposed between the stack structures and protruding in the horizontal direction from each of the vertical channel patterns to connect the vertical channel patterns of each of the stack structures to each other.
Including,
Each of the above connections,
A three-dimensional flash memory, characterized in that only the vertical channel patterns of each of the stack structures are connected to each other based on a single layer structure composed only of materials forming the vertical channel patterns. In paragraph 1
Each of the above connections,
When each of the vertical channel patterns includes a back gate extending in the vertical direction with at least a portion surrounded by each of the vertical channel patterns, an internal hole in which the back gate extends in the vertical direction It is formed in a tube shape including, or when each of the vertical channel patterns includes a vertical semiconductor pattern, the vertical semiconductor pattern included in the upper stack structure and the vertical semiconductor pattern included in the lower stack structure among the stack structures A three-dimensional flash memory characterized in that it is formed in the shape of a pillar with a closed interior so that it is separated by each of the connection parts. Preparing a lower stack structure including interlayer insulating films and gate electrodes extending in the horizontal direction and alternately stacked in the vertical direction, and vertical channel structures penetrating the interlayer insulating films and the gate electrodes in the vertical direction. ;
forming connections on the lower stack structure based on the positions of the vertical channel structures in the lower stack structure; and
The interlayer insulating films and the gate electrodes are formed extending in the horizontal direction and alternately stacked in the vertical direction on the upper part of the lower stack structure where the connecting portions are formed, and the interlayer insulating films and the gate electrodes are formed in the vertical direction. forming an upper stack structure comprising the vertical channel structures passing through
Including,
The step of forming the connections is,
A three-dimensional structure characterized in that only the vertical channel patterns of each of the lower stack structure and the upper stack structure are connected to each other based on a single-layer film structure composed only of a material forming a vertical channel pattern included in each of the vertical channel structures. Manufacturing method of flash memory. Preparing a lower stack structure including interlayer insulating films and gate electrodes extending in the horizontal direction and alternately stacked in the vertical direction, and vertical channel structures penetrating the interlayer insulating films and the gate electrodes in the vertical direction. ;
forming connections on the lower stack structure based on the positions of the vertical channel structures in the lower stack structure;
The interlayer insulating films and the gate electrodes are formed extending in the horizontal direction and alternately stacked in the vertical direction on the upper part of the lower stack structure where the connecting portions are formed, and the interlayer insulating films and the gate electrodes are formed in the vertical direction. forming an upper stack structure including channel holes penetrating through the channel holes, each of which has a data storage pattern and a vertical channel pattern extending from inner walls of each of the components of the vertical channel structures;
forming channel connection holes penetrating the connection parts in the vertical direction based on the positions of the channel holes; and
On the inner walls of the channel holes and the inner walls of the channel connection holes, at least one remaining component excluding the data storage pattern and the vertical channel pattern among the components of the vertical channel structures is formed to extend in the vertical direction. step
Including,
The step of forming the connections is,
A three-dimensional structure characterized in that only the vertical channel patterns of each of the lower stack structure and the upper stack structure are connected to each other based on a single-layer film structure composed only of a material forming a vertical channel pattern included in each of the vertical channel structures. Manufacturing method of flash memory. According to any one of paragraphs 3 or 4,
Forming connections on the lower stack structure includes:
etching the upper portion of the lower stack structure and forming the connection portions in the remaining spaces; or
Forming the connections on top of the lower stack structure
A method of manufacturing a three-dimensional flash memory comprising the step of any one of the following.