KR20230086382A - 3d flash memory having word line separation structure and manufacturing method thereof - Google Patents

Abstract

A three-dimensional flash memory having a word line separation structure and a manufacturing method thereof are disclosed. According to one embodiment, a three-dimensional flash memory may include interlayer insulating films and word lines extending in a horizontal direction and alternately stacked in a vertical direction; Vertical channel structures extending through the interlayer insulating films and the word lines in the vertical direction - each of the vertical channel structures surrounds a vertical channel pattern extending in the vertical direction and an outer wall of the vertical channel pattern; including the data storage pattern being formed; and at least one separation film formed of the same material as the data storage pattern and separating each of the word lines into a plurality of pieces on a horizontal plane.

Description

3D flash memory having word line separation structure and manufacturing method thereof

The following embodiments are technologies related to a 3D flash memory, and more specifically, to a 3D flash memory having a word line separation structure and a manufacturing method thereof.

A flash memory device is an electrically erasable programmable read only memory (EEPROM) by electrically controlling input and output of data by Fowler-Nordheimtunneling or hot electron injection. , can be commonly used in computers, digital cameras, MP3 players, game systems, memory sticks, and the like.

In such a flash memory device, a three-dimensional structure in which memory cell transistors are arranged in a vertical direction to form a cell string has been proposed to increase the degree of integration in order to meet the excellent performance and low price demanded by consumers.

Since a conventional 3D flash memory shares a word line within one block (stacked structure) formed by a plurality of memory cell strings, a fringing field exists in the same block during a memory operation of an arbitrary memory cell string in the block. It has a problem affecting adjacent memory cell strings.

Accordingly, the embodiments below seek to propose a technique that solves the described problem.

In one embodiment, in order to improve the influence of a fringing field due to a word line formed in one large area in a stacked structure, a three-dimensional flash memory in which each word line is separated into a plurality of pieces on a horizontal plane through at least one separator film , a manufacturing method thereof and an electronic system including the same are proposed.

At this time, in order to simplify the process of forming at least one separator, one embodiment is a three-dimensional flash memory in which at least one separator is simultaneously formed through the same process as vertical channel structures extending and formed in channel holes, and a method of manufacturing the same and an electronic system including the same.

In addition, in one embodiment, at least one separator trench in which at least one separator film is formed is used in a process of securing an etch profile for channel holes by forming at least one separator film to connect vertical channel structures to each other on a horizontal plane. A three-dimensional flash memory, a manufacturing method thereof, and an electronic system including the same are proposed.

However, the technical problems to be solved by the present invention are not limited to the above problems, and can be variously expanded without departing from the technical spirit and scope of the present invention.

According to one embodiment, a three-dimensional flash memory may include interlayer insulating films and word lines extending in a horizontal direction and alternately stacked in a vertical direction; Vertical channel structures extending through the interlayer insulating films and the word lines in the vertical direction - each of the vertical channel structures surrounds a vertical channel pattern extending in the vertical direction and an outer wall of the vertical channel pattern; including the data storage pattern being formed; and at least one separation film formed of the same material as the data storage pattern and separating each of the word lines into a plurality of pieces on a horizontal plane.

According to one aspect, the at least one separator may be formed to connect vertical channel structures included in at least one column or row of the vertical channel structures to each other on the horizontal plane.

According to another aspect, the at least one separator may include vertical channel structures included in the at least one column or row; and connecting parts connecting vertical channel structures included in the at least one column or row to each other on the horizontal plane.

According to another aspect, each of the vertical channel structures included in the at least one column or row may not include the vertical channel pattern.

According to another aspect, the at least one separator has a shape in which protrusions and recesses repeat along a direction extending on the horizontal plane to separate each of the word lines into a plurality of pieces on the horizontal plane. can be done with

According to another aspect, the at least one separator may be formed at the same time through the same process as the vertical channel structures.

One embodiment is a three-dimensional flash memory that improves the effect of a fringing field due to a word line formed as one large area in a stacked structure by separating each of the word lines into a plurality of pieces on a horizontal plane through at least one separator. , a manufacturing method thereof and an electronic system including the same may be proposed.

At this time, in one embodiment, at least one separator is formed at the same time through the same process as the vertical channel structures extending in the channel holes, thereby simplifying the process of forming at least one separator, a 3D flash memory, and a manufacturing method thereof. and an electronic system including the same.

In addition, in one embodiment, at least one separator trench in which at least one separator film is formed is used in a process of securing an etch profile for channel holes by forming at least one separator film to connect vertical channel structures to each other on a horizontal plane. A 3D flash memory, a manufacturing method thereof, and an electronic system including the same may be proposed.

However, the effects of the present invention are not limited to the above effects, and can be variously extended without departing from the technical spirit and scope of the present invention.

1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to one embodiment.
2 is a plan view illustrating the structure of a 3D flash memory according to an exemplary embodiment.
FIG. 3 is a cross-sectional view showing the structure of the 3D flash memory shown in FIG. 2, and corresponds to a cross-section of FIG. 2 taken along the line A-A'.
4 is a plan view illustrating the structure of a 3D flash memory according to another embodiment.
5 is a plan view illustrating the structure of a 3D flash memory according to another embodiment.
FIG. 6 is a flow chart illustrating a method of manufacturing a 3D flash memory according to an embodiment in which a gate first method is applied to manufacture the 3D flash memory shown in FIGS. 2 and 3 .
7A to 7D are plan views illustrating the structure of a 3D flash memory to explain a manufacturing method of the 3D flash memory shown in FIG. 6 .
8A to 8D are cross-sectional views illustrating the structure of the 3D flash memory shown in FIGS. 7A to 7D , and correspond to cross-sections taken along line A-A' in FIGS. 7A to 7D .
9A to 9D are cross-sectional views illustrating the structure of the 3D flash memory shown in FIGS. 7A to 7D, and correspond to cross-sections taken along the line BB′ in FIGS. 7A to 7D.
FIG. 10 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an embodiment in which a stack method is applied in addition to a gate first method to manufacture the 3D flash memory shown in FIGS. 2 and 3 .
FIG. 11 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an embodiment in which a word line replacement method is applied to manufacture the 3D flash memory shown in FIGS. 2 and 3 .
FIG. 12 is a flow chart illustrating a method of manufacturing a 3D flash memory according to an embodiment in which a stack method is applied in addition to a word line replacement method to manufacture the 3D flash memory shown in FIGS. 2 and 3 .
13 is a perspective view schematically illustrating an electronic system including a 3D flash memory according to embodiments.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the examples. Also, like reference numerals in each figure denote like members.

In addition, terms used in this specification (terminology) are terms used to appropriately express preferred embodiments of the present invention, which may vary according to the intention of a viewer or operator or customs in the field to which the present invention belongs. Therefore, definitions of these terms will have to be made based on the content throughout this specification. For example, in this specification, singular forms also include plural forms unless specifically stated otherwise in a phrase. Also, as used herein, "comprises" and/or "comprising" means that a referenced component, step, operation, and/or element is one or more other components, steps, operations, and/or elements. The presence or addition of elements is not excluded. In addition, although terms such as first and second are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish one area, direction or shape from another area, direction or shape. Accordingly, a portion referred to as a first portion in one embodiment may be referred to as a second portion in another embodiment.

Also, it should be understood that the various embodiments of the present invention are different from each other but are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in one embodiment in another embodiment without departing from the spirit and scope of the present invention. In addition, it should be understood that the location, arrangement, or configuration of individual components in the scope of each embodiment presented may be changed without departing from the spirit and scope of the present invention.

Hereinafter, a 3D flash memory according to embodiments, an operating method thereof, and an electronic system including the same will be described in detail with reference to the drawings.

1 is a simplified circuit diagram illustrating an array of three-dimensional flash memories according to one embodiment.

Referring to FIG. 1 , a three-dimensional flash memory array according to an embodiment includes a common source line CSL, a plurality of bit lines BL0, BL1, and BL2, and the common source line CSL and bit lines BL0. , BL1, and BL2) may include a plurality of cell strings CSTR.

The bit lines BL0 , BL1 , and BL2 may be two-dimensionally arranged while being spaced apart from each other along the first direction D1 while extending in the second direction D2 . Here, each of the first direction D1 , the second direction D2 , and the third direction D3 are orthogonal to each other and may form a rectangular coordinate system defined by X, Y, and Z axes.

A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0 , BL1 , and BL2 . The cell strings CSTR may be connected in common to the common source line CSL while being provided between the bit lines BL0 , BL1 , and BL2 and one common source line CSL. In this case, a plurality of common source lines CSL may be provided, and the plurality of common source lines CSL are spaced apart from each other along the second direction D2 while extending in the first direction D1 and have a two-dimensional can be arranged sequentially. The same voltage may be electrically applied to the plurality of common source lines CSL, but different voltages may be applied as each of the plurality of common source lines CSL is electrically independently controlled without being limited or limited thereto. there is.

The cell strings CSTR may be spaced apart from each other along the second direction D2 for each bit line while extending in the third direction D3 and may be arranged. According to an embodiment, each of the cell strings CSTR includes a ground select transistor GST connected to the common source line CSL and first and second strings connected in series to bit lines BL0, BL1, and BL2. Select transistors SST1 and SST2, memory cell transistors MCT connected in series while being disposed between the ground select transistor GST and the first and second string select transistors SST1 and SST2, and an erase control transistor ECT ) can be configured. Also, each of the memory cell transistors MCT may include a data storage element.

For example, each of the cell strings CSTR may include first and second string select transistors SST1 and SST2 connected in series, and the second string select transistor SST2 may include bit lines BL0 and BL1 , BL2). However, without being limited thereto, each of the cell strings CSTR may include one string select transistor. As another example, the ground select transistor GST in each of the cell strings CSTR may be composed of a plurality of MOS transistors connected in series similarly to the first and second string select transistors SST1 and SST2. .

One cell string CSTR may include a plurality of memory cell transistors MCT having different distances from the common source lines CSL. That is, the memory cell transistors MCT may be connected in series while being disposed along the third direction D3 between the first string select transistor SST1 and the ground select transistor GST. The erase control transistor ECT may be connected between the ground select transistor GST and the common source lines CSL. Each of the cell strings CSTR is formed between the first string select transistor SST1 and the uppermost one of the memory cell transistors MCT and between the ground select transistor GST and the lowermost one of the memory cell transistors MCT. Dummy cell transistors DMC connected to each other may be further included.

According to an embodiment, the first string select transistor SST1 may be controlled by the first string select lines SSL1-1, SSL1-2, and SSL1-3, and the second string select transistor SST2 may be It can be controlled by 2 string select lines (SSL2-1, SSL2-2, SSL2-3). The memory cell transistors MCT may be respectively controlled by a plurality of word lines WL0 - WLn, and the dummy cell transistors DMC may be respectively controlled by a dummy word line DWL. The ground select transistor GST may be controlled by the ground select lines GSL0 , GSL1 , and GSL2 , and the erase control transistor ECT may be controlled by the erase control line ECL. A plurality of erasure control transistors ECT may be provided. Common source lines CSL may be commonly connected to sources of erase control transistors ECT.

Gate electrodes of the memory cell transistors MCT, which are provided at substantially the same distance from the common source lines CSL, may be connected in common to one of the word lines WL0 - WLn and DWL to be in an equipotential state. . However, without being limited thereto, even if the gate electrodes of the memory cell transistors MCT are provided at substantially the same level from the common source lines CSL, the gate electrodes provided in different rows or columns may be independently controlled. there is.

Ground select lines (GSL0, GSL1, GSL2), first string select lines (SSL1-1, SSL1-2, SSL1-3) and second string select lines (SSL2-1, SSL2-2, SSL2-3) ) may extend along the first direction D1, be spaced apart from each other in the second direction D2, and be two-dimensionally arranged. ground selection lines GSL0, GSL1, and GSL2 provided at substantially the same level from the common source lines CSL, first string selection lines SSL1-1, SSL1-2, SSL1-3, and a second string The selection lines SSL2-1, SSL2-2, and SSL2-3 may be electrically separated from each other. Also, erase control transistors ECT of different cell strings CSTR may be controlled by a common erase control line ECL. The erase control transistors ECT may generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array. In some embodiments, an erase voltage may be applied to the bit lines BL0 , BL1 , and BL2 and/or the common source lines CSL during an erase operation of the memory cell array, and the string select transistor SST and/or Alternatively, gate induced leakage current may be generated in the erasure control transistors ECT.

The above-described string selection line SSL may be expressed as an upper selection line USL, and the ground selection line GSL may be expressed as a lower selection line.

FIG. 2 is a plan view showing the structure of a 3D flash memory according to an exemplary embodiment, and FIG. 3 is a cross-sectional view showing the structure of the 3D flash memory shown in FIG. 2 , taken along line A-A'. Corresponding to a cross section, FIG. 4 is a plan view showing the structure of a 3D flash memory according to another embodiment, and FIG. 5 is a plan view showing the structure of a 3D flash memory according to another embodiment.

2 to 5 , the substrate SUB may be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a monocrystalline epitaxial layer grown on a monocrystalline silicon substrate. . The substrate SUB may be doped with first conductivity-type impurities (eg, P-type impurities).

Stacked structures ST may be disposed on the substrate SUB. The stacked structures ST may be two-dimensionally disposed along the second direction D2 while extending in the first direction D1. In addition, the stacked structures ST may be spaced apart from each other in the second direction D2.

Each of the stacked structures ST includes gate electrodes EL1 , EL2 , and EL3 alternately stacked in a vertical direction perpendicular to the upper surface of the substrate SUB (eg, in the third direction D3 ), and interlayer insulating films ILD. can include The stacked structures ST may have substantially flat upper surfaces. That is, top surfaces of the stacked structures ST may be parallel to the top surface of the substrate SUB. Hereinafter, the vertical direction means the third direction D3 or a direction opposite to the third direction D3.

Referring back to FIG. 1 , each of the gate electrodes EL1 , EL2 , and EL3 includes an erase control line ECL, ground select lines GSL0 , GSL1 , and GSL2 sequentially stacked on the substrate SUB, and a word line. (WL0-WLn, DWL), one of the first string selection lines (SSL1-1, SSL1-2, SSL1-3) and the second string selection lines (SSL2-1, SSL2-2, SSL2-3) can be

Each of the gate electrodes EL1 , EL2 , and EL3 may have substantially the same thickness in the third direction D3 while extending in the first direction D1 . Hereinafter, the thickness means the thickness in the third direction D3. Each of the gate electrodes EL1 , EL2 , and EL3 may be formed of a conductive material. For example, each of the gate electrodes EL1 , EL2 , EL3 may be a doped semiconductor (ex, doped silicon, etc.), a metal (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), It may include at least one selected from Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.) or conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.). Each of the gate electrodes EL1 , EL2 , and EL3 may include at least one of all metal materials that can be formed by ALD in addition to the metal material described above.

More specifically, the gate electrodes EL1 , EL2 , and EL3 include a lowermost first gate electrode EL1 , an uppermost third gate electrode EL3 , and the first and third gate electrodes EL1 and EL3 . A plurality of second gate electrodes EL2 may be included therebetween. Although each of the first gate electrode EL1 and the third gate electrode EL3 is shown and described in the singular number, this is exemplary and not limited thereto, and the first gate electrode EL1 and the third gate electrode EL3 may be used as necessary. may be provided in plural. The first gate electrode EL1 may correspond to one of the ground selection lines GSL0 , GSL1 , and GLS2 shown in FIG. 1 . The second gate electrode EL2 may correspond to one of the word lines WL0 - WLn and DWL shown in FIG. 1 . The third gate electrode EL3 includes any one of the first string select lines SSL1-1, SSL1-2 and SSL1-3 of FIG. 1 shown in FIG. 1 or the second string select lines SSL2-1 and SSL2-1. SSL2-2, SSL2-3) may correspond to any one.

Although not shown, an end of each of the stacked structures ST may have a stepwise structure along the first direction D1. More specifically, the lengths of the gate electrodes EL1 , EL2 , and EL3 of the stack structures ST in the first direction D1 may decrease as the distance from the substrate SUB increases. The third gate electrode EL3 may have the smallest length in the first direction D1 and the largest distance from the substrate SUB in the third direction D3. The first gate electrode EL1 may have the longest length in the first direction D1 and the shortest distance from the substrate SUB in the third direction D3. Due to the stepped structure, the thickness of each of the stacked structures ST may decrease as the distance from the outermost one of the vertical channel structures VS described later increases, and the gate electrodes EL1, Sidewalls of EL2 and EL3 may be spaced apart at regular intervals along the first direction D1 when viewed in plan.

Each of the interlayer insulating layers ILD may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers ILD may have a smaller thickness than other interlayer insulating layers ILD. However, this is illustrative and not limited thereto, and the thickness of each of the interlayer insulating layers ILD may be different from each other according to the characteristics of the semiconductor device or all may be set to be the same. The interlayer insulating layers ILD may be formed of an insulating material to insulate between the gate electrodes EL1 , EL2 , and EL3 . For example, the interlayer insulating layers ILD may be formed of silicon oxide.

A plurality of channel holes CH penetrating portions of the stacked structures ST and the substrate SUB may be provided. Vertical channel structures VS may be provided in the channel holes CH. The vertical channel structures VS are the plurality of cell strings CSTR shown in FIG. 1 , and may extend in the third direction D3 while being connected to the substrate SUB. The connection of the vertical channel structures VS with the substrate SUB may be achieved by contacting the lower surface of each of the vertical channel structures VS with the upper surface of the substrate SUB, but is not limited or limited thereto. It may be formed by being embedded in the substrate SUB. When portions of each of the vertical channel structures VS are buried in the substrate SUB, lower surfaces of the vertical channel structures VS may be positioned at a lower level than the upper surface of the substrate SUB.

A plurality of columns of vertical channel structures VS passing through any one of the stacked structures ST may be provided. For example, as shown in FIG. 2 , columns of three vertical channel structures VS may pass through one of the stacked structures ST. However, it is not limited or limited thereto, and two columns of vertical channel structures VS pass through one of the stacked structures ST, or four or more columns of vertical channel structures VS pass through the stacked structures ST. ) can penetrate one of them. In a pair of adjacent columns, the vertical channel structures VS corresponding to one column may be shifted in the first direction D1 from the vertical channel structures VS corresponding to the other adjacent column. there is. When viewed from a plan view, the vertical channel structures VS may be arranged in a zigzag shape along the first direction D1. However, without being limited thereto, the vertical channel structures VS may form an array arranged side by side in rows and columns.

Each of the vertical channel structures VS may extend from the substrate SUB in the third direction D3. In the drawing, each of the vertical channel structures VS is shown as having a column shape having the same width at the top and bottom, but is not limited thereto, and is not limited thereto. It may have a shape in which the width to (D2) is increased. The upper surface of each of the vertical channel structures VS may have a circular shape, an elliptical shape, a rectangular shape, or a bar shape.

Each of the vertical channel structures VS may include a data storage pattern DSP, a vertical channel pattern VCP, a vertical semiconductor pattern VSP, and a conductive pad PAD. In each of the vertical channel structures VS, the data storage pattern DSP may have a pipe shape or macaroni shape with an open bottom, and the vertical channel pattern VCP may have a pipe shape or macaroni shape with a closed bottom. can have a shape. The vertical semiconductor pattern VSP may fill a space surrounded by the vertical channel pattern VCP and the conductive pad PAD.

The data storage pattern DSP covers the inner walls of each of the channel holes CH, innerly surrounds the outer walls of the vertical channel pattern VCP, and outerly surrounds the sidewalls of the gate electrodes EL1, EL2, and EL3. can come into contact with Accordingly, the regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP are the second gate electrodes along with the regions corresponding to the second gate electrodes EL2 of the vertical channel pattern VCP. Memory cells in which a memory operation (program operation, read operation, or erase operation) is performed by a voltage applied through EL2 may be configured. The memory cells correspond to the memory cell transistors MCT shown in FIG. 1 . That is, the data storage pattern DSP traps charges or holes by a voltage applied through the second gate electrodes EL2 or maintains a state of charges (eg, a polarization state of charges) in a 3D flash memory. It can act as a data repository. For example, an ONO (tunnel oxide-charge storage layer (Nitride)-blocking oxide layer) layer or a ferroelectric layer may be used as the data storage pattern DSP. Such a data storage pattern DSP may represent binary data values or multi-valued data values with changes in trapped charges or holes, or represent binary data values or multi-valued data values with changes in states of charges.

The vertical channel pattern VCP may cover an inner wall of the data storage pattern DSP. The vertical channel pattern VCP may include a first portion VCP1 and a second portion VCP2 on the first portion VCP1.

The first portion VCP1 of the vertical channel pattern VCP may be provided under each of the channel holes CH and may contact the substrate SUB. The first portion VCP1 of the vertical channel pattern VCP may be used to block, suppress, or minimize leakage current in each of the vertical channel structures VS and/or to form an epitaxial pattern. A thickness of the first portion VCP1 of the vertical channel pattern VCP may be greater than, for example, a thickness of the first gate electrode EL1. A sidewall of the first part VCP1 of the vertical channel pattern VCP may be surrounded by the data storage pattern DSP. A top surface of the first portion VCP1 of the vertical channel pattern VCP may be positioned at a higher level than a top surface of the first gate electrode EL1. More specifically, the top surface of the first part VCP1 of the vertical channel pattern VCP may be positioned between the top surface of the first gate electrode EL1 and the bottom surface of the lowermost one of the second gate electrodes EL2. A lower surface of the first portion VCP1 of the vertical channel pattern VCP may be positioned at a lower level than an uppermost surface of the substrate SUB (ie, a lower surface of a lowermost one of the interlayer insulating layers ILD). A portion of the first portion VCP1 of the vertical channel pattern VCP may overlap the first gate electrode EL1 in a horizontal direction. Hereinafter, the horizontal direction refers to an arbitrary direction extending on a plane parallel to the first and second directions D1 and D2.

The second portion VCP2 of the vertical channel pattern VCP may extend in the third direction D3 from the upper surface of the first portion VCP1. The second portion VCP2 of the vertical channel pattern VCP may be provided between the data storage pattern DSP and the vertical semiconductor pattern VSP, and may correspond to the second gate electrodes EL2. Accordingly, the second portion VCP2 of the vertical channel pattern VCP may form memory cells together with regions corresponding to the second gate electrodes EL2 of the data storage pattern DSP, as described above. .

A top surface of the second part VCP2 of the vertical channel pattern VCP may be substantially coplanar with a top surface of the vertical semiconductor pattern VSP. A top surface of the second part VCP2 of the vertical channel pattern VCP may be positioned at a level higher than a top surface of an uppermost one of the second gate electrodes EL2 . More specifically, the upper surface of the second portion VCP2 of the vertical channel pattern VCP may be positioned between the upper and lower surfaces of the third gate electrode EL3 .

The vertical channel pattern VCP is a component that transfers charges or holes to the data storage pattern DSP, and may be formed of monocrystalline silicon or polysilicon to form a channel or to be boosted by an applied voltage. However, without being limited thereto, the vertical channel pattern VCP may be formed of an oxide semiconductor material capable of blocking, suppressing, or minimizing leakage current. For example, the vertical channel pattern VCP may be formed of an oxide semiconductor material including at least one of In, Zn, and Ga having excellent leakage current characteristics, or a Group 4 semiconductor material. The vertical channel pattern VCP may be formed of, for example, a ZnOx-based material including AZO, ZTO, IZO, ITO, IGZO, or Ag-ZnO. Accordingly, the vertical channel pattern VCP may block, suppress, or minimize leakage current to the gate electrodes EL1 , EL2 , and EL3 or the substrate SUB, and at least one of the gate electrodes EL1 , EL2 , and EL3 Any one transistor characteristic (eg, threshold voltage distribution and program/read speed) may be improved, and consequently, electrical characteristics of the 3D flash memory may be improved.

The vertical semiconductor pattern VSP may be surrounded by the second portion VCP2 of the vertical channel pattern VCP. An upper surface of the vertical semiconductor pattern VSP may contact the conductive pad PAD, and a lower surface of the vertical semiconductor pattern VSP may contact the first portion VCP1 of the vertical channel pattern VCP. The vertical semiconductor pattern VSP may be spaced apart from the substrate SUB in the third direction D3. In other words, the vertical semiconductor pattern VSP may be electrically floated from the substrate SUB.

The vertical semiconductor pattern VSP may be formed of a material that helps diffusion of charges or holes in the vertical channel pattern VCP. More specifically, the vertical semiconductor pattern VSP may be formed of a material having excellent charge and hole mobility. For example, the vertical semiconductor pattern VSP may be formed of a semiconductor material doped with impurities, an intrinsic semiconductor material not doped with impurities, or a polycrystalline semiconductor material. For a more specific example, the vertical semiconductor pattern VSP may be formed of polysilicon doped with impurities of the same first conductivity type as the substrate SUB (eg, P-type impurities). That is, the vertical semiconductor pattern VSP can improve the electrical characteristics of the 3D flash memory to increase the speed of memory operation.

Referring back to FIG. 1 , the vertical channel structures VS include an erase control transistor ECT, first and second string select transistors SST1 and SST2 , a ground select transistor GST, and memory cell transistors MCT. ) may correspond to channels of

Conductive pads PAD may be provided on top surfaces of the second portion VCP2 of the vertical channel pattern VCP and on top surfaces of the vertical semiconductor pattern VSP. The conductive pad PAD may be connected to an upper portion of the vertical channel pattern VCP and an upper portion of the vertical semiconductor pattern VSP. A sidewall of the conductive pad PAD may be surrounded by the data storage pattern DSP. A top surface of the conductive pad PAD may be substantially coplanar with a top surface of each of the stack structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). A lower surface of the conductive pad PAD may be positioned at a lower level than an upper surface of the third gate electrode EL3 . More specifically, the lower surface of the conductive pad PAD may be positioned between the upper and lower surfaces of the third gate electrode EL3 . That is, at least a portion of the conductive pad PAD may overlap the third gate electrode EL3 in a horizontal direction.

The conductive pad PAD may be formed of a semiconductor doped with impurities or a conductive material. For example, the conductive pad PAD is doped with an impurity different from that of the vertical semiconductor pattern VSP (more precisely, an impurity of a second conductivity type (eg, N-type) different from the first conductivity type (eg, P-type)). It may be formed of a semiconductor material.

The conductive pad PAD may reduce contact resistance between the bit line BL and the vertical channel pattern VCP (or vertical semiconductor pattern VSP), which will be described later.

Although the vertical channel structures VS have been described as having a structure including the conductive pad PAD, it is not limited thereto and may have a structure in which the conductive pad PAD is omitted. In this case, as the conductive pad PAD is omitted from the vertical channel structures VS, the upper surfaces of each of the vertical channel pattern VCP and the vertical semiconductor pattern VSP are the upper surfaces of each of the stacked structures ST (ie, Each of the vertical channel pattern VCP and the vertical semiconductor pattern VSP may extend in the third direction D3 so as to be substantially coplanar with the top surface of the uppermost one of the interlayer insulating layers ILD. Also, in this case, the bit line contact plug BLPG, which will be described later, directly contacts the vertical channel pattern VCP instead of being indirectly electrically connected to the vertical channel pattern VCP through the conductive pad PAD. can be electrically connected.

Also, although it has been described that the vertical channel structures VS include the vertical semiconductor pattern VSP, the vertical semiconductor pattern VSP may be omitted without being limited or limited thereto.

In addition, although the vertical channel pattern VCP has been described as having a structure including the first part VCP1 and the second part VCP2, it is not limited thereto and may have a structure excluding the first part VCP1. can For example, the vertical channel pattern VCP is provided between the vertical semiconductor pattern VSP and the data storage pattern DSP and extends to the substrate SUB to contact the substrate SUB. can In this case, the lower surface of the vertical channel pattern VCP may be positioned at a lower level than the uppermost surface of the substrate SUB (the lower surface of the lowermost one of the interlayer insulating films ILD), and the upper surface of the vertical channel pattern VCP may be located at a level lower than that of the upper surface of the substrate SUB. A top surface of the pattern VSP may be substantially coplanar.

Although not shown in the drawing, an isolation trench TR extending in the first direction D1 may be provided between the stacked structures ST adjacent to each other. The isolation trench TR separates and isolates each of the stacked structures ST to form one block. Accordingly, in the conventional 3D flash memory, the vertical channel patterns VS included in each of the stacked structures ST share each of the word lines WL0-WLn, whereas in one embodiment, another 3D flash memory includes at least one separator SF so that the vertical channel patterns VS included in each of the stacked structures ST do not share each of the word lines WL0 - WLn. A detailed description of this will be described below.

The common source region CSR may be provided inside the substrate SUB exposed by the isolation trench TR. The common source region CSR may extend in the first direction D1 within the substrate SUB. The common source region CSR may be formed of a semiconductor material doped with impurities of the second conductivity type (eg, N-type impurities). The common source region CSR may correspond to the common source line CSL of FIG. 1 .

A common source plug CSP may be provided in the isolation trench TR. The common source plug CSP may be connected to the common source region CSR. A top surface of the common source plug CSP may be substantially coplanar with a top surface of each of the stacked structures ST (ie, a top surface of an uppermost one of the interlayer insulating layers ILD). The common source plug CSP may have a plate shape extending in the first and third directions D1 and D3. In this case, the common source plug CSP may have a shape in which a width in the second direction D2 increases toward the third direction D3.

Insulation spacers SP may be interposed between the common source plug CSP and the stacked structures ST. Insulation spacers SP may be provided to face each other between adjacent stacked structures ST. For example, the insulating spacers SP may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

A capping insulating layer CAP may be provided on the stacked structures ST, the vertical channel structures VS, and the common source plug CSP. The capping insulating layer CAP may cover the top surface of the uppermost one of the interlayer insulating layers ILD, the top surface of the conductive pad PAD, and the top surface of the common source plug CSP. The capping insulating layer CAP may be formed of an insulating material different from that of the interlayer insulating layers ILD. A bit line contact plug BLPG electrically connected to the conductive pad PAD may be provided inside the capping insulating layer CAP. The bit line contact plug BLPG may have a shape in which widths in the first and second directions D1 and D2 increase in the third direction D3.

A bit line BL may be provided on the capping insulating layer CAP and the bit line contact plug BLPG. The bit line BL corresponds to any one of the plurality of bit lines BL0 , BL1 , and BL2 shown in FIG. 1 , and may be formed of a conductive material to extend along the second direction D2 . The conductive material constituting the bit line BL may be the same material as the conductive material forming each of the gate electrodes EL1 , EL2 , and EL3 described above.

The bit line BL may be electrically connected to the vertical channel structures VS through the bit line contact plug BLPG. Here, that the bit line BL is connected to the vertical channel structures VS may mean that it is connected to the vertical channel pattern VCP included in the vertical channel structures VS.

At least one separator SF may separate and isolate each of the word lines WL0 -WLn into a plurality of pieces on a horizontal plane within each of the stacked structures VS. For example, the at least one separator SF separates and isolates the first word line WL0 into a 1_1st word line WL0_1 and a 1_2nd word line WL0_2, and separates the second word line WL1 from the first word line WL0_1. The 2_1-th word line WL1_1 and the 2_2-th word line WL1_2 are separated and isolated, and the n−1 th word line WLn is divided into the n−1_1 th word line Wn_1 and the n−1_2 th word line WLn_2. can be separated and isolated. In the drawing, it is shown that at least one separator SF is provided as one in the stack structure ST to separate and isolate each of the word lines WL0 - WLn into two, but by being provided in plurality, the word lines (WL0-WLn) Each can be separated and isolated into three or more.

Accordingly, at least one separation film SF is generated in an existing 3D flash memory in which each of the word lines WL0 to WLn in each of the stacked structures VS is not separated and isolated, but is provided as a single component as a whole. It is possible to achieve a technical effect of improving the influence of the fringing field.

In particular, at least one separator SF may be simultaneously formed through the same process as the vertical channel structures VS. More specifically, at least one separator SF may be simultaneously formed through a process of forming the data storage pattern DSP of the vertical channel structures VS. Accordingly, at least one separation layer SF may be formed of only the data storage pattern DSP. For example, when the data storage pattern DSP of each of the vertical channel structures VS is implemented as an ONO layer, at least one separator SF is formed of a charge storage layer (Nitride) and a blocking oxide layer (Oxide) of the ONO layer. It can be.

At this time, as shown in FIGS. 2 and 3 , at least one separator SF connects the vertical channel structures VS included in at least one column or row of the vertical channel structures VS on a horizontal plane. and may extend in a vertical direction (eg, the third direction D3). Hereinafter, that at least one separator SF connects the vertical channel structures VS to each other on a horizontal plane means to connect entire side surfaces of each of the vertical channel structures VS to each other.

In this case, at least one separator SF may be composed of connecting parts connecting the vertical channel structures VS included in at least one column or row to each other on a horizontal plane.

When the at least one separator SF is formed to connect the vertical channel structures VS included in at least one column or row to each other on a horizontal plane, the vertical channel structures connected by the at least one separator SF Each of VS may be used as a memory cell. That is, each of the vertical channel structures VS connected to each other on a horizontal plane by at least one separator SF is used as a memory cell as shown in FIGS. 2 and 3, and other vertical channel structures VS ( It may have a structure including a vertical channel pattern (VCP) in the same way as a vertical channel structure not connected to at least one separator (SF). However, without being limited thereto, each of the vertical channel structures VS connected by at least one separator SF does not include a vertical channel pattern VCP as shown in FIG. 4 and is used as a memory cell. It can only function as a constituent part of the separation membrane SF.

A width L1 at which the at least one separator SF is formed may be determined to be greater than or equal to a minimum width for electrically separating and isolating each of the word lines WL0 - WLn. In addition, when the vertical channel structures VS included in at least one column or row are connected to each other on a horizontal plane, the width L1 at which the at least one separator SF is formed corresponds to the width L1 of the word lines WL0 to WLn. A condition in which the vertical channel patterns VCP of each of the vertical channel structures VS connected to each other by at least one separator SF are not connected to each other while satisfying the minimum width condition for electrically separating and isolating each other. It can be determined as a value that satisfies That is, at least one separator SF may be formed with a width that satisfies a condition in which only the data storage pattern DSP is formed. For example, when an ONO layer is used as a data storage pattern (DSP), at least one separator SF is formed with a width of within 35 nm in which a 16 nm thick ONO layer can be deposited on both inner walls so that only the ONO layer can be formed. It can be.

As such, when the vertical channel structures VS included in at least one column or row are connected to each other on a horizontal plane, the at least one separator SF electrically separates and isolates each of the word lines WL0 - WLn. While satisfying the minimum width condition to be determined as a value that satisfies the condition that the vertical channel patterns (VCP) of each of the vertical channel structures (VS) connected to each other by at least one separator (SF) are not connected to each other, , vertical channel structures (VS) may maintain a GAA (Gate All Around) structure, and field characteristics applied to the cell string (CSTR) may also be maintained the same as the GAA structure.

However, it is not limited thereto, and the width L1 at which the at least one separator SF is formed is at least one separator trench SFT (at least one separator trench SFT is buried). formed) may be set to a value equal to or greater than the minimum width through which etching gas smoothly flows into the channel holes CH.

When the at least one separator SF connects the vertical channel structures VS included in at least one column or row to each other on a horizontal plane, the at least one separator trench SFT has the vertical channel structures VS In the process of etching the formed channel holes CH, it may be used as a passage through which an etching gas flows into the channel holes CH. Thus, an etch profile may be secured through at least one separator trench (SFT).

As described above, when the at least one separator SF is formed to extend in the vertical direction (eg, the third direction D3) while connecting the vertical channel structures VS included in at least one column or row to each other on a horizontal plane. Although has been described, at least one separator SF is not limited or limited thereto, and as shown in FIG. 5, it does not contact the vertical channel structures VS and separates and isolates each of the word lines WL0 -WLn. can be formed to In this case, at least one separator SF may have a shape in which protrusions 510 and indentations 520 repeat along a direction formed on a horizontal plane. This shape is to overcome the limitation that it is difficult to uniformly form at least one separator trench (SFT) with a constant width when at least one separator (SF) has a long line shape.

The three-dimensional flash memory having such a structure includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string selection line SSL, a voltage applied to each of the word lines WL0-WLn, and a ground selection line. A program operation, a read operation, and an erase operation may be performed based on the voltage applied to the GSL and the voltage applied to the common source line CSL. For example, the 3D flash memory includes a voltage applied to each of the cell strings CSTR, a voltage applied to the string select line SSL, a voltage applied to each of the word lines WL0 to WLn, and a ground select line GSL. ) and the voltage applied to the common source line (CSL), a channel is formed in the vertical channel pattern (VCP) to transfer charges or holes to the data storage pattern (DSP) of the target memory cell, thereby program operation. can be performed.

In addition, the 3D flash memory according to an embodiment is not limited or not limited to the described structure, and according to implementation examples, a vertical channel pattern (VCP), a data storage pattern (DSP), at least one separator (SF), and a gate electrode It may be implemented in various structures on the premise of including EL1 , EL2 , and EL3 , a bit line BL, and a common source line CSL.

For example, the 3D flash memory may be implemented with a structure including a back gate BG instead of the vertical semiconductor pattern VSP contacting the inner wall of the vertical channel pattern VCP. In this case, the back gate BG has at least a portion surrounded by the vertical channel pattern VCP to apply a voltage for a memory operation to the vertical channel pattern VCP in the vertical direction (eg, in the third direction D3). Doped semiconductors (ex, doped silicon, etc.), metals (ex, W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru ( ruthenium), Au (gold), etc.) or a conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.), etc.

6 is a flow chart illustrating a method of manufacturing a 3D flash memory according to an embodiment in which a gate first method is applied to manufacture the 3D flash memory shown in FIGS. 2 and 3, and FIGS. 7A to 7D are shown in FIG. 6 8A to 8D are cross-sectional views showing the structure of the 3D flash memory shown in FIGS. 7A to 7D. 7D correspond to cross-sections taken along the line A-A', and FIGS. 9A to 9D are cross-sectional views showing the structure of the 3D flash memory shown in FIGS. 7A to 7D. Corresponds to the cut section.

Hereinafter, a method of manufacturing a 3D flash memory according to an embodiment is for manufacturing a 3D flash memory having the structure described with reference to FIGS. 2 and 3 by applying a gate first method, by an automated and mechanized manufacturing system. assuming it is done.

In addition, hereinafter, for convenience of description, the manufacturing method is a three-dimensional structure including interlayer insulating films (ILD), word lines (WL0 - WLn), vertical channel structures (VS), and at least one separator (SF). It is described as making a flash memory. Since constituent materials constituting each constituent part of the 3D flash memory have been described with reference to FIGS. 2 and 3 , detailed description thereof will be omitted.

In step S610, as shown in FIGS. 7A, 8A and 9A, the manufacturing system extends in the horizontal direction (eg, the third direction D2) and is formed in the vertical direction (eg, the third direction D3). A semiconductor structure SEMI-STR including alternately stacked interlayer insulating layers ILD and word lines WL0 -WLn may be prepared.

In step S620, the manufacturing system, as shown in FIGS. 7B, 8B, and 9B, channel holes CH and at least one of the channel holes CH in a direction perpendicular to the semiconductor structure SEMI-STR (eg, in the third direction D3). The separation membrane trench SFT may be extended.

Here, the at least one separator trench SFT is formed at a position connecting the channel holes CH included in at least one column or at least one row of the channel holes CH in the stack structure ST to each other on a horizontal plane. It can be. This is limited in the case of manufacturing the 3D flash memory having the structure shown in FIGS. 2 to 4, and in the case of manufacturing the 3D flash memory having the structure shown in FIG. 5, at least one separator trench SFT has channel holes. It may be formed to separate and isolate the plurality of word lines (WL0 - WLn) without being in contact with (CH). More specifically, in the case of manufacturing the 3D flash memory having the structure shown in FIG. 5 , in step S620, the manufacturing system extends the word lines WL0-WLn on the horizontal plane to separate them into a plurality of pieces on the horizontal plane. At least one separator trench SFT having a shape in which protrusions and depressions repeat along a formation direction may be formed.

In addition, the manufacturing system may form at least one separator trench SFT with a size smaller than each of the channel holes CH on a horizontal plane. Through this, the vertical channel structures VS formed in step S630 to be described below can maintain a GAA (Gate All Around) structure, and the field characteristics applied to the cell string CSTR can be maintained the same as the GAA structure. there is.

In step S620, the extending of the channel holes CH and the extending of the at least one separator trench SFT may be simultaneously performed through a single process. Accordingly, the etching gas may smoothly flow into the channel holes CH through the at least one separator trench SFT, thereby ensuring an etching profile.

In step S630, the manufacturing system includes vertical channel structures (including the data storage pattern DSP and the vertical channel pattern VCP) in the vertical direction (eg, the third direction D3) in the channel holes CH. VS) can be formed by extension.

In more detail, step S630 is the first step of forming the data storage pattern DSP on the inner walls of the channel holes CH as shown in FIGS. 7c, 8c and 9c and shown in FIGS. 7d, 8d and 9d. As described above, a second step of forming a vertical channel pattern VCP on an inner wall of the data storage pattern DSP (when the vertical semiconductor pattern VSP is included, the vertical channel pattern VCP is formed together with the vertical channel pattern VCP). Semiconductor pattern (VSP) is also formed).

In operation S640 , the manufacturing system may extend and form at least one separator SF in a vertical direction (eg, in the third direction D3 ) in the at least one separator trench SFT.

Here, steps S630 and S640 may be performed simultaneously through the same process as shown in FIGS. 7c, 8c, and 9c. In more detail, the manufacturing system forms a data storage pattern (DSP) in at least one separator trench (SFT) through a process of depositing the data storage pattern (DSP) of each of the vertical channel structures (VS) in the channel holes (CH). At least one separator SF may be extended and formed by depositing. Accordingly, step S640 may be a step of forming at least one separation film SF as the data storage pattern DSP as the first step of step S630 is performed, and through this, at least one separation film trench SFT ), the simplification of the landfill process can be achieved.

Although it has been described above that the 3D flash memory is manufactured based on one semiconductor structure, it is not limited or limited thereto, and may be manufactured in a stack stacking method in which a plurality of stack structures are stacked. A detailed description thereof will be described with reference to FIG. 10 below.

FIG. 10 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an embodiment in which a stack method is applied in addition to a gate first method to manufacture the 3D flash memory shown in FIGS. 2 and 3 .

Hereinafter, a method of manufacturing a 3D flash memory according to an embodiment is for manufacturing a 3D flash memory having the structure described with reference to FIGS. 2 and 3 by applying a gate first method, by an automated and mechanized manufacturing system. assuming it is done.

In addition, hereinafter, for convenience of description, the manufacturing method is a three-dimensional structure including interlayer insulating films (ILD), word lines (WL0 - WLn), vertical channel structures (VS), and at least one separator (SF). It is described as making a flash memory. Since constituent materials constituting each constituent part of the 3D flash memory have been described with reference to FIGS. 2 and 3 , detailed description thereof will be omitted.

In step S1010, the manufacturing system extends in the horizontal direction (eg, the third direction D2) and alternately stacks the interlayer insulating films ILD and the word in the vertical direction (eg, the third direction D3). Stack structures ST-STR each including the lines WL0-WLn may be prepared.

In step S1020, the manufacturing system extends channel holes CH and at least one separator trench SFT in the vertical direction (eg, the third direction D3) in each of the stack structures ST-STR. can

Here, the at least one separator trench SFT is formed at a position connecting the channel holes CH included in at least one column or at least one row of the channel holes CH in the stack structure ST to each other on a horizontal plane. It can be. This is limited in the case of manufacturing the 3D flash memory having the structure shown in FIGS. 2 to 4, and in the case of manufacturing the 3D flash memory having the structure shown in FIG. 5, at least one separator trench SFT has channel holes. It may be formed to separate and isolate the plurality of word lines (WL0 - WLn) without being in contact with (CH). More specifically, in the case of manufacturing the 3D flash memory having the structure shown in FIG. 5 , in step S1020, the manufacturing system extends the word lines WL0-WLn on the horizontal plane to divide each of the word lines WL0-WLn into a plurality of pieces. At least one separator trench SFT having a shape in which protrusions and depressions repeat along a formation direction may be formed.

In addition, the manufacturing system may form at least one separator trench SFT with a size smaller than each of the channel holes CH on a horizontal plane. Through this, the vertical channel structures VS formed in step S1040 to be described below can maintain a GAA (Gate All Around) structure, and the field characteristics applied to the cell string CSTR can be maintained the same as the GAA structure. there is.

In step S1020, extending and forming the channel holes CH and extending and forming the at least one separator trench SFT may be performed simultaneously through a single process. Accordingly, the etching gas may smoothly flow into the channel holes CH through the at least one separator trench SFT, thereby ensuring an etching profile.

In operation S1030 , the manufacturing system may stack the stack structures ST-STR in a vertical direction (eg, in the third direction D3 ).

In step S1040, the manufacturing system performs a vertical direction (eg, in the channel holes CH in the semiconductor structure SEMI-STR in which the stack structures ST-STR are stacked in the vertical direction (eg, the third direction D3)). For example, vertical channel structures VS each including the data storage pattern DSP and the vertical channel pattern VCP may be extended in the third direction D3 .

In more detail, step S1040 is a first step of forming data storage patterns DSP on inner walls of channel holes CH and forming vertical channel patterns VCP on inner walls of data storage patterns DSP. A second step may be included (if the vertical semiconductor pattern VSP is included, the vertical semiconductor pattern VSP is also formed together with the vertical channel pattern VCP).

In operation S1050 , the manufacturing system may extend and form at least one separator SF in the at least one separator trench SFT in a vertical direction (eg, in the third direction D3 ).

Here, steps S1040 and S1050 may be performed simultaneously through the same process. In more detail, the manufacturing system forms a data storage pattern (DSP) in at least one separator trench (SFT) through a process of depositing the data storage pattern (DSP) of each of the vertical channel structures (VS) in the channel holes (CH). At least one separator SF may be extended and formed by depositing. Accordingly, step S1050 may be a step of forming at least one separation film SF as the data storage pattern DSP as the first step of step S1040 is performed, and through this, at least one separation film trench SFT ), the simplification of the landfill process can be achieved.

Although it has been described above that the 3D flash memory is manufactured based on the gate first method, it is not limited thereto and may be manufactured based on the word line replacement method. A detailed description thereof will be described with reference to FIGS. 11 and 12 below.

FIG. 11 is a flowchart illustrating a method of manufacturing a 3D flash memory according to an embodiment in which a word line replacement method is applied to manufacture the 3D flash memory shown in FIGS. 2 and 3 .

Hereinafter, a method of manufacturing a 3D flash memory according to an embodiment is for manufacturing a 3D flash memory having the structure described with reference to FIGS. 2 and 3 by applying a word line replacement method, and manufacturing is automated and mechanized. It is assumed that it is performed by the system.

In addition, hereinafter, for convenience of description, the manufacturing method is a three-dimensional structure including interlayer insulating films (ILD), word lines (WL0 - WLn), vertical channel structures (VS), and at least one separator (SF). It is described as making a flash memory. Since constituent materials constituting each constituent part of the 3D flash memory have been described with reference to FIGS. 2 and 3 , detailed description thereof will be omitted.

In step S1110, the manufacturing system extends in the horizontal direction (eg, the third direction D2) and alternately stacks the interlayer insulating films ILD and the sacrificial in the vertical direction (eg, the third direction D3). A semiconductor structure SEMI-STR including the layers SAC may be prepared.

In step S1120, the manufacturing system may extend and form channel holes CH and at least one separator trench SFT in the semiconductor structure SEMI-STR in a vertical direction (eg, in the third direction D3). .

Here, the at least one separator trench SFT is formed at a position connecting the channel holes CH included in at least one column or at least one row of the channel holes CH in the stack structure ST to each other on a horizontal plane. It can be. This is limited in the case of manufacturing the 3D flash memory having the structure shown in FIGS. 2 to 4, and in the case of manufacturing the 3D flash memory having the structure shown in FIG. 5, at least one separator trench SFT has channel holes. It is not in contact with (CH) and may be formed to separate and isolate the plurality of sacrificial layers (SAC). In more detail, in the case of manufacturing the three-dimensional flash memory having the structure shown in FIG. 5, in step S1120, the manufacturing system extends on the horizontal plane to separate each of the sacrificial layers SAC into a plurality of on the horizontal plane. At least one separator trench SFT having a shape in which protrusions and depressions repeat along a direction may be formed.

In addition, the manufacturing system may form at least one separator trench SFT with a size smaller than each of the channel holes CH on a horizontal plane. Through this, the vertical channel structures VS formed in step S1130 to be described later can maintain a GAA (Gate All Around) structure, and the field characteristics applied to the cell string CSTR can be maintained the same as the GAA structure. there is.

In step S1120, extending and forming the channel holes CH and extending and forming the at least one separator trench SFT may be performed simultaneously through a single process. Accordingly, the etching gas may smoothly flow into the channel holes CH through the at least one separator trench SFT, thereby ensuring an etching profile.

In operation S1130 , the manufacturing system may remove the sacrificial layers SAC to form word lines WL0 - WLn in spaces from which the sacrificial layers SAC are removed. The removal of the sacrificial layers SAC and the filling of the conductive material to form the word lines WL0 - WLn may be performed through the channel holes CH or at least one separator trench SFT, but are limited thereto. Alternatively, it may be formed through a separate trench (not shown) without being limited thereto.

In step S1140, the manufacturing system includes vertical channel structures (including the data storage pattern DSP and the vertical channel pattern VCP) in the vertical direction (eg, the third direction D3) in the channel holes CH. VS) can be formed by extension.

In more detail, step S1140 is a first step of forming data storage patterns DSP on inner walls of channel holes CH and forming vertical channel patterns VCP on inner walls of data storage patterns DSP. A second step may be included (if the vertical semiconductor pattern VSP is included, the vertical semiconductor pattern VSP is also formed together with the vertical channel pattern VCP).

In operation S1150 , the manufacturing system may extend and form at least one separator SF in the at least one separator trench SFT in a vertical direction (eg, in the third direction D3 ).

Here, steps S1140 and S1150 may be performed simultaneously through the same process. In more detail, the manufacturing system forms a data storage pattern (DSP) in at least one separator trench (SFT) through a process of depositing the data storage pattern (DSP) of each of the vertical channel structures (VS) in the channel holes (CH). At least one separator SF may be extended and formed by depositing. Accordingly, step S1150 may be a step of forming at least one separation film SF as the data storage pattern DSP as the first step of step S1140 is performed, and through this, at least one separation film trench SFT ), the simplification of the landfill process can be achieved.

Although it has been described above that the 3D flash memory is manufactured based on one semiconductor structure, it is not limited or limited thereto, and may be manufactured in a stack stacking method in which a plurality of stack structures are stacked. A detailed description thereof will be described with reference to FIG. 12 below.

FIG. 12 is a flow chart illustrating a method of manufacturing a 3D flash memory according to an embodiment in which a stack method is applied in addition to a word line replacement method to manufacture the 3D flash memory shown in FIGS. 2 and 3 .

Hereinafter, a method of manufacturing a 3D flash memory according to an embodiment is for manufacturing a 3D flash memory having the structure described with reference to FIGS. 2 and 3 by applying a gate first method, by an automated and mechanized manufacturing system. assuming it is done.

In addition, hereinafter, for convenience of description, the manufacturing method is a three-dimensional structure including interlayer insulating films (ILD), word lines (WL0 - WLn), vertical channel structures (VS), and at least one separator (SF). It is described as making a flash memory. Since constituent materials constituting each constituent part of the 3D flash memory have been described with reference to FIGS. 2 and 3 , detailed description thereof will be omitted.

In step S1210, the manufacturing system extends in the horizontal direction (eg, the third direction D2) and alternately stacks the interlayer insulating films ILD and the sacrificial in the vertical direction (eg, the third direction D3). Stack structures ST-STR each including layers SAC may be prepared.

In operation S1220, the manufacturing system extends channel holes CH and at least one separator trench SFT in the vertical direction (eg, the third direction D3) in each of the stack structures ST-STR. can

Here, the at least one separator trench SFT is formed at a position connecting the channel holes CH included in at least one column or at least one row of the channel holes CH in the stack structure ST to each other on a horizontal plane. It can be. This is limited in the case of manufacturing the 3D flash memory having the structure shown in FIGS. 2 to 4, and in the case of manufacturing the 3D flash memory having the structure shown in FIG. 5, at least one separator trench SFT has channel holes. It is not in contact with (CH) and may be formed to separate and isolate the plurality of sacrificial layers (SAC). In more detail, in the case of manufacturing the 3D flash memory having the structure shown in FIG. 5, in step S1220, the manufacturing system extends on the horizontal plane to separate each of the sacrificial layers SAC into a plurality of them on the horizontal plane. At least one separator trench SFT having a shape in which protrusions and depressions repeat along a direction may be formed.

In addition, the manufacturing system may form at least one separator trench SFT with a size smaller than each of the channel holes CH on a horizontal plane. Through this, the vertical channel structures VS formed in step S1250 to be described below can maintain a GAA (Gate All Around) structure, and the field characteristics applied to the cell string CSTR can be maintained the same as the GAA structure. there is.

In step S1220, extending and forming the channel holes CH and extending and forming the at least one separator trench SFT may be performed simultaneously through a single process. Accordingly, the etching gas may smoothly flow into the channel holes CH through the at least one separator trench SFT, thereby ensuring an etching profile.

In operation S1230 , the manufacturing system may stack the stack structures ST-STR in a vertical direction (eg, in the third direction D3 ).

In operation S1240 , the manufacturing system may remove the sacrificial layers SAC to form word lines WL0 - WLn in spaces where the sacrificial layers SAC are removed. The removal of the sacrificial layers SAC and the filling of the conductive material to form the word lines WL0 - WLn may be performed through the channel holes CH or at least one separator trench SFT, but are limited thereto. Alternatively, it may be formed through a separate trench (not shown) without being limited thereto.

In operation S1250, the manufacturing system performs a vertical direction (eg, in the channel holes CH in the semiconductor structure SEMI-STR in which the stack structures ST-STR are stacked in the vertical direction (eg, the third direction D3)). For example, vertical channel structures VS each including the data storage pattern DSP and the vertical channel pattern VCP may be extended in the third direction D3 .

In more detail, step S1250 is a first step of forming data storage patterns DSP on inner walls of channel holes CH and forming vertical channel patterns VCP on inner walls of data storage patterns DSP. A second step may be included (if the vertical semiconductor pattern VSP is included, the vertical semiconductor pattern VSP is also formed together with the vertical channel pattern VCP).

In operation S1260 , the manufacturing system may extend and form at least one separator SF in the at least one separator trench SFT in a vertical direction (eg, in the third direction D3 ).

Here, steps S1250 and S1260 may be performed simultaneously through the same process. In more detail, the manufacturing system forms a data storage pattern (DSP) in at least one separator trench (SFT) through a process of depositing the data storage pattern (DSP) of each of the vertical channel structures (VS) in the channel holes (CH). At least one separator SF may be extended and formed by depositing. Accordingly, step S1260 may be a step of forming at least one separation layer SF as the data storage pattern DSP as the first step of step S1250 is performed, and through this, at least one separation layer trench SFT ), the simplification of the landfill process can be achieved.

13 is a perspective view schematically illustrating an electronic system including a 3D flash memory according to embodiments.

Referring to FIG. 13 , an electronic system 1300 including a 3D flash memory according to embodiments includes a main board 1301, a controller 1302 mounted on the main board 1301, and one or more semiconductor packages 1303. ) and DRAM 1304.

The semiconductor package 1303 and the DRAM 1304 may be connected to the controller 1302 through wiring patterns 1305 provided on the main substrate 1301 .

The main board 1301 may include a connector 1306 including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 1306 may vary depending on the communication interface between the electronic system 1300 and an external host.

The electronic system 1300 may include, for example, one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCIExpress), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). Depending on one, you can communicate with external hosts. The electronic system 1300 may be operated by power supplied from an external host through, for example, a connector 1306 . The electronic system 1300 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from an external host to the controller 1302 and the semiconductor package 1303 .

The controller 1302 can write data to the semiconductor package 1303 or read data from the semiconductor package 1303 and can improve the operating speed of the electronic system 1300 .

The DRAM 1304 may be a buffer memory for mitigating a speed difference between the semiconductor package 1303, which is a data storage space, and an external host. The DRAM 1304 included in the electronic system 1300 may also operate as a kind of cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package 1303 . When the electronic system 1300 includes the DRAM 1304 , the controller 1302 may further include a DRAM controller for controlling the DRAM 1304 in addition to the NAND controller for controlling the semiconductor package 1303 .

The semiconductor package 1303 may include first and second semiconductor packages 1303a and 1103b spaced apart from each other. Each of the first and second semiconductor packages 1303a and 1103b may be a semiconductor package including a plurality of semiconductor chips 1320 . Each of the first and second semiconductor packages 1303a and 1103b includes a package substrate 1310 , semiconductor chips 1320 on the package substrate 1310 , and adhesive layers 1330 disposed on a lower surface of each of the semiconductor chips 1320 . ), connection structures 1340 electrically connecting the semiconductor chips 1320 and the package substrate 1310 and a molding layer 1350 covering the semiconductor chips 1320 and the connection structures 1340 on the package substrate 1310 can include

The package substrate 1310 may be a printed circuit board including package upper pads 1311 . Each of the semiconductor chips 1320 may include input/output pads 1321 . Each of the semiconductor chips 1320 may include the 3D flash memory described above with reference to FIGS. 1 to 5 . More specifically, each of the semiconductor chips 1320 may include gate stack structures 1322 and memory channel structures 1323 . The gate stack structures 1322 may correspond to the above-described stack structures ST, and the memory channel structures 1323 may correspond to the above-described vertical channel structures VS and at least one separator SF. can

The connection structures 1340 may be, for example, bonding wires electrically connecting the input/output pads 1321 and the package upper pads 1311 . Accordingly, in each of the first and second semiconductor packages 1303a and 1103b, the semiconductor chips 1320 may be electrically connected to each other using a bonding wire method, and the package upper pads 1311 of the package substrate 1310 and can be electrically connected. According to example embodiments, in each of the first and second semiconductor packages 1303a and 1103b, the semiconductor chips 1320 are connected to the through electrode (Through Silicon Via) instead of the bonding wire type connection structures 1340. may be electrically connected to each other.

Unlike shown, the controller 1302 and the semiconductor chips 1320 may be included in one package. The controller 1302 and the semiconductor chips 1320 may be mounted on a separate interposer substrate different from the main substrate 1301, and the controller 1302 and the semiconductor chips 1320 may be connected to each other by wiring provided on the interposer substrate. there is.

As described above, although the embodiments have been described with limited examples and drawings, those skilled in the art can make various modifications and variations from the above description. For example, the described techniques may be performed in an order different from the method described, and/or components of the described system, structure, device, circuit, etc. may be combined or combined in a different form than the method described, or other components may be used. Or even if it is replaced or substituted by equivalents, appropriate results can be achieved.

Therefore, other implementations, other embodiments, and equivalents of the claims are within the scope of the following claims.

Claims (6)

interlayer insulating films and word lines extending in the horizontal direction and alternately stacked in the vertical direction;
Vertical channel structures extending through the interlayer insulating films and the word lines in the vertical direction - each of the vertical channel structures surrounds a vertical channel pattern extending in the vertical direction and an outer wall of the vertical channel pattern; including the data storage pattern being formed; and
At least one separator formed of the same material as the data storage pattern and separating each of the word lines into a plurality of pieces on a horizontal plane
A three-dimensional flash memory comprising a. According to claim 1,
The at least one separator,
A three-dimensional flash memory, characterized in that formed to connect vertical channel structures included in at least one column or row of the vertical channel structures to each other on the horizontal plane. According to claim 2,
The at least one separator,
vertical channel structures included in the at least one column or row; and
Connections connecting the vertical channel structures included in the at least one column or row to each other on the horizontal plane.
A three-dimensional flash memory comprising a. According to claim 3,
Each of the vertical channel structures included in the at least one column or row,
A three-dimensional flash memory, characterized in that it does not include the vertical channel pattern. According to claim 1,
The at least one separator,
The three-dimensional flash memory according to claim 1 , wherein each of the word lines has a shape in which protrusions and depressions repeat along a direction extending on the horizontal plane to divide each of the word lines into a plurality of pieces on the horizontal plane. According to claim 1,
The at least one separator,
A three-dimensional flash memory, characterized in that formed at the same time through the same process as the vertical channel structures.

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