KR20210032891A - Semiconductor device - Google Patents

Abstract

According to an embodiment of the present invention, a semiconductor device includes: a substrate; a first stacked structure disposed on the substrate, and including first gate electrodes stacked apart from each other and first interlayer insulating layers stacked alternately with the first gate electrodes; a connection structure disposed on the first stacked structure, and including a metal oxide layer having a dielectric constant that is higher than a dielectric constant of each of the first interlayer insulating layers and a semiconductor oxide layer including a semiconductor oxide; a second stacked structure disposed on the connection structure, and including second gate electrodes stacked apart from each other and second interlayer insulating layers stacked alternately with the second gate electrodes; a channel structure including a first channel structure, a second channel structure, and a connection channel structure penetrating through the first stacked structure, the second stacked structure, and the connection structure, respectively; and a separation region passing through each of the first stacked structure, the second stacked structure, and the connection structure, and including a first separation region, a second separation region, and a third separation region extending in a horizontal direction of a top surface of the substrate, wherein the connection channel structure has a third width that is greater than a first width of an upper end of the first channel structure and greater than a second width of a lower end of the second channel structure, and the third separation region has a sixth width that is greater than the third width of the connection channel structure, a fourth width of an upper end of the first separation region, and a fifth width of a lower end of the second separation region. Accordingly, a degree of integration and reliability are improved.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device.

Semiconductor devices require high-capacity data processing while their volume is getting smaller. Accordingly, it is necessary to increase the degree of integration of semiconductor elements constituting such a semiconductor device. Accordingly, as one of methods for improving the degree of integration of a semiconductor device, a semiconductor device having a vertical transistor structure instead of a conventional planar transistor structure has been proposed.

One of the technical problems to be achieved by the technical idea of the present invention is to provide a semiconductor device with improved integration and reliability.

In the semiconductor device according to exemplary embodiments, the semiconductor device according to the exemplary embodiment includes a substrate, first gate electrodes disposed on the substrate and stacked apart from each other, and alternately with the first gate electrodes. A first stacked structure including first interlayer insulating layers stacked with, a metal oxide layer and a semiconductor oxide disposed on the first stacked structure and having a dielectric constant higher than that of the first interlayer insulating layers A connection structure including a semiconductor oxide layer, second gate electrodes disposed on the connection structure and stacked spaced apart from each other, and second interlayer insulating layers alternately stacked with the second gate electrodes A channel structure including a stacked structure, a first channel structure, a second channel structure, and a connection channel structure penetrating each of the stacked structure, the first stacked structure, the second stacked structure, and the connection structure, and the first stacked structure, A separation region including a first separation region, a second separation region, and a third separation region that penetrates each of the second stacked structure and the connection structure and extends in a horizontal direction of an upper surface of the substrate, and the connection The channel structure has a third width greater than a first width of an upper end of the first channel structure, and a third width greater than a second width of a lower end of the second channel structure, and the third separation region is the third width of the connection channel structure. It has a width, a fourth width at an upper end of the first separation area, and a sixth width greater than a fifth width at a lower end of the second separation area.

The semiconductor device according to exemplary embodiments is a first stacking including first gate electrodes disposed on a substrate and stacked to be spaced apart from each other, and first interlayer insulating layers alternately stacked with the first gate electrodes A structure, a connection structure disposed on the first stacked structure, second gate electrodes disposed on the connection structure and stacked apart from each other, and second interlayer insulating layers alternately stacked with the second gate electrodes A channel structure penetrating through the second stacked structure, the first stacked structure, the second stacked structure, and the connection structure including the first stacked structure, the second stacked structure, and the connection structure, and the A first dielectric layer having a first dielectric constant that is higher than a dielectric constant of the first interlayer insulating layers and the second interlayer insulating layers, wherein the connection structure includes a separation region extending in a horizontal direction of an upper surface of the substrate And a second dielectric layer in contact with the isolation region and having a second dielectric constant lower than the first dielectric constant.

The semiconductor device according to exemplary embodiments is a first stacking including first gate electrodes disposed on a substrate and stacked to be spaced apart from each other, and first interlayer insulating layers alternately stacked with the first gate electrodes A structure, a connection structure disposed on the first stacked structure, second gate electrodes disposed on the connection structure and stacked apart from each other, and second interlayer insulating layers alternately stacked with the second gate electrodes A second stacked structure including a second stacked structure, the first stacked structure, the second stacked structure, and a channel structure penetrating through the connection structure, and a second stacking structure penetrating each of the first stacked structure, the second stacked structure, and the connection structure And a separation region including a first isolation region, a second isolation region, and a third isolation region, and the connection structure is a dielectric constant higher than the dielectric constants of the first interlayer insulating layers and the second interlayer insulating layers. A first dielectric layer having a first dielectric constant is included, and a third width of the third isolation region is greater than a first width of the first isolation region and a second width of the second isolation region.

In a semiconductor device, by inserting a high-k layer between the upper and lower stacked structures, it can be used as an etch stop layer when forming upper and lower channel structures and separation regions.

By providing a connection channel structure extending in a horizontal direction at a connection portion to which the upper and lower channel structures are connected, the upper channel structure can be stably connected to the lower channel structure.

Various and beneficial advantages and effects of the present invention are not limited to the above description, and may be more easily understood in the course of describing specific embodiments of the present invention.

1 is a schematic cross-sectional view of a portion of a semiconductor device according to example embodiments.
2 is a schematic plan view of a portion of a semiconductor device according to example embodiments.
3 is a partially enlarged view of a semiconductor device according to example embodiments.
4 is a partially enlarged view of a semiconductor device according to example embodiments.
5A is a schematic plan view of a portion of a semiconductor device according to example embodiments.
5B is a partially enlarged view of a semiconductor device according to example embodiments.
6A is a schematic plan view illustrating a semiconductor device according to example embodiments.
6B is a partially enlarged view illustrating a semiconductor device according to example embodiments.
7A is a schematic plan view illustrating a semiconductor device according to example embodiments.
7B is a partially enlarged view illustrating an example of a semiconductor device according to example embodiments.
8A is a schematic cross-sectional view of a semiconductor device according to example embodiments.
8B is a partially enlarged view of a semiconductor device according to example embodiments.
8C is a partially enlarged view of a semiconductor device according to example embodiments.
9A to 9J are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic cross-sectional view of a portion of a semiconductor device according to example embodiments. A schematic plan view of a portion of a semiconductor device according to example embodiments.

2 is a schematic plan view of a portion of a semiconductor device according to example embodiments. FIG. 2 shows a plane cut along the cutting line I-I' of the semiconductor device of FIG. 1. For convenience of description, only major components of a semiconductor device are illustrated in FIGS. 1 and 2.

3 is a partially enlarged view of a semiconductor device according to example embodiments. FIG. 3 is an enlarged view of area A of FIG. 1.

4 is a partially enlarged view of a semiconductor device according to example embodiments. FIG. 4 is an enlarged view of area B of FIG. 1.

1 to 4, a semiconductor device 100 according to an exemplary embodiment includes a substrate 101, a first stacked structure ST1 sequentially stacked on the substrate, a connection structure CS, and a second stacked structure. The channel structure CH disposed to penetrate the structure ST2, the first stacked structure, the second stacked structures ST1 and ST2, and the connection structure CS, and the first and second stacked structures ST1 and ST2. ) And a separation region SR that passes through the connection structure CS and extends in a horizontal direction on an upper surface of the substrate. In addition, the semiconductor device 100 may further include first and second conductive layers 104 and 105 disposed between the substrate 101 and the interlayer insulating layer 120. The isolation region SR may include isolation insulating layers 185, and the isolation insulating layers 185 may include an insulating material, for example, silicon oxide. In example embodiments, the first and second conductive layers 104 and 105 may be omitted. In this case, the channel structure CH may include an epitaxial layer disposed under the channel layer 140, and the isolation region SR includes a conductive material, the conductive material, and the first and second stacked structures ST1. It may include an insulating material that electrically insulates ST2).

The substrate 101 may have an upper surface extending in the x and y directions. The substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 101 may be provided as a bulk wafer, an epitaxial layer, an epitaxial layer, a silicon on insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like.

The first stacked structure ST1 may include first interlayer insulating layers 120 and first gate electrodes 130 alternately stacked on the substrate 101. The second stacked structure ST2 may include second interlayer insulating layers 220 and second gate electrodes 230 alternately stacked on the first stacked structure ST1.

The first and second gate electrodes 130 and 230 may be stacked on the substrate 101 to be vertically spaced apart from each other. The first and second gate electrodes 130 and 230 may extend to different lengths on at least one region of the substrate 101.

The first lowermost gate electrode 130L disposed at the lowermost part of the first gate electrodes 130 may be a gate electrode of the ground selection transistor. The second uppermost gate electrode 230U disposed on the top of the second gate electrodes 230 may be a gate electrode of the string selection transistor. According to an embodiment, there may be one or two or more string selection gate electrodes and ground selection gate electrodes, respectively.

The first and second gate electrodes 130 and 230 between the first lowermost gate electrode 130L and the second uppermost gate electrode 230U may be memory cell gate electrodes constituting a plurality of memory cells. The number of first and second gate electrodes 130 and 230 constituting memory cells may be determined according to the capacity of the semiconductor device 100.

The first and second gate electrodes 130 and 230 may be separated and disposed in a predetermined unit by separation regions SR extending in one direction. The first and second gate electrodes 130 and 230 between the pair of isolation regions SR may form one memory block, but the range of the memory block is not limited thereto.

Some of the first and second gate electrodes 130 and 230, for example, the string selection gate electrode and the gate electrodes 130 and 230 adjacent to the ground selection gate electrode, may be dummy gate electrodes. The first uppermost gate electrode 130U positioned at the uppermost of the first gate electrodes 130 and the second lowermost gate electrode 230L positioned at the lowermost of the second gate electrodes 230 may also be dummy gate electrodes.

The first and second gate electrodes 130 and 230 may include a metallic material such as tungsten (W). According to an embodiment, the first and second gate electrodes 130 and 230 may include polycrystalline silicon or a metal silicide material.

The first and second gate electrodes 130 and 230 may include an internal gate conductive layer and a diffusion barrier surrounding the gate conductive layer. The diffusion barrier layer may include, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

The first and second interlayer insulating layers 120 and 220 may be disposed between the gate electrodes 130 and 230, respectively. Like the first and second gate electrodes 130 and 230, the first and second interlayer insulating layers 120 and 220 are spaced apart from each other in a direction perpendicular to the upper surface of the substrate 101 and extend in at least one direction. Can be placed. The first and second interlayer insulating layers 120 and 220 may include an insulating material such as silicon oxide or silicon nitride. In one embodiment, the uppermost first interlayer insulating layer 120U disposed on the uppermost of the first interlayer insulating layers 120 and the lowermost second interlayer insulating layer disposed at the lowermost part of the second interlayer insulating layers 220 ( 220L) may have substantially the same or relatively thin thickness as other interlayer insulating layers. In one embodiment, the thicknesses VT1 and VT2 of the uppermost first interlayer insulating layer 120U and the lowermost second interlayer insulating layer 220L may range from about 5 nm to 20 nm.

The isolation region SR may be disposed to extend in the horizontal direction of the substrate. The isolation region SR may be a through isolation region that penetrates the entire first and second gate electrodes 130 and 230 stacked on the substrate 101 and is connected to the substrate 101. The isolation region SR may separate the first and second gate electrodes 130 and 230. The isolation region SR may be disposed to partially recess the upper portion of the substrate 101 or may be disposed on the substrate 101 so as to contact the upper surface of the substrate 101. The isolation region SR may include the isolation insulating layer 185, and the isolation insulating layer 185 may include an insulating material, for example, silicon oxide.

The isolation region SR may include a first isolation region SR1, a second isolation region SR2, and a third isolation region SR3. The first separation region SR1 may penetrate the first stacked structure ST1, and the second separation region SR2 may penetrate the second stacked structure ST2. The third isolation region SR3 may connect the first isolation region SR1 and the second isolation region SR2 to each other. As shown in FIG. 3, the third separation area SR3 has a second width T1 that is greater than the first width T1 of the top of the first separation area SR1 and the second width T2 of the bottom of the second separation area SR2. It may have 3 widths (T3). The third width T3 of the third isolation region SR3 may be greater than the third width W3 of the connection channel structure CHM illustrated in FIG. 4.

The connection structure CS may be disposed between the first stacked structure ST1 and the second stacked structure ST2. The connection structure CS may include a high dielectric layer 190 including a high-k material as a first dielectric layer. Here, the high-k material means a dielectric material having a higher dielectric constant than _{silicon oxide (SiO 2 ).} That is, the high dielectric constant material of the high dielectric layer 190 may have a dielectric constant higher than that of the insulating material of the first and second interlayer insulating layers 120 and 220. The high-k materials are, for example, aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ) , Zirconium silicon oxide (ZrSi _x O _y ), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAl _x O _y ), lanthanum hafnium oxide (LaHf _x O _y ), hafnium aluminum oxide (HfAl _x O _y ), praseodymium oxide (Pr ₂ O ₃ ), or a combination thereof. In particular, the high-k layer 190 may be a metal oxide layer including a metal oxide as a high-k material. In exemplary embodiments, as shown in FIG. 4, the thickness VT0 of the high dielectric layer 190 is the thickness VT1 of the first uppermost interlayer insulating layer 120U and the second lowermost interlayer insulating layer 220L. It may be thicker than the thickness of (VT2). For example, the thickness VT0 of the high-k layer 190 may range from about 30 nm to about 150 nm.

The high-k layer 190 is provided as an etch stop layer in the etching process of the second channel structure CH2 and the second isolation region SR described below with reference to FIGS. Misalignment between the channel structure CH1 and the second channel structure CH2, or the first and second isolation regions SR1 and SR2 may be minimized.

In addition, the connection structure CS may include an oxide layer 194 as a second dielectric layer. The oxide layer 194 may have a dielectric constant smaller than that of the first dielectric layer, that is, the high dielectric layer 190. The oxide layer 194 may be a semiconductor oxide layer including a semiconductor oxide, and may include, for example, silicon oxide. The oxide layer 194 may be disposed between the isolation region SR and the connection channel structure CHM adjacent to the isolation region SR. In one embodiment, the high-k layer 190 may be disposed between the isolation region SR and the connection channel structure CHM adjacent to the isolation region SR. In this case, the oxide layer 194 is the isolation region ( SR) and the high-k dielectric layer 190 may be disposed between. The oxide layer 194 may cover the entire side surface of the high dielectric layer 190 adjacent to the isolation region SR. The oxide layer 194 is In the wet etching process described below with reference to FIG. 9J, the high dielectric layer 190 or the connection channel structure CHM may be prevented from being etched.

In one embodiment, the connection structure CS further includes a polycrystalline silicon layer 192 including, for example, polycrystalline silicon, between the connection channel structure CHM and the oxide layer 194 adjacent to the isolation region SR. Can include. The oxide layer 194 may cover the entire side of the polysilicon layer 192 adjacent to the isolation region SR. In one embodiment, the high dielectric layer 190 may be disposed between the isolation region SR and the connection channel structure CHM adjacent to the isolation region SR. In this case, the connection channel structure CHM and the isolation region A high-k layer 190, a polycrystalline silicon layer 192, and an oxide layer 194 may be disposed between the SRs in order from the connection channel structure CHM. The first uppermost interlayer insulating layer 120U and the second lowermost interlayer insulating layer 220L may protrude from the oxide layer 194 to the isolation region SR.

The channel structures CH may be spaced apart from each other while forming rows and columns on the substrate 101. The channel structures CH may be disposed to form a grid pattern or may be disposed in a zigzag shape in one direction. The channel structures CH may extend vertically on the substrate 101. The channel structures CH have a columnar shape, and may have inclined side surfaces that become narrower as they are closer to the substrate 101 according to an aspect ratio.

In the channel structure CH, the channel layer 140 may be formed in an annular shape surrounding the inner channel insulating layer 150, but according to the embodiment, a cylinder or a prism may be formed without the channel insulating layer 150. They may have the same pillar shape. The channel layer 140 may be directly connected to the substrate 101 from the bottom. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or single crystal silicon, and the semiconductor material may be an undoped material or a material including p-type or n-type impurities. The channel structures CH disposed on a straight line in the x direction may be respectively connected to different bit lines by arranging an upper wiring structure connected to the channel pad 255. In addition, some of the channel structures CH may be dummy channels that are not connected to the bit line.

4, the channel structure CH may sequentially include a tunneling layer 142, a charge storage layer 143, and a blocking layer 144 from the channel layer 140. The relative thicknesses of the tunneling layer 142, the charge storage layer 143, and the blocking layer 144 are not limited to those shown in the drawings, and may vary in various embodiments.

The tunneling layer 142 may tunnel electric charges to the charge storage layer 143 using an FN tunneling method. The tunneling layer 142 may include, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a combination thereof. The charge storage layer 143 may be a charge trap layer and may be made of silicon nitride. The blocking layer 144 may include silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), a high-k material, or a combination thereof.

In the channel structure CH, the tunneling layer 142, the charge storage layer 143, and the blocking layer 144 may be disposed to extend into the substrate 101. The tunneling layer 142, the charge storage layer 143, and the blocking layer 144 may be partially removed from the bottom, and the tunneling layer 142, the charge storage layer 143, and the blocking layer 144 are removed. The channel layer 140 may be connected to the first conductive layer 104.

The channel structure CH may include a first channel structure CH1, a connection channel structure CHM, and a second channel structure CH2. The connection channel structure CHM may connect the first channel structure CH1 and the second channel structure CH2.

The first channel structure CH1 may penetrate the first stacked structure ST1, and the second channel structure CH2 may penetrate the second stacked structure ST2. The connection channel structure CHM may be disposed between the first stacked structure ST1 and the second stacked structure ST2. That is, the connection channel structure CHM may be disposed in the connection structure CS. As illustrated in FIG. 4, the connection channel structure CHM is larger than the first width W1, which is the maximum width of the upper end of the first channel structure CH1, and It may have a third width W3 that is greater than the width W2. In an embodiment, the connection channel structure CHM may have a curved surface that is convex outward. In one embodiment, the distance d1 in the horizontal direction between the outer surface of the lower end of the second channel structure CH2 and the outer surface of the connection channel structure CHM may range from about 1 nm to about 5 nm.

The channel pad 255 may be disposed to cover the upper surface of the channel insulating layer 150 and be electrically connected to the channel layer 140. The channel pad 255 may include, for example, doped polycrystalline silicon.

The first and second conductive layers 104 and 105 may be stacked and disposed on the upper surface of the substrate 101. At least some of the first and second conductive layers 104 and 105 may function as a common source line of the semiconductor device 100. The first conductive layer 104 may be directly connected to the channel layer 140 around the channel structure CH. The first and second conductive layers 104 and 105 may include a semiconductor material, for example, polycrystalline silicon. In this case, at least the first conductive layer 104 may be a doped layer, and the second conductive layer 105 may be a doped layer or a layer including impurities diffused from the first conductive layer 104.

The cell region insulating layer 290 is disposed on the second stacked structure ST2 of the second gate electrodes 230 and may include an insulating material such as silicon oxide or silicon nitride.

In FIGS. 5A to 8C, descriptions of the same components as those described with reference to FIGS. 1 to 4 will be omitted, and only modified components of the semiconductor device will be described.

5A is a schematic plan view of a portion of a semiconductor device according to example embodiments.

5B is a partially enlarged view of a semiconductor device according to example embodiments. FIG. 5B is an enlarged view of an area corresponding to area'A' of FIG. 1.

5A and 5B, in the semiconductor device 100a, the high-k dielectric layer (CHM) is sequentially between the connection channel structure CHM and the isolation region SR adjacent to the isolation region SR. 190) and an oxide layer 194 may be disposed. Unlike FIG. 1, the connection structure CS may not include the polysilicon layer 192. The thickness of the oxide layer 194 in the x direction from the isolation region SR may be thicker than the thickness of the oxide layer 194 of the semiconductor device 100 of FIGS. 1 to 3, but is not limited thereto. In an exemplary embodiment, in the selective oxidation process of the polycrystalline silicon layer 192 described below with reference to FIG. 9I, all of the polycrystalline silicon layer 192 is oxidized so as not to include the polycrystalline silicon layer 192, but an oxide layer. It may contain only (194). In an exemplary embodiment, deposition of the polycrystalline silicon 192a described below with reference to FIG. 9G may be omitted, and only the oxide layer 194 may be included by depositing a semiconductor oxide instead of the polycrystalline silicon 192a. The oxide layer 194 may cover the entire side surface of the high dielectric layer 190 adjacent to the isolation region SR.

6A is a schematic plan view of a portion of a semiconductor device according to example embodiments.

6B is a partially enlarged view of a semiconductor device according to example embodiments. 6B is an enlarged view of an area corresponding to area'A' of FIG. 1.

6A and 6B, in the semiconductor device 100b, the connection structure CS may include a high dielectric layer 190, an oxide layer 194, and a polycrystalline silicon layer 192. The polysilicon layer 192 and the oxide layer 194 may be sequentially disposed between the connection channel structure CHM and the isolation region SR adjacent to the isolation region SR from the connection channel structure CHM. The polysilicon layer 192 may contact the connection channel structure CHM. In FIG. 6A, the distance from the isolation region SR to the first surface in contact with the high dielectric layer 190 of the polysilicon layer 192 along the x direction is the isolation region SR of the semiconductor device 100 of FIG. 2. ) To the first surface of the polysilicon layer 192 along the x direction. The first surface of the polysilicon layer 192 may contact the channel structure CH in a row adjacent to the isolation region SR. The width of the polysilicon layer 192 along the x direction from the isolation region SR may be greater than the width of the polysilicon layer 192 of the semiconductor device 100 of FIGS. 1 to 3, but is not limited thereto.

7A is a schematic plan view illustrating a modified example of a semiconductor device according to example embodiments.

7B is a partially enlarged view showing a modified example of a semiconductor device according to example embodiments. FIG. 7B is an enlarged view of an area corresponding to area'A' of FIG. 1.

7A and 7B, unlike FIG. 1, in the semiconductor device 100c, the connection structure CS adjacent to the isolation region SR may not include the polysilicon layer 192. The oxide layer 194 may contact the connection channel structure CHM. In FIG. 7A, the distance from the isolation region SR to the second surface in contact with the high dielectric layer 190 of the oxide layer 194 along the x direction is the isolation region SR of the semiconductor device 100 of FIG. 5A It may be greater than a distance from to the second surface of the oxide layer 194 along the x direction. The second surface of the oxide layer 194 may contact the channel structure CH in a row adjacent to the isolation region SR.

8A is a schematic cross-sectional view of a semiconductor device according to example embodiments.

8B is a partially enlarged view of a semiconductor device according to example embodiments. FIG. 8B is an enlarged view of area A of FIG. 8A.

8C is a partially enlarged view of a semiconductor device according to example embodiments. FIG. 8C is an enlarged view of area B of FIG. 8A.

Referring to FIGS. 8A to 8C, in the semiconductor device 100d, the center of the second channel structure CH2 is not aligned with the first channel structure CH1 but may be shifted and aligned. The second channel structure CH2 may be moved and positioned on the x-y plane from the first channel structure CH1. In this case as well, the channel layer 140, the tunneling layer 142, the charge storage layer 143, and the blocking layer in the first channel structure CH1, the second channel structure CH2, and the connection channel structure CHM 144) can be connected to each other. The connection channel structure (CHM) may be asymmetrical from the center, and the channel layer 140, the tunneling layer 142, the charge storage layer 143 and the blocking layer 144 in the connection channel structure (CHM) may be formed asymmetrically. I can. The second separation area SR2 may be aligned by shifting the center of the first separation area SR1 without being aligned in a straight line. The second isolation region SR2 may be moved and positioned on the x-y plane with respect to the first isolation region SR.

9A to 9J are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. 9A to 9J show cross-sections corresponding to FIG. 1.

Referring to FIG. 9A, first and second source sacrificial layers 111 and 112 and a second conductive layer 105 are formed on a substrate 101, and the first horizontal sacrificial layers 110 and the first The first stacked structure ST1 may be formed by alternately stacking the interlayer insulating layers 120. Next, after partially removing the first stacked structure ST1, the first and second through sacrificial layers 113 and 114 may be formed.

First, the first and second source sacrificial layers 111 and 112 may include different materials, and the first source sacrificial layers 111 are disposed above and below the second source sacrificial layer 112. It can be stacked on 101. The first and second source sacrificial layers 111 and 112 may be layers replaced with the first conductive layer 104 of FIG. 9J through a subsequent process. For example, the first source sacrificial layer 111 is made of the same material as the first interlayer insulating layers 120, and the second source sacrificial layer 112 is the same material as the first horizontal sacrificial layers 110 It can be made of. The second conductive layer 105 may be deposited on the first and second source sacrificial layers 111 and 112.

Next, the first stacked structure ST1 may be formed by alternately stacking horizontal sacrificial layers 110 and interlayer insulating layers 120 on the second conductive layer 105.

The first horizontal sacrificial layers 110 may be layers that are replaced with the first gate electrodes 130 through a subsequent process. The first horizontal sacrificial layers 110 may be formed of a material different from the first interlayer insulating layers 120. For example, the first interlayer insulating layer 120 may be made of at least one of silicon oxide and silicon nitride, and the first horizontal sacrificial layers 110 are interlayers selected from silicon, silicon oxide, silicon carbide, and silicon nitride. It may be made of a material different from that of the insulating layer 120. In embodiments, the first interlayer insulating layers 120 may not all have the same thickness. For example, the lowermost and uppermost first interlayer insulating layers 120L and 120U may be formed relatively thin. The thicknesses of the first interlayer insulating layers 120 and the first horizontal sacrificial layers 110 and the number of layers constituting may be variously changed from those shown.

The first and second penetrating sacrificial layers 113 and 114 penetrate through the first stacked structure ST1 at positions corresponding to the first channel structures CH1 and the first isolation region SR1 of FIG. 1, respectively. It can be formed to be. First, through holes corresponding to the first channel structures CH1 and through trenches corresponding to the first isolation region SR1 may be formed. Due to the height of the lower stacked structure GS1, the through holes and the through trenches may not be perpendicular to the top surface of the sidewall substrate 101. The through trenches may be formed to have a lower end on the second conductive layer 105, and the through holes may be formed to extend to the base substrate 101. In example embodiments, the through holes may be formed to recess a part of the substrate 101.

Referring to FIG. 9B, a high-k dielectric layer 190 may be stacked on the first stacked structure ST1.

A high dielectric layer 190 may be stacked on the first stacked structure ST1 on which the first and second through sacrificial layers 113 and 114 are formed. The high dielectric layer 190 may be relatively thicker than the thickness of the first interlayer insulating layers 120 including the uppermost first interlayer insulating layer 120U of the first stacked structure ST1. The high dielectric layer 190 may include a high-k material, and the high-k material means a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). The high-k materials include, for example, aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide ( HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), lanthanum hafnium oxide (LaHfxOy), hafnium aluminum oxide (HfAlxOy), praseodymium oxide (Pr2O3), or combinations thereof. have.

Referring to FIG. 9C, a second stacked structure ST2 may be formed by alternately stacking second interlayer insulating layers 220 and second horizontal sacrificial layers 210 on the high dielectric layer 190. . Next, after partially removing the second stacked structure ST2, a channel through hole CHH may be formed.

The interlayer insulating layers 220 and the second horizontal sacrificial layers 210 may be formed by alternately stacking on the high-k dielectric layer 190, similar to the first stacked structure ST1.

The second horizontal sacrificial layers 210 may be layers that are replaced with the second gate electrodes 230 through a subsequent process. The second horizontal sacrificial layers 210 may be formed of a material different from the second interlayer insulating layers 220. For example, the second interlayer insulating layer 220 may be made of at least one of silicon oxide and silicon nitride, and the second horizontal sacrificial layers 210 are interlayers selected from silicon, silicon oxide, silicon carbide, and silicon nitride. It may be made of a material different from that of the insulating layer 220. In embodiments, the thicknesses of the second interlayer insulating layers 220 may not all be the same. For example, the lowermost second interlayer insulating layer 220L may be formed relatively thin. The thicknesses of the second interlayer insulating layers 220 and the second horizontal sacrificial layers 210 and the number of layers constituting may be variously changed from those shown.

Next, the first through hole CHH performs an etching process at a position corresponding to the second channel structures CH2 of FIG. 1, similar to the first stacked structure GS1, and the second stacked structure ( It may be formed to penetrate through ST2). Since the high dielectric layer 190 and the second interlayer insulating layers 220 contain materials having different etch selectivity, the first through hole CHH may have a lower end formed on the high dielectric layer 190, for example In typical embodiments, the first through hole CHH may be formed to recess a part of the high dielectric layer 190.

Referring to FIG. 9D, a second through hole E1 extending the first through hole CHH may be formed in the high-k dielectric layer 190.

The second through hole E1 may be formed using an etching process of partially removing the high-k dielectric layer 190 exposed by the first through hole CHH. The etching process may be performed by, for example, a wet etching process. The width of the second through hole E1 may be etched so that the width of the first through hole CHH and the width of the first through sacrificial layer 113 are wider. A part of the high dielectric layer 190 may be isotropically etched through the etching process.

Referring to FIG. 9E, after the first through sacrificial layer 113 is removed, the first and second channel structures and the connection channel structures CH1 in the channel through hole CHH extending to the first stacked structure ST1. , CH2, CHM) channel layer 140 and channel insulating layer 150 may be formed, and tunneling layer 142, charge storage layer 143, and blocking layer 144 of FIG. 4 may be formed. Next, channel pads 255 may be formed on the second channel structure CH2.

At the bottom of the first channel structures CH1, the channel layers 140, the tunneling layer 142, the charge storage layer 143, and the blocking layer 144 may be disposed to extend into the substrate 101.

The channel layers 140, the tunneling layer 142, the charge storage layer 143, and the blocking layer 144 use an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process. Thus, it can be formed to have a uniform thickness. The channel insulating layer 150 is formed to fill the inner spaces of the channel layers 140 and may be an insulating material. However, according to embodiments, a space between the channel layers 140 may be filled with a conductive material other than the channel insulating layer 150. As such, in this step, the tunneling layer 142, the charge storage layer 143, the blocking layer 144, and the channel constituting the first and second channel structures, and the connection channel structures CH1, CH2, and CHM The layer 140 and the channel insulating layer 150 may be formed together in a single process, respectively.

Next, a channel pad 255 may be formed on the second channel structures CH2. The channel pad 255 may be made of a conductive material, for example, polycrystalline silicon.

Referring to FIG. 9F, the opening OP may be formed by removing a part of the second stacked structure ST2. Next, the high dielectric layer 190 exposed through the opening OP is removed to expose the top surface of the second penetrating sacrificial layer 114 to the opening OP, and the connection channel structure CHM adjacent to the opening OP is removed. The first tunnel part LT1 concave in the) direction may be formed.

At a position corresponding to the second separation region SR2 of FIG. 1, a part of the second stacked structure ST2 is removed by an etching process so as to penetrate the second stacked structure ST2 to form the opening OP. I can. Since the high dielectric layer 190 and the horizontal sacrificial layers 210 and the second interlayer insulating layers 220 of the second stacked structure ST2 contain materials having different etch selectivity, in the etching process, the opening OP ) May be disposed on the high-k dielectric layer 190. In example embodiments, the lower end of the opening OP may be formed to recess a part of the high dielectric layer 190.

Next, by removing the high-k dielectric layer 190 exposed by the opening OP, the opening OP is extended, and the top surface of the second penetrating sacrificial layer 114 may be exposed to the opening OP. In an embodiment, a top surface of the second through sacrificial layer 114 may be partially recessed.

The high dielectric layer 190 may be removed in the direction of the connection channel structure CHM adjacent to the opening OP to form the first tunnel part LT1. The high-k layer 190 may be removed by, for example, wet etching. In example embodiments, the first tunnel part LT1 may contact the connection channel structure CHM. The length L1 of the first tunnel part LT1 may range from about 50 nm to about 150 nm.

Referring to FIG. 9G, after removing the second through sacrificial layer 114 to extend the opening OP to the first stacked structure ST1, along the sidewalls of the first tunnel part LT1 and the opening OP. Polycrystalline silicon 192a may be formed.

The opening OP may be expanded to penetrate the first stacked structure ST1 by removing the second penetrating sacrificial layers 114 exposed by the opening OP. The second through sacrificial layers 114 may be removed by, for example, wet etching. Next, polycrystalline silicon or the like may be deposited along sidewalls of the first tunnel part LT1 and the opening OP. The polycrystalline silicon 192a may be filled with the first tunnel part LT1 to be deposited so that the high-k dielectric layer 190 or the connection channel structure CHM is not exposed to the opening OP. In example embodiments, in this step, a semiconductor oxide other than polycrystalline silicon 192a may be deposited.

Referring to FIG. 9H, the polycrystalline silicon layer 192a remaining on the sidewalls of the first and second interlayer insulating layers 120 and 220 and the source sacrificial layer 112 in the opening OP is removed to remove the polycrystalline silicon layer ( 192).

The polycrystalline silicon remaining in the openings OP may be removed by an etching process such that the polysilicon layer 192 is disposed only in the first tunnel part LT1 of FIG. 9G. The etching process may be, for example, a wet etching process. The polysilicon layer 192 may be formed to be recessed inward toward the channel structures CH rather than side surfaces of the first and second interlayer insulating layers 120 and 220.

Referring to FIG. 9I, an oxide layer 194 may be formed by selectively oxidizing the polysilicon layer 192.

The oxide layer 194 may be formed by selectively oxidizing the side surface of the polysilicon layer 192 exposed through the opening OP. The oxide layer 194 may cover the entire side of the polysilicon layer 192 adjacent to the opening OP. In example embodiments, the oxide layer 194 may be formed to be recessed inward toward the channel structures CH than the side surfaces of the first and second interlayer insulating layers 120 and 220, but limited thereto. I never do that. In example embodiments, the oxide layer 194 may protrude toward the opening OP rather than side surfaces of the first and second interlayer insulating layers 120 and 200. In example embodiments, by partially oxidizing the polycrystalline silicon layer 192, the oxide layer 194 may cover the entire side surface adjacent to the opening OP of the polycrystalline silicon layer 192. In example embodiments, the polycrystalline silicon layer 192 may be entirely oxidized to form only the oxide layer 194 except for the polycrystalline silicon layer 192 as illustrated in FIGS. 5B and 7B.

9J and 1, after removing the first and second source sacrificial layers 111 and 112 through the opening OP, the first conductive layer 104 may be formed. Next, after the sacrificial layers 110 exposed through the opening OP are removed to form the second tunnel part LT2, the first and second gate electrodes 130 and 230 are formed in the second tunnel part LT2. ) Can be formed. In addition, isolation insulating layers 185 may be formed in the openings OP.

In example embodiments, before removing the first and second source sacrificial layers 111 and 112, a spacer layer is formed on the sidewall of the opening OP to form the first and second horizontal sacrificial layers 110 and 210. Can be protected. After the second source sacrificial layer 112 is first removed through the opening OP, the first source sacrificial layers 111 may be removed. The first and second source sacrificial layers 111 and 112 may be removed by, for example, a wet etching process. During the removal process of the first source sacrificial layers 111, the tunneling layer 142, the charge storage layer 143, and the blocking layer 144 of FIG. 4 are exposed in the region from which the second source sacrificial layer 112 is removed. ) Some can be removed together. After forming the first conductive layer 104 by depositing a conductive material in a region from which the first and second source sacrificial layers 111 and 112 are removed, the spacer layer may be removed. The first conductive layer 104 may directly contact the channel layer 140 in a region from which the tunneling layer 142, the charge storage layer 143, and the blocking layer 144 are removed.

The first and second horizontal sacrificial layers 110 and 210 may be selectively removed from the first and second interlayer insulating layers 120 and 220 using, for example, wet etching. In the wet etching, for example, phosphoric acid (HP) or the like may be used. Accordingly, a plurality of second tunnel parts LT2 may be formed between the first and second interlayer insulating layers 120 and 220, and the first and second channel structures CH A part of the sidewall of) may be exposed. The connection structure CS including the high-k layer 190, the connection channel structure (CHM), the polycrystalline silicon layer 192, and the oxide layer 194 has an oxide layer 194 on an outer surface adjacent to the opening OP. It may be disposed so that it may not be etched by an etching gas in the etching process. Accordingly, a conductive material may be embedded in the plurality of second tunnel portions LT2 formed only between the first and second interlayer insulating layers 120 and 220 to be formed. The gate electrodes 230 may include a metal, polycrystalline silicon, or metal silicide material.

Next, isolation insulating layers 185 may be formed in the openings OP.

The invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Therefore, various types of substitutions, modifications, and changes will be possible by those of ordinary skill in the art within the scope not departing from the technical spirit of the present invention described in the claims, and this also belongs to the scope of the present invention. something to do.

CH: channel structure ST1,ST2: first and second stacked structures
SR: separation area CS: connection structure
101: substrate 104: first conductive layer
105: second conductive layer 113, 114: through sacrificial layer
110,210: horizontal sacrificial layer 120,220: interlayer insulating layer
130,230: gate electrode 140: channel layer
142: tunneling insulating layer 143: charge storage layer
144: blocking insulating layer 150: channel insulating layer
190: high dielectric layer 192: polycrystalline silicon layer
194: oxide layer 185: separation insulating layer
185: separation insulating layer 255: channel pad
290: cell area insulating layer

Claims (10)

Board;
A first stacked structure disposed on the substrate and including first gate electrodes stacked to be spaced apart from each other and first interlayer insulating layers alternately stacked with the first gate electrodes;
A connection structure disposed on the first stacked structure and including a metal oxide layer having a dielectric constant higher than that of the first interlayer insulating layers and a semiconductor oxide layer including semiconductor oxide;
A second stacked structure including second gate electrodes disposed on the connection structure and stacked to be spaced apart from each other, and second interlayer insulating layers alternately stacked with the second gate electrodes;
A channel structure including a first channel structure, a second channel structure, and a connection channel structure penetrating each of the first stacked structure, the second stacked structure, and the connection structure; And
A separation region that penetrates each of the first stacked structure, the second stacked structure, and the connection structure and includes a first separation region, a second separation region, and a third separation region extending in a horizontal direction of the upper surface of the substrate Including,
The connection channel structure has a third width greater than a first width of an upper end of the first channel structure and greater than a second width of a lower end of the second channel structure,
The third isolation region has a sixth width greater than the third width of the connection channel structure, a fourth width at an upper end of the first isolation region, and a fifth width at a lower end of the second isolation region.
The semiconductor device of claim 1, wherein the semiconductor oxide layer contacts the third isolation region.
The method of claim 1,
The connection structure includes a polycrystalline silicon layer between the connection channel structure and the semiconductor oxide layer adjacent to the third isolation region.
The method of claim 3,
The semiconductor oxide layer covers an entire side surface of the polysilicon layer adjacent to the third isolation region.
The method of claim 1,
In the connection structure, the metal oxide layer, the polycrystalline silicon layer, and the semiconductor oxide layer are disposed between the connection channel structure adjacent to the separation region and the separation region in order from the connection channel structure.
The method of claim 1,
The thickness of the metal oxide layer is in the range of 30nm to 150nm semiconductor device.
A first stacked structure disposed on a substrate and including first gate electrodes stacked apart from each other and first interlayer insulating layers alternately stacked with the first gate electrodes;
A connection structure disposed on the first stacked structure;
A second stacked structure including second gate electrodes disposed on the connection structure and stacked to be spaced apart from each other, and second interlayer insulating layers alternately stacked with the second gate electrodes;
A channel structure penetrating the first stacked structure, the second stacked structure, and the connection structure; And
A separation region including a first separation region, a second separation region, and a third separation region passing through each of the first stacked structure, the second stacked structure, and the connection structure,
The connection structure includes a first dielectric layer having a first dielectric constant that is higher than a dielectric constant of the first interlayer insulating layers and the second interlayer insulating layers,
A semiconductor device in which a third width of the third separation area is greater than a first width of the first separation area and a second width of the second separation area.
The method of claim 7,
The connection structure further includes a second dielectric layer in contact with the third isolation region and having a second dielectric constant lower than the first dielectric constant.
The method of claim 8,
The second dielectric layer covers an entire side surface of the third isolation region in contact with the connection structure.
The method of claim 8,
The connection structure includes a polycrystalline silicon layer between the second dielectric layer and the channel structure adjacent to the third isolation region.

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