KR20210080107A - Electroluminescent Display Device - Google Patents

Abstract

According to an embodiment of the present invention, an electroluminescent light emission display device includes a plurality of pixels. Each of the pixels includes: a driving element generating a pixel current; an internal compensation circuit connected to a gate electrode of the driving element, and sampling a voltage between a gate and a source of the driving element such that the pixel current is determined regardless of a threshold voltage shift of the driving element; a light emitting element emitting light by the pixel current; and first and second switch elements connected in parallel between an anode electrode of the light emitting element and a reference voltage input terminal for supplying a reference voltage into the internal compensation circuit. The first and second switch elements has different aspect ratios defined by channel width/channel length. Therefore, the present invention is capable of minimizing a driving defect caused by reverse aging.

Description

Electroluminescent Display Device

The present invention relates to an electroluminescent display device.

In an active matrix type electroluminescent display device, pixels each including a light emitting element and a driving element are arranged in a matrix form, and the luminance of an image implemented in the pixels is adjusted according to a gray level of image data. The driving element controls the pixel current flowing through the light emitting element according to a voltage applied between its gate electrode and its source electrode (hereinafter, referred to as “gate-source voltage”). The amount of light emitted by the light emitting device and the brightness of the screen are determined according to the pixel current.

The threshold voltage of the driving element may be shifted from an initial value in a (+) direction or a (-) direction from an initial value due to environmental factors such as temperature and driving time, and a shift degree of the threshold voltage may be different in pixels. An internal compensation circuit is applied to each pixel in order to minimize the luminance deviation due to the threshold voltage difference of the driving element. The internal compensation circuit serves to prevent the pixel current flowing through the pixel from being affected by the threshold voltage shift.

On the other hand, in the electroluminescent display device, a reverse aging process is performed on pixels to improve lifespan and yield, thereby repairing defects in a light emitting device. However, in the case of an electroluminescent display device to which an internal compensation circuit is applied to each pixel, a specific switch element of a bad pixel (that is, a switch element used to initialize specific nodes of a pixel) is overloaded during reverse aging driving, so that the specific switch element is overloaded. can inflict damage. In this case, since the specific switch element does not perform a proper function despite the reverse aging, there is a problem in that the corresponding pixel does not operate normally.

The present invention provides an electroluminescent display device capable of minimizing a driving defect caused by reverse aging.

An electroluminescent display device according to an embodiment of the present invention includes a plurality of pixels. Each of the pixels may include a driving element generating a pixel current; an internal compensation circuit connected to the gate electrode of the driving device and configured to sample the gate-source voltage of the driving device so that the pixel current is determined regardless of a threshold voltage shift of the driving device; a light emitting element emitting light by the pixel current; and a first switch element and a second switch element connected in parallel between a reference voltage input terminal for supplying a reference voltage to the internal compensation circuit and an anode electrode of the light emitting element. The first switch element and the second switch element have different aspect ratios of transistors defined as channel width/channel length.

The present invention may include two switch elements connected in parallel between the reference voltage input terminal and the anode electrode of the light emitting element in each pixel so that the driving failure caused by the reverse aging is minimized. Since the two switch elements are designed to have different aspect ratios of transistors defined by channel width/channel length, driving failure due to reverse aging can be minimized.

The effect according to the present invention is not limited by the contents exemplified above, and more various effects are included in the present specification.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention.
FIG. 2 is a view showing a pixel array provided in the display panel of FIG. 1 .
3 is an equivalent circuit diagram of one pixel included in the pixel array of FIG. 2 .
4 is a diagram illustrating a current path during reverse aging driving.
FIG. 5 is a waveform diagram showing driving signal signals necessary for the operation of one pixel of FIG. 3 .
6A is an equivalent circuit diagram of a pixel corresponding to the initialization period of FIG. 5 .
6B is an equivalent circuit diagram of a pixel corresponding to the sampling period of FIG. 5 .
FIG. 6C is an equivalent circuit diagram of a pixel corresponding to the holding period of FIG. 5 .
6D is an equivalent circuit diagram of a pixel corresponding to the light emission period of FIG. 5 .
7 is a waveform diagram illustrating potential changes of nodes included in one pixel of FIG. 3 .

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting of', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'next to', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

Although first, second, etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Like reference numerals refer to like elements throughout.

In the present invention, the pixel circuit and the gate driver formed on the substrate of the display panel may be implemented as TFTs having an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. A TFT is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the TFT, carriers start flowing from the source. The drain is an electrode through which carriers exit the TFT. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type TFT (NMOS), the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type TFT, since electrons flow from the source to the drain, the direction of the current flows from the drain to the source. In the case of a p-type TFT (PMOS), since a carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET may be changed according to an applied voltage.

Hereinafter, the gate-on voltage is the voltage of the gate signal at which the TFT can be turned on. The gate off voltage is a voltage at which the TFT can be turned off. In the PMOS, the gate-on voltage is the gate low voltage VGL, and the gate-off voltage is the gate high voltage VGH. In NMOS, the gate-on voltage is VGH and the gate-off voltage is VGL.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component names used in the following description are selected in consideration of the ease of writing the specification, and may be different from the component names of the actual product. In the embodiment of the present invention, the electroluminescent display device will be mainly described.

1 is a block diagram illustrating an electroluminescent display device according to an embodiment of the present invention. FIG. 2 is a view showing a pixel array provided in the display panel of FIG. 1 . 3 is an equivalent circuit diagram of one pixel included in the pixel array of FIG. 2 .

1 to 3 , in the electroluminescent display device according to the present invention, a display panel 10 including pixels PXL and a source driver driving data lines 14 connected to the pixels PXL are provided. (12), the gate driver 13 for driving the gate lines 15 connected to the pixels PXL, the timing controller 11 for controlling the operation timing of the drivers 12 and 13, and the pixels PXL ) and a power supply circuit 14 for generating a power supply voltage required for driving.

In the display panel 10 , a plurality of data lines 14 and a plurality of gate lines 15 cross each other, and pixels PXL are arranged in a matrix form to form a pixel array.

A plurality of horizontal pixel lines L1 to L4 are provided in a pixel array of the display panel 10 as shown in FIG. 2 , and each horizontal pixel line L1 to L4 is horizontally adjacent to each other and gate lines ( 15) includes a plurality of pixels PXL connected in common. Here, each of the horizontal pixel lines L1 to L4 does not mean a physical signal line, but a pixel block corresponding to one line implemented by horizontally adjacent pixels PXL. The pixel array includes a first power line 16 for supplying the reference voltage Vref to the pixels PXL and a second power line 17 for supplying the first power voltage EVDD to the pixels PXL. may be included. Also, the pixels PXL may receive the second power voltage EVSS through the power input terminal.

The gate lines 15 are the first gate lines 15a(1) to 15a(4) to which the first scan signals SCAN1(1) to SCAN1(4) are supplied, and the second scan signal SCAN2(1). ) to the second gate lines 15b(1) to 15b(4) to which SCAN2(4)) are supplied, and third gate lines to which the emission signals EM(1) to EM(4) are supplied. (15c(1) to 15c(4)).

Each of the pixels PXL may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel to implement various colors. A red pixel, a green pixel, a blue pixel, and a white pixel may constitute one unit pixel. Various colors may be implemented in a unit pixel according to emission ratios of a red pixel, a green pixel, a blue pixel, and a white pixel. Each of the pixels PXL has one data line 14 , one first gate line 15a , one second gate line 15b , one third gay line 15c , and a first power line ( 16) and the second power line 17 may be connected.

Each of the pixels PXL includes a driving device that generates a pixel current according to a gate-source voltage, a light emitting device that emits light according to the pixel current, and the driving device so that the pixel current is determined irrespective of a threshold voltage shift of the driving device. It may include an internal compensation circuit for sampling the gate-source voltage of the device, and two switch devices connected in parallel between the reference voltage input terminal and the anode electrode of the light emitting device to minimize driving failure caused by reverse aging. . The two switch elements are designed to have different aspect ratios of transistors defined as channel width/channel length, thereby minimizing driving failure due to reverse aging. That is, since the damage applied during the reverse aging driving is concentrated only on one switch element, the remaining one switch element may receive less damage. The driving failure means a failure in normal driving. Since the switch element that has received less damage during normal driving exhibits its functions, the problem of driving failure is solved.

The source driver 12 converts input image data DATA received from the timing controller 11 in every frame into a data voltage Vdata under the control of the timing controller 11, and then converts the data voltage Vdata to data. supply to lines 14 . The source driver 12 includes a digital-to-analog converter to convert the input image data DATA into a data voltage Vdata, and converts the data voltage Vdata through the data output terminals DCH. print out

The power supply circuit 40 generates a reference voltage Vref, a first power supply voltage EVDD, and a second power supply voltage EVSS. The power circuit 40 supplies the reference voltage Vref to the pixels PXL through the reference voltage input terminal connected to the first power line 16 , and applies the first power voltage EVDD to the second power line 17 . ) to the pixels PXL, and the second power voltage EVSS may be supplied to the pixels PXL through the power input terminal.

The power circuit 40 may lower the reference voltage Vref further during the reverse aging driving for repairing defective light emitting devices compared to the normal driving for reproducing the input image. Also, the power circuit 40 may further increase the second power voltage EVSS during the reverse aging driving compared to the normal driving. The power circuit 40 may lower the reference voltage Vref lower than the second power voltage EVSS during the reverse aging driving.

The gate driver 13 generates a gate signal for driving the pixels PXL. Specifically, the gate driver 13 generates a first gate driver generating first scan signals SCAN1(1) to SCAN1(4) and a second scan signal SCAN2(1) to SCAN2(4). and a second gate driver generating the emission signals EM( 1 ) to EM( 4 ), and a third gate driver generating the emission signals EM( 1 ) to EM( 4 ). The first gate driver applies the first scan signals SCAN1(1) to SCAN1(4) to the first gate lines 15a(1) to 15a(4) under the control of the timing controller 11 in a line sequential manner. is supplied, and the second gate driver lines the second scan signals SCAN2(1) to SCAN2(4) to the second gate lines 15b(1) to 15b(4) under the control of the timing controller 11 . It is supplied in a sequential manner, and the third gate driver supplies the emission signals EM( 1 ) to EM( 4 ) to the third gate lines 15c( 1 ) to 15c( 4 ) in a line-sequential manner.

The timing controller 11 receives digital data DATA of an input image and a timing signal synchronized therewith from a host system (not shown). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The host system may be any one of a television (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The timing controller 11 multiplies the input frame frequency by i to control the operation timing of the drivers 12 and 13 with a frame frequency of the input frame frequency Хi (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase-Alternating Line) scheme.

The timing controller 11 includes a data timing control signal DDC for controlling the operation timing of the source driver 12 based on the timing signals Vsync, Hsync, DE received from the host system, and the gate driver 13 . A gate timing control signal GDC for controlling the operation timing is generated.

The data timing control signal DDC includes a source start pulse, a source sampling clock, and a source output enable signal. The source start pulse controls the sampling start timing of the source driver 12 . The source sampling clock is a clock for shifting the data sampling timing. If the signal transmission interface between the timing controller 11 and the source driver 12 is a mini LVDS (Low Voltage Differential Signaling) interface, the source start pulse and the source sampling clock may be omitted.

The gate timing control signal GDC controls the output timing of the gate signal for the operation of the internal compensation circuit included in each of the pixels PXL, that is, the first and second scan signals and the emission signal.

3 is an equivalent circuit diagram of one pixel included in the pixel array of FIG. 2 . In FIG. 3, SCAN1 is any one of the first scan signals SCAN1(1) to SCAN1(4) of FIG. 2, and SCAN2 is the second scan signals SCAN2(1) to SCAN2(4) of FIG. ), and EM may be any one of the emission signals EM( 1 ) to EM( 4 ) of FIG. 2 . And, in FIG. 3, 15a is any one of the first gate lines 15a(1) to 15a(4) of FIG. 2, and 15b is the second gate lines 15b(1) to 15b( 4)), and 15c may be any one of the third gate lines 15c(1) to 15c(4) of FIG. 2 .

Referring to FIG. 4 , the pixel PXL of the present invention includes a light emitting element EL, a driving element DT, an internal compensation circuit ICS, and first and second switch elements T5 and T6. The driving element DT and the first and second switch elements T5 and T6 may all be implemented as thin film transistors (TFTs). The TFTs T1 to T6 and DT included in the pixel PXL may be implemented as PMOS-type LTPS (Low Temperature Poly Silicon) TFTs, and through this, desired response characteristics may be secured. However, the technical spirit of the present invention is not limited thereto. For example, at least one TFT among the switch TFTs T1 to T4 and the switch elements T5 and T6 is implemented as a PMOS type/NMOS type oxide TFT having good leakage current characteristics when off, and the remaining TFTs They can also be implemented as PMOS-type LTPS TFTs with good response characteristics. Hereinafter, the driving element will be described as the driving TFT DT, and the first and second switch elements will be described as fifth and sixth switch TFTs T5 and T6, respectively.

The light emitting element EL may be an organic light emitting diode including an organic light emitting layer or an inorganic light emitting diode including an inorganic light emitting layer. The light emitting element EL emits light by a pixel current adjusted according to the gate-source voltage Vgs of the driving TFT DT. The anode electrode of the light emitting element EL is connected to the node N4, and the cathode electrode of the light emitting element EL is connected to a power input terminal to which the second power voltage EVSS is applied. An organic compound layer is provided between the anode electrode and the cathode electrode. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) and an electron injection layer (Electron Injection layer, EIL), but is not limited thereto.

The driving TFT DT is a driving element that adjusts the pixel current supplied to the light emitting element EL according to the gate-source voltage Vgs. The driving TFT DT includes a gate electrode connected to the node N2, a source electrode connected to the second power supply line 17, and a drain electrode connected to the node N3. Accordingly, the gate-source voltage Vgs of the driving TFT DT is the voltage applied between the node N2 and the second power line 17 .

The internal compensation circuit ICS is for sampling the gate-source voltage Vgs to compensate for the threshold voltage change of the driving TFT DT, and includes the first to fourth switch TFTs ST1 to ST4 and the storage capacitor. (Cst).

The first switch TFT ST1 is a sampling element for sampling the threshold voltage of the driving element DT by diode-connecting the driving element DT according to the second scan signal SCAN2 . The first switch TFT ST1 is connected between the node N2 and the node N3 and is switched according to the second scan signal SCAN2. The gate electrode of the first switch TFT ST1 is connected to the second gate line 15b to which the second scan signal SCAN2 is applied, the source electrode of the first switch TFT ST1 is connected to the node N3, The drain electrode of the one-switch TFT ST1 is connected to the node N2. Since one electrode of the first switch TFT ST1 is connected to the gate electrode of the driving TFT DT, off current characteristics should be good. Accordingly, the first switch TFT ST1 may be designed to have a dual gate structure to suppress leakage current when it is turned off. In the dual gate structure, the first gate electrode and the second gate electrode are connected to each other to have the same potential, and the channel length becomes longer than that of the single gate structure. When the channel length is increased, the resistance is increased, so that the leakage current is reduced when the channel is turned off, so that the stability of operation can be secured. However, the first switch TFT ST1 may be implemented as a single gate structure, and in this case, the first switch TFT ST1 may be implemented as an oxide TFT.

The second switch TFT T2 is connected between the data line 14 and the node N1, and is switched according to the first scan signal SCAN1. The gate electrode of the second switch TFT ST2 is connected to the first gate line 15a to which the first scan signal SCAN1 is applied, and the source electrode of the second switch TFT ST2 is connected to the data line 14 . and the drain electrode of the second switch TFT ST2 is connected to the node N1.

The third switch TFT T3 is connected between the node N1 and the first power line 16 to which the reference voltage Vref is applied, and is switched according to the emission signal EM. The gate electrode of the third switch TFT T3 is connected to the third gate line 15c to which the emission signal EM is applied, the source electrode of the third switch TFT T3 is connected to the node N1, and the third The drain electrode of the switch TFT T3 is connected to the first power supply line 16 .

The fourth switch TFT T4 is connected between the node N3 and the node N4 and is switched according to the emission signal EM. The gate electrode of the fourth switch TFT T4 is connected to the third gate line 15c to which the emission signal EM is applied, the source electrode of the fourth switch TFT T4 is connected to the node N3, and the fourth The drain electrode of the switch TFT T4 is connected to the node N4.

The fifth and sixth switch TFTs T5 and T6 are first and second switch elements described in the claims, respectively. The fifth and sixth switch TFTs T5 and T6 are connected in parallel between the first power line 16 connected to the reference voltage input terminal and the anode electrode of the light emitting element EL to minimize driving failure caused by reverse aging. connected The fifth and sixth switch TFTs T5 and T6 are designed to have different aspect ratios of transistors defined as channel width/channel length, thereby minimizing driving failure due to reverse aging.

The fifth switch TFT T5 and the sixth switch TFT T6 are connected in parallel between the node N4 and the first power line 16 , and are simultaneously switched according to the second scan signal SCAN2 . Gate electrodes of the fifth and sixth switch TFTs T5 and T6 are connected to the second gate line 15b to which the second scan signal SCAN2 is applied, and the fifth and sixth switch TFTs T5 and T6 are connected to the second gate line 15b. ) are connected to the node N4 , and drain electrodes of the fifth and sixth switch TFTs T5 and T6 are connected to the first power supply line 16 .

The storage capacitor Cst is connected between the node N1 and the node N2.

4 is a diagram illustrating a current path during reverse aging driving.

Referring to FIG. 4 , the reverse aging driving is performed by applying a second power voltage EVSS higher than the reference voltage Vref to the power input terminal connected to the cathode electrode of the light emitting device EL, and the power input terminal and the reference voltage input terminal It is to form a reverse current path (Current Path) between. A current path is formed from the power input terminal toward the reference voltage input terminal. The reverse aging driving may be performed to repair a short defect of the light emitting element EL. During the manufacturing process, the anode electrode and the cathode electrode of the light emitting element EL may be shorted due to a foreign material interposed therebetween. In the reverse aging driving, a reverse voltage is applied between the anode electrode and the cathode electrode of the light emitting element EL to remove foreign substances, thereby improving defective pixels. The reverse aging driving is performed on all pixels of the panel.

During reverse aging driving, as the potential difference between the reference voltage Vref and the second power voltage EVSS increases, it is more effective to remove foreign substances. However, in this case, high drain current stress (hereinafter, HDCS) is applied to the switch element forming the reverse current path, thereby accelerating deterioration of the switch element. The switch element serves to initialize the anode electrode of the light emitting element EL and the gate electrode of the driving TFT DT. When the switch element loses the switching function due to the deterioration, the pixel initialization operation is not performed, and thus the pixel does not operate normally.

The pixel of the present invention includes two switch elements connected in parallel between the reference voltage input terminal and the anode electrode of the light emitting element so that the driving failure caused by the reverse aging is minimized. The two switch elements are fifth and sixth switch TFTs T5 and T6. The fifth and sixth switch TFTs T5 and T6 are connected in parallel between the first power line 16 connected to the reference voltage input terminal and the anode electrode of the light emitting element EL to minimize driving failure caused by reverse aging. connected, and furthermore, the aspect ratio of the transistors are designed to be different from each other.

The gate electrodes of the fifth and sixth switch TFTs T5 and T6 are commonly connected to the second gate line 15b and operate according to the same second scan signal SCAN2, so that the amount of current is large according to the external ratio. A main reverse current path (①) and a sub-reverse current path (②) with a small amount of current are formed. As the aspect ratio of the transistor increases, the on-resistance of the channel decreases and a relatively large current flows. Accordingly, among the fifth and sixth switch TFTs T5 and T6, a switch TFT having a relatively large external aspect ratio forms a main reverse current path (①), and the remaining switch TFTs form a sub reverse current path (②). HDCS due to reverse aging driving increases in proportion to the amount of current. HDCS is concentrated on the switch TFT forming the main reverse current path (①), and the switch TFT forming the sub reverse current path (②) suffers less damage. During normal driving for image reproduction, the switch TFT, which is less damaged, can properly perform the switching function, so that the problem of driving failure can be solved.

For example, as shown in FIG. 4 , when the external ratio of the sixth switch TFT (T6) is designed to be larger than that of the fifth switch TFT (T5), the main reverse current path (①) is the sixth switch TFT during reverse aging driving. (T6), and a sub-reverse current path (②) is made through the fifth switch TFT (T5). Therefore, even if the sixth switch TFT T6 is destroyed due to the HDCS, the fifth switch TFT T5 has little damage and thus can exhibit a normal switching function.

FIG. 5 is a waveform diagram showing driving signal signals necessary for the operation of one pixel of FIG. 3 . 6A is an equivalent circuit diagram of a pixel corresponding to the initialization period of FIG. 5 . 6B is an equivalent circuit diagram of a pixel corresponding to the sampling period of FIG. 5 . FIG. 6C is an equivalent circuit diagram of a pixel corresponding to the holding period of FIG. 5 . 6D is an equivalent circuit diagram of a pixel corresponding to the light emission period of FIG. 5 . And, FIG. 7 is a waveform diagram showing potential changes of nodes included in one pixel of FIG. 3 . In the following description, it is assumed in FIGS. 3 and 4 that the sixth switch TFT T6 loses a function due to the reverse aging driving and only the fifth switch TFT T5 exhibits a normal switching function.

Referring to FIG. 5 , each pixel PXL may be driven in the order of an initialization period (①), a sampling period (②), a holding period (③), and an emission period (④) during normal driving for image reproduction. During the normal driving, the second power voltage EVSS is lower than the reference voltage Vref.

In the initialization period (①), the second scan signal SCAN2 and the emission signal EM are input to the on level (ON), and the first scan signal (SCAN1) is input to the off level (OFF).

In the sampling period (②), the first scan signal SCAN1 and the second scan signal SCAN2 are input to the on level (ON), and the emission signal (EM) is input to the off level (OFF).

In the holding period ③, the first scan signal SCAN1, the second scan signal SCAN2, and the emission signal EM are input to the OFF level OFF.

In the light emission period ④, the emission signal EM is input to the on level ON, and is input to the first scan signal SCAN1 and the second scan signal SCAN2.

The initialization period (①), the sampling period (②), and the holding period (③) may be made within one horizontal period (1H). One horizontal period (1H) is a time allocated for initialization, sampling, and holding operations of one horizontal pixel line in FIG. 2 .

The emission period (④) allocated to the light emission operation of the first horizontal pixel line (eg, L1 in FIG. 2 ) includes the initialization period (①) and the sampling period (②) of the second horizontal pixel line (eg, L2 in FIG. 2 ). ), and the holding section (③) may overlap.

Referring to FIG. 6A , in the initialization period (①), in response to the second scan signal SCAN2 of the on level (ON), the first and fifth switch TFTs T1 and T5 maintain an on state, The third and fourth switch TFTs T3 and T4 maintain an off state in response to the emission signal EM of the level ON. Then, in response to the first scan signal SCAN1 of the off level OFF, the second switch TFT T2 maintains an off state. As a result, all of the nodes N1 , N2 , N3 , and N4 have reference voltages. It is initialized to (Vref). This initialization operation is to secure internal compensation and reliability of driving by resetting the potentials of the nodes N1, N2, N3, and N4 to a constant value prior to the sampling operation.

The reference voltage Vref is a voltage lower than the first power voltage EVDD and is set near the second power voltage EVSS to be lower than the operating point voltage Voled of the light emitting device EL. Accordingly, in the initialization period (①), the reference voltage Vref applied to the node N4 is lower than the operating point voltage Voled of the light emitting element EL, so that the light emitting element EL does not emit light.

As a result, as shown in FIG. 7 and Table 1, in the initialization period ①, the potentials of the first to fourth nodes N1, N2, N3, and N4 are set to the reference voltage Vref.

Referring to FIG. 6B , in the sampling period (②), the first, second and fifth switch TFTs T1 and T2 in response to the first and second scan signals SCAN1 and SCAN2 of the on level ON. , T5 maintains an on state, and the third and fourth switch TFTs T3 and T4 maintain an off state in response to the emission signal EM of the off level OFF.

Since the gate-source voltage (Vgs) of the driving TFT (DT), that is, “EVDD-Vref”, set in the initialization period (①) is greater than the threshold voltage (Vth) of the driving TFT (DT), during the sampling period (②) A pixel current flows through the driving TFT (DT). At this time, the gate electrode and the drain electrode of the driving TFT (DT) are short-circuited by the first switch TFT (T1) is turned on, so that the driving TFT (DT) is diode-connected, and the fourth switch TFT (T4) By turning off the pixel current flows along the diode wiring path. The threshold voltage Vth of the driving TFT DT is sampled by this pixel current and stored in the nodes N2 and N3.

During the sampling period (②), the current flow between the node N1 and the first power line 16 is cut off by turning off the third switch TFT ST3. At this time, the data voltage Vdata output to the output channel DCH of the source driver is applied to the node N1 through the data line 14 and the second switch TFT T2.

During the sampling period (②), the reference voltage Vref is continuously applied to the node N4 by turning on the fifth switch TFT ST5, and the light emitting element EL maintains a non-emission state.

As a result, as shown in FIG. 7 and Table 1, in the sampling period (②), the potential of the node N1 is set to the data voltage (Vdata), the potentials of the nodes N2 and N3 are set to “EVDD-1Vthl”, and the node N4 The potential of is set as the reference voltage Vref.

Referring to FIG. 6C , in the holding period (③), the first, second, and fifth switch TFTs T1, T2, by the first and second scan signals SCAN1 and SCAN2 of the OFF level (OFF) T5) remains off. In addition, the third and fourth switch TFTs T3 and T4 maintain an OFF state by the emission signal EM of the OFF level.

In the holding period (③), all of the first to fourth nodes N1, N2, N3, and N4 are floated by turning off the first to fifth switch TFTs T1 to T5. Since the first to fourth nodes N1, N2, N3, and N4 are connected to the first and second gate lines 15a and 15b through parasitic capacitors, the first and second scan signals SCAN1 ,SCAN2 may also change potentials of the first to fourth nodes N1 , N2 , N3 , and N4 when inverted from the on level (ON) to the off level (OFF). In other words, as the first and second scan signals SCAN1 and SCAN2 increase from the on level (ON) to the off level (OFF), the first to fourth nodes N1 , N2 , N3 , and N4 The potential may also rise.

As a result, in the holding section ③ as shown in FIG. 7 and Table 1, the potential of the node N1 rises to “Vdata+α”, the potential of the node N2 rises to “VDD-1Vthl +β”, and the potential of the node N3 The potential may rise to “VDD-1Vthl +γ”, and the potential of the node N4 may rise to “Vref +δ”. Each of the potential increases α, β, γ, and δ of the first to fourth nodes N1, N2, N3, and N4 corresponds to the first to fourth nodes N1, N2, N3, N4 and the first and It may vary depending on the parasitic capacitance between the second gate lines 15a and 15b. Meanwhile, when the parasitic capacitance between the first to fourth nodes N1, N2, N3, and N4 and the first and second gate lines 15a and 15b is small, the first to fourth nodes N1 and N2 Each potential rise (α, β, γ, δ) of ,N3,N4) can be neglected. In the following light emission section (④), the electric potential increase (α, β, γ, δ) is ignored and described. In the holding period ③, the potential of the fourth node, “Vref +δ”, is lower than the operating point voltage Voled of the light emitting device EL, so that the light emitting device EL does not emit light.

OFF) 타이밍을 에미션 신호(EM)의 반전(OFF-

ON) 타이밍보다 앞당겨 동작의 안정성을 높이기 위한 것이다. 제1 및 제2 스캔 신호들(SCAN1,SCAN2)의 반전(ON-

OFF) 타이밍과 에미션 신호(EM)의 반전(OFF-

ON) 타이밍이 서로 같거나, 또는 제1 및 제2 스캔 신호들(SCAN1,SCAN2)의 반전(ON-

OFF) 타이밍이 에미션 신호(EM)의 반전(OFF-

ON) 타이밍보다 늦어지면, 상기 문턱전압 샘플링 동작이 불안정하게 되므로, 홀딩 구간(③)은 이를 방지하기 위해 마련된 것이다. 다만, 홀딩 구간(③)은 모델 및 스펙에 따라 생략될 수 있다.On the other hand, the holding period (③) is an inversion (ON-) of the first and second scan signals SCAN1 and SCAN2.

OFF) Timing of the emission signal (EM) is inverted (OFF-

ON) This is to improve the stability of the operation by earlier than the timing. Inversion of the first and second scan signals SCAN1 and SCAN2 (ON-

OFF) Timing and inversion of the emission signal (EM) (OFF-

ON) timing is the same, or inversion of the first and second scan signals SCAN1 and SCAN2 (ON-

OFF) Timing is the inversion of the emission signal (EM) (OFF-

When the ON) timing is delayed, the threshold voltage sampling operation becomes unstable, so the holding period (③) is provided to prevent this. However, the holding section (③) may be omitted depending on the model and specifications.

Referring to FIG. 6D , in the light emission period ④, the first, second and fifth switch TFTs T1 and T2 in response to the first and second scan signals SCAN1 and SCAN2 of the OFF level ,T5) remains off. In addition, the third and fourth switch TFTs T3 and T4 maintain an on state in response to the on-level emission signal EM.

In the light emission period ④, the reference voltage Vref is applied to the node N1 by the turn-on of the third switch TFT T3, so that the potential of the node N1 is changed from the data voltage Vdata in the immediately preceding compensation period B It is lowered to the reference voltage Vref.

During the light emission period ④, the node N2 is floated and coupled to the node N1 through the storage capacitor Cst. Accordingly, the change in potential of the node N1 during the light emitting period (4) is reflected in the node N2. As a result, the potential of the node N2 during the light-emitting period (④) is lowered by "Vdata-Vref" compared to "EVDD- lVthl" in the previous holding period (③). In other words, the potential of the node N2 during the light emission period ④ becomes "EVDD- lVthl -Vdata+Vref" as shown in FIG. 7 and Table 1 .

Through this, the Vgs voltage of the driving TFT DT capable of compensating for the change in the threshold voltage Vth of the driving TFT DT is set, and the driving TFT DT has a voltage corresponding to the Vgs voltage as shown in Equation 1 below. A pixel current Ioled flows.

The potential of the nodes N3 and N4 is increased to the operating point voltage Voled of the light emitting element EL by the pixel current Ioled, so that the light emitting element EL conducts. As a result, the light emitting element EL emits light by the pixel current Ioled.

[Equation 1]

Here, K is a constant value determined by the mobility, channel ratio, parasitic capacitance, etc. of the driving TFT DT, and Vth is the threshold voltage of the driving TFT DT.

As can be seen from Equation 1, the pixel current Ioled of the light emitting element EL is not affected by the high potential power voltage EVDD as well as the threshold voltage Vth of the driving TFT DT. In the embodiment of the present invention, since the pixel current Ioled of the light emitting device EL is not affected by the high potential power voltage EVDD, the second power supply line 17 is not designed with a low resistance or the second power supply line 17 ) in the form of a mesh, the luminance and color of pixels can be uniformed across the screen. Accordingly, the present invention is very advantageous in realizing a uniform image quality in a high-resolution panel having a small pixel size. In addition, the present invention has the effect of providing a panel of a large screen with improved luminance and image quality.

Section ① Section ② Section ③ Section ④ N1 Vref Vdata Vdata +α Vref N2 Vref EVDD-lVthl EVDD-lVthl +β EVDD-lVthl-Vdata+Vref N3 Vref EVDD-lVthl EVDD-lVthl +γ Voled N4 Vref Vref Vref +δ Voled

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 11: timing controller
12: source driver 13: gate driver

Claims (8)

In the electroluminescent display device provided with a plurality of pixels,
Each of the pixels,
a driving element for generating a pixel current;
an internal compensation circuit connected to the gate electrode of the driving device and sampling the gate-source voltage of the driving device so that the pixel current is determined regardless of a shift in threshold voltage of the driving device;
a light emitting element emitting light by the pixel current; and
a first switch element and a second switch element connected in parallel between a reference voltage input terminal for supplying a reference voltage to the internal compensation circuit and the anode electrode of the light emitting element;
The first switch element and the second switch element have different aspect ratios of transistors defined by a channel width/channel length. The method of claim 1,
The gate electrode of the first switch element and the gate electrode of the second switch element are connected to the same gate line. The method of claim 1,
The first switch element and the second switch element operate according to the same gate signal. The method of claim 1,
In normal driving of applying a power voltage lower than the reference voltage to a power input terminal connected to the cathode electrode of the light emitting device,
The internal compensation circuit includes a sampling element for sampling a threshold voltage of the driving element by diode-connecting the driving element according to a gate signal,
The first switch element and the second switch element operate according to the gate signal so that the anode electrode of the light emitting element and the gate electrode of the driving element are initialized to the reference voltage. The method of claim 1,
In the reverse aging driving of forming a reverse current path between the power input terminal and the reference voltage input terminal by applying a power voltage higher than the reference voltage to the power input terminal connected to the cathode electrode of the light emitting device,
The high drain current stress applied to the first switch element and the high drain current stress applied to the second switch element are different from each other. 6. The method of claim 5,
An electroluminescent display device in which the high drain current stress is greater in a switch element having a relatively large external ratio of the transistor among the first switch element and the second switch element. 6. The method of claim 5,
An electroluminescent display device in which the high-drain current stress is smaller in a switch element having a relatively small aspect ratio of the transistor among the first switch element and the second switch element. 8. The method according to claim 6 or 7,
The first switch element and the second switch element are deteriorated in proportion to the high-drain current stress.

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