KR101907959B1 - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an organic light emitting diode display, comprising: a first capacitor connected between a first node and a second node; A second capacitor connected between the second node and the fourth node; An organic light emitting diode including a cathode connected to a low potential power supply voltage source and an anode connected to the fourth node; A driving TFT for adjusting a current flowing between the high potential power supply voltage source and the organic light emitting diode according to the voltage of the gate electrode connected to the second node; A first switch TFT for switching a current path between a data line to which a data voltage is supplied and the first node; A second switch TFT for switching a current path between a reference voltage source generating a reference voltage and the first node; A third switch TFT for switching a current path between the second node and a third node connected to a drain electrode of the driving TFT; A fourth switch TFT for switching a current path between the third node and the fourth node; And a fifth switch TFT for switching a current path between the reference voltage source and the fourth node.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display.

Since the organic light emitting diode display device is a self light emitting device, a separate light source such as a backlight is not required. Therefore, the organic light emitting diode display device is advantageous in terms of thinness, and has a higher contrast ratio and response speed than a liquid crystal display And it has an advantage over a liquid crystal display device in power consumption because of its high efficiency. In order to expand the market of organic light emitting diode display devices, many problems still remain to be solved, such as large-screen mass production technology, expensive manufacturing cost, and life span.

The organic light emitting diode display device has characteristics such as a threshold voltage (Vth) and a mobility of a driving thin film transistor (hereinafter, referred to as " TFT "), When it is not uniform, the quality of the image is deteriorated on the large screen. For example, in an organic light emitting diode display device, a residual image can be seen in a display image due to a low threshold voltage and a non-uniformity in the mobility of the driving TFT.

The present invention provides an organic light emitting diode display device capable of improving image quality by compensating a threshold voltage and a mobility of a driving TFT.

The organic light emitting diode display of the present invention includes: a first capacitor connected between a first node and a second node; A second capacitor connected between the second node and the fourth node; An organic light emitting diode including a cathode connected to a low potential power supply voltage source and an anode connected to the fourth node; A driving TFT for adjusting a current flowing between the high potential power supply voltage source and the organic light emitting diode according to the voltage of the gate electrode connected to the second node; A first switch TFT for switching a current path between a data line to which a data voltage is supplied and the first node; A second switch TFT for switching a current path between a reference voltage source generating a reference voltage and the first node; A third switch TFT for switching a current path between the second node and a third node connected to a drain electrode of the driving TFT; A fourth switch TFT for switching a current path between the third node and the fourth node; And a fifth switch TFT for switching a current path between the reference voltage source and the fourth node.

The third and fifth switch TFTs are turned off in response to the selection pulse of the first logic voltage during the first to third times, while being turned off at the fourth time.

The second and fourth switch TFTs are turned off in response to the emission control pulse of the second logic voltage for the second and third times while being turned on at the first and fourth times.

The first switch TFT is turned off in response to a scan pulse of the first logic voltage during the third time, while being turned off during the first, second and fourth times.

The present invention senses the threshold voltage of the driving TFT at the second node of the pixel circuit and drives the voltage of the fourth node which depends on the mobility of the driving TFT by using a capacitor formed between the second node and the fourth node And reflected on the gate voltage of the TFT. As a result, the present invention can improve the image quality of the organic light emitting diode display device by compensating the threshold voltage and the mobility of the driving TFT.

1 is a block diagram showing an organic light emitting diode display device according to an embodiment of the present invention.
2 is a circuit diagram showing a pixel circuit of an organic light emitting diode display device according to an embodiment of the present invention.
3 is a waveform diagram showing a driving waveform of the pixel circuit shown in Fig.
4A to 4D are diagrams showing the operation of the pixel circuit shown in FIG. 2 in a step-by-step manner.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 to 3, the organic light emitting diode display of the present invention includes a display panel 100 in which pixels are arranged in a matrix, a data driver 102 for supplying a data voltage to the data lines 11, A scan driver 104 for sequentially supplying a selection pulse SEN, a scan pulse SCAN and a light emission control pulse EM to the scan lines 12 crossing the data lines 11, 102 and a timing controller 106 for controlling the scan driver 104.

The scan lines 12 include a first scan line group including first scan lines 12a to which a selection pulse SEN is sequentially supplied and a second scan line group including second scan lines 12b to which a scan pulse SCAN is sequentially supplied , And a third scan line group including third scan lines 12c to which emission control pulses EN are sequentially supplied.

The data driver 102 converts the digital video data RGB input from the timing controller 106 into a gamma compensation voltage and supplies the gamma compensation voltage to the data lines 111. The scan driver 104 applies a selection pulse SEN of a low logic voltage, a scan pulse SCAND of a low logic voltage, and a light emission control pulse of a high logic voltage EM) to the scan lines 12 in sequence.

Each of the pixels of the display panel 100 includes a pixel circuit as shown in Fig. Each of the pixels includes red, green, and blue subpixels including a pixel circuit as shown in FIG. 2 for color implementation, and may further include a white subpixel or other color subpixels.

The timing controller 106 transfers digital video data (RGB) received from an external host system (not shown) to the data driver 102. The timing controller 106 controls the data driver (not shown) using timing signals received from the host system such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock CLK And timing control signals (SDC, GDC) for controlling the operation timings of the scan driver (102) and the scan driver (104). The host system may be various information devices such as a navigation system, a set-top box, a DVD player, a Blu-ray player, a computer, a home theater system, a broadcast receiver, a phone system, or a home appliance system.

The pixel circuit formed in each of the pixels of the display panel 100 includes a plurality of TFTs M1 to M5 and DT, capacitors Cst1 and Cst2 and an organic light emitting diode OLED as shown in FIG.

The TFTs M1 to M5 and DT may be implemented as a p-type MOSFET (metal-oxide-semiconductor field-effect transistor) as shown in FIG. The TFTs M1 to M5 and DT are not limited to p-type MOSFETs but may be implemented as n-type MOSFETs and CMOS (complementary metal semiconductor) TFTs. The pulse voltage of the selection pulse SEN, the scan pulse SCAN, and the emission control pulse EM in the drive waveform of FIG. 3 when the TFTs M1 to M5 and DT are implemented as n type MOSFETs or CMOS TFTs Can be inverted. In FIG. 2, the third and the third switching TFTs M3a and M3b are combined with two TFTs for enhancing the leakage current blocking effect. If one of the TFTs M3a and M3b has a larger channel ratio, the other one can be omitted.

The first switch TFT M1 forms a current path between the data line 11 and the first node n1 in response to the scan pulse SCAN. The first switch TFT M1 includes a source electrode connected to the data line 11, a drain electrode connected to the first node n1, and a gate electrode connected to the second scan line 12b to which the scan pulse SCAN is applied . The first node n1 is a node formed between the drain electrode of the first switch TFT M1, the drain electrode of the second switch TFT M2, and one electrode of the first capacitor Cst1.

The second switch TFT M2 switches the current path between the data line 11 and the reference voltage source according to the voltage of the third scan line 12c. The reference voltage source generates the reference voltage Vref. The reference voltage Vref is a voltage lower than the threshold voltage of the organic light emitting diode, and can be set to a voltage of 2 V or less, the difference between the reference voltage Vref and the low potential power supply voltage ELVSS or GND. The second switch TFT M2 is turned on when the voltage of the third scan line 12c is a low logic voltage to supply the reference voltage Vref to the first node n1. The second switch TFT M2 is turned off when a discharge control pulse EM of a high logic voltage is applied to the third scan line 12c to turn on the first switch n1 Disconnect the current path. The second switch TFT M2 includes a source electrode connected to the reference voltage source, a drain electrode connected to the first node n1, and a gate electrode connected to the third scan line 12c to which the emission control pulse EM is applied .

The 3a and 3b switch TFTs M3a and M3b switch the current path between the second node n2 and the third node in response to the voltage of the first scan line 12a. The third and the third switching TFTs M3a and M3b are turned on simultaneously when a selection pulse SEN of a low logic voltage is applied to the first scan line 12a to turn on the second node n2, (n3) to connect the gate electrode of the driving TFT DT to the drain electrode, thereby operating the driving TFT DT as a diode. On the other hand, the third and the third switching TFTs M3a and M3b are turned off when the voltage of the first scan line 12a is a high logic voltage so that the potential difference between the second node n2 and the third node n3 Of the current path. The third switch TFT M3a includes a source electrode connected to the second node n2, a drain electrode connected to the source electrode of the third switching TFT M3b, and a first scan line 12a to which the selection pulse SEN is applied. And a gate electrode connected to the gate electrode. The third switching TFT M3b includes a source electrode connected to the drain electrode of the third TFT M3a, a drain electrode connected to the third node n3, and a gate electrode connected to the first scan line 12a. The second node n2 is connected between the source electrode of the third TFT M3a, the other electrode of the first capacitor Cst1, one electrode of the second capacitor Cst2, and the gate electrode of the driving TFT DT, to be. The third node n3 is a node formed between the drain electrode of the driving TFT DT, the drain electrode of the thirdb TFT M3b, and the source electrode of the fourth switch TFT M4.

One TFT among the third and thirdb switch TFTs M3a and M3b may be omitted. When the third switching TFT M3b is omitted, the source electrode of the third switching TFT M3a is connected to the second node n2, and the drain electrode thereof is connected to the third node n3. The gate electrode of the third switching TFT M3b is connected to the first scan line 12a.

The fourth switch TFT M4 switches the current path between the third node n3 and the fourth node n4 in response to the voltage of the third scan line 12c. The fourth switch TFT M4 is turned on when the voltage of the third scan line 12c is a low logic voltage to connect the third node n3 to the fourth node n4, The electrode is connected to the anode of the organic light emitting diode (OLED). On the other hand, the fourth switch TFT M4 is turned off when a discharge control pulse EM of a high logic voltage is applied to the third scan line 12c to turn on the third node n3 and the fourth node n4, Thereby blocking the current path. The fourth switch TFT M4 includes a source electrode connected to the third node n3, a drain electrode connected to the fourth node n4, and a gate connected to the third scan line 12c to which the discharge control pulse EM is applied. Electrode. The fourth node n4 is connected between the drain electrode of the fourth switch TFT M4, the drain electrode of the fifth switch TFT M5, the other electrode of the second capacitor Cst2, and the anode of the organic light emitting diode OLED Lt; / RTI >

The fifth switch TFT M5 switches the current path between the reference voltage source and the fourth node n4 in response to the voltage of the first scan line 12a. The fifth switch TFT M5 is turned on when the select pulse SEN of the low logic voltage is applied to the first scan line 12a to connect the reference voltage source to the fourth node n4 to generate the reference voltage Vref, To the fourth node (n4). On the other hand, the fourth switch TFT M4 is turned off when the voltage of the first scan line 12a is at the high logic voltage to cut off the current path between the reference voltage source and the fourth node n4. The fifth switch TFT M5 includes a source electrode connected to the reference voltage source, a drain electrode connected to the fourth node n4, and a gate electrode connected to the first scan line 12a to which the selection pulse SEN is applied.

The driving TFT DT adjusts the channel current Ids according to the voltage of the second node n2, that is, the gate voltage, and adjusts the current of the organic light emitting diode OLED according to the data voltage. The driving TFT DT includes a source electrode connected to the high potential power source, a drain electrode connected to the third node n3, and a gate electrode connected to the second node n2. The high-potential power supply voltage source supplies the high-potential power supply voltage ELVDD of 5 V or more to the source electrode of the driving TFT DT.

The first capacitor Cst1 charges the gate voltage of the driving TFT DT to sample the threshold voltage Vth of the driving TFT DT and charges and stores the data voltage. The first capacitor Cst1 includes one electrode connected to the first node n1 and the other electrode connected to the second node n2.

The second capacitor Cst2 adds to the second node n2 a voltage which varies depending on the mobility difference of the driving TFT DT to compensate the mobility of the driving TFT DT. The second capacitor Cst2 includes one electrode connected to the second node n2 and the other electrode connected to the fourth node n4.

The organic light emitting diode OLED emits light according to the current supplied through the driving TFT DT when the difference between the anode voltage and the cathode voltage is equal to or greater than the threshold voltage of the organic light emitting diode OLED. The organic light emitting diode OLED includes an anode connected to the fourth node n4 and a cathode connected to the low potential power source. The low potential power source supplies a low potential power supply voltage (ELVSS) of 0 V or less or a ground voltage to the cathode of the organic light emitting diode (OLED). A multilayer organic compound layer is formed between the anode and the cathode of the organic light emitting diode (OLED). The organic compound layer may include a hole injection layer (HIL) connected to the anode, a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) Layer (Electron Injection layer, EIL).

3, the time t1 is an initial time for initializing the anode voltage of the organic light emitting diode OLED, a second node n2 connected to the gate electrode of the driving TFT DT, to be. The time t2 is a Vth sensing time for sensing the threshold voltage Vth of the driving TFT DT and storing it in the capacitors Cst1 and Cst2. The time t3 is a data writing time for supplying the data voltage n to the first node n1 to drive the driving TFT DT with the data voltage whose threshold voltage of the driving TFT DT is compensated. t4 is mobility compensation and emission time (mu compensation & emission time) in which the mobility of the driving TFT DT is compensated and the organic light emitting diode (OLED) emits light.

In Fig. 3, "Vs" is the source voltage of the driving TFT DT. "Vg" is the gate voltage of the driving TFT DT, that is, the voltage of the second node n2.

FIGS. 4A to 4D are diagrams illustrating the operation of a pixel circuit according to an exemplary embodiment of the present invention. The operation of this pixel circuit will be described with reference to the waveform diagram of Fig. In Figs. 4A to 4D, the TFTs indicated by dotted circles mean turned-on TFTs.

Referring to FIG. 4A, a logic voltage selection pulse SEN starts to be applied to the first scan line 12a at the start time t1. The selection pulse SEN is applied to the first scan line 12a from the start time of the time t1 to the end time of the time t3. During t1, the voltage of the second scan line 12b maintains a high logic voltage and the voltage of the third scan line 12c maintains a low logic voltage.

the second and fourth switch TFTs M2 and M4 are turned on by the low logic voltage of the third scan line 12c and the third and fourth switch TFTs M3a, M3b and M5 Is turned on by the select pulse SEN of the low logic voltage. The driving TFT DT is turned on since the voltage of the second node n2 is lowered to the reference voltage Vref at time t1 to form a current path toward the reference voltage source. The first switch TFT Ml remains off for the time tl.

During t1, a current path is formed in which the first node n1, the fourth node n4, the third node n3, and the second node n2 are connected to the reference voltage source as shown by the solid line arrow in Fig. 4A . Therefore, the first to fourth nodes n1 to n4 are discharged to the reference voltage Vref and initialized. The reference voltage Vref is a voltage lower than the threshold voltage of the organic light emitting diode OLED as described above. The organic light emitting diode OLED does not emit light because the voltage of the anode connected to the fourth node n4 is lowered to the reference voltage Vref.

Table 1 below shows the source voltage (Vs) of the first node n1, the second node n2, and the driver TFT DT during the time t1.

t1 hour n1 n2 Source node of DT Node voltage Vref Vg = Vref Vs = ELVDD action n1 initialization Initialize gate node of DT Fixed with constant voltage ELVDD

Referring to FIG. 4B, the emission control pulse EM of the high voltage starts to be applied to the third scan line 12c at the start of the time t2. The emission control pulse EM is applied to the third scan line 12c from the start time of the time t2 to the start time of the time t4. During t2, the voltage of the first scan line 12a maintains the low logic voltage by the selection pulse SEN while the voltage of the second scan line 12b maintains the high logic voltage.

During the time t2, the second and fourth switch TFTs M2 and M4 are turned off because the voltage of the third scan line 12c is inverted to a high logic voltage. During the time t2, the 3a, 3b and the fifth switch TFTs M3a, M3b, M5 are kept on by the selection pulse SEN of the low logic voltage. The first switch TFT (M1) remains off for the time t2.

the gate electrode and the drain electrode of the driving TFT DT are connected through the third and the third switching TFTs M3a and M3b and the voltage of the second node n2 is connected to the driving TFT The threshold voltage Vth of the driving TFT DT is sensed at the second node n2 by changing to ELVDD - | Vth | immediately before the data signal DT is turned off. The threshold voltage Vth of the driving TFT DT is a negative voltage when the driving TFT DT is implemented as a p-type MOSFET. The threshold voltage Vth of the driving TFT DT sensed by the second node n2 is stored in the first and second capacitors Cst1 and Cst2. The organic light emitting diode OLED does not emit light because the voltage of the anode connected to the fourth node n4 maintains the reference voltage Vref for the time t2.

Table 2 below shows the source voltage (Vs) of the first node n1, the second node n2, and the driver TFT DT for t2 time.

t2 hour n1 n2 Source node of DT Node voltage Vref Vref? Vref Vs = ELVDD action - Due to the turn-off of M5, the gate voltage of the DT driving TFT DT increases to ELVDD - | Vth | -

Referring to FIG. 4C, the scan pulse SCAN of the low logic voltage starts to be applied to the second scan line 12b at the start time of the time t3. The scan pulse SCAN is applied to the second scan line 12b for t3 time. the voltage of the first scan line 12a maintains the low logic voltage by the selection pulse SEN and the voltage of the third scan line 12c maintains the high logic voltage by the emission control pulse EM .

During t3, the first switch TFT M1 is turned on by the low logic voltage applied to the second scan line 12b. During t3, the 3a, 3b and fifth switch TFTs M3a, M3b, M5 are kept on by the selection pulse SEN of the low logic voltage. The second and fourth switch TFTs M2 and M4 are kept off by the emission control pulse EM of the high logic voltage for t3 time.

"만큼 상승한다. t3 시간과 t4 시간 사이에는 제2 노드의 전압이 포화될 때까지 일정한 지연시간이 설정될 수 있다.During t3, a current path as shown by the solid line arrow in Fig. 4C is formed and the data voltage Vdata supplied through the data line 11 is supplied to the first node n1 through the first switch TFT M1. The voltage of the first node n1 changes to the data voltage Vdata. The second node n2 is coupled to the first node n1 through the first capacitor Cst1 storing the threshold voltage of the driving TFT DT. As a result, the data voltage Vdata boosts the voltage of the second node n2 and is distributed to the voltages of the capacitors Cst1 and Cst2 connected to the second node n2. Therefore, the voltage of the second node n2 is set to "

Between t3 and t4, a constant delay time can be set until the voltage of the second node is saturated.

t3 hour n1 n2 Source node of DT Node voltage Vref? Vdata

Vs = ELVDD action Apply Vdata to n1
Vdata is boosted and delivered to n2 and distributed to Cst1 and Cst2. -

Referring to FIG. 4D, the voltage of the third scan line 12c is inverted to a low logic voltage at the start time of t4 time. During a period of t4, the second and fourth switch TFTs M2 and M4 are turned on in response to the low logic voltage of the third scan line 12c. the first switch TFT M1 is turned off by the high logic voltage of the second scan line 12b for t4 hours and the third, third and fifth switch TFTs M3a, M3b and M5 are turned off by the first scan And is turned off by the high logic voltage on line 12a.

During a period of t4, the voltage of the first node n1 is changed to the reference voltage Vref via the second switch TFT M2. The organic light emitting diode OLED emits light by the current supplied through the drive TFT DT and the fourth switch TFT M4 for t4 hours. The anode voltage of the organic light emitting diode OLED is changed according to the mobility μ of the driving TFT DT when the organic light emitting diode OLED emits light. The anode of the organic light emitting diode OLED is coupled to the second node n2 connected to the gate electrode of the driving TFT DT through the second capacitor Cst2. Therefore, the anode voltage of the organic light emitting diode OLED, which varies with the mobility deviation DELTA mu of the driving TFT DT as shown in Table 4, is reflected in the gate voltage of the driving TFT DT, (mu) is compensated. The voltage of the second node n2 is adjusted by Vth + Vdata -? 占 for t4 time.

t3 hour n1 n2 Source node of DT Node voltage Vdata? Vref

Vs = ELVDD action -
The anode voltage of the OLED changes according to μ of DT when the OLED emits light, and is reflected in the gate voltage of DT DT and M5 are turned on and a current path is formed between ELVDD and ELVSS so that the OLED emits light

, Vanode는 유기 발광 다이오드(OLED)의 애노드 전압이다. In Table 4,

, And Vanode is the anode voltage of the organic light emitting diode (OLED).

When the organic light emitting diode OLED emits light, the gate-source voltage Vsg of the driving TFT DT is affected by the ELVDD as shown in the following equation (1). As a result, the current I _OLED of the organic light emitting diode OLED is independent of ELVDD and Vth and is not affected by the high potential power supply voltage ELVDD and the threshold voltage Vth of the driving TFT DT, And compensates for the mobility deviation DELTA mu of the driving TFT DT by DELTA V *.

The data charging characteristics of the pixel circuit and the mobility compensation of the driving TFT DT are in a tradeoff relationship according to the ratio of the first and second capacitors Cst1 and Cst2.

Here, 'k' is a constant value defined by the product of the mobility μ of the driving TFT DT and the parasitic capacitance Cox, 'L' is the channel length of the driving TFT DT, 'W' (DT).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

100: display panel 102: data driver
104: scan driver 106: timing controller
OLED: Organic light emitting diode Cst1, Cst2: Capacitor
DT: driving TFTs M1 to M5: switch TFT

Claims (5)

A first capacitor coupled between the first node and the second node;
A second capacitor connected between the second node and the fourth node;
An organic light emitting diode including a cathode connected to a low potential power supply voltage source and an anode connected to the fourth node;
A driving TFT for adjusting a current flowing between the high potential power supply voltage source and the organic light emitting diode according to the voltage of the gate electrode connected to the second node;
A first switch TFT for switching a current path between a data line to which a data voltage is supplied and the first node;
A second switch TFT for switching a current path between a reference voltage source generating a reference voltage and the first node;
A third switch TFT for switching a current path between the second node and a third node connected to a drain electrode of the driving TFT;
A fourth switch TFT for switching a current path between the third node and the fourth node; And
And a fifth switch TFT for switching a current path between the reference voltage source and the fourth node,
The third and fifth switch TFTs are turned on in response to the selection pulse of the first logic voltage for the first to third times while being turned off at the fourth time,
The second and fourth switch TFTs are turned off at the first and fourth times while being turned off in response to the light emission control pulse of the second logic voltage for the second and third times,
Wherein the first switch TFT is turned on in response to a scan pulse of the first logic voltage for the third time while being turned off for the first, second and fourth times. Display device. The method according to claim 1,
Wherein the first switch TFT includes a source electrode connected to the data line, a drain electrode connected to the first node, and a gate electrode connected to the second scan line to which the scan pulse is applied,
The second switch TFT includes a source electrode connected to the reference voltage source, a drain electrode connected to the first node, and a gate electrode connected to the third scan line to which the emission control pulse is applied,
The fourth switch TFT includes a source electrode connected to the third node, a drain electrode connected to the fourth node, and a gate electrode connected to the third scan line,
The fifth switch TFT includes a source electrode connected to the reference voltage source, a drain electrode connected to the fourth node, and a gate electrode connected to the first scan line to which the selection pulse is applied,
Wherein the driving TFT includes a source electrode connected to the high potential power source, a drain electrode connected to the third node, and a gate electrode connected to the second node. 3. The method of claim 2,
Wherein the third switch TFT comprises a source electrode connected to the second node, a drain electrode connected to the third node, and a gate electrode connected to the first scan line. 3. The method of claim 2,
The third switch TFT includes third and third switch TFTs,
The third switch TFT includes a source electrode connected to the second node, a drain electrode connected to the source electrode of the third switch TFT, and a gate electrode connected to the first scan line,
Wherein the third switch TFT includes a source electrode connected to a drain electrode of the third switch TFT, a drain electrode connected to the third node, and a gate electrode connected to the first scan line. . 5. The method according to any one of claims 1 to 4,
When the organic light emitting diode emits light,
The current I _OLED flowing through the organic light emitting diode

,

ego,
'L' is a channel length of the driving TFT, 'W' is a channel width of the driving TFT, and 'Cst1' is a constant value defined by a product of mobility and parasitic capacitance of the driving TFT. Wherein a capacitance of the first capacitor, 'Cst2' is a capacitance of the second capacitor, and 'Vanode' is an anode voltage of the organic light emitting diode.

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