KR102578163B1 - Organic light emitting display device and method for manufacturing the same - Google Patents

Abstract

One embodiment of the present invention includes an organic light emitting device corresponding to each of a plurality of pixel regions, a driving thin film transistor disposed in series with the organic light emitting device between a first power line and a second power line, and data of each pixel region. An organic light emitting display device is provided including a first thin film transistor disposed between a data line that supplies a signal and a first node. Here, one side of the active layer of the driving thin film transistor partially overlaps the first power line, and the first power line is a driving contact disposed in an overlap area between the active layer of the driving thin film transistor and the first power line. It is connected to the active layer of the driving thin film transistor through a hole. In addition, one side of the active layer of the first thin film transistor partially overlaps the data line, and the data line is connected to the data line through a data contact hole disposed in an overlapping area between the active layer of the first thin film transistor and the data line. It is connected to the active layer of the first thin film transistor.

Description

Organic light emitting display device and manufacturing method thereof {ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to an organic light emitting display device including at least one thin film transistor corresponding to each pixel area and a method of manufacturing the same.

Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. Accordingly, research is continuing to develop display devices that are thinner, lighter, and have lower power consumption.

Representative examples of display devices include Liquid Crystal Display device (LCD), Plasma Display Panel device (PDP), Field Emission Display device (FED), and Electro Luminescence. Display device (ELD), Electro-Wetting Display device (EWD), and Organic Light Emitting Display device (OLED).

Among them, the organic light emitting display device includes a plurality of organic light emitting elements corresponding to a plurality of pixel areas defined in a display area where an image is displayed. Since organic light-emitting devices are self-luminous devices that emit light on their own, organic light-emitting displays have the advantages of faster response speed, greater luminous efficiency, higher luminance and viewing angle, and superior contrast ratio and color gamut compared to liquid crystal displays.

The organic light emitting display device can be implemented in an active matrix method that individually drives a plurality of pixel areas. This active matrix organic light emitting display device includes a pixel driving circuit that supplies driving current to the organic light emitting element corresponding to each pixel area.

The pixel driving circuit includes a driving thin-film transistor connected in series with the organic light-emitting element between the first and second driving power supplies corresponding to the driving of the organic light-emitting element, a switching thin-film transistor that supplies data signals for each pixel area, and a data signal. It is common to include a storage capacitor that is charged based on and supplies a turn-on signal to the gate electrode of the driving thin film transistor.

Accordingly, the organic light emitting display device includes a plurality of conductive layers insulated from each other by two or more insulating films in order to implement a plurality of thin film transistors and storage capacitors corresponding to each pixel area and various signal lines. Additionally, the organic light emitting display device may further include a contact hole passing through at least one insulating film to connect conductive layers separated by at least one insulating film and a bridge pattern connecting the contact holes.

When arranging such contact holes and bridge patterns, a typical organic light emitting display device may implement the bridge pattern using the uppermost conductive layer among multiple conductive layers for a simpler manufacturing process. In this case, in order to prevent short circuit defects, etc., the contact holes and bridge patterns must be arranged to be spaced apart from each other by at least a process margin distance on a plane. Accordingly, there is a problem in that there is a limit to improving the space utilization of each pixel area.

In addition, due to differences in driving stress for each pixel region, the characteristics of the driving thin film transistor and organic light emitting device of each pixel region may vary. In this case, a difference in luminance between pixel areas may occur, causing deterioration in image quality such as spots. To prevent this, the organic light emitting display device may further include a driving thin film transistor corresponding to each pixel area and a compensation circuit to compensate for the characteristics of the organic light emitting device. Accordingly, in each pixel area, not only elements corresponding to the pixel driving circuit but also elements to implement the compensation circuit must be placed.

Therefore, if the space utilization of each pixel area is not improved, there is a problem in that there is a limit to reducing the area of the pixel area. As a result, there is a problem that there is a limit to the high resolution of the organic light emitting display device.

The present invention is intended to provide an organic light emitting display device and a manufacturing method thereof that can improve space utilization of the pixel area and are advantageous for high resolution.

The objects of the present invention are not limited to the objects mentioned above, and other objects and advantages of the present invention that are not mentioned can be understood by the following description and will be more clearly understood by the examples of the present invention. Additionally, it will be readily apparent that the objects and advantages of the present invention can be realized by the means and combinations thereof indicated in the patent claims.

An example of the present invention includes an organic light emitting element corresponding to each of a plurality of pixel areas defined in a display area, a first power line supplying a first driving power, and a second driving power having a voltage lower than the first driving power. a driving thin film transistor disposed in series with an organic light emitting element corresponding to each pixel region between a second power line, and a first thin film disposed between a first node and a data line supplying a data signal for each pixel region. An organic light emitting display device including a transistor is provided.

Here, one side of the active layer of the driving thin film transistor extends toward the first power line and partially overlaps the first power line, and the first power line is between the active layer of the driving thin film transistor and the first power line. It is connected to the active layer of the driving thin film transistor through a driving contact hole disposed in the overlapping area. In addition, one side of the active layer of the first thin film transistor extends toward the data line and partially overlaps the data line, and the data line is disposed in an overlapping area between the active layer of the first thin film transistor and the data line. It is connected to the active layer of the first thin film transistor through a data contact hole.

The organic light emitting display device further includes a storage capacitor disposed between the first node and a second node connected to the gate electrode of the driving thin film transistor. Here, the channel region of the active layer of the driving thin film transistor overlaps the gate electrode disposed on the gate insulating film covering the active layer, and the storage capacitor is a capacitor electrode pattern disposed on the first interlayer insulating film covering the gate electrode. and corresponds to the overlap area between the gate electrode. Additionally, the data line and the first power line are disposed on a second interlayer insulating film covering the capacitor electrode pattern.

The capacitor electrode pattern is connected to the active layer of the first thin film transistor through a first capacitor contact hole disposed in an overlapping area between the other side of the active layer of the first thin film transistor and the capacitor electrode pattern, and the first The capacitor contact hole overlaps the data line with the second interlayer insulating film interposed therebetween.

The organic light emitting display device includes a second thin film transistor disposed between the second node and a third node connected to one of the first and second electrodes of the driving thin film transistor corresponding to the organic light emitting element, and each pixel area. A third thin film transistor disposed between the first node and a reference power line that supplies reference power to the first node, a fourth thin film transistor disposed between the third node and a fourth node connected to the anode electrode of the organic light emitting device, and It further includes a fifth thin film transistor disposed between the reference power line and the fourth node.

Here, the reference power line is disposed on the first interlayer insulating film in a direction crossing the data line, and the reference power line is located in an overlapping area between one side of the active layer of the third thin film transistor and the reference power line. It is connected to the active layer of the third thin film transistor through a reference power contact hole. And, the capacitor electrode pattern is connected to the active layer of the third thin film transistor through a second capacitor contact hole disposed in an overlapping area between the other side of the active layer of the third thin film transistor and the capacitor electrode pattern, Each of the reference power contact hole and the second capacitor contact hole overlaps the data line with the second interlayer insulating film interposed therebetween.

Another example of the present invention includes disposing an active layer corresponding to at least one thin film transistor included in each pixel area on a substrate, disposing a gate insulating film covering the active layer, and placing one or more thin film transistors on the gate insulating film. Disposing a gate electrode overlapping the channel region of the active layer, disposing a first interlayer insulating film covering the gate electrode, and patterning the gate insulating film and the first interlayer insulating film to correspond to a plurality of contact holes. , performing heat treatment on the active layer, and arranging a capacitor electrode pattern overlapping the gate electrode and a reference power line for supplying reference power on the first interlayer insulating film. Provides a manufacturing method.

The method of manufacturing the organic light emitting display device includes disposing a second interlayer insulating film covering the capacitor electrode pattern, patterning the second interlayer insulating film to correspond to a portion of the plurality of contact holes, and the second interlayer insulating film. It further includes arranging a data line for supplying data signals of each pixel area and a first power line for supplying a first driving power corresponding to driving the organic light emitting device. Here, the reference power line is disposed in a direction crossing the data line and the first power line.

At least one thin film transistor included in each pixel region includes a driving thin film transistor disposed in series with an organic light emitting element corresponding to each pixel region, a first thin film transistor disposed between the data line and the first node, and the driving thin film transistor. A second thin film transistor disposed between a second node connected to the gate electrode of the thin film transistor and a third node connected to one of the first and second electrodes of the driving thin film transistor corresponding to the organic light emitting element, each pixel area A third thin film transistor disposed between the first node and a reference power line that supplies reference power to the first node, a fourth thin film transistor disposed between the third node and a fourth node connected to the anode electrode of the organic light emitting device, and It includes a fifth thin film transistor disposed between the reference power line and the fourth node. Here, each pixel area further includes a storage capacitor corresponding to an overlapping area between the gate electrode and the capacitor electrode pattern, and the storage capacitor is disposed between the first and second nodes.

In the step of patterning the gate insulating film and the first interlayer insulating film, the plurality of contact holes include a driving contact hole corresponding to one side of the active layer of the driving thin film transistor and a driving contact hole corresponding to one side of the active layer of the first thin film transistor. A data contact hole, a first capacitor contact hole corresponding to the other side of the active layer of the first thin film transistor, and a reference power contact hole corresponding to one side of the active layer of the third thin film transistor, the active layer of the third thin film transistor and a second capacitor contact hole corresponding to the other side of the layer.

The step of patterning the second interlayer insulating film is performed corresponding to the driving contact hole and the data contact hole among the plurality of contact holes, and in the step of arranging the data line and the first power line, the first power supply The line is connected to the active layer of the driving thin film transistor through the driving contact hole, and the data line is connected to the active layer of the first thin film transistor through the data contact hole.

In the step of arranging the capacitor electrode pattern and the reference power line, the capacitor electrode pattern is connected to the active layer of the first thin film transistor through the first capacitor contact hole and the third through the second capacitor contact hole. It is connected to the active layer of the thin film transistor, and the reference power line is connected to the active layer of the third thin film transistor through the reference power contact hole.

In the step of arranging the data line and the first power line, the data line overlaps the reference power contact hole and the first and second capacitor contact holes.

According to one embodiment of the present invention, the driving contact hole for connecting the first power line and the driving thin film transistor is an overlap area between the first power line and one side of the active layer of the driving thin film transistor extending toward the first power line. and a data contact hole for connecting the data line and the first thin film transistor is disposed in an overlapping area between the data line and one side of the active layer of the first thin film transistor extending toward the data line.

That is, the first power line can be connected to the driving thin film transistor through the driving contact hole without a separate bridge pattern. Likewise, the data line can be connected to the first thin film transistor through the data contact hole without a separate bridge pattern. As a result, the space utilization of the pixel area is improved as the area corresponding to the bridge pattern for the connection between the first power line and the driving thin film transistor and the bridge pattern for the connection between the data line and the first thin film transistor are not allocated. There are advantages to this.

And, according to one embodiment of the present invention, the storage capacitor corresponds to an overlap area between the gate electrode of the driving thin film transistor and the capacitor electrode pattern on the first interlayer insulating film covering the gate electrode. At this time, the capacitor electrode pattern is connected to the first thin film transistor through the first capacitor contact hole and to the third thin film transistor through the second capacitor contact hole.

That is, without a separate bridge pattern, the capacitor electrode pattern can be connected to the first and third thin film transistors through the first and second capacitor contact holes. Accordingly, there is an advantage that space utilization of the pixel area can be improved as the area corresponding to the bridge pattern for connection between each of the first and third thin film transistors and the capacitor electrode pattern is not allocated.

In addition, since the bridge pattern between each of the first and third thin film transistors and the capacitor electrode pattern can be excluded, the pattern is reduced accordingly, which has the advantage of reducing foreign matter defects.

Additionally, the first and second capacitor contact holes are arranged to overlap the data line. Accordingly, there is an advantage that space utilization of the pixel area can be improved as a separate area for the first and second capacitor contact holes is not allocated.

Additionally, according to one embodiment of the present invention, before disposing the capacitor electrode pattern, a contact hole exposing a portion of the active layer must be disposed. Accordingly, heat treatment on the active layer can be performed after arranging the contact hole and before arranging the capacitor electrode pattern. That is, the capacitor electrode pattern may not be exposed to heat treatment. Therefore, the capacitor electrode pattern can be selected from a low-resistance metal that is vulnerable to heat treatment, and thus the signal line can be placed on the same layer as the capacitor electrode pattern.

In particular, when the reference power line is placed on the same layer as the capacitor electrode pattern, the reference power line is placed on a different layer from the data line and the first power line, so that it can be placed in a direction crossing the data line and the first power line. there is. As a result, the reference power contact hole for connection between each of the third and fifth thin film transistors and the reference power line can be arranged to overlap the data line. Therefore, there is an advantage that space utilization of the pixel area can be improved as a separate area for the reference power contact hole is not allocated.

In addition, as the reference power line corresponds to a horizontal line, the separation distance between pixel areas is reduced by the width of the reference power line compared to the case where the reference power line is placed vertically on the same layer as the data line and the first power line. Therefore, there is an advantage that it can be advantageous for high resolution.

1 is a diagram showing an organic light emitting display device according to an embodiment of the present invention.
FIG. 2 is a diagram showing an equivalent circuit corresponding to one pixel area shown in FIG. 1.
FIG. 3 is a diagram showing an example of a plane of a thin film transistor array substrate corresponding to the equivalent circuit of FIG. 2.
FIG. 4 is a cross-sectional view taken along line A-A' of FIG. 3.
FIG. 5 is a cross-sectional view taken along line B-B' of FIG. 3.
FIG. 6 is a cross-sectional view taken along line C-C' of FIG. 3.
FIG. 7 is a diagram illustrating an example of the first and third thin film transistors and a storage capacitor shown in FIG. 2 in a thin film transistor array substrate of a general organic light emitting display device.
Figure 8 is a diagram showing a method of manufacturing an organic light emitting display device according to an embodiment of the present invention.
Figures 9 to 20 are diagrams showing each process in Figure 8.

The above-mentioned objects, features, and advantages will be described in detail later with reference to the attached drawings, so that those skilled in the art will be able to easily implement the technical idea of the present invention. In describing the present invention, if it is determined that a detailed description of known technologies related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. In the drawings, identical reference numerals are used to indicate identical or similar components.

Hereinafter, an organic light emitting display device according to an embodiment of the present invention will be described in detail with reference to the attached drawings.

1 is a diagram showing an organic light emitting display device according to an embodiment of the present invention. FIG. 2 is a diagram showing an equivalent circuit corresponding to one pixel area shown in FIG. 1.

FIG. 3 is a diagram showing an example of a plane of a thin film transistor array substrate corresponding to the equivalent circuit of FIG. 2. FIG. 4 is a cross-sectional view taken along line A-A' of FIG. 3. FIG. 5 is a cross-sectional view taken along line B-B' of FIG. 3. FIG. 6 is a cross-sectional view taken along line C-C' of FIG. 3.

FIG. 7 is a diagram illustrating an example of the first and third thin film transistors and a storage capacitor shown in FIG. 2 in a thin film transistor array substrate of a general organic light emitting display device.

As shown in FIG. 1, an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 including a plurality of pixel areas (PXL) defined in a display area (AA) on which an image is displayed, A data driver 12 that drives the data line 14 of the display panel 10, a gate driver 13 that drives the scan line 15 of the display panel 10, a data driver 12, and a gate driver. It includes a timing controller (11) for controlling the driving timing of (13).

The display panel 10 has a scan line 15 corresponding to each horizontal line composed of pixel areas arranged side by side in the horizontal direction among the plurality of pixel areas PXL, and a vertical line among the plurality of pixel areas PXL. It includes a data line 14 corresponding to each vertical line composed of pixel areas arranged in parallel.

Here, the scan line 15 may include first, second, and third scan lines for supplying different first and second scan signals (SCAN1, SCAN2) and emission signals (EM). The first scan signal SCAN may be used to sequentially select each horizontal line during an addressing period for writing data in the pixel area PXL. The second scan signal SCAN2 may correspond to the initial period for supplying the reference power VREF to the pixel area PXL. The emission signal (EM) may correspond to the emission period for supplying driving current to the organic light emitting device.

A plurality of pixel areas (PXL) may be defined by scan lines 15 and data lines 14 that intersect each other. Accordingly, the plurality of pixel areas (PXL) are arranged in a matrix form in the display area (AA).

In addition, the display panel 10 has a first driving power line that supplies the first driving power (VDD) to the plurality of pixel areas (PXL), and a second driving power (VSS) with a potential lower than the first driving power (VDD). ) and a reference power line that supplies reference power (VREF).

The timing controller 11 rearranges digital video data (RGB) input from the outside to match the resolution of the display panel 10, and supplies the rearranged digital video data (RGB') to the data driver 12.

And, the timing controller 11 operates the data driver 12 based on timing signals such as the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the dot clock signal (DCLK), and the data enable signal (DE). A data control signal (DDC) for controlling the operation timing and a gate control signal (GDC) for controlling the operation timing of the gate driver 13 are supplied.

The data driver 12 converts the rearranged digital video data (RGB') into an analog data voltage based on the data control signal (DDC). Then, the data driver 12 supplies a data signal (VDATA) to each pixel area during each horizontal period based on the rearranged digital video data (RGB').

The gate driver 13 may sequentially supply the first scan signal SCAN1 to the scan line 15 of each horizontal line based on the gate control signal GDC.

Although not separately shown, the display panel 10 includes a pair of opposing substrates bonded together and an organic light emitting element array disposed between them. Additionally, one of the pair of substrates is a thin film transistor array substrate for defining a plurality of pixel areas (PXL) and supplying driving current to the organic light emitting elements of each pixel area (PXL), and the other is an organic light emitting element. It may be an encapsulation substrate for sealing the array.

As shown in FIG. 2, each pixel area (PXL) includes an organic light emitting device (OLED), a driving thin film transistor (DT), and first, second, third, fourth, and fifth thin film transistors (T1, T2, T3, T4, T5) and storage capacitor (Cst).

An organic light emitting device (OLED) includes an anode electrode, a cathode electrode, and an organic light emitting layer (not shown) disposed between them. Exemplarily, the organic light-emitting layer includes a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer. Alternatively, the organic light-emitting layer may further include an electron injection layer.

The driving thin film transistor (DT) has a first driving power line 16 that supplies the first driving power (VDD) and a second driving power line (16) that supplies a second driving power (VSS) with a potential lower than the first driving power (VDD). It is placed in series with an organic light emitting device (OLED) between the power lines.

The first thin film transistor T1 is disposed between the data line 14 that supplies the data signal VDATA of each pixel area and the first node ND1.

When this first thin film transistor T1 is turned on based on the first scan signal SCAN1 of the first scan line 15a, it supplies the data signal VDATA to the first node ND1.

The storage capacitor Cst is disposed between the second node ND2 and the first node ND1 connected to the gate electrode of the driving thin film transistor DT.

This storage capacitor Cst is charged based on the data signal VDATA supplied to the first node ND1 through the turned-on first thin film transistor T1.

Then, the driving thin film transistor (DT) turns on based on the charging voltage of the storage capacitor (Cst), and supplies a driving current corresponding to the data signal (VDATA) to the third node (ND3), that is, the organic light emitting device (OLED). do. Here, one of the first and second electrodes of the driving thin film transistor (DT) is connected to the first power line (VDD), and the other is connected to the third node (ND3).

The second thin film transistor T2 is disposed between the second node ND2 and the third node ND3. Here, the second node (ND2) is connected to the gate electrode of the driving thin film transistor (DT), and the third node (ND3) is connected to the organic light emitting device (OLED) among the first and second electrodes of the driving thin film transistor (DT). It is connected to a corresponding one (for example, a drain electrode). Accordingly, the second thin film transistor (T2) is used to compensate for the threshold voltage of the driving thin film transistor (DT).

When this second thin film transistor T2 is turned on based on the second scan signal SCAN2 of the second scan line 15b, it connects the second node ND2 and the third node ND3.

The third thin film transistor T3 is disposed between the first node ND1 and the reference power line 15d, which supplies the reference power VREF to each pixel area PXL.

When the third thin film transistor T3 is turned on based on the emission signal EM of the third scan line 15c, it supplies the reference power VREF to the first node ND1.

The fourth thin film transistor (T4) is disposed between the fourth node (ND4) and the third node (ND3) connected to the anode electrode of the organic light emitting device (OLED).

When this fourth thin film transistor T4 is turned on based on the emission signal EM of the third scan line 15c, it connects the third node ND3 and the fourth node ND4.

The fifth thin film transistor T5 is disposed between the reference power line 15d and the fourth node ND4.

When the fifth thin film transistor T5 is turned on based on the second scan signal SCAN2 of the second scan line 15b, it supplies the reference power VREF to the fourth node ND4.

However, the equivalent circuit of the pixel area shown in FIG. 2 is only an example, and an embodiment of the present invention is not limited to the equivalent circuit of FIG. 2. That is, one embodiment of the present invention includes at least one thin film transistor (T3, T5) connected to the reference power line (15d), including a driving thin film transistor (DT), a first thin film transistor (T1), and a storage capacitor (Cst). It is natural that it can be applied to any organic light emitting display device that includes a pixel area (PXL) of the equivalent circuit. For example, in addition to the 6T1C structure shown in FIG. 2, it can also be applied to equivalent circuits such as 7T1C and 8T1C.

As shown in FIG. 3, the organic light emitting display device according to an embodiment of the present invention includes a driving thin film transistor (DT in FIG. 2) corresponding to each pixel region (PXL), first, second, third, and third. It includes fourth and fifth thin film transistors (T1, T2, T3, T4, and T5 in FIG. 2) and a storage capacitor (Cst in FIG. 2).

In addition, the organic light emitting display device according to an embodiment of the present invention has first, second, and Data corresponding to each vertical line consisting of the third scan line (15a, 15b, 15c), the reference power line (15d), and pixel areas arranged in parallel in the vertical direction among a plurality of pixel areas (PXL in FIG. 1) It further includes a line 14 and a first power line 16.

The channel region of the active layer 110 of the driving thin film transistor (DT) overlaps the gate electrode 120.

Here, the gate electrode 120 is connected to the first conductive pattern 141 through the first conductive contact hole 141_H1. The first conductive pattern 141 is connected to the active layer 112 of the second thin film transistor T2 through the second conductive contact hole 141_H2. That is, since the gate electrode 120 of the driving thin film transistor (DT) and the second thin film transistor (T2) are connected through the first conductive pattern 141, the first conductive pattern 141 is connected to the second node (Figure 2). Corresponds to ND2).

One side of the active layer 110 of the driving thin film transistor DT extends toward the first power line 16 and partially overlaps the first power line 16. Accordingly, the first power line 16 is connected to the active layer 110 of the driving thin film transistor through the driving contact hole 16_H disposed in the overlapping area between the active layer 110 of the driving thin film transistor and the first power line 16. ) is connected to. Here, the driving contact hole 16_H is not in an area branched from the first power line 16, but is disposed on the same line as the first power line 16.

And, the other side of the active layer 110 of the driving thin film transistor corresponds to the third node (ND3 in FIG. 2), and the active layer 112 of the second thin film transistor and the active layer (T4) of the fourth thin film transistor T4 114).

The storage capacitor (Cst in FIG. 2) corresponds to the overlap area between the gate electrode 120 and the capacitor electrode pattern 130.

The channel region of the active layer 111 of the first thin film transistor T1 overlaps the first scan line 15a that supplies the first scan signal (SCAN1 in FIG. 2).

One side of the active layer 111 of the first thin film transistor extends toward the data line 14 and partially overlaps the data line 14. Accordingly, the data line 14 is connected to the active layer 111 of the first thin film transistor through the data contact hole 14_H disposed in the overlapping area between the active layer 111 of the first thin film transistor and the data line 14. connected.

And, the other side of the active layer 111 of the first thin film transistor partially overlaps the capacitor electrode pattern 130. Accordingly, the capacitor electrode pattern 130 is connected to the active layer of the first thin film transistor through the first capacitor contact hole 130_H1 disposed in the overlapping area between the active layer 111 of the first thin film transistor and the capacitor electrode pattern 130. Connected to (111).

Here, the first capacitor contact hole 130_H1 overlaps the data line 14.

That is, the data contact hole 14_H and the first capacitor contact hole 130_H1 are not located in an area branched from the data line 14, but are disposed on the same line as the data line 14.

The channel region of the active layer 112 of the second thin film transistor T2 overlaps the second scan line 15b that supplies the second scan signal (SCAN2 in FIG. 2).

One side of the active layer 112 of the second thin film transistor is connected to the first conductive pattern 141 through the second conductive contact hole 141_H2.

The other side of the active layer 112 of the second thin film transistor corresponds to the third node (ND3 in FIG. 2), and the active layer 110 of the driving thin film transistor and the active layer 114 of the fourth thin film transistor (T4) It continues.

The channel region of the active layer 113 of the third thin film transistor T3 overlaps the third scan line 15c that supplies an emission signal (EM in FIG. 2).

One side of the active layer 113 of the third thin film transistor partially overlaps the capacitor electrode pattern 130. Accordingly, the capacitor electrode pattern 130 is connected to the active layer of the third thin film transistor through the second capacitor contact hole 130_H2 disposed in the overlapping area between the active layer 113 of the third thin film transistor and the capacitor electrode pattern 130. Connected to (113).

Here, the second capacitor contact hole 130_H2 overlaps the data line 14.

That is, the second capacitor contact hole 130_H2, along with the data contact hole 14_H and the first capacitor contact hole 130_H1, is not an area branched from the data line 14, but is located on the same line as the data line 14. It is placed.

The channel area of the active layer 114 of the fourth thin film transistor T4 overlaps the third scan line 15c.

One side of the active layer 114 of the fourth thin film transistor corresponds to the third node ND3 and is connected to the active layer 110 of the driving thin film transistor and the active layer 112 of the second thin film transistor.

The other side of the active layer 114 of the fourth thin film transistor is connected to the second conductive pattern 142 through the third conductive contact hole 142_H.

Although not shown in detail in FIG. 3, the second conductive pattern 142 is connected to the anode electrode of the organic light emitting device (OLED in FIG. 2) through the anode contact hole (Anode_H). That is, the second conductive pattern 142 corresponds to the fourth node (ND4 in FIG. 2).

The channel region of the active layer 115 of the fifth thin film transistor T5 overlaps the branched region of the couple line 15b' of the second scan line that supplies the second scan signal (SCAN2 in FIG. 2).

One side of the active layer 115 of the fifth thin film transistor extends toward the reference power line 15d that supplies the reference power (VREF in FIG. 2) and partially overlaps the reference power line 15d. Accordingly, the reference power line 15d is connected to the active layer ( 115).

Here, the reference power contact hole 15d_H overlaps the data line 14.

That is, since the reference power line 15d is arranged in a direction that intersects the data line 14, an overlapping area is created between the reference power line 15d and the data line 14. And, by extending one side of the active layer 115 of the fifth thin film transistor to the overlap area between the reference power line 15d and the data line 14, the reference power contact hole 15d_H overlaps the data line 14. It can be.

In addition, like the data contact hole 14_H and the first and second capacitor contact holes 130_H1 and 130_H2, the reference power contact hole 15d_H is not an area branched from the data line 14, but is connected to the data line 14. is placed on the same line as

The other side of the active layer 115 of the fifth thin film transistor corresponds to the fourth node (ND4 in FIG. 2) and is connected to the active layer 114 of the fourth thin film transistor.

As described above, according to an embodiment of the present invention, the first power line 16 is connected to the active layer 110 of the driving thin film transistor through the driving contact hole 16_H located on the same line as the first power line 16. is directly connected to Accordingly, since a separate bridge pattern for connecting the first power line 16 and the active layer 110 of the driving thin film transistor can be excluded, space utilization of the pixel area PXL can be improved accordingly.

Likewise, the data line 14 is directly connected to the active layer 111 of the first thin film transistor through the data contact hole 14_H located on the same line as the data line 14. Accordingly, since a separate bridge pattern for connecting the data line 14 and the active layer 111 of the first thin film transistor can be excluded, space utilization of the pixel area PXL can be improved accordingly.

In addition, the data contact hole 14_H, the reference power contact hole 15d_H, and the first and second capacitor contact holes 130_H1 and 130_H2 are all arranged to overlap the data line 14. Accordingly, as separate areas are not allocated for the data contact hole (14_H), the reference power contact hole (15d_H), and the first and second capacitor contact holes (130_H1, 130_H2), the space utilization of the pixel area (PXL) is reduced. It can be improved.

As shown in FIG. 5, the active layer 111 of the first thin film transistor T1 is disposed on the substrate 101 and covered with the gate insulating film 102.

And, the first scan line 15a is disposed on the gate insulating film 102.

Like the first scan line 15a, the second scan line 15b, the couple line 15b' of the second scan line, the third scan line 15c, and the gate electrode 120 of the driving thin film transistor T1. is disposed on the gate insulating film 102.

And, the capacitor electrode pattern 130 corresponding to the storage capacitor Cst is disposed on the first interlayer insulating film 103 covering the gate electrode 120. Here, the storage capacitor Cst corresponds to an area where the gate electrode 120 and the capacitor electrode pattern 130 overlap each other with the first interlayer insulating film 103 interposed therebetween.

Like the capacitor electrode pattern 130, the reference power line 15d is disposed on the first interlayer insulating film 103.

The data line 14 is disposed on the second interlayer insulating film 104 covering the capacitor electrode pattern 130 and the reference power line 15d.

The active layer 111 of the first thin film transistor includes a channel region 111a overlapping the first scan line 15a on the gate insulating film 102, and first and second electrodes corresponding to both sides of the channel region 111a. It includes areas 111b and 111c.

For example, the first electrode region 111b of the active layer 111 of the first thin film transistor is connected to the data line 14 on the second interlayer insulating film 104 through the data contact hole 14_H, and the second electrode The region 111c may be connected to the capacitor electrode pattern 130 on the first interlayer insulating film 103 through the first capacitor contact hole 130_H1.

The active layer 113 of the third thin film transistor T3 is disposed on the substrate 101, is covered with the gate insulating film 102, and has a channel region overlapping the third scan line 15c on the gate insulating film 102. It includes (113a) and first and second electrode regions (113b, 113c) corresponding to both sides of the channel region (113a).

As an example, the first electrode region 113b of the active layer 113 of the third thin film transistor is connected to the reference power line 15d on the first interlayer insulating film 103 through the reference power contact hole 15d_H, and the The second electrode area 113c may be connected to the capacitor electrode pattern 130 on the first interlayer insulating film 103 through the second capacitor contact hole 130_H2.

At this time, as shown in FIG. 4, the data contact hole 14_H, the reference power contact hole 15d_H, and the first and second capacitor contact holes 130_H1 and 130_H2 all overlap the data line 14.

As shown in FIGS. 5 and 6, the first power line 16 and the first and second conductive patterns 141 and 142 are disposed on the second interlayer insulating film 104, like the data line 14. do.

And, the anode of the organic light emitting device (OLED in FIG. 2) is an overcoat film 105 that covers the data line 14, the first power line 16, and the first and second conductive patterns 141 and 142. ) can be placed on. In this case, the anode electrode (Anode) may be connected to the second conductive pattern 142 through the anode contact hole (Anode_H) penetrating the overcoat film 105.

The second conductive pattern 142 is connected to the active layer 114 of the fourth thin film transistor T4 through the third conductive contact hole 142_H.

The active layer 110 of the driving thin film transistor (DT) is disposed on the substrate 101, is covered with the gate insulating film 102, and has a channel region 110a overlapping the gate electrode 120 on the gate insulating film 102. and first and second electrode regions 110b and 110c corresponding to both sides of the channel region 110a.

As an example, the first electrode region 110b of the active layer 110 of the driving thin film transistor is connected to the first power line 16 on the second interlayer insulating film 104 through the driving contact hole 16_H, and the second The electrode area 110c may be connected to the active layer 114 of the fourth thin film transistor T4.

The active layer 114 of the fourth thin film transistor T4 is disposed on the substrate 101, is covered with the gate insulating film 102, and has a channel region overlapping the third scan line 15c on the gate insulating film 102. It includes 114a and first and second electrode regions 114b and 114c corresponding to both sides of the channel region 114a.

For example, the first electrode region 114b of the active layer 114 of the fourth thin film transistor is connected to the active layer 110 of the driving thin film transistor, and the second electrode region 114c is connected to the third conductive contact hole 142_H. ) may be connected to the second conductive pattern 142 on the second interlayer insulating film 104.

As shown in FIG. 6, the second electrode region 114c of the active layer 114 of the fourth thin film transistor continues to the active layer 115 of the fifth thin film transistor T5.

The active layer 115 of the fifth thin film transistor T5 is disposed on the substrate 101, is covered with the gate insulating film 102, and is connected to the couple line 15b' of the second scan line on the gate insulating film 102. It includes an overlapping channel area 115a and first and second electrode areas 115a and 115b corresponding to both sides of the channel area 115a.

For example, the first electrode region 115b of the active layer 115 of the fifth thin film transistor is connected to the active layer 113 of the third thin film transistor T3, and the second electrode region 115c is connected to the fourth thin film transistor. It continues to the active layer 114 of (T4).

Here, as shown in FIG. 4, the first electrode region 113b of the active layer 113 of the third thin film transistor T3 is connected to the reference power line 16.

Although not shown in detail in FIG. 6, the first electrode area 115b of the active layer 115 of the fifth thin film transistor T5 is the first electrode area 115b of the active layer 113 of the third thin film transistor T3. Since 113b is followed, the first electrode region 115b of the active layer 115 of the fifth thin film transistor T5 is also connected to the reference power line 16.

The active layer 112 of the second thin film transistor T2 is disposed on the substrate 101 and covered with the gate insulating film 102.

The active layer 112 of the second thin film transistor T2 includes first and second channel regions 112a and 112b overlapping the second scan line 15b on the gate insulating film 102, and a first channel region 112a. ), the first electrode area (112c) corresponding to one side of the second channel area (112b), the second electrode area (112d) corresponding to one side of the second channel area (112b), and between the first and second channel areas (112a, 112b). It includes a connection area 112e.

As an example, the first electrode region 112c of the active layer 112 of the second thin film transistor is connected to the driving thin film transistor DT through the first and second conductive contact holes 141_H1 and 141_H2 and the first conductive pattern 141. ), and the second electrode region 112d may be connected to the active layer 114 of the fourth thin film transistor.

Meanwhile, as shown in FIG. 2, a typical organic light emitting display device also includes a storage capacitor (Cst) disposed between the first node (ND1) and the second node (ND2), the first and second capacitors (Cst) connected to the first node (ND1). It may include third thin film transistors (T1, T3).

In this case, as shown in FIG. 7, in a typical organic light emitting display device, the storage capacitor (Cst) is formed by the gate electrode 120 on the gate insulating film 102 and the capacitor electrode pattern (CP) on the first interlayer insulating film 103. ) can correspond to the overlap area between.

The capacitor electrode pattern (CP) corresponding to the first node (ND1) is connected to each of the first and third thin film transistors (T1 and T3) through the bridge pattern (BP). Here, the bridge pattern BP is disposed on the second interlayer insulating film 104, which is the highest level among the plurality of insulating films 102, 103, and 104. As such, the bridge pattern BP is disposed on a different layer from both the active layers 111 and 113 and the capacitor electrode pattern CP of the first and third thin film transistors T1 and T3. Therefore, the bridge pattern BP is connected to the active layers 111 and 113 of the first and third thin film transistors T1 and T3 and the capacitor through the first, second and third bridge contact holes BP_H1, BP_H2 and BP_H3. It can be connected to the electrode pattern (CP).

Here, since the first, second, and third bridge contact holes (BP_H1, BP_H2, BP_H3) must be arranged on the same plane and spaced apart from each other, the first, second, and third bridge contact holes are installed in each pixel area (PXL). Areas corresponding to (BP_H1, BP_H2, BP_H3) must be allocated separately. Additionally, an area corresponding to the bridge pattern (BP) must be separately allocated to each pixel area (PXL). Therefore, there is a problem that there is a limit to improving the space utilization of the pixel area.

In addition, the first, second and third bridge contact holes (BP_H1, BP_H2, BP_H3) penetrate the second interlayer insulating film 104, and the capacitor electrode pattern (CP) is covered with the second interlayer insulating film 104. become. Accordingly, the capacitor electrode pattern CP is exposed to a heat treatment process performed after disposing the first, second, and third bridge contact holes BP_H1, BP_H2, and BP_H3. Therefore, the capacitor electrode pattern (CP) needs to be made of a high-resistance metal material such as Mo (molybdenum), which is relatively resistant to heat treatment. Accordingly, there is a problem in that it is difficult to place the signal line on the same layer as the capacitor electrode pattern (CP). In other words, the signal line disposed on the same layer as the capacitor electrode pattern (CP) must be wide due to high resistance, so there is a problem that it is not suitable for high resolution.

In contrast, according to one embodiment of the present invention, the capacitor electrode pattern 130 is directly connected to the first and third thin film transistors (T1 and T3) through the first and second capacitor contact holes (130_H1 and 130_H2). do. Therefore, a separate bridge pattern for connecting each of the first and third thin film transistors (T1, T3) and the capacitor electrode pattern 130 can be removed, so that the pixel area is not allocated to the area corresponding to the bridge pattern. There is an advantage that space utilization can be improved.

In addition, unlike a typical organic light emitting display device, since the bridge pattern is excluded from the layer where the data line 14 and the first power line 16 are arranged, there is an advantage that foreign matter defects can be reduced.

In addition, the first and second capacitor contact holes (130_H1, 130_H2) are formed to penetrate the gate insulating film 102 and the first interlayer insulating film 103, and the capacitor electrode pattern 130 is formed on the first interlayer insulating film 103. is placed in Accordingly, a heat treatment process may be performed between the process of arranging the first and second capacitor contact holes 130_H1 and 130_H2 and the process of arranging the capacitor electrode pattern 130. Accordingly, since the capacitor electrode pattern 130 is not exposed to the heat treatment process, a low-resistance metal that is relatively vulnerable to the heat treatment process can be selected. By way of example, the low-resistance metal may include Al (aluminum). Accordingly, since the signal line can be placed on the same layer as the capacitor electrode pattern 130, the utilization of the conductive layer corresponding to the capacitor electrode pattern 130 can be improved.

According to one embodiment of the present invention, a signal line disposed on the same layer as the capacitor electrode pattern 130 may be selected as the reference power line 15d. Accordingly, the reference power line 15d is disposed on a different layer from the data line 14 and the first power line 16, so that it can be disposed in a direction crossing the data line 14 and the first power line 16. there is.

That is, in the case of a general organic light emitting display device, the reference power line is on the same layer as the data line 14 and the first power line 16 and in the same vertical direction as the data line 14 and the first power line 16. It is placed.

On the other hand, according to one embodiment of the present invention, the reference power line 15d is arranged horizontally rather than vertically. Accordingly, by removing the reference power line in the vertical direction, the separation distance between pixel areas can be reduced by the width of the reference power line. As a result, it can be advantageous for higher resolution.

Next, a method of driving an organic light emitting display device according to an embodiment of the present invention will be described.

Figure 8 is a diagram showing a method of manufacturing an organic light emitting display device according to an embodiment of the present invention. Figures 9 to 20 are diagrams showing each process in Figure 8.

As shown in FIG. 8, the method of manufacturing an organic light emitting display device according to an embodiment of the present invention includes at least one thin film transistor (DT, T1, T2, T3, Step (S10) of disposing the active layer corresponding to T4, T5), step (S11) of disposing the gate insulating film 102 covering the active layer, and placing the active layer of any one thin film transistor on the gate insulating film 102. A step of arranging the gate electrode 120 overlapping in the channel area (S12), a step of arranging the first interlayer insulating film 103 covering the gate electrode 120 (S13), and forming a gate insulating film (S13) corresponding to the plurality of contact holes. 102) and a step of patterning the first interlayer insulating film 103 (S14), performing heat treatment on the active layer (S15), and a capacitor electrode overlapping the gate electrode 120 on the first interlayer insulating film 103. Step (S16) of arranging the pattern 130 and the reference power line 15d that supplies the reference power supply (VREF), forming a second interlayer insulating film 104 covering the capacitor electrode pattern 130 and the reference power line 15d. A step of arranging (S17), a step of patterning the second interlayer insulating film 104 corresponding to some of the plurality of contact holes (S18), and data signals of each pixel region (PXL) on the second interlayer insulating film 104. It includes a step (S19) of arranging the data line 14 that supplies (VDATA) and the first power line 16 that supplies the first driving power (VDD).

As shown in FIGS. 9 and 10, an active layer ( 110, 111, 112, 113, 114, 115) are placed. (S10) At this time, the active layers 110, 111, 112, 113, 114, and 115 are made of an undoped semiconductor material.

As shown in FIGS. 11 and 12, a gate insulating film 102 covering the active layers 110, 111, 112, 113, 114, and 115 is disposed (S11), and any one of the gate insulating films 102 is placed on the gate insulating film 102. A gate electrode 120 is disposed overlapping the active layer 110 of the thin film transistor. (S12)

At this time, in addition to the gate electrode 120, first, second, and third scan lines 15a, 15b, 15b', and 15c corresponding to each horizontal line are disposed on the gate insulating film 102.

Next, the first interlayer insulating film 103 covering the gate electrode 120 and the first, second, and third scan lines 15a, 15b, 15b', and 15c is disposed. (S13)

And, while using the conductive patterns on the gate insulating film 102, that is, the gate electrode 120, and the first, second, and third scan lines (15a, 15b, 15b', and 15c) as masks, the active layer (FIG. The doping process for numbers 110, 111, 112, 113, 114, and 115 of 9 is performed.

Accordingly, as shown in FIG. 12, each of the active layers 111 and 113 corresponding to at least one thin film transistor T1 and T3 has a channel region 111a and 113a made of an undoped semiconductor material and a layer higher than the channel region. It is composed of a structure including first and second electrode regions (111b, 111c) (113b, 113c) made of a heavily doped semiconductor material.

13 and 14, a plurality of contact holes 14_H', 15d_H, 16_H', and 130_H1 for exposing portions of the active layers 110, 111, 112, 113, 114, and 115 of each thin film transistor. , 130_H2, 141_H1', and 141_H2'), the gate insulating film 102 and the first interlayer insulating film 103 are patterned. (S14)

At this time, a first conductive contact hole 141_H1 to expose a portion of the gate electrode 120 may be further disposed through patterning of the first interlayer insulating film 103.

As shown in FIG. 15, a heat treatment process is performed on the active layers 111 and 113. (S15)

As shown in FIGS. 16 and 17, the capacitor electrode pattern 130 and the reference power line 15d are disposed on the first interlayer insulating film 103. (S16)

Here, the reference power line 15d corresponds to each horizontal line, like the first, second, and third scan lines 15a, 15b, and 15c. That is, the reference power line 15d is arranged in the horizontal direction.

The capacitor electrode pattern 130 overlaps the gate electrode 120.

This capacitor electrode pattern 130 is connected to the second layer of the active layer 111 of the first thin film transistor T1 through the first capacitor contact hole 130_H1 penetrating the gate insulating film 102 and the first interlayer insulating film 103. It is connected to the electrode area 111c.

In addition, the capacitor electrode pattern 130 is connected to the first layer of the active layer 113 of the third thin film transistor T3 through the second capacitor contact hole 130_H2 penetrating the gate insulating film 102 and the first interlayer insulating film 103. 2 Connected to the electrode area (111c).

As shown in FIG. 18, a second interlayer insulating film 104 is disposed to cover the capacitor electrode pattern 130 and the reference power line 15d. (S17)

Then, the second interlayer insulating film 104 is patterned to correspond to some of the plurality of contact holes (14_H, 16_H, 141_H1, 141_H2, and 142_H). (S18)

Here, some of the plurality of contact holes (14_H, 16_H, 141_H1, 141_H2, 142_H) are the data line 14, the first power line 16, the first and second contact holes to be disposed on the second interlayer insulating film 104. Connected to conductive patterns (141, 142).

Subsequently, as shown in FIGS. 19 and 20, the data line 14, the first power line 16, and the first and second conductive patterns 141 and 142 are disposed on the second interlayer insulating film 104. do. (S19)

At this time, the data line 14 is connected to the active layer 111 of the first thin film transistor (T1) through the data contact hole (14_H), and the first power line 16 is driven through the driving contact hole (16_H). It is connected to the active layer 110 of the thin film transistor (DT).

And, the first conductive pattern 141 is connected to the gate electrode 120 and the active layer 112 of the second thin film transistor T2 through the first and second conductive contact holes 141_H1 and 141_H2. That is, the first conductive pattern 141 corresponds to the second node ND2 and serves as a bridge pattern for connecting the gate electrode 120 and the active layer 112 of the second thin film transistor T2.

The second conductive pattern 142 is connected to the active layer 114 of the fourth thin film transistor T4 through the third conductive contact hole 142_H.

As described above, in the method of manufacturing an organic light emitting display device according to an embodiment of the present invention, before the step (S16) of arranging the capacitor electrode pattern 130, each active layer is formed by patterning at least the first interlayer insulating film 103. A step of arranging a plurality of contact holes to expose a portion of the layers 110, 111, 112, 113, 114, and 115 (S14) and heat treating the active layers 110, 111, 112, 113, 114, and 115. Step S15 is carried out.

As a result, the capacitor electrode pattern 130 is not exposed to the heat treatment process (S15) and can be made of a low-resistance metal material that is relatively vulnerable to heat treatment. As a result, the signal wire 15d can be disposed on the same layer as the capacitor electrode pattern 130, that is, on the first interlayer insulating film 103. Therefore, space utilization for the conductive layer on the first interlayer insulating film 103 can be improved.

In addition, as the reference power line 15d is disposed on a different layer from the data line 14 and the first power line 16, it will be disposed in a direction intersecting the data line 14 and the first power line 16. You can. That is, the reference power line 15d may correspond to each horizontal line.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of.

DT: Driving thin film transistor
T1, T2, T3, T4, T5: 1st, 2nd, 3rd, 4th, 5th thin film transistors
Cst: capacitor
OLED: Organic light emitting device
14: data line
15a, 15b, 15c: 1st, 2nd, 3rd scan lines
15d: Reference power line
16: 1st power line
110, 111, 112, 113, 114, 115: active layer
120: Gate electrode
130: Capacitor electrode pattern
141, 142: 1st and 2nd challenge patterns
14_H: Data contact hole
130_H1, 130_H2: first and second capacitor contact holes
15d_H: Standard power contact hole

Claims (14)

Organic light emitting elements corresponding to each of a plurality of pixel areas defined in the display area;
A driving thin film disposed in series with the organic light emitting element corresponding to each pixel area between a first power line supplying a first driving power and a second power line supplying a second driving power with a voltage lower than the first driving power. transistor; and
It includes a first thin film transistor disposed between a data line that supplies a data signal for each pixel area and a first node,
One side of the active layer of the driving thin film transistor extends toward the first power line and partially overlaps the first power line,
The first power line is connected to the active layer of the driving thin film transistor through a driving contact hole disposed in an overlapping area between the active layer of the driving thin film transistor and the first power line,
One side of the active layer of the first thin film transistor extends toward the data line and partially overlaps the data line,
The data line is connected to the active layer of the first thin film transistor through a data contact hole disposed in an overlapping area between the active layer of the first thin film transistor and the data line,
Further comprising a storage capacitor disposed between the first node and a second node connected to the gate electrode of the driving thin film transistor,
The channel region of the active layer of the driving thin film transistor overlaps the gate electrode disposed on the gate insulating film covering the active layer,
The storage capacitor corresponds to an overlap area between the gate electrode and a capacitor electrode pattern disposed on the first interlayer insulating film covering the gate electrode,
The data line and the first power line are disposed on a second interlayer insulating film covering the capacitor electrode pattern.
delete According to claim 1,
The capacitor electrode pattern is connected to the active layer of the first thin film transistor through a first capacitor contact hole disposed in an overlapping area between the other side of the active layer of the first thin film transistor and the capacitor electrode pattern,
The organic light emitting display device wherein the first capacitor contact hole overlaps the data line with the second interlayer insulating film interposed therebetween.
According to claim 3,
An organic light emitting display device wherein a channel region of the active layer of the first thin film transistor overlaps a first scan line disposed on the gate insulating film.
According to claim 3,
a second thin film transistor disposed between the second node and a third node connected to one of the first and second electrodes of the driving thin film transistor corresponding to the organic light emitting device;
a third thin film transistor disposed between the first node and a reference power line that supplies reference power to each pixel area;
a fourth thin film transistor disposed between a fourth node connected to the anode electrode of the organic light emitting device and the third node; and
The organic light emitting display device further includes a fifth thin film transistor disposed between the reference power line and the fourth node.
According to claim 5,
The reference power line is disposed on the first interlayer insulating film in a direction intersecting the data line,
The reference power line is connected to the active layer of the third thin film transistor through a reference power contact hole disposed in an overlapping area between one side of the active layer of the third thin film transistor and the reference power line,
The capacitor electrode pattern is connected to the active layer of the third thin film transistor through a second capacitor contact hole disposed in an overlapping area between the other side of the active layer of the third thin film transistor and the capacitor electrode pattern,
Each of the reference power contact hole and the second capacitor contact hole overlaps the data line with the second interlayer insulating film therebetween.
According to claim 5,
The second and fifth thin film transistors are turned on based on the second scan signal of the second scan line,
The third and fourth thin film transistors are turned on based on the emission signal of the third scan line,
The second and third scan lines are disposed on the gate insulating film.
Disposing an active layer corresponding to at least one thin film transistor included in each pixel area on a substrate;
disposing a gate insulating film covering the active layer;
disposing a gate electrode overlapping a channel region of one active layer on the gate insulating film;
disposing a first interlayer insulating film covering the gate electrode;
patterning the gate insulating layer and the first interlayer insulating layer to correspond to a plurality of contact holes;
performing heat treatment on the active layer;
Arranging a capacitor electrode pattern overlapping the gate electrode and a reference power line supplying reference power on the first interlayer insulating film;
disposing a second interlayer insulating film covering the capacitor electrode pattern;
patterning the second interlayer insulating film to correspond to some of the plurality of contact holes; and
On the second interlayer insulating film, disposing a data line for supplying data signals of each pixel area and a first power line for supplying a first driving power corresponding to driving the organic light emitting device,
At least one thin film transistor included in each pixel area is
A driving thin film transistor arranged in series with the organic light emitting element corresponding to each pixel area, and
It includes a first thin film transistor disposed between the data line and the first node,
Each pixel area further includes a storage capacitor corresponding to an overlap area between the gate electrode and the capacitor electrode pattern,
The storage capacitor is disposed between the first node and a second node connected to the gate electrode of the driving thin film transistor.
According to claim 8,
A method of manufacturing an organic light emitting display device, wherein the reference power line is disposed in a direction crossing the data line and the first power line.
According to clause 9,
At least one thin film transistor included in each pixel area is
A second thin film transistor disposed between a second node connected to the gate electrode of the driving thin film transistor and a third node connected to one of the first and second electrodes of the driving thin film transistor corresponding to the organic light emitting element,
A third thin film transistor disposed between the first node and a reference power line that supplies reference power to each pixel area,
A fourth thin film transistor disposed between the third node and a fourth node connected to the anode electrode of the organic light emitting device, and
A method of manufacturing an organic light emitting display device further comprising a fifth thin film transistor disposed between the reference power line and the fourth node.
According to claim 10,
In the step of patterning the gate insulating film and the first interlayer insulating film,
The plurality of contact holes are
A driving contact hole corresponding to one side of the active layer of the driving thin film transistor,
A data contact hole corresponding to one side of the active layer of the first thin film transistor,
a first capacitor contact hole corresponding to the other side of the active layer of the first thin film transistor, and
A reference power contact hole corresponding to one side of the active layer of the third thin film transistor,
A method of manufacturing an organic light emitting display device including a second capacitor contact hole corresponding to the other side of the active layer of the third thin film transistor.
According to claim 11,
The step of patterning the second interlayer insulating film is performed corresponding to the driving contact hole and the data contact hole among the plurality of contact holes,
In the step of arranging the data line and the first power line,
The first power line is connected to the active layer of the driving thin film transistor through the driving contact hole,
A method of manufacturing an organic light emitting display device, wherein the data line is connected to an active layer of the first thin film transistor through the data contact hole.
According to claim 11,
In the step of arranging the capacitor electrode pattern and the reference power line,
The capacitor electrode pattern is connected to the active layer of the first thin film transistor through the first capacitor contact hole and to the active layer of the third thin film transistor through the second capacitor contact hole,
The method of manufacturing an organic light emitting display device wherein the reference power line is connected to the active layer of the third thin film transistor through the reference power contact hole.
According to claim 13,
In the step of arranging the data line and the first power line,
The method of manufacturing an organic light emitting display device, wherein the data line overlaps the reference power contact hole and the first and second capacitor contact holes.

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