KR20190079856A - Organic light emitting display device and method for manufacturing the same - Google Patents

Abstract

One embodiment of the present invention provides an organic light emitting diode display apparatus capable of increasing spatial utility of a pixel area. According to one embodiment of the present invention, the organic light emitting diode display apparatus comprises: an OLED corresponding to each of a plurality of pixel areas; a driving thin film transistor arranged in series with the OLED between first and second power lines; and a first thin film transistor disposed between a first node and a data line supplying a data signal to each pixel area. One side of an active layer of the driving thin film transistor partially overlaps with the first power line and the first power line is connected to the active layer of the driving thin film transistor through a driving contact hole arranged in an overlapped area between the active layer of the driving thin film transistor and the first power line. Moreover, one side of an active layer of the first thin film transistor partially overlaps with the data line and the data line is connected to the active layer of the first thin film transistor through a data contact hole arranged in an overlapped area between the active layer of the first thin film transistor and the data line.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting display including at least one thin film transistor corresponding to each pixel region and a method of manufacturing the same.

The display device is applied to various electronic devices such as a TV, a mobile phone, a notebook, and a tablet. Therefore, studies are being continued to develop a thin display device, a light weight display device, and a low power consumption display device.

Typical examples of the display device include a liquid crystal display device (LCD), a plasma display panel (PDP), a field emission display (FED), an electroluminescence Display device (ELD), an electro-wetting display device (EWD), and an organic light emitting display device (OLED).

The organic light emitting display device includes a plurality of organic light emitting elements corresponding to a plurality of pixel regions defined in a display region in which an image is displayed. Since the organic light emitting device is a self-emitting device that emits light by itself, the organic light emitting display device has a faster response speed than a liquid crystal display device, has a high luminous efficiency, high brightness and viewing angle, and is excellent in contrast ratio and color reproducibility.

The organic light emitting display device may be implemented in an active matrix manner in which a plurality of pixel regions are individually driven. Such an active matrix type organic light emitting display includes a pixel driving circuit for supplying a driving current to an organic light emitting element corresponding to each pixel region.

The pixel driving circuit includes a driving thin film transistor connected in series with the organic light emitting element between a first driving power supply and a second driving power supply corresponding to the driving of the organic light emitting element, a switching thin film transistor for supplying a data signal of each pixel region, And supplies a turn-on signal to the gate electrode of the drive thin film transistor.

The organic light emitting display includes a plurality of conductive layers that are mutually insulated by two or more insulating layers to implement a plurality of thin film transistors, storage capacitors, and various signal lines corresponding to each pixel region. The organic light emitting diode display may further include a bridge pattern connecting between the contact hole and the contact hole passing through the at least one insulating layer to connect between the conductive layers separated by the at least one insulating layer.

In placing such a contact hole and a bridge pattern, a general organic light emitting display device can realize a bridge pattern with a conductive layer at the uppermost one of a plurality of conductive layers for a simpler manufacturing process. In this case, in order to prevent short defects and the like, the contact holes and the bridge patterns must be arranged so as to be spaced apart from each other by a distance of at least a process margin. Thus, there is a limit in improving the space utilization of each pixel region.

In addition, characteristics of the driving thin film transistor and the organic light emitting element in each pixel region may be different from each other due to the driving stress difference in each pixel region. In this case, a luminance difference between pixel regions is generated, so that image quality degradation such as a smear may be caused. In order to prevent this, the organic light emitting display device may further include a driving thin film transistor corresponding to each pixel region and a compensation circuit for compensating the characteristics of the organic light emitting element. Accordingly, in addition to the elements corresponding to the pixel driver circuits, elements for implementing the compensation circuit must be disposed in each pixel region.

Therefore, unless the space utilization of each pixel region is improved, there is a problem that there is a limit in reducing the area of the pixel region. As a result, there is a problem that the resolution of the organic light emitting display device is limited.

The present invention provides an organic light emitting display device and a method of manufacturing the same, which can improve space utilization of a pixel region and can be advantageous for high resolution.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention which are not mentioned can be understood by the following description and more clearly understood by the embodiments of the present invention. It will also be readily apparent that the objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

An exemplary embodiment of the present invention provides an organic light emitting display device including an organic light emitting element corresponding to each of a plurality of pixel regions defined in a display region, a first power supply line supplying a first driving power supply, and a second driving power supply having a voltage lower than the first driving power supply A first thin film transistor disposed between the data line supplying the data signal of each pixel region and the first node, and a second thin film transistor disposed between the data line supplying the data signal of the pixel region and the first node, An organic light emitting display device including a transistor is provided.

One side of the active layer of the driving thin film transistor extends toward the first power source line and is partially overlapped with the first power source line, and the first power source line is connected between the active layer of the driving thin film transistor and the first power source line To the active layer of the driving thin film transistor through a driving contact hole disposed in the overlapping region of the driving thin film transistor. One side of the active layer of the first thin film transistor extends to the data line side and partially overlaps the data line, and the data line is disposed in an overlapping region between the active layer and the data line of the first thin film transistor And is connected to the active layer of the first thin film transistor through a data contact hole.

The OLED display further includes a storage capacitor disposed between the first node and a second node coupled to the gate electrode of the drive thin film transistor. Here, a channel region of the active layer of the driving thin film transistor overlaps a gate electrode disposed on a gate insulating film covering the active layer, and the storage capacitor includes a capacitor electrode pattern disposed on a first interlayer insulating film covering the gate electrode, And the gate electrode. The data line and the first power supply line are disposed on a second interlayer insulating film covering the capacitor electrode pattern.

Wherein the capacitor electrode pattern is connected to the active layer of the first thin film transistor through a first capacitor contact hole disposed in an overlapping region between the other side of the active layer of the first thin film transistor and the capacitor electrode pattern, And the capacitor contact hole is overlaid on the data line with the second interlayer insulating film interposed therebetween.

Wherein the organic light emitting display includes a second thin film transistor disposed between a third node and a second node, the third node being connected to one of the first and second electrodes of the driving thin film transistor corresponding to the organic light emitting element, A fourth thin film transistor disposed between the third node and the fourth node connected to the anode electrode of the organic light emitting device, and a fourth thin film transistor disposed between the third node and the third node, And a fifth thin film transistor disposed between the reference power line and the fourth node.

Here, the reference power supply line is arranged on the first interlayer insulating film in a direction crossing the data line, and the reference power supply line is connected to the overlapping area between one side of the active layer of the third thin film transistor and the reference power supply line And is connected to the active layer of the third thin film transistor through a reference power source contact hole to be disposed. The capacitor electrode pattern is connected to the active layer of the third thin film transistor through a second capacitor contact hole disposed in an overlapping region between the other side of the active layer of the third thin film transistor and the capacitor electrode pattern, Each of the reference power source contact hole and the second capacitor contact hole is overlapped with the data line with the second interlayer insulating film interposed therebetween.

According to another embodiment of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: disposing an active layer corresponding to at least one thin film transistor included in each pixel region on a substrate; disposing a gate insulating film covering the active layer; Disposing a first interlayer insulating film covering the gate electrode; patterning the gate insulating film and the first interlayer insulating film in correspondence to the plurality of contact holes; A step of performing heat treatment on the active layer, and a step of disposing, on the first interlayer insulating film, a reference power line for supplying a capacitor electrode pattern and a reference power supply overlapping the gate electrode, Of the present invention.

The method of fabricating an organic light emitting display includes disposing a second interlayer insulating film covering the capacitor electrode pattern, patterning the second interlayer insulating film in correspondence with a part of the plurality of contact holes, Disposing a data line for supplying a data signal of each pixel region and a first power line supplying a first driving power corresponding to the driving of the organic light emitting element. Here, the reference power line is disposed in a direction crossing the data line and the first power line.

At least one thin film transistor included in each pixel region includes a driving thin film transistor arranged in series with an organic light emitting element corresponding to each pixel region, a first thin film transistor disposed between the data line and a first node, A second thin film transistor disposed between a second node connected to the gate electrode of the thin film transistor and a third node connected to one of the first and second electrodes of the driving thin film transistor corresponding to the organic light emitting element, A fourth thin film transistor disposed between the third node and the fourth node connected to the anode electrode of the organic light emitting device, and a fourth thin film transistor disposed between the third node and the third node, And a fifth thin film transistor disposed between the reference power line and the fourth node. Each of the pixel regions further includes a storage capacitor corresponding to an overlap region between the gate electrode and the capacitor electrode pattern, and the storage capacitor is disposed between the first and second nodes.

Wherein the plurality of contact holes are patterned so as to correspond to one side of the active layer of the first thin film transistor, the driving contact hole corresponding to one side of the active layer of the driving thin film transistor, the step of patterning the gate insulating film and the first interlayer insulating film, A data contact hole, a first capacitor contact hole corresponding to the other side of the active layer of the first thin film transistor, and a reference power contact hole corresponding to one side of the active layer of the third thin film transistor, And a second capacitor contact hole corresponding to the other side of the layer.

Wherein patterning the second interlayer insulating film is performed corresponding to the drive contact holes and the data contact holes among the plurality of contact holes, and in the step of disposing the data line and the first power line, A line is connected to the active layer of the driving thin film transistor through the driving contact hole and the data line is connected to the active layer of the first thin film transistor through the data contact hole.

In the step of arranging the capacitor electrode pattern and the reference power supply line, the capacitor electrode pattern is connected to the active layer of the first thin film transistor through the first capacitor contact hole, and the third capacitor contact hole And the reference power supply line is connected to the active layer of the third thin film transistor through the reference power supply contact hole.

In arranging the data line and the first power supply line, the data line overlaps the reference power contact hole and the first and second capacitor contact holes.

According to an embodiment of the present invention, a driving contact hole for connecting the first power line and the driving thin film transistor is formed in an overlap region between one side of the active layer of the driving thin film transistor extending to the first power line side and the first power line And a data contact hole for connecting between the data line and the first thin film transistor is disposed in an overlapping region between one side of the active layer of the first thin film transistor and the data line extending to the data line side.

That is, without a separate bridge pattern, the first power supply line can be connected to the driving thin film transistor through the driving contact hole. Likewise, without a separate bridge pattern, the data line can be connected to the first thin film transistor through the data contact hole. As a result, the bridge pattern for connection between the first power supply line and the driving thin film transistor and the area corresponding to the bridge pattern for connection between the data line and the first thin film transistor are not allocated, so that the space utilization of the pixel area is improved There are advantages to be able to.

According to an embodiment of the present invention, the storage capacitor corresponds to the overlap region between the gate electrode of the driving thin film transistor and the capacitor electrode pattern on the first interlayer insulating film covering the gate electrode. At this time, the capacitor electrode pattern is connected to the first thin film transistor through the first capacitor contact hole and to the third thin film transistor through the second capacitor contact hole.

That is, without a separate bridge pattern, the capacitor electrode pattern can be connected to the first and third thin film transistors through the first and second capacitor contact holes. As a result, the area corresponding to the bridge pattern for connection between the first and third thin film transistors and the capacitor electrode pattern is not allocated, so that the space utilization of the pixel region can be improved.

Also, since the bridge pattern between each of the first and third thin film transistors and the capacitor electrode pattern can be excluded, the pattern is reduced correspondingly, and foreign matter defect can be reduced.

In addition, the first and second capacitor contact holes are arranged to overlap the data lines. This has the advantage that the space utilization of the pixel region can be improved by not allocating a separate area for the first and second capacitor contact holes.

Further, according to one embodiment of the present invention, before arranging the capacitor electrode pattern, a contact hole for exposing a part of the active layer should be disposed. Thus, the heat treatment can be performed on the active layer after arranging the contact holes and before arranging the capacitor electrode pattern. That is, the capacitor electrode pattern may not be exposed to the heat treatment. Therefore, the capacitor electrode pattern can also be selected as a low-resistance metal which is vulnerable to heat treatment, and thus the signal line can be disposed on the same layer as the capacitor electrode pattern.

Particularly, when the reference power supply line is arranged in the same layer as the capacitor electrode pattern, the reference power supply line is arranged in a layer different from the data line and the first power supply line, so that it can be arranged in a direction crossing the data line and the first power supply line have. Thereby, the reference power source contact holes for connection between each of the third and fifth TFTs and the reference power source line can be arranged to overlap the data lines. Therefore, there is an advantage that the space utilization of the pixel region can be improved by not allocating a separate area for the reference power source contact hole.

In addition, as the reference power supply line corresponds to the horizontal line, as compared with the case where the reference power supply line is arranged in the same layer as the data line and the first power supply line in the vertical direction, Therefore, there is an advantage that it can be advantageous to high resolution.

1 is a view illustrating an organic light emitting display according to an embodiment of the present invention.
FIG. 2 is a diagram showing an equivalent circuit corresponding to any one of the pixel regions shown in FIG. 1. FIG.
3 is a view showing an example of a plane of a thin film transistor array substrate corresponding to the equivalent circuit of FIG.
4 is a cross-sectional view taken along the line A-A 'in FIG.
5 is a cross-sectional view taken along the line B-B 'in Fig.
6 is a cross-sectional view taken along line C-C 'of FIG.
FIG. 7 is a view showing an example of the first and third thin film transistors and the storage capacitor shown in FIG. 2 in the thin film transistor array substrate of a general organic light emitting diode display device.
8 is a view illustrating a method of manufacturing an organic light emitting display according to an embodiment of the present invention.
FIGS. 9 to 20 are views showing the respective steps of FIG.

The above and other objects, features, and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, which are not intended to limit the scope of the present invention. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to denote the same or similar elements.

Hereinafter, an OLED display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view illustrating an organic light emitting display according to an embodiment of the present invention. FIG. 2 is a diagram showing an equivalent circuit corresponding to any one of the pixel regions shown in FIG. 1. FIG.

3 is a view showing an example of a plane of a thin film transistor array substrate corresponding to the equivalent circuit of FIG. 4 is a cross-sectional view taken along the line A-A 'in FIG. 5 is a cross-sectional view taken along the line B-B 'in Fig. 6 is a cross-sectional view taken along line C-C 'of FIG.

FIG. 7 is a view showing an example of the first and third thin film transistors and the storage capacitor shown in FIG. 2 in the thin film transistor array substrate of a general organic light emitting diode display device.

1, an organic light emitting display according to an exemplary embodiment of the present invention includes a display panel 10 including a plurality of pixel regions PXL defined in a display region AA in which an image is displayed, A data driver 12 for driving the data lines 14 of the display panel 10, a gate driver 13 for driving the scan lines 15 of the display panel 10, And a timing controller (11) for controlling the driving timing of the driving circuit (13).

The display panel 10 includes a scan line 15 corresponding to each horizontal line made up of pixel regions arranged in a horizontal direction among a plurality of pixel regions PXL and a plurality of scan lines 15 corresponding to vertical lines among the plurality of pixel regions PXL And a data line 14 corresponding to each vertical line made up of pixel regions arranged side by side.

Here, the scan line 15 may include first, second and third scan lines for supplying first and second scan signals SCAN1 and SCAN2 and an emission signal EM, which are different from each other. The first scan signal SCAN may be for sequentially selecting each horizontal line during the addressing period for writing data into the pixel region PXL. The second scan signal SCAN2 may correspond to the initial period for supplying the reference power source VREF to the pixel region PXL. The emission signal EM may correspond to an emission period for supplying a driving current to the organic light emitting element.

The plurality of pixel regions PXL may be defined by the scan lines 15 and the data lines 14 intersecting with each other. Thus, the plurality of pixel regions PXL are arranged in a matrix form in the display region AA.

The display panel 10 includes a first driving power supply line for supplying a first driving power VDD to a plurality of pixel regions PXL and a second driving power VSS having a lower potential than the first driving power VDD, And a reference power supply line for supplying the reference power supply VREF.

The timing controller 11 rearranges the digital video data RGB input from the outside according to the resolution of the display panel 10 and supplies the rearranged digital video data RGB '

The timing controller 11 controls the timing of the data driver 12 based on the timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK and the data enable signal DE. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the gate driver 13 are supplied.

The data driver 12 converts the reordered digital video data RGB 'into an analog data voltage based on the data control signal DDC. Then, the data driver 12 supplies the data signal VDATA to each pixel region for each horizontal period based on the re-arranged digital video data RGB '.

The gate driver 13 may sequentially supply the first scan signal SCAN1 to the scan lines 15 of the respective horizontal lines based on the gate control signal GDC.

Although not shown separately, the display panel 10 includes a pair of substrates bonded to each other and an organic light emitting element array disposed therebetween. One of the pair of substrates is a thin film transistor array substrate for defining a plurality of pixel regions PXL and supplying driving current to the organic light emitting elements of each pixel region PXL, And may be an encapsulating substrate for sealing the array.

2, each pixel region PXL includes an organic light emitting diode OLED, a driving thin film transistor DT, first, second, third, fourth, and fifth thin film transistors T1, T2, T3, T4, and T5, and a storage capacitor Cst.

The organic light emitting device OLED includes an anode electrode, a cathode electrode, and an organic light emitting layer (not shown) disposed therebetween. Illustratively, the organic luminescent layer includes a hole injecting layer, a hole transporting layer, a light emitting layer, and an electron transporting layer. Alternatively, the organic light emitting layer may further include an electron injection layer.

The driving thin film transistor DT includes a first driving power supply line 16 for supplying a first driving power supply VDD and a second driving power supply line 16 for supplying a second driving power supply VSS having a potential lower than the first driving power supply VDD. And is disposed in series with the organic light emitting device OLED between the power supply lines.

The first thin film transistor T1 is disposed between the data line 14 and the first node ND1 for supplying the data signal VDATA of each pixel region.

When the first thin film transistor T1 is turned on based on the first scan signal SCAN1 of the first scan line 15a, the first thin film transistor T1 supplies the data signal VDATA to the first node ND1.

The storage capacitor Cst is disposed between the first node ND1 and the second node ND2 connected to the gate electrode of the driving thin film transistor DT.

The storage capacitor Cst is charged based on the data signal VDATA supplied to the first node ND1 through the turned-on first thin film transistor T1.

The driving thin film transistor DT is turned on based on the charging voltage of the storage capacitor Cst and supplies the driving current corresponding to the data signal VDATA to the third node ND3, do. Here, one of the first and second electrodes of the driving thin film transistor DT is connected to the first power supply line VDD and the other is connected to the third node ND3.

The second thin film transistor T2 is disposed between the second node ND2 and the third node ND3. Here, the second node ND2 is connected to the gate electrode of the driving thin film transistor DT, and the third node ND3 is connected to the organic light emitting element OLED among the first and second electrodes of the driving thin film transistor DT. (For example, a drain electrode). Accordingly, the second thin film transistor T2 compensates the threshold voltage of the driving thin film transistor DT.

The second thin film transistor T2 connects between the second node ND2 and the third node ND3 when the second thin film transistor T2 is turned on based on the second scan signal SCAN2 of the second scan line 15b.

The third thin film transistor T3 is disposed between the first power source line 15d and the first node ND1 for supplying the reference power source VREF to each pixel region PXL.

When the third thin film transistor T3 is turned on based on the emission signal EM of the third scan line 15c, the third thin film transistor T3 supplies the reference power source VREF to the first node ND1.

The fourth thin film transistor T4 is disposed between the fourth node ND4 and the third node ND3 connected to the anode electrode of the organic light emitting device OLED.

The fourth thin film transistor T4 connects between the third node ND3 and the fourth node ND4 when the fourth thin film transistor T4 is turned on based on the emission signal EM of the third scan line 15c.

The fifth thin film transistor T5 is disposed between the reference power supply line 15d and the fourth node ND4.

The fifth thin film transistor T5 supplies the reference power source VREF to the fourth node ND4 when the fifth thin film transistor T5 is turned on based on the second scan signal SCAN2 of the second scan line 15b.

However, the equivalent circuit of the pixel region shown in Fig. 2 is merely an example, and an embodiment of the present invention is not limited to the equivalent circuit of Fig. That is, one embodiment of the present invention includes at least one thin film transistor T3, T5 connected to the reference power supply line 15d, including the driving thin film transistor DT, the first thin film transistor T1 and the storage capacitor Cst It is obvious that the present invention can be applied to any organic light emitting display device including a pixel region PXL of an equivalent circuit. Illustratively, in addition to the 6T1C structure shown in Fig. 2, it can also be applied to equivalent circuits such as 7T1C and 8T1C.

As shown in FIG. 3, the organic light emitting display according to an embodiment of the present invention includes a driving thin film transistor (DT in FIG. 2) corresponding to each pixel region PXL, first, 4 and a fifth thin film transistor (T1, T2, T3, T4, and T5 in FIG. 2) and a storage capacitor (Cst in FIG. 2).

The organic light emitting display according to an embodiment of the present invention includes a plurality of pixel regions (PXLs in FIG. 1) having first, second, and third pixel regions corresponding to horizontal lines, Data corresponding to each vertical line consisting of the pixel regions arranged in the vertical direction among the third scan lines 15a, 15b and 15c, the reference power source line 15d and the plurality of pixel regions (PXL in Fig. 1) And further includes a line 14 and a first power supply line 16.

The channel region of the active layer 110 of the driving thin film transistor DT is superimposed on the gate electrode 120. [

Here, the gate electrode 120 is connected to the first conductive pattern 141 through the first conductive contact hole 141_H1. The first conductive pattern 141 is connected to the active layer 112 of the second thin film transistor T2 through the second conductive contact hole 141_H2. That is, since the gate electrode 120 of the driving thin film transistor DT and the second thin film transistor T2 are connected through the first conductive pattern 141, the first conductive pattern 141 is connected to the second node ND2).

One side of the active layer 110 of the driving thin film transistor DT extends toward the first power source line 16 and partially overlaps the first power source line 16. The first power line 16 is connected to the active layer 110 of the driving thin film transistor through the driving contact hole 16_H disposed in the overlapping region between the active layer 110 of the driving thin film transistor and the first power source line 16 . Here, the driving contact hole 16_H is arranged on the same line as the first power supply line 16, not the region branched from the first power supply line 16.

The other side of the active layer 110 of the driving thin film transistor corresponds to the third node (ND3 in Fig. 2), and the active layer 112 of the second thin film transistor and the active layer of the fourth thin film transistor T4 114).

The storage capacitor (Cst in Fig. 2) corresponds to the overlapping region between the gate electrode 120 and the capacitor electrode pattern 130. Fig.

The channel region of the active layer 111 of the first thin film transistor T1 is superimposed on the first scan line 15a for supplying the first scan signal SCAN1 of FIG.

One side of the active layer 111 of the first thin film transistor extends to the data line 14 side and is partially overlapped with the data line 14. The data line 14 is connected to the active layer 111 of the first thin film transistor through the data contact hole 14_H arranged in the overlapping region between the active layer 111 and the data line 14 of the first thin film transistor .

The other side of the active layer 111 of the first thin film transistor is partially overlapped with the capacitor electrode pattern 130. The capacitor electrode pattern 130 is electrically connected to the active layer 111 of the first thin film transistor through the first capacitor contact hole 130_H1 disposed in the overlapping region between the active layer 111 of the first thin film transistor and the capacitor electrode pattern 130, (Not shown).

Here, the first capacitor contact hole 130_H1 is overlaid on the data line 14.

That is, the data contact hole 14_H and the first capacitor contact hole 130_H1 are arranged on the same line as the data line 14, not the area diverged from the data line 14.

The channel region of the active layer 112 of the second thin film transistor T2 is superimposed on the second scan line 15b for supplying the second scan signal SCAN2 in FIG.

One side of the active layer 112 of the second thin film transistor is connected to the first conductive pattern 141 through the second conductive contact hole 141_H2.

The other side of the active layer 112 of the second thin film transistor corresponds to the third node (ND3 in Fig. 2), and the active layer 110 of the driving thin film transistor and the active layer 114 of the fourth thin film transistor T4, Respectively.

The channel region of the active layer 113 of the third thin film transistor T3 is superimposed on the third scan line 15c for supplying an emission signal (EM in FIG. 2).

One side of the active layer 113 of the third thin film transistor is partially overlapped with the capacitor electrode pattern 130. The capacitor electrode pattern 130 is electrically connected to the active layer 113 of the third thin film transistor through the second capacitor contact hole 130_H2 disposed in the overlapping region between the active layer 113 and the capacitor electrode pattern 130, Lt; / RTI >

Here, the second capacitor contact hole 130_H2 is superimposed on the data line 14.

In other words, the second capacitor contact hole 130_H2 is formed on the same line as the data line 14, not the area branched from the data line 14, in addition to the data contact hole 14_H and the first capacitor contact hole 130_H1 .

The channel region of the active layer 114 of the fourth thin film transistor T4 is superimposed on the third scan line 15c.

One side of the active layer 114 of the fourth thin film transistor corresponds to the third node ND3 and leads to the active layer 110 of the driving thin film transistor and the active layer 112 of the second thin film transistor.

The other side of the active layer 114 of the fourth thin film transistor is connected to the second conductive pattern 142 through the third conductive contact hole 142_H.

Although not shown in detail in FIG. 3, the second conductive pattern 142 is connected to the anode electrode of the organic light emitting element (OLED of FIG. 2) through the anode contact hole (Anode_H). That is, the second conductive pattern 142 corresponds to the fourth node (ND4 in FIG. 2).

The channel region of the active layer 115 of the fifth thin film transistor T5 is superimposed on the branched region of the couple line 15b 'of the second scan line supplying the second scan signal (SCAN2 of FIG. 2).

One side of the active layer 115 of the fifth thin film transistor extends to the reference power supply line 15d side that supplies the reference power supply (VREF in FIG. 2) and partially overlaps the reference power supply line 15d. The reference power supply line 15d is connected to the active layer of the fifth thin film transistor through the reference power supply contact hole 15d_H disposed in the overlap region between the active layer 115 and the reference power supply line 15d of the fifth thin film transistor 115).

Here, the reference power source contact hole 15d_H is superposed on the data line 14.

That is, since the reference power supply line 15d is arranged in the direction crossing the data line 14, an overlap region is generated between the reference power supply line 15d and the data line 14. [ One side of the active layer 115 of the fifth thin film transistor is extended to the overlapping region between the reference power supply line 15d and the data line 14 so that the reference power supply contact hole 15d_H overlaps the data line 14 .

In addition, the reference power contact hole 15d_H is connected to the data line 14 instead of the region branched from the data line 14, similarly to the data contact hole 14_H and the first and second capacitor contact holes 130_H1 and 130_H2. As shown in FIG.

The other side of the active layer 115 of the fifth thin film transistor corresponds to the fourth node (ND4 in Fig. 2) and leads to the active layer 114 of the fourth thin film transistor.

As described above, according to an embodiment of the present invention, the first power source line 16 is connected to the active layer 110 of the driving thin film transistor through the driving contact hole 16_H located in the same line as the first power source line 16, Lt; / RTI > Therefore, since a separate bridge pattern for connecting the first power line 16 and the active layer 110 of the driving thin film transistor can be eliminated, space utilization of the pixel region PXL can be improved accordingly.

Likewise, the data line 14 is connected directly to the active layer 111 of the first thin film transistor through the data contact hole 14_H located co-linear with the data line 14. [ Therefore, since a separate bridge pattern for connecting the data line 14 and the active layer 111 of the first thin film transistor can be eliminated, space utilization of the pixel region PXL can be improved accordingly.

The data contact hole 14_H, the reference power source contact hole 15d_H and the first and second capacitor contact holes 130_H1 and 130_H2 are all arranged so as to overlap the data line 14. Therefore, the space utilization of the pixel region PXL is reduced by not allocating a separate area for the data contact hole 14_H, the reference power source contact hole 15d_H, and the first and second capacitor contact holes 130_H1 and 130_H2 Can be improved.

5, the active layer 111 of the first thin film transistor T1 is disposed on the substrate 101 and covered with the gate insulating film 102. [

Then, the first scan line 15a is disposed on the gate insulating film 102.

The gate electrode 120 of the second scan line 15b, the couple line 15b 'of the second scan line, the third scan line 15c and the drive thin film transistor T1, as in the case of the first scan line 15a, Is disposed on the gate insulating film 102.

The capacitor electrode pattern 130 corresponding to the storage capacitor Cst is disposed on the first interlayer insulating film 103 covering the gate electrode 120. [ The storage capacitor Cst corresponds to a region where the gate electrode 120 and the capacitor electrode pattern 130 overlap with each other with the first interlayer insulating film 103 interposed therebetween.

Similar to the capacitor electrode pattern 130, the reference power supply line 15d is disposed on the first interlayer insulating film 103. [

The data line 14 is disposed on the second interlayer insulating film 104 covering the capacitor electrode pattern 130 and the reference power supply line 15d.

The active layer 111 of the first thin film transistor has a channel region 111a overlapping the first scan line 15a on the gate insulating film 102 and a first and a second electrodes 111a, And regions 111b and 111c.

The first electrode region 111b of the active layer 111 of the first thin film transistor is connected to the data line 14 on the second interlayer insulating film 104 through the data contact hole 14_H, The region 111c may be connected to the capacitor electrode pattern 130 on the first interlayer insulating film 103 through the first capacitor contact hole 130_H1.

The active layer 113 of the third thin film transistor T3 is disposed on the substrate 101 and is covered with the gate insulating film 102. The active layer 113 covers the channel region overlapping the third scan line 15c on the gate insulating film 102, And first and second electrode regions 113b and 113c corresponding to both sides of the channel region 113a.

For example, the first electrode region 113b of the active layer 113 of the third thin film transistor is connected to the reference power supply line 15d on the first interlayer insulating film 103 through the reference power supply contact hole 15d_H, The second electrode region 113c may be connected to the capacitor electrode pattern 130 on the first interlayer insulating film 103 through the second capacitor contact hole 130_H2.

4, the data contact hole 14_H, the reference power source contact hole 15d_H, and the first and second capacitor contact holes 130_H1 and 130_H2 all overlap the data line 14. As shown in FIG.

5 and 6, the first power supply line 16, the first and second conductive patterns 141 and 142 are arranged on the second interlayer insulating film 104 in the same manner as the data lines 14 do.

An anode electrode of the organic light emitting element OLED of FIG. 2 is connected to the data line 14, the first power supply line 16, the overcoat layer 105 covering the first and second conductive patterns 141 and 142, ). ≪ / RTI > In this case, the anode electrode may be connected to the second conductive pattern 142 through an anode contact hole (Anode_H) passing through the overcoat film 105.

The second conductive pattern 142 is connected to the active layer 114 of the fourth thin film transistor T4 through the third conductive contact hole 142_H.

The active layer 110 of the driving thin film transistor DT is disposed on the substrate 101 and covered with the gate insulating film 102 and has a channel region 110a overlapping the gate electrode 120 on the gate insulating film 102, And first and second electrode regions 110b and 110c corresponding to both sides of the channel region 110a.

The first electrode region 110b of the active layer 110 of the driving thin film transistor is connected to the first power source line 16 on the second interlayer insulating film 104 through the driving contact hole 16_H, The electrode region 110c may lead to the active layer 114 of the fourth thin film transistor T4.

The active layer 114 of the fourth thin film transistor T4 is disposed on the substrate 101 and is covered with the gate insulating film 102 and has a channel region overlapping with the third scan line 15c on the gate insulating film 102. [ And first and second electrode regions 114b and 114c corresponding to both sides of the channel region 114a.

The first electrode region 114b of the active layer 114 of the fourth thin film transistor is connected to the active layer 110 of the driving thin film transistor and the second electrode region 114c is connected to the third conductive contact hole 142_H To the second conductive pattern 142 on the second interlayer insulating film 104.

As shown in Fig. 6, the second electrode region 114c of the active layer 114 of the fourth thin film transistor also extends to the active layer 115 of the fifth thin film transistor T5.

The active layer 115 of the fifth thin film transistor T5 is disposed on the substrate 101 and covered with the gate insulating film 102 and is connected to the couple line 15b 'of the second scan line on the gate insulating film 102 And includes first and second electrode regions 115a and 115b corresponding to both sides of the channel region 115a.

The first electrode region 115b of the active layer 115 of the fifth thin film transistor is connected to the active layer 113 of the third thin film transistor T3 and the second electrode region 115c is connected to the fourth thin film transistor T3, Lt; RTI ID = 0.0 > T4. ≪ / RTI >

Here, as shown in FIG. 4, the first electrode region 113b of the active layer 113 of the third thin film transistor T3 is connected to the reference power source line 16.

6, the first electrode region 115b of the active layer 115 of the fifth thin film transistor T5 is connected to the first electrode region 115b of the active layer 113 of the third thin film transistor T3, The first electrode region 115b of the active layer 115 of the fifth thin film transistor T5 is also connected to the reference power source line 16 since the second electrode region 113b is connected to the first electrode region 113b.

The active layer 112 of the second thin film transistor T2 is disposed on the substrate 101 and covered with the gate insulating film 102. [

The active layer 112 of the second thin film transistor T2 includes first and second channel regions 112a and 112b which overlap the second scan line 15b on the gate insulating film 102 and first and second channel regions 112a and 112b A second electrode region 112d corresponding to one side of the second channel region 112b and a second electrode region 112d corresponding to one side of the first and second channel regions 112a and 112b, And a connection region 112e.

The first electrode region 112c of the active layer 112 of the second thin film transistor is connected to the driving thin film transistor DT through the first and second conductive contact holes 141_H1 and 141_H2 and the first conductive pattern 141, And the second electrode region 112d may be connected to the active layer 114 of the fourth thin film transistor.

2, a general organic light emitting diode display also includes a storage capacitor Cst disposed between a first node ND1 and a second node ND2, a first and a second capacitors Cst and Cst connected to the first node ND1, And third thin film transistors T1 and T3.

7, the storage capacitor Cst is connected to the gate electrode 120 on the gate insulating film 102 and the capacitor electrode pattern CP on the first interlayer insulating film 103. In this case, In the overlapping region.

The capacitor electrode pattern CP corresponding to the first node ND1 is connected to each of the first and third thin film transistors T1 and T3 through the bridge pattern BP. Here, the bridge pattern BP is disposed on the second interlayer insulating film 104 corresponding to the uppermost one of the plurality of insulating films 102, 103, and 104. Thus, the bridge pattern BP is disposed in a layer different from both the active layers 111 and 113 and the capacitor electrode pattern CP of the first and third thin film transistors T1 and T3. Therefore, the bridge pattern BP is electrically connected to the active layers 111 and 113 of the first and third thin film transistors T1 and T3 through the first, second and third bridge contact holes BP_H1, BP_H2 and BP_H3, And can be connected to the electrode pattern CP.

Since the first, second, and third bridge contact holes BP_H1, BP_H2, and BP_H3 must be spaced apart from each other on the same plane, the first, second, and third bridge contact holes (BP_H1, BP_H2, BP_H3) must be allocated separately. In addition, an area corresponding to the bridge pattern BP must be separately allocated to each pixel region PXL. Therefore, there is a problem that space utilization of the pixel region is improved.

In addition, the first, second and third bridge contact holes BP_H1, BP_H2 and BP_H3 pass through the second interlayer insulating film 104, and the capacitor electrode pattern CP is formed by the second interlayer insulating film 104, become. Accordingly, the capacitor electrode pattern CP is exposed to the heat treatment process performed after the first, second, and third bridge contact holes BP_H1, BP_H2, and BP_H3 are disposed. Therefore, the capacitor electrode pattern CP needs to be made of a high-resistance metal material such as Mo (molybdenum) or the like which is relatively strong for the heat treatment. Thus, there is a problem that it is difficult to arrange the signal line on the same layer as the capacitor electrode pattern CP. That is, signal lines arranged on the same layer as the capacitor electrode pattern CP have a wide width due to high resistance, which is not suitable for high resolution.

Alternatively, according to an embodiment of the present invention, the capacitor electrode pattern 130 may be directly connected to the first and third thin film transistors T1 and T3 through the first and second capacitor contact holes 130_H1 and 130_H2 do. Therefore, since a separate bridge pattern for connecting each of the first and third thin film transistors T1 and T3 and the capacitor electrode pattern 130 can be removed, the area corresponding to the bridge pattern is not allocated, There is an advantage that the space utilization of the space can be improved.

In addition, unlike a general organic light emitting display device, the bridging pattern is excluded from the layer where the data line 14 and the first power supply line 16 are disposed, so that foreign matter defect can be reduced.

The first and second capacitor contact holes 130_H1 and 130_H2 penetrate the gate insulating film 102 and the first interlayer insulating film 103 and the capacitor electrode pattern 130 is formed on the first interlayer insulating film 103 . Therefore, the heat treatment process can be performed between the process of disposing the first and second capacitor contact holes 130_H1 and 130_H2 and disposing the capacitor electrode pattern 130. [ Thus, since the capacitor electrode pattern 130 is not exposed to the heat treatment process, the capacitor electrode pattern 130 can also be selected as a low resistance metal which is relatively vulnerable to the heat treatment process. Illustratively, low resistance metals include Al (aluminum). Accordingly, since the signal line can be disposed on the same layer as the capacitor electrode pattern 130, the utilization of the conductive layer corresponding to the capacitor electrode pattern 130 can be improved.

According to an embodiment of the present invention, a signal line arranged on the same layer as the capacitor electrode pattern 130 may be selected as the reference power supply line 15d. The reference power supply line 15d may be disposed in a different layer from the data line 14 and the first power supply line 16 so that the reference power supply line 15d may be disposed in a direction crossing the data line 14 and the first power supply line 16. [ have.

That is, in the case of a general organic light emitting display, the reference power supply line is formed in the same layer as the data line 14 and the first power supply line 16, in the same vertical direction as the data line 14 and the first power supply line 16 .

On the other hand, according to one embodiment of the present invention, the reference power supply line 15d is arranged in the horizontal direction, not in the vertical direction. Thus, by removing the reference power supply line in the vertical direction, the distance between the pixel regions can be reduced by the width of the reference power supply line. Therefore, it can be advantageous for higher resolution.

Next, a driving method of an OLED display according to an embodiment of the present invention will be described.

8 is a view illustrating a method of manufacturing an organic light emitting display according to an embodiment of the present invention. FIGS. 9 to 20 are views showing the respective steps of FIG.

8, a method of manufacturing an organic light emitting display according to an exemplary embodiment of the present invention includes forming at least one thin film transistor DT, T1, T2, T3, and T3 included in each pixel region PXL on a substrate, A step S11 of disposing a gate insulating film 102 covering the active layer, a step S11 of arranging an active layer corresponding to one of the thin film transistors T4 and T5 on the gate insulating film 102, A step (S12) of disposing a gate electrode (120) superimposed on the channel region, a step (S13) of arranging a first interlayer insulating film (103) covering the gate electrode (120) A step S15 of patterning the first interlayer insulating film 102 and the first interlayer insulating film 103 and a step S15 of performing a heat treatment on the active layer, A step S16 of arranging a pattern 130 and a reference power supply line 15d for supplying a reference power supply VREF, A step (S17) of disposing a second interlayer insulating film 104 covering the sheeter electrode pattern 130 and the reference power supply line 15d, a step of patterning the second interlayer insulating film 104 corresponding to a part of the plurality of contact holes A data line 14 for supplying a data signal VDATA of each pixel region PXL and a first power supply line VDD for supplying a first driving power VDD are formed on the second interlayer insulating film 104, (S19).

The active layer corresponding to at least one thin film transistor DT, T1, T2, T3, T4, and T5 included in each pixel region PXL is formed on the substrate 101 as shown in FIGS. 9 and 10 110, 111, 112, 113, 114, and 115 are disposed. (S10) At this time, the active layers 110, 111, 112, 113, 114, and 115 are made of undoped semiconductor material.

11 and 12, the gate insulating film 102 covering the active layers 110, 111, 112, 113, 114, and 115 is disposed (S11), and a gate insulating film 102 is formed on the gate insulating film 102 A gate electrode 120 overlapping the active layer 110 of the thin film transistor is disposed. (S12)

At this time, the first, second and third scan lines 15a, 15b, 15b ', and 15c corresponding to the respective horizontal lines are disposed on the gate insulating film 102 together with the gate electrode 120.

Next, a first interlayer insulating film 103 covering the gate electrode 120, the first, second and third scan lines 15a, 15b, 15b ', and 15c is disposed. (S13)

Using the conductive patterns on the gate insulating film 102, that is, the gate electrode 120, the first, second and third scan lines 15a, 15b, 15b 'and 15c as masks, 9, 110, 111, 112, 113, 114, and 115).

12, each of the active layers 111 and 113 corresponding to at least one thin film transistor T1 and T3 has channel regions 111a and 113a made of undoped semiconductor material, And first and second electrode regions 111b, 111c (113b, 113c) made of a semiconductor material doped with a predetermined concentration.

A plurality of contact holes 14_H ', 15d_H, 16_H', and 130_H1 for exposing a part of the active layers 110, 111, 112, 113, 114 and 115 of the respective thin film transistors, , 130_H2, 141_H1 ', and 141_H2', the gate insulating film 102 and the first interlayer insulating film 103 are patterned. (S14)

At this time, the first conductive contact hole 141_H1 for exposing a part of the gate electrode 120 through the patterning of the first interlayer insulating film 103 may be further disposed.

As shown in Fig. 15, the active layers 111 and 113 are subjected to a heat treatment process. (S15)

The capacitor electrode pattern 130 and the reference power supply line 15d are disposed on the first interlayer insulating film 103 as shown in Figs. (S16)

Here, the reference power supply line 15d corresponds to each horizontal line like the first, second and third scan lines 15a, 15b and 15c. That is, the reference power supply line 15d is arranged in the horizontal direction.

The capacitor electrode pattern 130 is superimposed on the gate electrode 120.

This capacitor electrode pattern 130 is electrically connected to the second electrode of the active layer 111 of the first thin film transistor Tl through the first capacitor contact hole 130_H1 passing through the gate insulating film 102 and the first interlayer insulating film 103 And is connected to the electrode region 111c.

The capacitor electrode pattern 130 is formed on the active layer 113 of the third thin film transistor T3 through the gate insulating film 102 and the second capacitor contact hole 130_H2 passing through the first interlayer insulating film 103 And is connected to the second electrode region 111c.

The second interlayer insulating film 104 covering the capacitor electrode pattern 130 and the reference power supply line 15d is disposed as shown in FIG. (S17)

Then, the second interlayer insulating film 104 is patterned corresponding to a part (14_H, 16_H, 141_H1, 141_H2, 142_H) of the plurality of contact holes. (S18)

Here, a part (14_H, 16_H, 141_H1, 141_H2, 142_H) of the plurality of contact holes includes a data line 14 to be disposed on the second interlayer insulating film 104, a first power source line 16, Conductive patterns 141 and 142, respectively.

19 and 20, the data line 14, the first power source line 16, the first and second conductive patterns 141 and 142 are disposed on the second interlayer insulating film 104 do. (S19)

At this time, the data line 14 is connected to the active layer 111 of the first thin film transistor T1 through the data contact hole 14_H, and the first power line 16 is driven through the driving contact hole 16_H And is connected to the active layer 110 of the thin film transistor DT.

The first conductive pattern 141 is connected to the gate electrode 120 and the active layer 112 of the second thin film transistor T2 through the first and second conductive contact holes 141_H1 and 141_H2. That is, the first conductive pattern 141 corresponds to the second node ND2 and becomes a bridge pattern for connecting between the gate electrode 120 and the active layer 112 of the second thin film transistor T2.

The second conductive pattern 142 is connected to the active layer 114 of the fourth thin film transistor T4 through the third conductive contact hole 142_H.

As described above, in the method of manufacturing an organic light emitting diode display according to an embodiment of the present invention, before the step S16 of arranging the capacitor electrode pattern 130, at least the first interlayer insulating film 103 is patterned, A step S14 of arranging a plurality of contact holes for exposing a part of the layers 110, 111, 112, 113, 114 and 115 and a step S14 of heat treating the active layers 110, 111, 112, 113, 114 and 115 Step S15 is performed.

Thus, the capacitor electrode pattern 130 is not exposed to the heat treatment step S15, and thus can be made of a low resistance metal material which is relatively vulnerable to heat treatment. Thus, the signal wiring 15d can be disposed on the same layer as the capacitor electrode pattern 130, that is, on the first interlayer insulating film 103. [ Therefore, space utilization for the conductive layer on the first interlayer insulating film 103 can be improved.

In addition, the reference power line 15d is disposed in a different layer from the data line 14 and the first power line 16, so that the reference power line 15d is disposed in a direction intersecting the data line 14 and the first power line 16 . That is, the reference power supply line 15d may correspond to each horizontal line.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

DT: driving thin film transistor
T1, T2, T3, T4, T5: first, second, third, fourth, fifth thin film transistors
Cst: Capacitor
OLED: Organic light emitting device
14: Data line
15a, 15b and 15c: first, second and third scan lines
15d: Reference power line
16: first power supply line
110, 111, 112, 113, 114, 115: active layer
120: gate electrode
130: capacitor electrode pattern
141, 142: first and second conductive patterns
14_H: Data contact hole
130_H1, 130_H2: First and second capacitor contact holes
15d_H: Reference power supply contact hole

Claims (14)

An organic light emitting element corresponding to each of the plurality of pixel regions defined in the display region;
A driving circuit which is arranged in series with an organic light emitting element corresponding to each pixel region between a first power supply line for supplying a first driving power supply and a second power supply line for supplying a second driving power supply voltage lower than the first driving power supply, Thin film transistor; And
And a first thin film transistor disposed between a first node and a data line for supplying a data signal of each pixel region,
Wherein one side of the active layer of the driving thin film transistor extends toward the first power source line and is partially overlapped with the first power source line,
The first power line is connected to the active layer of the driving thin film transistor through a driving contact hole disposed in an overlapping region between the active layer of the driving thin film transistor and the first power line,
One side of the active layer of the first thin film transistor extends to the data line side and is partially overlapped with the data line,
Wherein the data line is connected to the active layer of the first thin film transistor through a data contact hole disposed in an overlapping region between the active layer of the first thin film transistor and the data line.
The method according to claim 1,
Further comprising a storage capacitor disposed between the first node and a second node coupled to the gate electrode of the drive thin film transistor,
Wherein the channel region of the active layer of the driving thin film transistor overlaps the gate electrode disposed on the gate insulating film covering the active layer,
Wherein the storage capacitor corresponds to an overlapping region between the capacitor electrode pattern disposed on the first interlayer insulating film covering the gate electrode and the gate electrode,
Wherein the data line and the first power line are disposed on a second interlayer insulating film covering the capacitor electrode pattern.
3. The method of claim 2,
The capacitor electrode pattern is connected to the active layer of the first thin film transistor through a first capacitor contact hole disposed in an overlapping region between the other side of the active layer of the first thin film transistor and the capacitor electrode pattern,
And the first capacitor contact hole overlaps the data line with the second interlayer insulating film interposed therebetween.
The method of claim 3,
Wherein a channel region of the active layer of the first thin film transistor overlaps a first scan line disposed on the gate insulating film.
The method of claim 3,
A second thin film transistor disposed between the second node and a third node connected to one of the first and second electrodes of the driving thin film transistor corresponding to the organic light emitting element;
A third thin film transistor disposed between the first power supply line and the first node for supplying a reference power supply to each pixel region;
A fourth thin film transistor disposed between a fourth node connected to an anode electrode of the organic light emitting device and the third node; And
And a fifth thin film transistor disposed between the reference power line and the fourth node.
6. The method of claim 5,
The reference power supply line is disposed on the first interlayer insulating film in a direction crossing the data line,
The reference power supply line is connected to the active layer of the third thin film transistor through a reference power supply contact hole disposed in an overlapping region between one side of the active layer of the third thin film transistor and the reference power supply line,
The capacitor electrode pattern is connected to the active layer of the third thin film transistor through a second capacitor contact hole disposed in an overlapping region between the other side of the active layer of the third thin film transistor and the capacitor electrode pattern,
Wherein each of the reference power contact hole and the second capacitor contact hole is overlapped with the data line with the second interlayer insulating film interposed therebetween.
6. The method of claim 5,
The second and fifth TFTs are turned on based on the second scan signal of the second scan line,
The third and fourth thin film transistors are turned on based on the emission signal of the third scan line,
And the second and third scan lines are disposed on the gate insulating layer.
Disposing an active layer corresponding to at least one thin film transistor included in each pixel region on a substrate;
Disposing a gate insulating film covering the active layer;
Disposing a gate electrode overlying the channel region of one of the active layers on the gate insulating film;
Disposing a first interlayer insulating film covering the gate electrode;
Patterning the gate insulating film and the first interlayer insulating film in correspondence with the plurality of contact holes;
Performing a heat treatment on the active layer; And
And disposing, on the first interlayer insulating film, a capacitor electrode pattern overlapping the gate electrode and a reference power supply line for supplying a reference power supply.
9. The method of claim 8,
Disposing a second interlayer insulating film covering the capacitor electrode pattern;
Patterning the second interlayer insulating film corresponding to a part of the plurality of contact holes; And
Further comprising disposing, on the second interlayer insulating film, a first power supply line for supplying a data line for supplying a data signal of each pixel region and a first driving power supply corresponding to driving of the organic light emitting element,
Wherein the reference power line is disposed in a direction crossing the data line and the first power line.
10. The method of claim 9,
At least one thin film transistor included in each pixel region
A driving thin film transistor arranged in series with the organic light emitting element corresponding to each pixel region,
A first thin film transistor disposed between the data line and the first node,
A second thin film transistor disposed between a second node connected to the gate electrode of the driving thin film transistor and a third node connected to one of the first and second electrodes of the driving thin film transistor corresponding to the organic light emitting element,
A third thin film transistor disposed between the first node and a reference power supply line for supplying a reference power to each pixel region,
A fourth thin film transistor disposed between a fourth node connected to the anode electrode of the organic light emitting element and the third node,
And a fifth thin film transistor disposed between the reference power supply line and the fourth node,
Wherein each pixel region further includes a storage capacitor corresponding to an overlapping region between the gate electrode and the capacitor electrode pattern,
Wherein the storage capacitor is disposed between the first and second nodes.
11. The method of claim 10,
In the step of patterning the gate insulating film and the first interlayer insulating film,
The plurality of contact holes
A driving contact hole corresponding to one side of the active layer of the driving thin film transistor,
A data contact hole corresponding to one side of the active layer of the first thin film transistor,
A first capacitor contact hole corresponding to the other side of the active layer of the first thin film transistor,
A reference power source contact hole corresponding to one side of the active layer of the third thin film transistor,
And a second capacitor contact hole corresponding to the other side of the active layer of the third thin film transistor.
12. The method of claim 11,
Wherein patterning the second interlayer insulating film is performed corresponding to the drive contact holes and the data contact holes among the plurality of contact holes,
In the step of arranging the data line and the first power supply line,
The first power supply line is connected to the active layer of the driving thin film transistor through the driving contact hole,
Wherein the data line is connected to the active layer of the first thin film transistor through the data contact hole.
12. The method of claim 11,
In the step of arranging the capacitor electrode pattern and the reference power supply line,
The capacitor electrode pattern is connected to the active layer of the first thin film transistor through the first capacitor contact hole and to the active layer of the third thin film transistor through the second capacitor contact hole,
Wherein the reference power supply line is connected to the active layer of the third thin film transistor through the reference power supply contact hole.
14. The method of claim 13,
In the step of arranging the data line and the first power supply line,
Wherein the data line overlaps the reference power contact hole and the first and second capacitor contact holes.

Images