KR102536731B1 - Organic light emitting display device - Google Patents

Abstract

According to an embodiment of the present invention, an organic light emitting element corresponding to each of a plurality of pixel areas defined in a display area, a first power line supplying a first driving power corresponding to driving of the organic light emitting element, and the first driving power A first thin film transistor disposed in series with the organic light emitting element between a second power supply line supplying a second driving power supply of a lower voltage, and a data line supplying a data signal of each pixel area and the first thin film transistor An organic light emitting display device including a second thin film transistor disposed between nodes corresponding to a gate electrode of the first thin film transistor, wherein the second thin film transistor is disposed above the first thin film transistor and partially overlaps the first thin film transistor. do.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present invention relates to an organic light emitting display device including an organic light emitting element corresponding to each pixel area.

Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. Accordingly, research is being conducted to develop thinning, lightening, and low power consumption of display devices.

Representative examples of the display device include a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an electro luminescence display device. Display device: ELD), Electro-Wetting Display device (EWD), Organic Light Emitting Display device (OLED), and the like.

Among them, an organic light emitting display device includes a plurality of organic light emitting elements corresponding to a plurality of pixel areas defined in a display area where an image is displayed. Since the organic light emitting device is a self-emitting device that emits light by itself, the organic light emitting display device has advantages in that it has a fast response speed, high luminous efficiency, luminance and viewing angle, and excellent contrast ratio and color gamut compared to liquid crystal display devices.

An organic light emitting display device may be implemented in an active matrix method that individually drives a plurality of pixel areas. Such an active matrix organic light emitting display device includes a pixel driving circuit for supplying a driving current to an organic light emitting element corresponding to each pixel area.

The pixel driving circuit includes a driving thin film transistor connected in series with the organic light emitting element between a first driving power supply and a second driving power supply corresponding to driving of the organic light emitting element, and a switching thin film transistor supplying a data signal to each pixel area. It is common to do

That is, a general organic light emitting display device includes a driving thin film transistor and a switching thin film transistor disposed in each pixel area. At this time, since the driving thin film transistor and the switching thin film transistor are disposed on the same plane, they correspond to different partial areas of each pixel area.

On the other hand, there is a recent demand for higher resolution display devices for clearer picture quality, and as a result, the area of each pixel region tends to be reduced. In particular, in the case of a 3D VR device (3-Dimension Virtual Reality Device), the area of each pixel region can be reduced by 1/20 times or more compared to a general display device.

In this way, as the area of each pixel area is reduced, the area of the area where each of the two or more thin film transistors corresponding to each pixel area is disposed is reduced. That is, the channel width and channel length of the thin film transistor are reduced by the reduced area of the pixel region. As a result, as the Kink Effect is intensified, the voltage-current characteristics of the thin film transistor deteriorate.

In particular, if the uniformity of the voltage-current (Vds-Ids) characteristics of the driving thin film transistor is lowered, the luminance of the organic light emitting element in each pixel area cannot be stably controlled, so the image quality of the display device may deteriorate. there is.

An object of the present invention is to provide an organic light emitting display device capable of preventing deterioration of characteristics of a thin film transistor even in a reduced area of a pixel area.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned above can be understood by the following description and will be more clearly understood by the examples of the present invention. It will also be readily apparent that the objects and advantages of the present invention may be realized by means of the instrumentalities and combinations indicated in the claims.

An example of the present invention is an organic light emitting element corresponding to each of a plurality of pixel areas defined in a display area, a first power line for supplying a first driving power corresponding to driving of the organic light emitting element, and a first driving power source. A first thin film transistor arranged in series with the organic light emitting element between a second power supply line supplying a second low voltage driving power supply, and a data line supplying a data signal of each pixel area and the first thin film transistor An organic light emitting display device including a second thin film transistor disposed between nodes corresponding to a gate electrode, wherein the second thin film transistor is disposed above the first thin film transistor and partially overlaps the first thin film transistor. .

The organic light emitting display device further includes a bias pattern disposed on a layer between the first and second thin film transistors and insulated from each of the first and second thin film transistors.

The first thin film transistor includes a gate electrode disposed on a substrate and a first active layer disposed on a first gate insulating layer covering the gate electrode and partially overlapping the gate electrode, and the bias pattern is formed on the first gate insulating layer. It is disposed on the first bias insulating layer covering the active layer and overlaps the gate electrode.

The organic light emitting display device further includes a scan line corresponding to each horizontal line made up of pixel areas arranged in parallel in a horizontal direction among the plurality of pixel areas, and the second thin film transistor covers the bias pattern. A second active layer disposed on a bias insulating layer and partially overlapping the bias pattern, and the scan line is disposed on a second gate insulating layer covering the second active layer and partially overlapping the second active layer.

The first active layer includes a first channel region overlapping the gate electrode and first and second electrode regions corresponding to both sides of the first channel region, and the second active layer overlaps the scan line. and third and fourth electrode regions corresponding to both sides of the second channel region. The first channel region and the second channel region at least partially overlap each other, and the bias pattern corresponds to at least an overlapping region of the first and second channel regions.

One of the first and second electrode regions is connected to the first power line and the other is connected to a first conductive pattern, and each of the first power line, the data line, and the first conductive pattern is connected to each other. spaced apart from each other and disposed on a first interlayer insulating film covering the scan line.

One of the third and fourth electrode regions is connected to the data line and the other is connected to the gate electrode.

In the longitudinal direction of the first channel region, the bias pattern is longer than the gate electrode, and the first active layer is disposed between at least one of the first and second electrode regions and the first channel region. and a buffer region doped at a lower concentration than the first and second electrode regions.

An organic light emitting display device according to an exemplary embodiment of the present invention includes a first thin film transistor disposed in series with an organic light emitting element in each pixel area, and a second thin film transistor disposed above the first thin film transistor and partially overlapping the first thin film transistor. It includes a thin film transistor.

That is, as the first and second thin film transistors are disposed on different planes, they may be disposed to overlap each other. Accordingly, more efficient integration can be realized in element arrangement of each pixel region, and voltage-current characteristic deterioration of the thin film transistor due to the reduced area of the pixel region can be prevented. In addition, since the deterioration of the image quality of the display device can be prevented even in the pixel area of the reduced area, there is an advantage that can be advantageous for high resolution.

1 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating an example of an equivalent circuit corresponding to one pixel area in the organic light emitting display device of FIG. 1 .
FIG. 3 is a diagram showing an example of a plane of a thin film transistor array substrate corresponding to the equivalent circuit of FIG. 2 .
FIG. 4 is a view showing a cross section AA′ of FIG. 3 .
FIG. 5 is a view showing a cross section BB′ of FIG. 3 .
6 is a view showing a cross section AA′ of FIG. 3 according to another embodiment of the present invention.
7 to 21 are views illustrating each process of a method of manufacturing an organic light emitting display device according to an exemplary embodiment of the present invention.

The above objects, features and advantages will be described later in detail with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention belongs will be able to easily implement the technical spirit of the present invention. In describing the present invention, if it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

Hereinafter, an organic light emitting display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating an example of an equivalent circuit corresponding to one pixel area in the organic light emitting display device of FIG. 1 .

FIG. 3 is a diagram showing an example of a plane of a thin film transistor array substrate corresponding to the equivalent circuit of FIG. 2 . FIG. 4 is a view showing a cross section taken along line A-A' of FIG. 3 . FIG. 5 is a view showing a cross section BB′ of FIG. 3 . 6 is a view showing a cross section taken along line A-A' of FIG. 3 according to another embodiment of the present invention.

As shown in FIG. 1, an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 including a plurality of pixel areas PXL corresponding to a display area AA where an image is displayed; The data driver 12 driving the data line 14 of the display panel 10, the gate driver 13 driving the scan line 15 of the display panel 10, the data driver 12 and the gate driver and a timing controller 11 for controlling the drive timing of (13).

The display panel 10 includes a scan line 15 corresponding to each horizontal line made up of pixel areas arranged in parallel in a horizontal direction among a plurality of pixel areas PXL, and a scan line 15 corresponding to a vertical direction among the plurality of pixel areas PXL. It includes a data line 14 corresponding to each vertical line made up of pixel areas arranged in parallel.

Here, the scan signal SCAN1 by the scan line 15 may be used to sequentially select each horizontal line in order to write data in the pixel area PXL.

The plurality of pixel areas PXL may be defined by the scan lines 15 and the data lines 14 crossing each other. Accordingly, the plurality of pixel areas PXL are arranged in a matrix form in the display area AA.

Further, the display panel 10 includes a first driving power line for supplying the first driving power source VDD to the plurality of pixel regions PXL, and a second driving power source VSS having a lower potential than the first driving power source VDD. ) It further includes a second driving power line for supplying.

The timing controller 11 rearranges digital video data RGB input from the outside according to the resolution of the display panel 10 and supplies the rearranged digital video data RGB′ to the data driver 12 .

Also, the timing controller 11 operates the data driver 12 based on timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE. A data control signal DDC for controlling the operation timing and a gate control signal GDC for controlling the operation timing of the gate driver 13 are supplied.

The data driver 12 converts the rearranged digital video data RGB' into an analog data voltage based on the data control signal DDC. Also, the data driver 12 supplies the data signal VDATA to the pixel area of each horizontal line during each horizontal period based on the rearranged digital video data RGB'.

The gate driver 13 may sequentially supply the scan signal SCAN1 to the scan lines 15 of each horizontal line based on the gate control signal GDC.

Although not separately shown, the display panel 10 includes a pair of substrates facing each other and bonded to each other and an organic light emitting diode array disposed therebetween. Also, one of the pair of substrates is a thin film transistor array substrate for defining a plurality of pixel areas PXL and supplying a driving current to the organic light emitting device of each pixel area PXL.

As shown in FIG. 2 , each pixel region PXL includes an organic light emitting diode (OLED), first and second thin film transistors T1 and T2, and a storage capacitor Cst.

The organic light emitting diode (OLED) includes an anode electrode, a cathode electrode, and an organic light emitting layer (not shown) disposed between them. Illustratively, the organic light emitting layer includes a hole injection layer, a hole transport layer, a light emitting layer, and an electron transport layer. Alternatively, the organic light emitting layer may further include an electron injection layer.

The first thin film transistor T1 includes a first driving power line 16 supplying the first driving power supply VDD and a second driving power supply VSS having a lower potential than the first driving power supply VDD. It is disposed in series with the organic light emitting diode (OLED) between the driving power lines.

The second thin film transistor T2 is disposed between the data line 14 supplying the data signal VDATA of each pixel area and the first node ND1 corresponding to the gate electrode of the first thin film transistor T1.

When the second thin film transistor T2 is turned on based on the scan signal SCAN of the scan line 15, it supplies the data signal VDATA to the first node ND1.

The storage capacitor Cst is disposed between the first node ND1 and the second node ND2. The second node ND2 is a contact point between the first thin film transistor T1 and the organic light emitting diode OLED.

The storage capacitor Cst is charged based on the data signal VDATA supplied to the first node ND1 through the turned-on second thin film transistor T2.

Further, the first thin film transistor T1 is turned on based on the charging voltage of the storage capacitor Cst, and the driving current corresponding to the data signal VDATA is applied to the second node ND2, that is, the organic light emitting diode OLED. supply

As shown in FIG. 3, the thin film transistor array substrate of the organic light emitting display device according to an embodiment of the present invention includes first and second thin film transistors (T1 and T2 in FIG. 2) corresponding to each pixel area PXL. includes

Further, the thin film transistor array substrate of the organic light emitting display device includes scan lines 15 in a first direction (horizontal direction in FIG. 3), data lines 14 in a second direction (vertical direction in FIG. 3), and a first power supply. It further includes line 16.

The first thin film transistor T1 includes a gate electrode 110 and a first active layer 120 partially overlapping the gate electrode 110 .

One side of the first active layer 120 is connected to the first power line 16 through the contact hole 16a, and the other side of the first active layer 120 is connected to the first conductive pattern through the contact hole 151a. (151) is connected.

Although not shown in detail in FIG. 3 , the first conductive pattern 151 is subsequently connected to an anode electrode (anode in FIG. 4 ) of an organic light emitting device (OLED in FIG. 2 ). That is, the first conductive pattern 151 corresponds to the second node (ND2 in FIG. 2 ).

The second thin film transistor T2 includes the second active layer 140 disposed above the first active layer 120 . Here, the second active layer 140 partially overlaps the first active layer 120 .

That is, according to an embodiment of the present invention, the second thin film transistor T2 is disposed above the first thin film transistor T1 and partially overlaps the first thin film transistor T1.

One side of the second active layer 140 is connected to the data line 14 through the contact hole 14a, and the other side of the second active layer 140 is connected to the second conductive pattern 152 through the contact hole 152a. ) is connected to

Also, the second conductive pattern 152 is connected to the gate electrode 110 of the first thin film transistor T1 through the contact hole 152b. That is, the other side of the second active layer 140 is connected to the gate electrode 110 of the first thin film transistor T1 through the second conductive pattern 152 .

In addition, the organic light emitting display device according to an embodiment of the present invention includes a bias disposed in a layer between the first and second thin film transistors T1 and T2 and insulated from the first and second thin film transistors T1 and T2, respectively. A pattern 130 is further included.

Specifically, the bias pattern 130 is disposed on a layer between the first and second active layers 120 and 140 and is insulated from the first and second active layers 120 and 140 , respectively. That is, the bias pattern 130 is disposed on the insulating layer covering the first active layer 120 , and the second active layer 140 is disposed on the insulating layer covering the bias pattern 130 .

Also, the bias pattern 130 partially overlaps each of the first and second active layers 120 and 140 .

Specifically, the bias pattern 130 is disposed in an overlapping region between the first and second active layers 120 and 140 . Thus, the mutual influence of the first and second active layers 120 and 140 may be blocked by the bias pattern 130 .

In addition, the bias pattern 130 may overlap at least a channel region of the first active layer 120 , that is, an overlapping region between the first active layer 120 and the gate electrode 110 .

Similarly, the bias pattern 130 may further overlap at least a channel region of the second active layer 140 , that is, an overlapping region between the second active layer 140 and the scan line 15 .

At this time, the bias pattern 130 may be maintained at a predetermined constant voltage. Illustratively, any one of the first driving power source VDD and the second driving power source VSS may be supplied to the bias pattern 130 . Alternatively, although not separately shown, a separate bias power source (not shown) may be supplied to the bias pattern 130 .

A channel can be stably maintained in the channel region of the first active layer 120 by the positive voltage of the bias pattern 130 . In addition, the channel can be stably maintained even in the channel region of the second active layer 140 by the positive voltage of the bias pattern 130 .

In addition, the horizontal scan line 15 is disposed on the insulating film covering the second active layer 140 and partially overlaps the second active layer 140 .

The vertical data line 14 and the first power supply line 16 are disposed on an insulating film covering the scan line 15 . In addition, the first and second conductive patterns 151 and 152 may also be disposed on the insulating layer covering the scan line 15 .

Specifically, as shown in FIG. 4 , the first thin film transistor T1 is disposed on the gate electrode 110 disposed on the substrate 101 and the first gate insulating film 102 covering the gate electrode 110. It includes a first active layer 120 to be.

The first active layer 120 partially overlaps the gate electrode 110 .

That is, the first active layer 120 includes the first channel region 121 overlapping the gate electrode 110 and the first and second electrode regions 122 and 123 corresponding to both sides of the first channel region 121 . ).

Any one of the first and second electrode regions 122 and 123 of the first active layer 120 (the first electrode region 122 in FIG. 4 ) connects to the first power line 16 through the contact hole 16a. , and the other one (the second electrode region 123 in FIG. 4 ) is connected to the first conductive pattern 151 through the contact hole 151a.

Also, the first conductive pattern 151 is connected to an anode of an organic light emitting device (OLED in FIG. 2 ) disposed on the insulating film 107 covering the first conductive pattern 151 . That is, since the second electrode region 123 of the first active layer 120 and the anode electrode are interconnected through the first conductive pattern 151, the first conductive pattern 151 is the second node (Fig. Corresponds to ND2) of 2.

The bias pattern 130 is disposed on the first bias insulating layer 103 covering the first active layer 120 .

The bias pattern 130 overlaps the gate electrode 110 . That is, the bias pattern 130 overlaps the channel region 121 of the first active layer 120 corresponding to the gate electrode 110 . Thus, the channel in the first channel region 121 of the first active layer 120 can be stably maintained by the positive voltage of the bias pattern 130 .

The second thin film transistor T2 includes the second active layer 140 disposed on the second bias insulating layer 104 covering the bias pattern 130 .

The scan line 15 is disposed on the second gate insulating layer 105 covering the second active layer 140 and partially overlaps the second active layer 140 .

As shown in FIG. 5 , the second active layer 140 includes a second channel region 141 overlapping the scan line 15 and third and fourth channels corresponding to both sides of the second channel region 141 . It includes electrode regions 142 and 143 .

The second active layer 140 partially overlaps the bias pattern 130 . Specifically, the bias pattern 130 overlaps an overlapping region between the second active layer 140 and the scan line 15 , that is, the second channel region 141 of the second active layer 140 . Thus, the channel in the second channel region 141 of the second active layer 140 can be stably maintained by the positive voltage of the bias pattern 130 .

Any one of the third and fourth electrode regions 142 and 143 of the second active layer 140 (the third electrode region 142 in FIG. 5) is connected to the data line 14 through the contact hole 14a. and the other one (the fourth electrode region 143 in FIG. 5) is connected to the second conductive pattern 152 through the contact hole 152a.

The second conductive pattern 152 is connected to the gate electrode 110 on the substrate 101 through the contact hole 152b. That is, since the fourth electrode region 143 of the second active layer 140 and the gate electrode 110 are interconnected through the second conductive pattern 152, the second conductive pattern 152 is connected to the first node (Fig. Corresponds to ND1) of 2.

As shown in FIGS. 4 and 5 , the data line 14, the first power supply line 16, and the first and second conductive patterns 151 and 152 form a first interlayer insulating film covering the scan line 15 ( 106) is placed on it.

At this time, as shown in FIG. 4 , the first power supply line 16 passes through the first interlayer insulating film 106, the second gate insulating film 105, the second bias insulating film 104, and the first bias insulating film 103. may be connected to the first electrode region 122 through the contact hole 16a.

In addition, although not separately shown, the first power supply line 16 has a contact hole (16b in FIG. 3) penetrating the first interlayer insulating film 106, the second gate insulating film 105, and the second bias insulating film 104. It can be connected to the bias pattern 130 through the.

The first conductive pattern 151 is formed through the contact hole 151a penetrating the first interlayer insulating film 106, the second gate insulating film 105, the second bias insulating film 104, and the first bias insulating film 103. It may be connected to the second electrode area 123 .

As shown in FIG. 5 , the data line 14 has a contact hole (passing through the first interlayer insulating film 106, the second gate insulating film 105, the second bias insulating film 104, and the first bias insulating film 103). It may be connected to the third electrode region 142 through 14a).

The second conductive pattern 152 forms a contact hole 152a penetrating the first interlayer insulating film 106, the second gate insulating film 105, the second bias insulating film 104, and the first bias insulating film 103. connected to the fourth electrode region 143 through the first interlayer insulating film 106, the second gate insulating film 105, the second bias insulating film 104, the first bias insulating film 103, and the first gate insulating film 102 ) may be connected to the gate electrode 110 through the contact hole 152b passing through.

And, as shown in FIG. 4, the anode electrode is a second interlayer insulating film 107 covering the data line 14, the first power supply line 16, and the first and second conductive patterns 151 and 152. placed on top And, the anode electrode (Anode) is connected to the first conductive pattern 151 through the contact hole penetrating the second interlayer insulating film 107, whereby the anode electrode (Anode) and the second electrode region 123 are 1 can be interconnected through the conductive pattern 151.

Meanwhile, according to FIG. 4 , in the longitudinal direction of the first channel region 121 , the bias pattern 130 has a length similar to or equal to that of the gate electrode 110 .

However, in the longitudinal direction of the first channel region 121 , the bias pattern 130 may be formed to have a longer length than the gate electrode 110 .

6 is a view showing a cross section taken along line A-A' of FIG. 3 according to another embodiment of the present invention.

As shown in FIG. 6, the organic light emitting display device according to another embodiment of the present invention is similar to FIGS. 1 to 5 except that the first active layer 121 further includes a buffer region 124. Since it is the same as the illustrated embodiment, redundant description will be omitted below.

As shown in FIG. 6 , according to another embodiment of the present invention, the bias pattern 130 in the longitudinal direction of the first channel region 121 has a longer length than the gate electrode 110 .

Thus, the first active layer 121 may further include a buffer region 124 disposed between at least one of the first and second electrode regions 122 and 123 and the first channel region 121 .

The buffer region 124 is a region doped with a lower concentration than the first and second electrode regions 122 and 123 by the bias pattern 130 without overlapping with the gate electrode 110 .

Illustratively, the buffer region 124 may be disposed between each of the first and second electrode regions 122 and 123 and the first channel region 121 .

A carrier crowding phenomenon caused at the edge of the first channel region 121 adjacent to the first and second electrode regions 122 and 123 may be alleviated by the buffer region 124 . Accordingly, since the kink effect can be suppressed, the voltage-current characteristic deterioration of the first thin film transistor T1 can be further prevented.

Alternatively, in order to reduce the turn-on resistance of the first thin film transistor T1, the buffer region 124 is a second electrode region corresponding to the first conductive pattern 151 among the first and second electrode regions 122 and 123. 123 and the first channel region 121 may be disposed only.

As described above, according to another embodiment of the present invention, by disposing the bias pattern 130 overlapping the gate electrode 110 and having a longer length than the gate electrode 110, the first active layer 120 forms a buffer region 124. ) It may be easy to prepare the first active layer 120 made of a structure including.

That is, during the doping process, the first active layer 120 including the buffer region 124 can be easily formed by the bias pattern 130 without using a separate doping mask having a length longer than the gate electrode 110. can be provided. Accordingly, since a separate doping mask corresponding to the buffer region 124 is unnecessary, the doping process can be performed more easily.

Next, a method of manufacturing an organic light emitting display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 7 to 21 .

7 to 21 are views illustrating each process of a method of manufacturing an organic light emitting display device according to an exemplary embodiment of the present invention.

First, as shown in FIGS. 7, 8 and 9, a gate electrode 110 corresponding to the first thin film transistor T1 is disposed on a substrate 101, and a first layer covering the gate electrode 110 is disposed. A gate insulating film 102 is disposed. Subsequently, a first semiconductor material layer 120' partially overlapping the gate electrode 110 is disposed on the first gate insulating film 102, and a first bias insulating film 103 covering the first semiconductor material layer 120'. ) is placed. Here, the first semiconductor material layer 120' may be low-temperature grown polysilicon (LTPS).

Next, as shown in FIGS. 10, 11 and 12, a bias pattern 130 overlapping the gate electrode 110 is disposed on the first bias insulating film 103, and a second layer covering the bias pattern 130 is disposed. 2 bias insulating film 104 is disposed.

Subsequently, as shown in FIGS. 13, 14, and 15, a second semiconductor material layer 140' partially overlapping the bias pattern 130 is disposed on the second bias insulating film 104, and the second semiconductor material layer 140' is disposed. A second gate insulating layer 105 covering the material layer 140' is disposed.

Next, as shown in FIGS. 16, 17, and 18, a scan line 15 partially overlapping the second semiconductor material layer 140' is disposed on the second gate insulating film 105, and the scan line ( 15), a first interlayer insulating film 106 is disposed.

Then, a doping process is performed on the first and second semiconductor material layers 120' and 140' while using the scan line 15 and the bias pattern 130 as masks. Thus, the first active layer 120 including the first channel region 121 and the first and second electrode regions 122 and 123 is prepared by a doping process on the first semiconductor material layer 120'. do. Then, the second active layer 140 including the second channel region 141 and the third and fourth electrode regions 142 and 143 is prepared by a doping process on the second semiconductor material layer 140'. do.

Thereafter, a plurality of contact holes 14a, 16a, 151a, 152a, and 152b are prepared by partially patterning the insulating layers.

Then, as shown in FIGS. 19, 20 and 21, the data lines 14, the first power line 16, the first and second conductive patterns ( 151, 152) are placed.

As described above, according to one embodiment of the present invention, in the organic light emitting display device including the first and second thin film transistors T1 and T2 corresponding to each pixel area, the first and second thin film transistors T1, T2) are disposed so as to at least partially overlap each other in the vertical direction with the bias pattern 130 interposed therebetween. That is, the first and second thin film transistors T1 and T2 are not disposed apart from each other in the horizontal direction on the same plane, but are disposed so as to at least partially overlap each other in the vertical direction.

Accordingly, since element arrangement in each pixel region can be integrated more efficiently, deterioration in voltage-current characteristics of the thin film transistor due to the reduced area of each pixel region can be prevented. As a result, high resolution may be advantageous.

In addition, mutual interference between the first and second thin film transistors T1 and T2 may be prevented by the bias pattern 130 disposed between the first and second thin film transistors T1 and T2. Therefore, degradation of characteristics of the first and second thin film transistors T1 and T2 overlapping each other in the horizontal direction can be prevented.

In addition, the first and second channel regions 121 and 141 overlap the bias pattern 130 . Also, a constant voltage is supplied to the bias pattern 130 . Accordingly, the electric field of the channel generated in each of the first and second channel regions 121 and 141 is affected by the positive voltage of the bias pattern 130 . Therefore, the channel in each of the first and second thin film transistors T1 and T2 can be more stably maintained by the positive voltage of the bias pattern 130 . Accordingly, stabilization of characteristics of the first and second thin film transistors T1 and T2 may be more advantageous.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the technical spirit of the present invention. Conventionally in the art to which the present invention belongs It will be clear to those who have knowledge of

T1, T2, T3: first, second, third thin film transistors
15: scan line 14: data line
16: first driving power line
110: gate electrode 120: first active layer
130: bias pattern 140: second active layer
151, 152: first and second conductive patterns

Claims (8)

an organic light emitting element corresponding to each of a plurality of pixel areas defined in the display area;
between a first power line supplying first driving power corresponding to driving of the organic light emitting device and a second power line supplying second driving power having a lower voltage than the first driving power in series with the organic light emitting device a first thin film transistor disposed thereon;
a second thin film transistor disposed between a data line supplying a data signal of each pixel area and a node corresponding to the gate electrode of the first thin film transistor; and
a bias pattern disposed on a layer between the first and second thin film transistors and insulated from each of the first and second thin film transistors;
The second thin film transistor is disposed above the first thin film transistor and partially overlaps the first thin film transistor.
delete According to claim 1,
The first thin film transistor includes a gate electrode disposed on a substrate and a first active layer disposed on a first gate insulating layer covering the gate electrode and partially overlapping the gate electrode,
The bias pattern is disposed on a first bias insulating layer covering the first active layer and overlaps the gate electrode.
According to claim 3,
Further comprising a scan line corresponding to each horizontal line consisting of pixel areas arranged in parallel in a horizontal direction among the plurality of pixel areas;
The second thin film transistor includes a second active layer disposed on a second bias insulating layer covering the bias pattern and partially overlapping the bias pattern,
The scan line is disposed on a second gate insulating layer covering the second active layer and partially overlaps the second active layer.
According to claim 4,
The first active layer includes a first channel region overlapping the gate electrode and first and second electrode regions corresponding to both sides of the first channel region,
The second active layer includes a second channel region overlapping the scan line, and third and fourth electrode regions corresponding to both sides of the second channel region,
The first channel region and the second channel region overlap each other at least partially;
The bias pattern corresponds to at least an overlapping region of the first and second channel regions.
According to claim 5,
One of the first and second electrode regions is connected to the first power line and the other is connected to the first conductive pattern;
The first power line, the data line, and the first conductive pattern are spaced apart from each other and disposed on a first interlayer insulating layer covering the scan line.
According to claim 5,
wherein one of the third and fourth electrode regions is connected to the data line and the other one is connected to the gate electrode.
According to claim 5,
In the longitudinal direction of the first channel region, the bias pattern has a length longer than that of the gate electrode;
The first active layer may further include a buffer region disposed between at least one of the first and second electrode regions and the first channel region and doped with a lower concentration than the first and second electrode regions. Device.

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