KR102551582B1 - Organic light emitting display device - Google Patents

Abstract

An embodiment of the present invention provides an organic light emitting element corresponding to each pixel region, a first power supply line for supplying a first driving power having a first voltage corresponding to driving of the organic light emitting element, and a voltage lower than the first voltage. A first thin film transistor disposed in series with the organic light emitting element between a second power supply line for supplying a second driving power of 2 voltage, a first node corresponding to a gate electrode of the first thin film transistor, and the first thin film An organic light emitting display device including a second thin film transistor disposed between a transistor and a second node between the organic light emitting element, and a first capacitor disposed between the second node and the second power line.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present invention relates to an organic light emitting display device including an organic light emitting element corresponding to each pixel area.

Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. Accordingly, research is being conducted to develop thinning, lightening, and low power consumption of display devices.

Representative examples of the display device include a liquid crystal display device (LCD), a plasma display panel device (PDP), a field emission display device (FED), and an electro luminescence display device. Display device: ELD), Electro-Wetting Display device (EWD), Organic Light Emitting Display device (OLED), and the like.

Among them, an organic light emitting display device includes a plurality of organic light emitting elements corresponding to a plurality of pixel areas defined in a display area where an image is displayed. Since the organic light emitting device is a self-emitting device that emits light by itself, the organic light emitting display device has advantages in that it has a fast response speed, high luminous efficiency, luminance and viewing angle, and excellent contrast ratio and color gamut compared to liquid crystal display devices.

An organic light emitting display device may be implemented in an active matrix method that individually drives a plurality of pixel areas. Such an active matrix organic light emitting display device includes a pixel driving circuit for supplying a driving current to an organic light emitting element corresponding to each pixel area.

The pixel driving circuit generally includes a driving thin film transistor connected in series with the organic light emitting element between a first driving power supply and a second driving power supply corresponding to the organic light emitting element, and a switching thin film transistor supplying a data signal to each pixel area. am.

However, due to a difference in driving stress for each pixel region, the characteristics of the driving thin film transistor and the organic light emitting device of each pixel region may vary differently from each other. In this case, a difference in luminance between pixel areas may cause deterioration in image quality such as stains. To prevent this, the organic light emitting display device may further include a driving thin film transistor corresponding to each pixel area and a compensation circuit for compensating for characteristics of the organic light emitting device.

On the other hand, there is a recent demand for higher resolution display devices for clearer picture quality, and as a result, the area of each pixel region tends to be reduced. In particular, in the case of a 3D VR device (3-Dimension Virtual Reality Device), the area of each pixel region can be reduced by 1/20 times or more compared to a general display device.

As the area of each pixel region is reduced in this way, the area allocated to each of the plurality of thin film transistors corresponding to each pixel region is reduced, and device characteristics may be degraded. However, since the pixel driving circuit and the compensation circuit must be disposed within the reduced area of the pixel region, there is a limit to adding separate elements to the compensation circuit to compensate for the degradation of the characteristics of the elements.

Accordingly, in order to compensate for the deterioration of characteristics of elements due to the reduced area of each pixel region, a method of varying the voltage supplied to each signal line instead of adding a separate element to the compensation circuit has been proposed.

For example, during the compensation period, the second driving power is set to the same voltage as the first driving power to block the driving of the organic light emitting element, and thereafter, the second driving power during an emission period for emitting light for displaying an image may be changed to a voltage lower than that of the first driving power source.

However, peak current may be generated when the voltage of the second driving power source fluctuates. The organic light emitting device may be driven based on the peak current, and thus black luminance may increase. Accordingly, there is a limitation in improving the contrast ratio, and thus, there is a limitation in improving the image quality.

An object of the present invention is to provide an organic light emitting display device capable of preventing an increase in black luminance due to a voltage change of a driving power source.

The objects of the present invention are not limited to the above-mentioned objects, and other objects and advantages of the present invention not mentioned above can be understood by the following description and will be more clearly understood by the examples of the present invention. It will also be readily apparent that the objects and advantages of the present invention may be realized by means of the instrumentalities and combinations indicated in the claims.

An example of the present invention is an organic light emitting device corresponding to each pixel region, a first power supply line for supplying a first driving power having a first voltage corresponding to driving of the organic light emitting device, and a second voltage lower than the first voltage. A first thin film transistor arranged in series with the organic light emitting element between a second power supply line for supplying a second driving power of voltage, a first node corresponding to a gate electrode of the first thin film transistor and the first thin film transistor and a second thin film transistor disposed between the second nodes between the organic light emitting elements, and a first capacitor disposed between the second node and the second power line.

The second power line corresponds to each horizontal line composed of pixel areas arranged in a horizontal direction among a plurality of pixel areas defined in the display area and is connected to the first capacitor, and the organic light emitting device and a cathode power line corresponding to the cathode electrode of

The first thin film transistor is disposed on a first active pattern including a channel region and first and second electrode regions corresponding to both ends of the channel region, and a gate insulating layer covering the first active pattern, and is disposed on the first active pattern. and a gate electrode overlapping the channel region of the pattern and covered with a plurality of interlayer insulating films.

The horizontal power line is disposed on any one interlayer insulating film among the plurality of interlayer insulating films, and the first power line is disposed differently from the horizontal power line on any one other interlayer insulating film among the plurality of interlayer insulating films. , the first electrode region of the first active pattern is connected to the first power line.

The first capacitor is disposed on the same layer as the first power line and corresponds to an overlapping area between the first conductive pattern connected to the second electrode area of the first active pattern and the horizontal power line.

An anode electrode of the organic light emitting device is disposed on a final insulating film covering the horizontal power line and is connected to a second electrode region of the first active pattern, and the first capacitor overlaps between the horizontal power line and the anode electrode. correspond to the area.

Alternatively, the organic light emitting display device may include a third thin film transistor disposed between a data line for supplying a data signal of each pixel area and a third node, and a second capacitor disposed between the third node and the first node. , and a third capacitor disposed between the third node and the first power line.

The second capacitor corresponds to an overlapping region between a first capacitor electrode disposed on the first interlayer insulating film covering the gate electrode and the gate electrode, and the third capacitor is a second interlayer insulating film covering the first capacitor electrode. It corresponds to an overlapping area between the second capacitor electrode disposed on the first capacitor electrode and the first capacitor electrode.

The horizontal power line is disposed on a third interlayer insulating film covering the second capacitor electrode, and the first power line is disposed on a fourth interlayer insulating film covering the horizontal power line. The electrode region is connected to the first power line through a contact hole penetrating the gate insulating layer and the first, second, third, and fourth interlayer insulating layers.

The first capacitor is disposed on the fourth interlayer insulating layer and is connected to the second electrode region of the first active pattern through a contact hole passing through the gate insulating layer and the first, second, third, and fourth interlayer insulating layers. It corresponds to an overlapping area between the connected first conductive pattern and the horizontal power line.

The first power line is disposed on a third interlayer insulating layer covering the second capacitor electrode, and the first electrode region of the first active pattern passes through the gate insulating layer and the first, second, and third interlayer insulating layers. is connected to the first power line through a contact hole, and the horizontal power line is disposed on a fourth interlayer insulating film covering the first power line.

An anode electrode of the organic light emitting device is disposed on a final insulating layer covering the horizontal power line, and the first capacitor corresponds to an overlapping area between the horizontal power line and the anode electrode.

An organic light emitting display device according to an embodiment of the present invention includes a first thin film transistor connected in series with an organic light emitting element between first and second power lines, and an organic light emitting element among first and second electrodes of the first thin film transistor. A second thin film transistor disposed between any one corresponding to and a gate electrode of the first thin film transistor, and a first capacitor disposed between the second thin film transistor and the second power line.

The peak current according to the voltage change of the second driving power source may be dispersed by the first capacitor. Accordingly, since driving of the organic light emitting device by the peak current can be prevented, an increase in black luminance can be prevented. Thus, a decrease in contrast ratio can be prevented, and deterioration in image quality can be prevented.

In addition, the organic light emitting display device according to an embodiment of the present invention includes horizontal power lines corresponding to each horizontal line and supplying second driving power. Through such a horizontal power line, there is an advantage in that the first capacitor for distributing the peak current can be implemented more simply and easily.

1 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram illustrating an equivalent circuit corresponding to any one pixel area shown in FIG. 1 .
FIG. 3 is an example of a driving timing diagram corresponding to the equivalent circuit of FIG. 2 .
4, 5 and 6 are diagrams illustrating operations of each period shown in FIG. 3 .
FIG. 7 is a view showing an example of a plane of a thin film transistor array substrate corresponding to the pixel area of FIG. 2 .
FIG. 8 is a view showing line A-A' of FIG. 7 .
FIG. 9 is a view showing line BB′ of FIG. 7 .
FIG. 10 is a view showing line C-C′ of FIG. 7 .
11 is a view showing line A-A' of FIG. 7 according to another embodiment of the present invention.

The above objects, features and advantages will be described later in detail with reference to the accompanying drawings, and accordingly, those skilled in the art to which the present invention belongs will be able to easily implement the technical spirit of the present invention. In describing the present invention, if it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar components.

Hereinafter, an organic light emitting display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, an organic light emitting display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 4 .

1 is a diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating an equivalent circuit corresponding to any one pixel area shown in FIG. 1 . FIG. 3 is an example of a driving timing diagram corresponding to the equivalent circuit of FIG. 2 . 4, 5 and 6 are diagrams illustrating operations of each period shown in FIG. 3 .

As shown in FIG. 1 , an organic light emitting display device according to an exemplary embodiment includes a display panel 10 , a timing controller 11 , a data driver 12 and a gate driver 13 .

The display panel 10 includes a plurality of pixel areas PXL defined in a display area AA where an image is displayed, and pixels arranged side by side in a vertical direction (vertical direction in FIG. 1 ) among the plurality of pixel areas PXL. A data line 14 corresponding to each vertical line composed of regions and a gate corresponding to each horizontal line composed of pixel regions arranged side by side in a horizontal direction (left-right direction in FIG. 1) among a plurality of pixel regions PXL line 15.

A plurality of pixel areas PXL arranged in a matrix form in the display area AA may be defined by the gate lines 15 and the data lines 14 crossing each other as described above.

The gate line 15 may include first and second gate lines ( 15a and 15b in FIG. 2 ) for supplying different first and second scan signals SCAN1 and SCAN2 to each vertical line.

The first scan signal SCAN1 may be a gate signal corresponding to an addressing period for supplying the data signal VDATA of each pixel area PXL.

The second scan signal SCAN2 may be a gate signal corresponding to an initial period for supplying the reference power VREF to each pixel region PXL.

The data line 14 is for selectively supplying any one of the data signal VDATA and the reference power supply VREF of each pixel region PXL.

In addition, although not shown in detail in FIG. 1 , the display panel 10 includes a first power line (FIG. 2) for supplying a first driving power source (VDD) of a first voltage for driving an organic light emitting device (OLED in FIG. 2). 16) and a second power line 17 (18 in FIG. 2) for supplying a second driving power source VSS having a second voltage lower than the first voltage and corresponding to the driving of the organic light emitting diode OLED. .

In addition, according to an embodiment of the present invention, in order to prevent the organic light emitting diode (OLED) from driving during the remaining period (eg, initial period and addressing period) except for the emission period for emitting light for image display , The second driving power source VSS may be maintained at a third voltage corresponding to a similar range to the first voltage. Illustratively, the third voltage may have an equipotential with the first voltage.

The timing controller 11 rearranges the digital video data RGB input from the outside according to the resolution of the display panel 10 and supplies the rearranged digital video data RGB′ to the data driver 12 .

Also, the timing controller 11 operates the data driver 12 based on timing signals such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the dot clock signal DCLK, and the data enable signal DE. A data control signal DDC for controlling the driving timing and a gate control signal GDC for controlling the driving timing of the gate driver 13 are supplied.

The data driver 12 converts the rearranged digital video data RGB' into an analog data voltage based on the data control signal DDC. Then, the data driver 12 supplies the data signal VDATA corresponding to each pixel area PXL to the data line 14 during the addressing period of each horizontal period based on the rearranged digital video data RGB'. .

Also, the data driver 12 supplies the reference power VREF to the data line 14 during at least some of the remaining periods (eg, an initial period and an emission period) excluding the addressing period.

The gate driver 13 sequentially applies first and second scan signals SCAN1 and SCAN2 to the gate line 15 corresponding to each horizontal line included in the display panel 10 based on the gate control signal GDC. supply

As shown in FIG. 2 , each pixel region PXL of the display panel 10 includes an organic light emitting diode (OLED), first, second and third thin film transistors T1, T2 and T3, and a first , and second and third capacitors C1, C2, and C3.

The first thin film transistor T1 includes a first power line 16 for supplying a first driving power source VDD having a first voltage corresponding to driving the organic light emitting diode OLED, and a second voltage lower than the first voltage. It is arranged in series with the organic light emitting diode (OLED) between the second power line 17 for supplying the second driving power source (VSS) of the voltage.

Here, the first electrode of the first thin film transistor T1 may be connected to the first power line 16 and the second electrode may be connected to the organic light emitting diode OLED.

The second thin film transistor T2 includes a first node ND1 corresponding to the gate electrode of the first thin film transistor T1 and a second node ND2 between the first thin film transistor T1 and the organic light emitting diode OLED. and is turned on based on the second scan signal SCAN2 of the second gate line 15b.

The first node ND1 is connected to the gate electrode of the first gate electrode T1, and the second node ND2 is connected to the second electrode of the first thin film transistor T1 and the organic light emitting diode OLED.

When the second thin film transistor T2 is turned on based on the second scan signal SCAN2, between the first and second nodes ND1 and ND2, that is, between the gate electrode and the second electrode of the first thin film transistor T1. connect

The second thin film transistor (T2) is to compensate for the threshold voltage of the first thin film transistor (T1).

The first capacitor C1 is disposed between the second node ND2 and the second power line 18 supplying the second driving power source VSS.

Here, the second power lines 17 and 18 supplying the second driving power source VSS are connected to the cathode power line 17 connected to the cathode electrode of the organic light emitting diode OLED and to the first capacitor C1. It includes a horizontal power line 18 to be.

As shown in FIG. 1 , the horizontal power line 18 corresponds to each horizontal line composed of pixel areas arranged in parallel in a horizontal direction among a plurality of pixel areas PXL.

In addition, the cathode power line 17 may be disposed separately from the horizontal power line 18 and connected in common to the cathode electrodes of the plurality of organic light emitting diodes (OLED) corresponding to the plurality of pixel regions PXL. there is.

The third thin film transistor T3 is disposed between the data line 14 supplying the data signal VDATA or the reference power supply VREF of each pixel region PXL and the third node ND3, and the first gate line It is turned on based on the first scan signal (SCAN1) of (15a).

That is, when the third thin film transistor T3 is turned on based on the first scan signal SCAN1, it supplies either the data signal VDATA or the reference power supply VREF to the third node ND3.

The second capacitor C2 is disposed between the third node ND3 and the first node ND1.

The third capacitor C3 is disposed between the first power line 16 supplying the first driving power supply VDD and the third node ND3.

The second and third capacitors C2 have a voltage corresponding to any one of the data signal VDATA and the reference power supply VREF supplied to the third node ND3 through the turned-on third thin film transistor T3. is charged

Also, the second and third capacitors C2 and C3 are connected in series with the gate electrode of the first thin film transistor T1. Therefore, the potential of the gate electrode of the first thin film transistor T1, that is, the first node ND1 corresponds to the amount of charge in the second and third capacitors C2 and C3.

As shown in FIG. 3, one frame period for each horizontal line to display each video frame includes an initial period (IP), an addressing period (AP), and an emission period (EP). includes

During the initial period IP, the second driving power source VSS is supplied with a third voltage VSS_H in a similar range to the first voltage of the first driving power source to block driving of the organic light emitting diode OLED.

In order to initialize the first node ND1 , the reference power source VREF is supplied to the data line DL ( 14 in FIG. 2 ).

Also, the first and second scan signals SCAN1 and SCAN2 are supplied at turn-on levels.

At this time, as shown in FIG. 4, the second and third thin film transistors T2 and T3 are turned on based on the first and second scan signals SCAN1 and SCAN2 of the turn-on level.

Accordingly, the reference power VREF of the data line DL is supplied to the third node ND3 through the turned-on third thin film transistor T3.

Further, Vgs of the first thin film transistor T1 is brought close to the threshold voltage due to the turned on second thin film transistor T2, so that the first thin film transistor T1 is turned on. Accordingly, the difference (VDD-Vth) between the threshold voltage Vth of the first thin film transistor T1 in the first driving power source VDD is supplied to the first node ND1.

As illustrated in FIG. 3 , in order to block driving of the organic light emitting diode OLED during the addressing period AP, the second driving power source VSS is supplied as a third voltage VSS_H.

Further, in order to write data corresponding to each image frame in each pixel region PXL, the data signal VDATA of each pixel region PXL is supplied to the data line DL.

In addition, the first scan signal SCAN1 of each horizontal line is sequentially supplied at a turn-on level. On the other hand, the second scan signal SCAN2 is supplied at a turn-off level.

Accordingly, as shown in FIG. 5, the second thin film transistor T2 is turned off based on the second scan signal SCAN2 of the turn-off level.

Also, when the third thin film transistor T3 is turned on based on the first scan signal SCAN1 having a turn-on level, the data signal VDATA of the data line DL is supplied to the third node ND3. At this time, the second and third capacitors C2 and C3 are charged based on the data signal VDATA.

Next, as shown in FIG. 3 , in order to drive the organic light emitting device OLED during the emission period EP, the second driving power source VSS is supplied with a second voltage VSS_L lower than the first voltage of the first driving power source. ) is supplied.

Also, the first and second scan signals SCAN1 and SCAN2 are supplied at a turn-off level.

Accordingly, as shown in FIG. 6 , a current path including the turned-on first thin film transistor T1 and the organic light emitting diode OLED is generated between the first and second driving power sources VDD and VSS. A driving current is supplied to the organic light emitting diode (OLED) through this current path.

Meanwhile, as shown in FIG. 3 , according to an embodiment of the present invention, at the start time of the emission period EP, the second driving power source VSS changes from the third voltage VSS_H to the second voltage VSS_L change rapidly to A peak current may be generated due to the voltage fluctuation of the second driving power source VSS, and thus the organic light emitting diode OLED may be driven. That is, the organic light emitting diode (OLED) corresponding to the black luminance pixel area may also be driven under the influence of the peak current.

However, the organic light emitting display device according to an embodiment of the present invention includes a first capacitor C1 disposed between the second node ND2 and the horizontal power line 18 supplying the second driving power source VSS. Accordingly, the influence of the peak current on the organic light emitting diode (OLED) can be reduced.

Accordingly, since the organic light emitting diode OLED can be prevented from being driven based on the peak current due to the voltage fluctuation of the second driving power source VSS, an increase in black luminance can be prevented, thereby increasing the contrast ratio. and image quality can be improved.

Next, an example of implementing the first capacitor C1 of the organic light emitting display device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 7 to 11 .

FIG. 7 is a view showing an example of a plane of a thin film transistor array substrate corresponding to the pixel area of FIG. 2 . FIG. 8 is a view showing line A-A' of FIG. 7 . FIG. 9 is a view showing line BB′ of FIG. 7 . FIG. 10 is a view showing line C-C′ of FIG. 7 .

As shown in FIG. 7, the organic light emitting display device includes first and second gate lines 15a and 15b in a horizontal direction (left and right directions in FIG. 7), a horizontal power line 18, and a vertical direction (in the left and right directions in FIG. 7). It includes a data line 14 and a first power line 17 in a vertical direction).

Also, the organic light emitting display device includes first, second, and third thin film transistors (T1, T2, and T3 in FIG. 2) corresponding to each pixel area PXL.

The first thin film transistor T1 includes a first active pattern 111 and a gate electrode 120 overlapping a channel region of the first active pattern 111 .

One end of the first active pattern 111 partially overlaps the first power supply line 16 , and the other end of the first active pattern 111 partially overlaps the first conductive pattern 151 .

A portion of the first conductive pattern 151 overlaps the anode contact hole CT_A corresponding to the anode electrode of the organic light emitting device (OLED of FIG. 2 ).

The gate electrode 120 of the first thin film transistor T1 overlaps the first and second capacitor electrodes 130 and 140 .

The second thin film transistor T2 includes the second active pattern 112 .

One end of the second active pattern 112 partially overlaps the gate electrode 120 and the second conductive pattern 152 of the first thin film transistor T1, and the other end of the second active pattern 112 is the first conductive layer. It partially overlaps with the pattern 151.

The third thin film transistor T3 includes the third active pattern 113 .

One end of the third active pattern 113 partially overlaps the data line 14, and the other end of the second active pattern 113 partially overlaps the first capacitor electrode 130 and the third conductive pattern 153. .

As shown in FIG. 8 , the first thin film transistor T1 is disposed on the first active pattern 111 disposed on the substrate 101 and the gate insulating layer 102 covering the first active pattern 111. A gate electrode 120 covered with a plurality of interlayer insulating films 103 , 104 , 105 , and 106 is included. For example, the gate electrode 120 may be covered with sequentially stacked first, second, third, and fourth interlayer insulating films 103 , 104 , 105 , and 106 . And, a final insulating layer 107 for separation from the organic light emitting diode array (Anode) may be further disposed on the fourth interlayer insulating layer 106 .

The first active pattern 111 includes a channel region 111a overlapping the gate electrode 120 and first and second electrode regions 111b and 111c corresponding to both ends of the channel region 111a.

The horizontal power line 18 is disposed on one of a plurality of interlayer insulating films (third interlayer insulating film 105 in FIG. 8).

And, the first power line 16 is disposed on any one other interlayer insulating film among a plurality of interlayer insulating films (the fourth interlayer insulating film 106 in FIG. 8 ). That is, the first power line 16 is disposed on a different layer from the horizontal power line 18.

The first electrode region 111b of the first active pattern is connected to the first power line 16 . That is, the first power supply line 16 on the fourth interlayer insulating film 106 is a contact passing through the gate insulating film 102 and the first, second, third, and fourth interlayer insulating films 103, 104, 105, and 106. It is connected to the first electrode region 111b of the first active pattern through the hole 16a.

The second electrode region 111c of the first active pattern is connected to the first conductive pattern 151 . In other words, the first conductive pattern 151 is disposed on the same layer as the first power supply line 16, that is, on the fourth interlayer insulating film 106, and the first, second, third, and fourth interlayer insulating films ( It is connected to the second electrode region 111c of the first active pattern through the contact hole 151a passing through 103 , 104 , 105 , and 106 .

Also, the anode of the organic light emitting device (OLED of FIG. 2 ) may be disposed on the final insulating layer 107 covering the first power line 16 and the first conductive pattern 151 . Also, the anode electrode Anode is connected to the first conductive pattern 151 through the anode contact hole CT_A penetrating the final insulating layer 107 . As a result, the anode electrode (Anode) is connected to the second electrode region 111c of the first active pattern through the first conductive pattern 151 .

Here, the first capacitor (C1 in FIG. 2 ) between the second node ND2 and the second reference power supply VSS has a first conductive pattern connected to the anode electrode of the organic light emitting device (OLED in FIG. 2 ). 151 and the horizontal power line 18 supplying the second reference power VSS.

That is, the first conductive pattern 151 and the horizontal power line 18 overlap each other with the fourth interlayer insulating film 106 interposed therebetween, and the first capacitor C1 is connected to the first conductive pattern 151 and the horizontal power line. It occurs in the overlapping region of (18).

The second capacitor (C2 in FIG. 2 ) between the first node ND1 and the third node ND3 is an overlapping region between the gate electrode 120 and the first capacitor electrode 130 of the first thin film transistor T1. respond to

Here, the first capacitor electrode 130 is disposed on the first interlayer insulating layer 103 covering the gate electrode 120 of the first thin film transistor T1. And, as shown in FIG. 10, the first capacitor electrode 130 is connected to the third thin film transistor T3.

That is, the gate electrode 120 of the first thin film transistor T1 and the first capacitor electrode 130 overlap each other with the first interlayer insulating film 103 therebetween, and the second capacitor C2 is the first thin film transistor It is generated in the overlapping region between the gate electrode 120 and the first capacitor electrode 130 of (T1).

A third capacitor (C3 in FIG. 2 ) between the first power line 16 and the third node ND3 corresponds to an overlapping region between the first capacitor electrode 130 and the second capacitor electrode 140 .

Here, the second capacitor electrode 140 is disposed on the second interlayer insulating film 104 covering the first capacitor electrode 130 . And, the second capacitor electrode 140 is connected to the first power line 16 .

That is, the first and second capacitor electrodes 130 and 140 overlap each other with the second interlayer insulating film 104 therebetween, and the third capacitor C3 is between the first and second capacitor electrodes 130 and 140. occurs in the overlapping area of

The horizontal power line 18 is disposed on the third interlayer insulating film 105 covering the second capacitor electrode 140 .

Further, the first power line 16 is disposed on the fourth interlayer insulating film 106 covering the horizontal power line 18 and has a contact hole 16b passing through the third and fourth interlayer insulating films 105 and 106. It is connected to the second capacitor electrode 140 through.

As shown in FIG. 9 , the second thin film transistor T2 includes the second active pattern 112 disposed on the substrate 101 .

The second active pattern 112 includes first and second channel regions 112a and 112b overlapping the second gate line 15b and a first electrode region 112c disposed at one end of the first channel region 112a. and a second electrode region 112d disposed at one end of the second channel region 112b, and a connection region 112e between the first and second channel regions 112a and 112b.

The second gate line 15b is disposed on the gate insulating layer 102 covering the second active pattern 112 and overlaps the channel regions 112a and 112b of the second active pattern 112 .

The first electrode region 112c of the second active pattern is connected to the first conductive pattern 151 on the fourth interlayer insulating layer 104 . That is, the first conductive pattern 151 passes through the gate insulating layer 102 and the first, second, third, and fourth interlayer insulating layers 103, 104, 105, and 106 through the contact hole 151c to form the second conductive pattern 151c. It is connected to the first electrode region 112c of the active pattern.

Thus, the first electrode region 112c of the second active pattern 112 is connected to the anode electrode (Anode in FIG. 8 ) and the first active pattern of the first thin film transistor T1 through the first conductive pattern 151 . It is connected to the second electrode region 111b. That is, the first conductive pattern 151 corresponds to the second node (ND2 in FIG. 2 ).

The second electrode region 112d of the second active pattern is connected to the second conductive pattern 152 on the fourth interlayer insulating layer 104 .

The second conductive pattern 152 is the second active pattern through the contact hole 152a penetrating the gate insulating film 102 and the first, second, third, and fourth interlayer insulating films 103, 104, 105, and 106. The first thin film transistor T1 is connected to the second electrode region 112d of the first thin film transistor T1 through the contact hole 152b passing through the first, second, third, and fourth interlayer insulating films 103, 104, 105, and 106. ) is connected to the gate electrode 120. Thus, the gate electrode 120 of the first thin film transistor T1 and the second electrode 112d of the second thin film transistor T2 are interconnected through the second conductive pattern 152 . That is, the second conductive pattern 152 corresponds to the first node (ND1 in FIG. 2 ).

As shown in FIG. 10 , the third thin film transistor T3 includes the third active pattern 113 disposed on the substrate 101 .

The third active pattern 113 includes a channel region 113a overlapping the first gate line 15a and first and second electrode regions 113b and 113c corresponding to both ends of the channel region 113a.

The first gate line 15a is disposed on the gate insulating layer 102 covering the third active pattern 113 and overlaps the channel region 113a of the third active pattern 113 .

The first electrode region 113b of the third active pattern is connected to the data line 14 on the fourth interlayer insulating layer 104 . That is, the data line 14 forms the third active pattern through the contact hole 14a penetrating the gate insulating layer 102 and the first, second, third, and fourth interlayer insulating layers 103, 104, 105, and 106. is connected to the first electrode region 113b of

The second electrode region 113c of the third active pattern is connected to the first capacitor electrode 130 through the third conductive pattern 153 on the fourth interlayer insulating layer 104 .

That is, the third conductive pattern 153 passes through the contact hole 153a penetrating the gate insulating layer 102 and the first, second, third, and fourth interlayer insulating layers 103, 104, 105, and 106 to form the third conductive pattern 153. It is connected to the second electrode region 113c of the active pattern and connected to the first capacitor electrode 130 through the contact hole 153b passing through the second, third and fourth interlayer insulating films 104, 105 and 106. do.

Thus, the first capacitor electrode 130 corresponding to the second and third capacitors C2 and C3 and the second electrode region 113c of the third active pattern are interconnected through the third conductive pattern 153 . That is, the third conductive pattern 153 corresponds to the third node (ND3 in FIG. 2 ).

As described above, the organic light emitting display device according to an embodiment of the present invention supplies the second driving power source VSS and corresponds to each horizontal power line and is disposed on a different layer from the first power line 16 ( 18) is further included. Thus, between the first conductive pattern 151 connected to the anode of the organic light emitting device and the second electrode region 111c of the first active pattern of the first thin film transistor T1 and the horizontal power supply line 18 The first capacitor C1 corresponding to the overlapping area of can be easily disposed.

Meanwhile, in FIG. 8 , the horizontal power line 18 is disposed below the first conductive pattern 151, and the first capacitor C1 overlaps between the horizontal power line 18 and the first conductive pattern 151. shows what happens in Alternatively, the horizontal power line 18 may be disposed above the first conductive pattern 151 .

11 is a view showing line A-A' of FIG. 7 according to another embodiment of the present invention.

As shown in FIG. 11, according to another embodiment of the present invention, the first power line 16 and the first conductive pattern 151 form a third interlayer insulating film 105 covering the second capacitor electrode 140. The horizontal power line 18' is disposed on the fourth interlayer insulating film 106' covering the first power line 16 and the first conductive pattern 151, and the anode electrode is horizontal Except for being disposed on the final insulating film 107' covering the power line 18', it is the same as the embodiment shown in Figs.

According to another embodiment of the present invention, the first power line 16 and the first conductive pattern 151 are disposed on the third interlayer insulating layer 105 covering the second capacitor electrode 140 . Although not shown separately, the second and third conductive patterns (152 in FIG. 9 and 153 in FIG. 10 ) may also be disposed on the same layer as the first conductive pattern 151, that is, on the third interlayer insulating film 105. .

The horizontal power line 18' is disposed on the fourth interlayer insulating layer 106' covering the first power line 16 and the first conductive pattern 151 and partially overlaps the first conductive pattern 151.

In addition, unlike the illustration of FIG. 7, the fourth conductive pattern 154 connected to the first conductive pattern 151 on the same layer as the horizontal power line 18', that is, on the fourth interlayer insulating film 106' is further formed. can be placed. In this way, the anode contact hole CT_A' penetrates only the final insulating layer 107' and is connected to the fourth conductive pattern 154, thereby forming the first conductive pattern 151 and the first active pattern of the first thin film transistor ( 111), the formation of the anode contact hole CT_A' can be facilitated.

The anode electrode is disposed on the final insulating film 107' covering the horizontal power line 18' and partially overlaps the horizontal power line 18'.

At this time, the first capacitor (C1 in FIG. 2) between the second node ND2 and the second reference power source VSS corresponds to an overlapping area between the horizontal power line 18' and the anode electrode Anode. In addition, the first capacitor C1 also corresponds to an overlapping region between the horizontal power line 18' and the first conductive pattern 151'.

That is, according to another embodiment of the present invention, the horizontal power line 18' is disposed in a layer between the first conductive pattern 151' and the anode electrode. Accordingly, the first capacitor C1 is generated in an overlapping region between the horizontal power line 18' and the anode electrode and in an overlapping region between the horizontal power line 18' and the first conductive pattern 151'. It can be. Accordingly, there is an advantage in that the capacitance of the first capacitor C1 corresponding to the limited area can be increased.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the technical spirit of the present invention. Conventionally in the art to which the present invention belongs It will be clear to those who have knowledge of

T1, T2, T3: first, second, third thin film transistors
C1, C2, C3: 1st, 2nd, 3rd capacitors
OLED: organic light emitting device
14: data line
15a, 15b: first and second gate lines
16: 1st power line
17: cathode power line
18: horizontal power line

Claims (12)

an organic light emitting element corresponding to each pixel area;
Between a first power line for supplying first driving power of a first voltage corresponding to driving of the organic light emitting device and a second power line for supplying second driving power of a second voltage lower than the first voltage a first thin film transistor disposed in series with the organic light emitting device;
a second thin film transistor disposed between a first node corresponding to the gate electrode of the first thin film transistor and a second node between the first thin film transistor and the organic light emitting element; and
A first capacitor disposed between the second node and the second power line;
The second power line is connected to the first capacitor through a horizontal power line and connected to the organic light emitting device through a cathode power line.
According to claim 1,
The second power line is
the horizontal power line corresponding to each horizontal line composed of pixel areas arranged in parallel in a horizontal direction among a plurality of pixel areas defined in the display area and connected to the first capacitor; and
An organic light emitting display device comprising the cathode power line connected to the cathode electrode of the organic light emitting device.
According to claim 2,
The first thin film transistor
a first active pattern including a channel region and first and second electrode regions corresponding to both ends of the channel region; and
and a gate electrode disposed on a gate insulating layer covering the first active pattern, overlapping a channel region of the first active pattern, and covered with a plurality of interlayer insulating layers.
According to claim 3,
The horizontal power line is disposed on any one of the plurality of interlayer insulating films,
The first power line is disposed on a layer different from the horizontal power line on any other interlayer insulating film among the plurality of interlayer insulating films,
A first electrode region of the first active pattern is connected to the first power line.
According to claim 4,
The first capacitor is disposed on the same layer as the first power line and corresponds to an overlapping area between the horizontal power line and a first conductive pattern connected to the second electrode area of the first active pattern. .
According to claim 4,
An anode electrode of the organic light emitting device is disposed on a final insulating layer covering the horizontal power supply line and is connected to a second electrode region of the first active pattern,
The first capacitor corresponds to an overlapping region between the horizontal power line and the anode electrode.
According to claim 3,
a third thin film transistor disposed between a third node and a data line for supplying a data signal to each of the pixel areas;
a second capacitor disposed between the third node and the first node; and
and a third capacitor disposed between the third node and the first power line.
According to claim 7,
The second capacitor corresponds to an overlapping region between the gate electrode and the first capacitor electrode disposed on the first interlayer insulating film covering the gate electrode,
The third capacitor corresponds to an overlapping region between the first capacitor electrode and the second capacitor electrode disposed on the second interlayer insulating layer covering the first capacitor electrode.
According to claim 8,
The horizontal power line is disposed on a third interlayer insulating film covering the second capacitor electrode,
The first power line is disposed on a fourth interlayer insulating film covering the horizontal power line,
The first electrode region of the first active pattern is connected to the first power line through a contact hole penetrating the gate insulating layer and the first, second, third, and fourth interlayer insulating layers.
According to claim 9,
The first capacitor is disposed on the fourth interlayer insulating layer and is connected to the second electrode region of the first active pattern through a contact hole passing through the gate insulating layer and the first, second, third, and fourth interlayer insulating layers. An organic light emitting display device corresponding to an overlapping region between a connected first conductive pattern and the horizontal power line.
According to claim 8,
The first power line is disposed on a third interlayer insulating film covering the second capacitor electrode,
A first electrode region of the first active pattern is connected to the first power line through a contact hole penetrating the gate insulating layer and the first, second, and third interlayer insulating layers;
The horizontal power line is disposed on a fourth interlayer insulating layer covering the first power line.
According to claim 11,
An anode electrode of the organic light emitting device is disposed on a final insulating film covering the horizontal power line,
The first capacitor corresponds to an overlapping region between the horizontal power line and the anode electrode.

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