KR102584150B1 - Thin film transistor and organic light emitting display device comprising the same - Google Patents

Abstract

One embodiment of the present invention includes a first active pattern, a gate pattern disposed on a first active insulating film covering the first active pattern and overlapping the first active pattern, and a gate insulating film covering the gate pattern, and A portion of the first active pattern and a second active pattern overlapping the gate pattern are disposed on an interlayer insulating film covering the second active pattern and correspond to an overlap area between the first and second active patterns, and the first and an active jumping pattern connecting the first and second active patterns through an active contact hole exposing the second active pattern.

Description

Thin film transistor and organic light emitting display device including the same {THIN FILM TRANSISTOR AND ORGANIC LIGHT EMITTING DISPLAY DEVICE COMPRISING THE SAME}

The present invention relates to a thin film transistor and an organic light emitting display device including the same.

Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. Accordingly, research is continuing to develop display devices that are thinner, lighter, and have lower power consumption.

Representative examples of display devices include Liquid Crystal Display device (LCD), Plasma Display Panel device (PDP), Field Emission Display device (FED), and Electro Luminescence. Display device (ELD), Electro-Wetting Display device (EWD), and Organic Light Emitting Display device (OLED).

These flat panel displays generally include a polarizing material or light-emitting material disposed between a pair of opposing substrates bonded together.

For example, in the case of an organic light emitting display device, it is disposed between a pair of substrates and includes an organic light emitting device corresponding to each pixel area, and the organic light emitting device includes a light emitting layer made of an organic light emitting material. As another example, in the case of a liquid crystal display device, it is disposed between a pair of substrates and includes a liquid crystal layer made of liquid crystal, and the liquid crystal is a material that polarizes light by tilting according to an electric field.

In addition, each display device defines a plurality of pixel areas corresponding to a display area where an image is actually displayed, and may include a thin film transistor array substrate that drives each pixel area. The thin film transistor array substrate includes at least one thin film transistor corresponding to each pixel area.

Meanwhile, the scope of application of flat panel displays is expanding through thinner, lighter, and higher resolution. In particular, the flat panel display device can be implemented as a 3-Dimension Virtual Reality Device (3D VR device).

In order to implement higher resolution of the display device, when a larger number of pixel areas are arranged in a limited display area, the area of each pixel area is greatly reduced. In particular, in the case of a 3-Dimension Virtual Reality Device (3D VR device), the area of each pixel area can be reduced by more than 1/20 times compared to a typical display device.

In this way, as the area of each pixel area is reduced, the area allocated to the thin film transistor of each pixel area is reduced.

That is, by being disposed in a reduced area of the pixel area, the channel width and channel length of the thin film transistor are reduced. As a result, there is a problem in that the voltage-current characteristics of the thin film transistor deteriorate as the kink effect intensifies.

In particular, in the case of an organic light emitting display device, the thin film transistor array substrate includes a driving transistor that supplies driving current to the organic light emitting element corresponding to each pixel area. If the uniformity of the voltage-current (Vds-Ids) characteristics of the driving transistor deteriorates, the luminance of the organic light emitting device in each pixel area cannot be stably controlled, which may lead to a decrease in the image quality of the display device.

Accordingly, there is a need to provide a thin film transistor that can prevent deterioration in uniformity of voltage-current characteristics even if it is disposed in a reduced area of the pixel area.

The present invention is intended to provide a thin film transistor and an organic light emitting display device including the thin film transistor that can prevent deterioration in uniformity of voltage-current characteristics even if disposed in a reduced area of the pixel area.

The objects of the present invention are not limited to the objects mentioned above, and other objects and advantages of the present invention that are not mentioned can be understood by the following description and will be more clearly understood by the examples of the present invention. Additionally, it will be readily apparent that the objects and advantages of the present invention can be realized by the means and combinations thereof indicated in the patent claims.

An example of the present invention includes a first active pattern, a gate pattern disposed on a first active insulating film covering the first active pattern and overlapping the first active pattern, and a gate pattern disposed on the gate insulating film covering the gate pattern and the first active insulating film. 1 A second active pattern overlapping a portion of the active pattern and the gate pattern, and disposed on an interlayer insulating film covering the second active pattern and corresponding to an overlap area between the first and second active patterns, and A thin film transistor including an active jumping pattern connecting the first and second active patterns through an active contact hole exposing the second active pattern is provided.

The thin film transistor may be disposed on a second active insulating film covering the second active pattern, and may further include at least a first back channel pattern overlapping the gate pattern. Here, the interlayer insulating film is disposed on the second active insulating film.

Each of the first and second active patterns overlaps a contact area corresponding to the active jumping pattern, a channel area overlapping the gate pattern, an electrode area corresponding to one side of the channel area, and the first back channel pattern. and includes a buffer area disposed between the channel area and the electrode area.

Here, the first back channel pattern is arranged to have a wider width than the gate pattern, and the buffer area corresponds to an area where the first back channel pattern protrudes compared to the gate pattern.

The electrode region of each of the first and second active patterns is a region doped with a P-type dopant at a higher concentration than the channel region, and the channel region and the buffer region of each of the first and second active patterns are This is a doping area.

Alternatively, the electrode region of each of the first and second active patterns is a region doped with a P-type dopant at a higher concentration than the channel region, the channel region of each of the first and second active patterns, and the second The buffer area of the active pattern is an undoped area, and the buffer area of the first active pattern is an area doped with a P-type dopant at a concentration lower than that of the electrode area and higher than that of the channel area.

Another example of the present invention is an organic light emitting display device including a plurality of pixel areas corresponding to a display area, an organic light emitting element corresponding to each pixel area, and a first driving device that supplies first driving power. An organic light emitting display device is provided including a first thin film transistor disposed in series with the organic light emitting element between a power line and a second driving power line that supplies a second driving power of a lower potential than the first driving power. Here, the first thin film transistor is disposed on a first active pattern, a first active insulating film covering the first active pattern, a gate pattern overlapping the first active pattern, and a gate insulating film covering the gate pattern, A second active pattern overlapping a portion of the first active pattern and the gate pattern, a first back channel pattern disposed on a second active insulating film covering the second active pattern and overlapping at least the gate pattern, and The first and second contact holes are disposed on the interlayer insulating film covering the first back channel pattern, correspond to an overlapping area between the first and second active patterns, and expose the first and second active patterns. Includes active jumping patterns that connect active patterns.

Each of the first and second active patterns overlaps a contact area corresponding to the active jumping pattern, a channel area overlapping the gate pattern, an electrode area corresponding to one side of the channel area, and the first back channel pattern. and includes a buffer area disposed between the channel area and the electrode area.

The electrode region of each of the first and second active patterns is a region doped with a P-type dopant at a higher concentration than the channel region, and the channel region and the buffer region of each of the first and second active patterns are This is a doping area.

Alternatively, the electrode region of each of the first and second active patterns is a region doped with a P-type dopant at a higher concentration than the channel region, the channel region of each of the first and second active patterns, and the second The buffer area of the active pattern is a non-doped area, and the buffer area of the first active pattern is an area doped with P-type dopant at a concentration higher than the channel area and lower than the electrode area.

A thin film transistor according to an embodiment of the present invention includes a first active pattern, a gate pattern on a first active insulating film covering the first active pattern, a second active pattern on a gate insulating film covering the gate pattern, and a second active pattern. It is disposed on the covering interlayer insulating film and includes an active jumping pattern connecting the first and second active patterns.

Here, the first and second active patterns are connected to each other by an active jumping pattern, and each of the first and second active patterns includes a channel region that overlaps the gate pattern. That is, the channel regions of the first and second active patterns correspond to the potential of the gate pattern and are connected to each other.

As a result, the thin film transistor can generate a channel with a length longer than the channel length of each active pattern by the first and second active patterns arranged in different layers and connected to each other. Therefore, there is an advantage that the voltage-current characteristics of the thin film transistor can be prevented from being deteriorated even if the thin film transistor is placed in a small area.

In the case of an organic light emitting display device including such a thin film transistor, there is an advantage in that it can be advantageous in high resolution and in that its usability can be improved.

1 is a diagram showing an organic light emitting display device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an example of an equivalent circuit of one pixel area shown in FIG. 1.
3 and 4 are diagrams showing an example of a plane of a thin film transistor array substrate including the pixel area of FIG. 2.
FIG. 5 is a diagram showing a cross section taken along line AA′ of FIG. 3.
Figure 6 is a diagram showing a cross section taken along line BB' in Figure 4.
FIG. 7 is a diagram showing a cross section taken along line CC' of FIG. 4.
Figure 8 is a diagram showing a method of manufacturing a thin film transistor array substrate for an organic light emitting display device according to a first embodiment of the present invention.
Figures 9 to 20 are diagrams showing each process in Figure 8.
FIG. 21 is a diagram showing line A-A' of FIG. 3 according to a second embodiment of the present invention.
Figure 22 is a diagram showing a method of manufacturing a thin film transistor array substrate for an organic light emitting display device according to a second embodiment of the present invention.
Figures 23 to 25 are diagrams showing some processes in the method of Figure 22.

The above-mentioned objects, features, and advantages will be described in detail later with reference to the attached drawings, so that those skilled in the art will be able to easily implement the technical idea of the present invention. In describing the present invention, if it is determined that a detailed description of known technologies related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the attached drawings. In the drawings, identical reference numerals are used to indicate identical or similar components.

Hereinafter, a thin film transistor and an organic light emitting display device including the same according to each embodiment of the present invention will be described in detail with reference to the attached drawings.

First, with reference to FIGS. 1 to 6, an organic light emitting display device and a thin film transistor included therein according to a first embodiment of the present invention will be described.

1 is a diagram showing an organic light emitting display device according to a first embodiment of the present invention. FIG. 2 is a diagram showing an example of an equivalent circuit of one pixel area shown in FIG. 1.

3 and 4 are diagrams showing an example of a plane of a thin film transistor array substrate including the pixel area of FIG. 2. FIG. 5 is a diagram showing a cross section taken along line A-A' of FIG. 3. FIG. 6 is a diagram showing a cross section taken along line B-B' of FIG. 4. FIG. 7 is a diagram showing a cross section taken along line C-C' of FIG. 4.

As shown in FIG. 1, an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 including a plurality of pixel areas (PXL) corresponding to a display area (AA) on which an image is displayed, A data driver 12 that drives the data line 14 of the display panel 10, a gate driver 13 that drives the scan line 15 of the display panel 10, a data driver 12, and a gate driver. It includes a timing controller (11) for controlling the driving timing of (13).

The display panel 10 has a scan line 15 corresponding to each horizontal line composed of pixel areas arranged side by side in the horizontal direction among the plurality of pixel areas PXL, and a vertical line among the plurality of pixel areas PXL. It includes a data line 14 corresponding to each vertical line composed of pixel areas arranged in parallel.

Here, the scan line may include a first scan line (15 in FIG. 2) that supplies the first scan signal (SCAN1) and a second scan line (17 in FIG. 2) that supplies the second scan signal (SCAN2). You can. As an example, the first scan signal SCAN1 may be used to sequentially select each horizontal line to write data in the pixel area PXL. Additionally, the second scan signal SCAN2 may be used to sequentially select each horizontal line for initialization or sensing of the pixel area.

A plurality of pixel areas (PXL) may be defined by scan lines 15 and data lines 14 that intersect each other. Accordingly, the plurality of pixel areas (PXL) are arranged in a matrix form in the display area (AA).

In addition, the display panel 10 has a first driving power line that supplies the first driving power (VDD) to the plurality of pixel areas (PXL), and a second driving power (VSS) with a potential lower than the first driving power (VDD). ) and a reference power line that supplies reference power (VREF).

The timing controller 11 rearranges digital video data (RGB) input from the outside to match the resolution of the display panel 10, and supplies the rearranged digital video data (RGB') to the data driver 12.

And, the timing controller 11 operates the data driver 12 based on timing signals such as the vertical synchronization signal (Vsync), the horizontal synchronization signal (Hsync), the dot clock signal (DCLK), and the data enable signal (DE). A data control signal (DDC) for controlling the operation timing and a gate control signal (GDC) for controlling the operation timing of the gate driver 13 are supplied.

The data driver 12 converts the rearranged digital video data (RGB') into an analog data voltage based on the data control signal (DDC). Then, the data driver 12 supplies a data signal (VDATA) to the pixel area of each horizontal line during each horizontal period based on the rearranged digital video data (RGB').

The gate driver 13 may generate a first scan signal (SCAN1) and a second scan signal (SCAN2) based on the gate control signal (GDC).

Although not separately shown, the display panel 10 includes a pair of opposing substrates bonded together and an organic light emitting element array disposed between them. In addition, one of the pair of substrates is a thin film transistor array substrate for defining a plurality of pixel regions (PXL) and supplying driving current to the organic light emitting device of each pixel region (PXL).

As shown in FIG. 2, each pixel area (PXL) includes an organic light emitting device (OLED), first, second, and third thin film transistors (T1, T2, T3), and a storage capacitor (Cst).

An organic light emitting device (OLED) includes an anode electrode, a cathode electrode, and an organic light emitting layer (not shown) disposed between them. Exemplarily, the organic light-emitting layer includes a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer. Alternatively, the organic light-emitting layer may further include an electron injection layer.

The first thin film transistor (T1) has a first driving power line 16 that supplies the first driving power (VDD) and a second driving power line (16) that supplies a second driving power (VSS) with a potential lower than the first driving power (VDD). It is placed in series with an organic light emitting device (OLED) between the driving power lines.

The second thin film transistor T2 is disposed between the data line 14 that supplies the data signal VDATA and the gate electrode of the first thin film transistor T1.

When this second thin film transistor (T2) is turned on based on the first scan signal (SCAN1) of the first scan line (15), the gap between the gate electrode of the first thin film transistor (T1) and the second thin film transistor (T2) is turned on. A data signal (VDATA) is supplied to the first node (ND1).

The storage capacitor Cst is disposed between the first node ND1 and the second node ND2. The second node (ND2) is a contact point between the first thin film transistor (T1) and the organic light emitting device (OLED).

This storage capacitor Cst is charged based on the data signal VDATA supplied to the first node ND1 through the turned-on second thin film transistor T2.

And, when the first thin film transistor (T1) is turned on based on the charging voltage of the storage capacitor (Cst), the driving current corresponding to the data signal (VDATA) is supplied to the second node (ND2), that is, to the organic light emitting device (OLED). supply.

The third thin film transistor T3 is disposed between the reference power line 18 that supplies the reference power VREF and the second node ND2.

When this third thin film transistor (T3) is turned on based on the second scan signal (SCAN2) of the second scan line (17), it supplies the reference power (VREF) to the second node (ND2), or The potential of (ND2) is transmitted to the reference power line (18).

As shown in FIG. 3, the thin film transistor array substrate 100 of the organic light emitting display device according to the first embodiment of the present invention includes first, second, and third thin film transistors ( T1, T2, T3) and a storage capacitor (Cst in FIG. 2).

In addition, the thin film transistor array substrate 100 has first and second scan lines 15 and 17 in a first direction (horizontal direction in FIG. 3) and a data line 14 in a second direction (vertical direction in FIG. 3). ), and further includes a first driving power line 16 and a reference power line 18.

The first thin film transistor T1 has first and second active patterns 120 and 141, a gate pattern 130 overlapping with the first and second active patterns 120 and 141, and first and second active patterns, respectively. It includes an active jumping pattern (161) connecting (120, 141).

Here, the first active pattern 120 is disposed lower than the gate pattern 130, and the second active pattern 141 is disposed higher than the gate pattern 130. That is, the gate pattern 130 becomes a top gate for the first active pattern 120 and a bottom gate for the second active pattern 141.

In addition, the first thin film transistor T1 further includes first and second back channel patterns 150 and 110 overlapping the gate pattern 130. Here, the first back channel pattern 150 is disposed above the second active pattern 141, and the second back channel pattern 110 is disposed below the first active pattern 120.

The first back channel pattern 150 is arranged to have a wider width than the gate pattern 130. In particular, the first back channel pattern 150 is arranged to have a width greater than that of the gate pattern 130 in a direction parallel to the channel length of the first and second active patterns 120 and 141. Accordingly, the first back channel pattern 150 includes a region that protrudes compared to the gate pattern 130.

The first and second back channel patterns 150 and 110 may be connected to each other through a back channel jumping pattern 162. Additionally, the back channel jumping pattern 162 may extend in the horizontal direction and be connected to the reference power line 18. Accordingly, the first and second back channel patterns 150 and 110 can be connected to the reference power line 18 through the back channel jumping pattern 162.

However, although not separately shown, the back channel jumping pattern 162 connected to the first and second back channel patterns 150 and 110 is not the reference power line 18, but the first driving power supply (VDD in FIG. 2). ), a second driving power line (not shown) supplying the second driving power (VSS in FIG. 2), and a constant voltage line (not shown) supplying a separate back channel constant voltage. It may be connected to any one of the following.

One side of the first active pattern 120 is adjacent to the first driving power line 16. A portion of the first active pattern 120 is connected to the first driving power line 16 through the first electrode jumping pattern 163. Here, the first electrode jumping pattern 163 corresponds to the overlap area between the first active pattern 120 and the first driving power line 16.

A portion of the second active pattern 141 is connected to the second electrode jumping pattern 164.

Although not shown in detail in FIG. 3, the organic light emitting device (OLED in FIG. 2) is connected to the second active pattern 141 of the first thin film transistor T1 through the second electrode jumping pattern 164. That is, the second electrode jumping pattern 164 corresponds to the second node (ND2 in FIG. 2) between the first thin film transistor T1 and the organic light emitting device (OLED in FIG. 2).

In addition, although not shown in detail in FIG. 3, the storage capacitor (Cst in FIG. 2) may correspond to an area where the gate pattern 130 and the second active pattern 141 of the first thin film transistor T1 overlap.

As shown in FIG. 4, the gate pattern 130 of the first thin film transistor T1 is connected to the second thin film transistor T2 through the gate jumping pattern 165.

The second thin film transistor T2 includes a third active pattern 142 disposed on the same layer as the second active pattern 141. The third active pattern 142 partially overlaps the first scan line 15.

One side of the third active pattern 142 is connected to the gate pattern 130 of the first thin film transistor T1 through the gate jumping pattern 165.

The other side of the third active pattern 142 is connected to the data line 14 through the data jumping pattern 166.

And, the third thin film transistor T3 includes a fourth active pattern 143 disposed on the same layer as the second active pattern 141. The fourth active pattern 143 partially overlaps the second scan line 17.

The fourth active pattern 143 may be a pattern that is continuous with the second active pattern 141.

One side of the fourth active pattern 143 is connected to the organic light emitting device (OLED in FIG. 2) through the second electrode jumping pattern 164.

The other side of the fourth active pattern 143 is connected to the reference power line 18 through the reference power jumping pattern 167.

As shown in FIG. 5, the first thin film transistor T1 includes a first active pattern 120, a gate pattern 130 disposed on the first active insulating film 103 covering the first active pattern 120, and A second active pattern 141 disposed on the gate insulating film 104 covering the gate pattern 130, and an active jumping pattern ( 161).

In addition, the first thin film transistor T1 may further include a first back channel pattern 150 disposed on the second active insulating film 105 covering the second active pattern 141.

Additionally, the first thin film transistor T1 may further include a second back channel pattern 110 on the substrate 101. In this case, the first active pattern 120 is disposed on the dummy insulating film 102 covering the second back channel pattern 110.

First, the first active pattern 120 is disposed on the dummy insulating film 102 and may overlap the second back channel pattern 110.

This first active pattern 120 overlaps the second active pattern 141 and includes a contact area 120a corresponding to the active jumping pattern 161, a channel area 120b overlapping the gate pattern 130, and a channel area. An electrode area 120c corresponding to one side (right side of FIG. 5) of 120b and a buffer area overlapping with the first back channel pattern 150 and disposed between the channel area 120b and the electrode area 120c ( 120d).

In addition, the first active pattern 120 may further include an additional buffer area 120d' that overlaps the first back channel pattern 150 and is disposed between the contact area 120a and the channel area 120b. However, this is only an example, and the first active pattern 120 may not include the additional buffer area 120d' depending on the target for the voltage-current characteristics of the first thin film transistor T1.

The gate pattern 130 is disposed on the first active insulating film 103 covering the first active pattern 120. The gate pattern 130 overlaps the channel region 120b of the first active pattern 120.

The second active pattern 141 is disposed on the gate insulating film 104 covering the gate pattern 130.

This second active pattern 141 overlaps the first active pattern 120 and includes a contact area 141a corresponding to the active jumping pattern 161, a channel area 141b overlapping the gate pattern 130, and a channel area. An electrode area (141c) corresponding to one side (left side of FIG. 5) of (141b) and a buffer area (141c) that overlaps with the first back channel pattern (150) and is disposed between the channel area (141b) and the electrode area (141c) 141d).

Additionally, the second active pattern 141 may further include an additional buffer area 141d' that overlaps the first back channel pattern 150 and is disposed between the contact area 141a and the channel area 141b. However, this is only an example, and the second active pattern 141 may not include the additional buffer area 141d' depending on the target for the voltage-current characteristics of the first thin film transistor T1.

The first back channel pattern 150 is disposed on the second active insulating film 105 covering the second active pattern 141.

The first back channel pattern 150 has a wider width than the gate pattern 130. In particular, in the direction of the length of the channel generated in the channel regions 120b and 141b of the first and second active patterns 120 and 141, the width of the first back channel pattern 150 is equal to that of the gate pattern 130. greater than the width of That is, the first back channel pattern 150 includes a protruding area compared to the gate pattern 130.

By this first back channel pattern 150, each of the first and second active patterns 120 and 141 forms a buffer area (120d, 141d) between the channel area (120b, 141b) and the electrode area (120c, 141c). may include.

Only the first active insulating layer 103 and the gate insulating layer 104 are disposed between the contact areas 120a and 141a of the first and second active patterns 120 and 141, respectively. That is, the gate pattern 130 is not disposed between the contact areas 120a and 141a of the first and second active patterns 120 and 141, respectively.

In addition, the contact areas 120a and 141a of the first and second active patterns 120 and 141 not only do not overlap with the gate pattern 130, but also do not overlap with the first back channel pattern 150.

Accordingly, the contact regions 120a and 141a of each of the first and second active patterns 120 and 141 are regions doped with a higher concentration of P-type dopant than the channel regions 120b and 141b.

The contact areas 120a and 141a of the first and second active patterns 120 and 141 are connected to each other through the active jumping pattern 161.

In this way, the contact areas (120a, 141a) of the highly doped first and second active patterns (120, 141) and the active jumping pattern (161) connecting them are the first and second active patterns disposed on different layers. It becomes a wiring connecting the channel areas (120b, 141b) of (120, 141).

Channel regions 120b and 141b of the first and second active patterns 120 and 141, respectively, overlap the gate pattern 130 and the first back channel pattern 150. Accordingly, the channel regions 120b and 141b of each of the first and second active patterns 120 and 141 become non-doped regions, and create a channel for carrier movement based on the potential of the gate pattern 130. .

Since the electrode regions (120c, 141c) of each of the first and second active patterns (120, 141) do not overlap with the first back channel pattern (150), they are doped with a P-type dopant with a higher concentration than the channel regions (120b, 141b). This is the doped area.

One of the electrode regions 120c and 141c of the first and second active patterns 120 and 141 (141c in FIG. 5) corresponds to a source electrode connected to the organic light emitting device (OLED in FIG. 2), and the other The remaining one (120c in FIG. 5) corresponds to the drain electrode connected to the first driving power line 16.

That is, when the organic light emitting device (OLED in FIG. 2) (not shown) is disposed above the interlayer insulating film 107, the drain electrode of the first thin film transistor T1 connected to the first driving power line 16 is Among the first and second active patterns 120 and 141, it may correspond to the electrode area 120c of the first active pattern 120 located relatively far from the organic light emitting device (not shown). And, the source electrode of the first thin film transistor (T1) connected to the organic light emitting device (OLED) is the second electrode disposed relatively adjacent to the organic light emitting device (not shown) among the first and second active patterns 120 and 141. It may correspond to the electrode area 141c of the active pattern 141. In this case, the electrode region 141c of the second active pattern 141 is connected to the second electrode jumping pattern 164 to be connected to the organic light emitting device (OLED).

Buffer areas (120d, 141d') of each of the first and second active patterns (120, 141) overlap with the first back channel pattern (150). Accordingly, the buffer areas 120d and 141d' of each of the first and second active patterns 120 and 141 become non-doped areas by the first back channel pattern 150.

However, the buffer areas 120d and 141d' of the first and second active patterns 120 and 141 do not overlap the gate pattern 130, and therefore do not generate a channel.

Carrier crowding phenomenon caused at the edges of the channel regions 120b and 141b adjacent to the electrode regions 120c and 141c by the buffer regions 120d and 141d' of the first and second active patterns 120 and 141, respectively. This can be alleviated. As a result, the kink effect of the first thin film transistor T1 can be suppressed.

Here, the kink effect is caused by carriers concentrated at the edges of the channel regions 120b and 141b under the influence of the source-drain voltage (Vds), so that the turn-on current of the thin film transistor according to the gate voltage above the threshold voltage is the source-drain voltage corresponding to the gate voltage. It is not maintained at the drain current (Ids) and shows a phenomenon that fluctuates under the influence of the source-drain voltage (Vds).

According to one embodiment of the present invention, the edges of the channel regions 120b and 141b are formed by the buffer regions 120d and 141d' disposed between the electrode regions 120c and 141c and the channel regions 120b and 141b. Since it does not contact the areas 120c and 141c, the carrier crowding phenomenon can be alleviated. As a result, it can be advantageous to stabilize the voltage-current characteristics of the first thin film transistor T1.

Meanwhile, the second back channel pattern 110 is disposed on the substrate 101 and overlaps at least the channel regions 120b and 141b of the first and second active patterns 120 and 141. By this second back channel pattern 110, light irradiated to the channel regions 120b and 141b of the first and second active patterns 120 and 141 is blocked, thereby causing the first thin film transistor T1 by light. The occurrence of leakage current can be prevented.

In addition, a predetermined constant voltage may be applied to the first and second back channel patterns 150 and 110. In this way, the channel generated in the channel region 141b of the second active pattern 141 by the constant voltage of the first back channel pattern 150 can be stably maintained. In addition, the channel generated in the channel region 120b of the first active pattern 120 can be stably maintained by the constant voltage of the second back channel pattern 110.

Illustratively, the first and second back channel patterns 150 and 110 are connected to each other through the back channel jumping pattern 162, and the first driving power line 16 and the second driving power line (not shown) and the reference power line 18. Alternatively, although not separately shown, the first and second back channel patterns 150 and 110 may be connected to a line that supplies separate back channel power.

Among the plurality of pixel areas, the data line 14, the first driving power line 16, and the reference power line 18 corresponding to the vertical lines composed of pixel areas arranged side by side in the vertical direction are the first back channel pattern ( It may be disposed on the first interlayer insulating film 106 covering the 150).

In addition, the jumping patterns 161, 162, and 163 for connecting patterns or lines of different layers are a second interlayer insulating film covering the data line 14, the first driving power line 16, and the reference power line 18. (107) It can be placed on phase.

As an example, the active jumping pattern 161 on the second interlayer insulating film 107 is formed through the active contact hole 161a exposing the contact areas 120a and 141a of the first and second active patterns 120 and 141. The contact areas 120a and 141a of the first and second active patterns 120 and 141 may be connected.

Here, the active contact hole 161a includes the first active insulating film 103, the gate insulating film 104, the second active pattern 141, the second active insulating film 105, the first interlayer insulating film 106, and the second interlayer. It may be a hole penetrating the insulating film 107.

The back channel jumping pattern 162 on the second interlayer insulating film 107 is disposed in an overlapping area between the first and second back channel patterns 150 and 110 and connects the first and second back channel patterns 150 and 110. The first and second back channel patterns 150 and 110 may be connected to each other through the exposed first back channel contact hole 162a.

In addition, the back channel jumping pattern 162 extends to the second back channel contact hole 162b exposing the reference power line 18, and is connected to the reference power line 18 through the second back channel contact hole 162b. can be connected

Accordingly, the first and second back channel patterns 150 and 110 can be connected to the reference power line 18 through the second back channel contact hole 162b.

The first electrode jumping pattern 163 on the second interlayer insulating film 107 is a first electrode that exposes the electrode area 120c of the first active pattern 120 and a portion of the first driving power line 16 overlapping therewith. The electrode area 120c of the first active pattern 120 and the first driving power line 16 are connected through the contact hole 163a.

However, this is only an example, and according to the design, the first electrode jumping pattern 163 extends in the horizontal direction, has a hole (not shown) corresponding to the electrode region 120c of the first active pattern 120, and a first electrode jumping pattern 163. 1 It may be a pattern connecting holes (not shown) corresponding to the driving power line 16.

As shown in FIG. 6, the second thin film transistor T2 includes a third active pattern 142 and a third active pattern 142 disposed on the gate insulating film 104 on the same layer as the second active pattern 141. ) includes a gate electrode formed as part of the first scan line 15.

Here, the first scan line 15 may be disposed on the second active insulating layer 105, like the first back channel pattern 150.

However, this is an example of the case where the second thin film transistor (T2) has a top gate structure, and when the second thin film transistor (T2) has a bottom gate structure, the first scan line 15 is similar to the gate pattern 130. , may be disposed on the first active insulating film 103.

The third active pattern 142 includes a channel region 142a overlapping the gate electrode formed as part of the first scan line 15, first and second electrode regions 142b disposed on both sides of the channel region 142a, and 142c).

One of the first and second electrode regions 142b and 142c of the third active pattern 142 (142b) is connected to the first thin film transistor (T1) through the gate jumping pattern 165 on the second interlayer insulating film 107. It can be connected to the gate pattern 130 of .

In addition, the remaining one (142c) of the first and second electrode regions (142b, 142c) of the third active pattern (142) is connected to the first interlayer insulating film through the data jumping pattern (166) on the second interlayer insulating film (107). It can be connected to the data line 14 on (106).

As shown in FIG. 7, the third thin film transistor T3 is formed on the fourth active pattern 143 and the fourth active pattern 143 disposed on the gate insulating film 104 on the same layer as the second active pattern 141. ) includes a gate electrode formed as part of the second scan line 17.

Here, the second scan line 17 may be disposed on the second active insulating layer 105, like the first back channel pattern 150.

However, this is an example of the case where the third thin film transistor (T3) has a top gate structure, and when the third thin film transistor (T3) has a bottom gate structure, the second scan line 17 has the same shape as the gate pattern 130. , may be disposed on the first active insulating film 103.

The fourth active pattern 143 includes a channel region 143a overlapping the gate electrode formed as part of the second scan line 17, first and second electrode regions 143b disposed on both sides of the channel region 143a, 143c).

One of the first and second electrode regions 143b and 143c of the fourth active pattern 143 (143b) is connected to the first interlayer insulating film 106 through the reference power jumping pattern 167 on the second interlayer insulating film 107. ) can be connected to the reference power line 18 on the

And, the remaining one (143c) of the first and second electrode regions (143b, 143c) of the fourth active pattern (143) is the electrode region (141c) of the second active pattern (141) of the first thin film transistor (T1). ), and may be connected to the second electrode jumping pattern 164 for connection to the organic light emitting device (OLED).

As described above, the first thin film transistor (T1) according to the first embodiment of the present invention includes the first and second active patterns (120, 141) arranged in different layers and an active contact hole (161a) connecting them. Includes. That is, the channel regions 120b and 141b of the first and second active patterns 120 and 141 are connected to each other through the contact regions 120a and 141a and the active contact hole 161a, thereby forming the first and second active patterns 120 and 141. The length of the channel generated at (120, 141) may not be limited to the area of the pixel area. Accordingly, even if it is disposed in a pixel area of a reduced area, a decrease in current-voltage characteristics of the thin film transistor due to a decrease in channel length can be prevented. Display devices containing such thin film transistors can be advantageous for higher resolution and improved usability.

Next, a method of manufacturing an organic light emitting display device according to a first embodiment of the present invention will be described with reference to FIGS. 8 to 22.

Figure 8 is a diagram showing a method of manufacturing a thin film transistor array substrate for an organic light emitting display device according to a first embodiment of the present invention. Figures 9 to 20 are diagrams showing each process in Figure 8.

As shown in FIG. 8, the method of manufacturing an organic light emitting display device according to the first embodiment of the present invention includes the steps of disposing a second back channel pattern on a substrate and disposing a dummy insulating film covering the second back channel pattern. (S10), disposing a first semiconductor material pattern on the dummy insulating film, and disposing a first active insulating film covering the first semiconductor material pattern (S20), disposing a gate pattern on the first active insulating film, and forming the gate pattern. A step of disposing a gate insulating film covering (S30), disposing a second semiconductor material pattern on the gate insulating film, and disposing a second active insulating film covering the second semiconductor material pattern (S40), on the second active insulating film. Arranging the first back channel pattern (S50), doping the first and second semiconductor material patterns using a high concentration of P ⁺ type dopants (S60), Disposing a first interlayer insulating film, disposing a first driving power line on the first interlayer insulating film, disposing a second interlayer insulating film covering the first driving power line (S70), and disposing at least one contact hole, It includes arranging at least one jumping pattern on the second interlayer insulating film (S80).

As shown in FIGS. 9 and 10, a second back channel pattern 110 corresponding to a part of each pixel area (PXL in FIG. 1) is disposed on the substrate 101, and the second back channel pattern 110 ) is placed to cover the dummy insulating film 102. (S10) Here, the second back channel pattern 110 may be made of a metal material that is conductive and reflective.

Next, the first semiconductor material pattern 201 overlapping a portion of the second back channel pattern 110 is disposed on the dummy insulating film 102, and the first active insulating film 103 covers the first semiconductor material pattern 201. ) is placed. (S20) Here, the first semiconductor material pattern 201 may be made of a semiconductor material whose conductivity can be increased by doping. By way of example, the first semiconductor material pattern 201 may be made of LTPS (low-temperature grown polysilicon).

As shown in FIGS. 11 and 12, a gate pattern 130 is disposed on the first active insulating film 103 to overlap a portion of the first semiconductor material pattern 201, and a gate covering the gate pattern 130 is formed. An insulating film 104 is disposed. (S30)

13 and 14, the second semiconductor material pattern 202 is disposed on the gate insulating layer 104, and the second active insulating layer 105 is disposed to cover the second semiconductor material pattern 202. . (S40)

Here, in addition to the second semiconductor material pattern 202 corresponding to the first thin film transistor (T1 in FIG. 2), the third semiconductor material pattern 202a and the third semiconductor material pattern 202a corresponding to the second thin film transistor (T2 in FIG. 2). A fourth semiconductor material pattern 202b corresponding to a thin film transistor (T3 in FIG. 2) may be disposed on the gate insulating film 104. In this case, the third and fourth semiconductor material patterns 202a and 202b are covered with the second active insulating film 105.

As shown in FIGS. 15 and 16, the first back channel pattern 150 is disposed on the second active insulating layer 105. (S50) At this time, the first and second scan lines 15 and 17, along with the first back channel pattern 150, are disposed on the second active insulating film 105.

The first back channel pattern 150 overlaps the gate pattern 130 and has a width larger than the gate pattern 130.

The first scan line 15 is arranged in the horizontal direction (left and right directions in FIG. 15), and a portion of the first scan line 15 overlaps the third semiconductor material pattern 202a.

The second scan line 17 is arranged in the horizontal direction (left and right directions in FIG. 15), and a portion of the second scan line 17 overlaps the fourth semiconductor material pattern 202b.

Subsequently, using the first back channel pattern 150 and the first and second scan lines 15 and 17 as masks, the first, second, third and fourth semiconductor material patterns 201, 202, and 202a , 202b) is doped (P ⁺ dopping) with a high concentration of P-type dopant. (S60)

In this way, a portion of the first semiconductor material pattern 201 is doped with a high concentration of P-type dopant, thereby corresponding to the first thin film transistor T1 and forming a contact region 120a, a channel region 120b, and an electrode region 120c. ) and a buffer area 120d. A first active pattern 120 is provided.

In the first active pattern 120, the channel area 120b overlaps the first back channel pattern 150 to become a non-doped area and overlaps the gate pattern 130. The contact area 120a and the electrode area 120c correspond to both sides of the channel area 120b and are doped with high concentration P ⁺ type. The buffer area 120d does not overlap the gate pattern 130 but overlaps the first back channel pattern 150, thereby becoming a non-doped area, and is disposed between the channel area 120b and the electrode area 120c.

In addition, a portion of the second semiconductor material pattern 202 is doped with a high concentration of P-type dopant, thereby corresponding to the first thin film transistor T1 and forming a contact region 141a, a channel region 141b, and an electrode region 141c. and a second active pattern 141 composed of a structure including a buffer area 141d is provided.

In the second active pattern 141, the channel area 141b becomes a non-doped area by overlapping with the first back channel pattern 150 and overlapping with the gate pattern 130. The contact area 141a and the electrode area 141c correspond to both sides of the channel area 141b and are doped with high concentration P ⁺ type. The buffer area 141d does not overlap the gate pattern 130 but overlaps the first back channel pattern 150, thereby becoming a non-doped area, and is disposed between the channel area 141b and the electrode area 141c.

And, referring to FIG. 6, a portion of the third semiconductor material pattern 202a is doped with a high concentration of P-type dopant, thereby corresponding to the second thin film transistor T2 and forming the channel region 142a and the channel region 142a. A third active pattern 142 composed of a structure including first and second electrode regions 142b and 142c on both sides is provided.

In the third active pattern 142, the channel region 142a overlaps the first scan line 15 to become an undoped region, and the first and second electrode regions 142b and 142c are high-concentration P ⁺ type. It is doped.

Additionally, referring to FIG. 7, a portion of the fourth semiconductor material pattern 202b is doped with a high concentration of P-type dopant, thereby corresponding to the third thin film transistor T3 and the channel region 143a. A fourth active pattern 143 composed of a structure including first and second electrode regions 143b and 143c on both sides is provided.

In the fourth active pattern 143, the channel region 143a overlaps the second scan line 17 to become an undoped region, and the first and second electrode regions 143b and 143c are high-concentration P ⁺ type. It is doped.

Next, as shown in FIGS. 17 and 18, the first interlayer insulating film 106 covering the first back channel pattern 150 and the first and second scan lines 15 and 17 is disposed, and the first interlayer insulating film 106 is formed. A data line 14, a first driving power line 16, and a reference power line 18 corresponding to vertical lines are disposed on the insulating film 106. Next, a second interlayer insulating film 107 is disposed to cover the data line 14, the first driving power line 16, and the reference power line 18. (S70)

Here, the data line 14 may include a protruding area that overlaps a portion of the third active pattern 143.

Additionally, the first driving power line 16 may include a protruding area that overlaps a portion of the first active pattern 120 .

19 and 20, a plurality of contact holes penetrating at least the second interlayer insulating film 107 are disposed, and a plurality of contact holes each corresponding to at least one contact hole are formed on the second interlayer insulating film 107. Arrange jumping patterns (161, 162, 163, 164, 165, 166, 167). (S80)

As an example, the active jumping pattern 161 is connected to the first and second active patterns 120 and 141 through the active contact hole 161a exposing a portion of each of the first and second active patterns 120 and 141. Connects the contact areas 120a and 141a.

The first electrode jumping pattern 163 is connected between the first active pattern 120 and the first driving power line 16 through a contact hole exposing the first active pattern 120 and the first driving power line 16. Connect.

As described above, according to the first embodiment of the present invention, the high-concentration P ⁺ type doping process is performed only once on the first and second active patterns 120 and 141 disposed in different layers. This has the advantage that the manufacturing process can be relatively simplified.

Meanwhile, according to the first embodiment, between the channel regions 120b and 141b and the electrode regions 120c and 141c of each of the first and second active patterns 120 and 141, a gate pattern 130 is formed in an undoped state. ) and buffer areas (120d, 141d) that do not overlap are arranged.

These buffer areas (120d, 141d) have the advantage of relieving the carrier crowding phenomenon and suppressing the kink effect, but have the disadvantage of increasing the turn-on resistance of the thin film transistor.

Accordingly, the second embodiment provides a thin film transistor capable of reducing turn-on resistance and an organic light emitting display device including the same.

FIG. 21 is a diagram showing line A-A' of FIG. 3 according to a second embodiment of the present invention.

As shown in FIG. 21, the first thin film transistor T1 of the organic light emitting display device 100' according to the second embodiment of the present invention has a buffer area 120d" of the first active pattern 120. Since it is the same as the first embodiment except that it is a low concentration P ^- type doped region rather than a doped region, redundant description will be omitted below.

That is, the first active pattern 120 of the first thin film transistor T1 according to the second embodiment is in an undoped state, and the channel region 120b overlaps the gate pattern 130 and both sides of the channel region 120b. The contact region 120a and the electrode region 120c are doped with a high concentration of P ⁺ type and are disposed between the channel region 120b and the electrode region 120c and doped with a P ⁺ type at a lower concentration than the electrode region 120c. It is doped with a structure that includes a buffer area (120d") that does not overlap the gate pattern (130).

Figure 22 is a diagram showing a method of manufacturing a thin film transistor array substrate for an organic light emitting display device according to a second embodiment of the present invention. Figures 23 to 25 are diagrams showing some processes in the method of Figure 22.

As shown in FIG. 22, the method of manufacturing an organic light emitting display device according to the second embodiment of the present invention uses a low concentration of P ^- type dopant before the step of disposing the gate insulating film (S40') to form a first semiconductor device. Since it is the same as the first embodiment of FIG. 8 except that it further includes a step of doping the material pattern (S100), redundant description will be omitted below.

As shown in FIG. 23, after placing the gate pattern 130 on the first active insulating film 103 (S30'), using the gate pattern 130 as a mask, the first active insulating film 102 is 1 The semiconductor material pattern (201 in FIG. 10) is doped with a low concentration of P ^- type dopant. (S100)

Accordingly, some areas of the first semiconductor material pattern 201' overlapping with the gate pattern 130 are undoped, and the remaining areas excluding this are doped with a low concentration of P ^- type.

Next, as shown in FIG. 24, a gate insulating film 104 covering the gate pattern 130 is disposed (S30), a second semiconductor material pattern 202 is disposed on the gate insulating film 104, and the second semiconductor material pattern 202 is disposed on the gate insulating film 104. A second active insulating film 105 covering the active pattern 141 is disposed. (S40')

And, as shown in FIG. 25, after arranging the first back channel pattern 150 and the first and second scan lines 15 and 17 on the second active insulating film 105 (S50), the first Using the back channel pattern 150 and the first and second scan lines 15 and 17 as masks, the first, second, third and fourth semiconductor material patterns 201', 202, 202a, 202b Doping (P ⁺ dopping) is performed with a high concentration of P-type dopant. (S60)

Accordingly, the first active pattern 120 is in an undoped state and has a channel region 120b overlapping the gate pattern 130, and a contact region 120a corresponding to both sides of the channel region 120b and doped with a high concentration of P ⁺ type. ) and an electrode region 120c, and a buffer region 120d" disposed between the channel region 120b and the electrode region 120c, doped with a low concentration of P ^- type, and does not overlap the gate pattern 130. It consists of a structure.

In addition, the second active pattern 141 is in an undoped state and has a channel region 141b overlapping the gate pattern 130, and a contact region 141a corresponding to both sides of the channel region 141b and doped with a high concentration of P ⁺ type. ) and an electrode region 141c, and a buffer region 141d that is disposed between the channel region 141b and the electrode region 141c, is in an undoped state, and does not overlap the gate pattern 130.

As described above, according to the second embodiment, the turn-on of the first thin film transistor T1 is achieved by including the first active pattern 120 having a structure including a buffer region 120d" doped with a low concentration of P ^- type. Resistance can be reduced compared to the first embodiment.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible without departing from the technical spirit of the present invention. It will be clear to those who have the knowledge of.

T1, T2, T3: 1st, 2nd, 3rd thin film transistors
15: first scan line 17: second scan line
14: data line 16: first driving power line
18: Standard power line
120: first active pattern 130: gate pattern
141: 2nd active pattern
142, 143: 3rd and 4th active patterns
150: 1st back channel pattern 110: 2nd back channel pattern
161: Active jumping pattern 161a: Active contact hole
162: Back channel jumping pattern 163: First electrode jumping pattern
164: Second electrode jumping pattern 165: Gate jumping pattern
166: Data jumping pattern 167: Standard power jumping pattern
120a, 141a: contact area
120b, 141b: Channel area
120c, 141c: electrode area
120d, 120d", 141d: Buffer area

Claims (19)

first active pattern;
a gate pattern disposed on a first active insulating film covering the first active pattern and overlapping the first active pattern;
a second active pattern disposed on the gate insulating film covering the gate pattern and overlapping a portion of the first active pattern and the gate pattern; and
The first and second contact holes are disposed on the interlayer insulating film covering the second active pattern, correspond to an overlap area between the first and second active patterns, and expose the first and second active patterns. Includes an active jumping pattern connecting active patterns,
further comprising a first back channel pattern disposed on a second active insulating film covering the second active pattern and overlapping at least the gate pattern;
A thin film transistor wherein the interlayer insulating film is disposed on the second active insulating film.
delete According to claim 1,
Each of the first and second active patterns is
a contact area corresponding to the active jumping pattern;
a channel area overlapping the gate pattern;
an electrode area corresponding to one side of the channel area; and
A thin film transistor including a buffer region overlapping the first back channel pattern and disposed between the channel region and the electrode region.
According to claim 3,
The first back channel pattern is arranged to have a wider width than the gate pattern,
The buffer area is a thin film transistor corresponding to an area where the first back channel pattern protrudes compared to the gate pattern.
According to claim 3,
The electrode region of each of the first and second active patterns is a region doped with a P-type dopant at a higher concentration than the channel region,
A thin film transistor wherein the channel region and the buffer region of each of the first and second active patterns are undoped regions.
According to claim 3,
The electrode region of each of the first and second active patterns is a region doped with a P-type dopant at a higher concentration than the channel region,
The channel area of each of the first and second active patterns and the buffer area of the second active pattern are non-doped areas,
A thin film transistor wherein the buffer region of the first active pattern is doped with a P-type dopant at a concentration lower than the electrode region and higher than the channel region.
According to claim 3,
A thin film transistor wherein one of the electrode areas of the first and second active patterns corresponds to a source electrode, and the other one corresponds to a drain electrode.
According to claim 1,
a second back channel pattern disposed on the substrate and overlapping at least the gate pattern; and
Further comprising a dummy insulating film covering the second back channel pattern,
The first active pattern is a thin film transistor disposed on the dummy insulating film.
According to claim 8,
The first and second back channel patterns are disposed on the interlayer insulating film and correspond to an overlap area between the first and second back channel patterns through back channel contact holes exposing the first and second back channel patterns. A thin film transistor further including a back channel jumping pattern connecting the.
In an organic light emitting display device including a plurality of pixel areas corresponding to a display area,
Organic light emitting elements corresponding to each pixel area; and
A first thin film transistor disposed in series with the organic light emitting element between a first driving power line that supplies a first driving power and a second driving power line that supplies a second driving power with a potential lower than the first driving power. Contains,
The first thin film transistor is
first active pattern;
a gate pattern disposed on a first active insulating film covering the first active pattern and overlapping the first active pattern;
a second active pattern disposed on the gate insulating film covering the gate pattern and overlapping a portion of the first active pattern and the gate pattern;
a first back channel pattern disposed on a second active insulating film covering the second active pattern and overlapping at least the gate pattern; and
The first and second contact holes are disposed on the interlayer insulating film covering the first back channel pattern, correspond to an overlap area between the first and second active patterns, and expose the first and second active patterns. 2 An organic light emitting display device including an active jumping pattern connecting active patterns.
According to claim 10,
Each of the first and second active patterns is
a contact area corresponding to the active jumping pattern;
a channel area overlapping the gate pattern;
an electrode area corresponding to one side of the channel area; and
An organic light emitting display device comprising a buffer area overlapping the first back channel pattern and disposed between the channel area and the electrode area.
According to claim 11,
The first back channel pattern is arranged to have a wider width than the gate pattern,
The buffer area is an organic light emitting display device corresponding to an area where the first back channel pattern protrudes compared to the gate pattern.
According to claim 11,
The electrode region of each of the first and second active patterns is a region doped with a P-type dopant at a higher concentration than the channel region,
The organic light emitting display device wherein the channel area and the buffer area of each of the first and second active patterns are undoped areas.
According to claim 11,
The electrode region of each of the first and second active patterns is a region doped with a P-type dopant at a higher concentration than the channel region,
The channel area of each of the first and second active patterns and the buffer area of the second active pattern are non-doped areas,
The organic light emitting display device wherein the buffer region of the first active pattern is doped with a P-type dopant at a concentration higher than the channel region and lower than that of the electrode region.
According to claim 11,
One of the electrode areas of the first and second active patterns corresponds to a source electrode, and the other one corresponds to a drain electrode.
According to claim 15,
A first electrode disposed on the interlayer insulating film, corresponding to an overlap area between the electrode area of the first active pattern and the first driving power line, and exposing the electrode area of the first active pattern and the first driving power line. a first electrode jumping pattern connecting the electrode area of the first active pattern and the first driving power line through a contact hole; and
It further includes a second electrode jumping pattern connected to the electrode area of the second active pattern through a second electrode contact hole exposing a portion of the electrode area of the second active pattern,
An organic light emitting display device wherein the organic light emitting element is connected to the second electrode jumping pattern.
According to claim 10,
a second back channel pattern disposed on the substrate and overlapping at least the gate pattern;
a dummy insulating film covering the second back channel pattern; and
The first and second back channel patterns are disposed on the interlayer insulating film and correspond to an overlap area between the first and second back channel patterns through back channel contact holes exposing the first and second back channel patterns. It further includes a back channel jumping pattern connecting,
The first active pattern is disposed on the dummy insulating film.
According to claim 17,
The first driving power line and the reference power line supplying the reference power are disposed on the first interlayer insulating film covering the first back channel pattern,
The active jumping pattern and the back channel jumping pattern are disposed on a second interlayer insulating film covering the first driving power line and the reference power supply,
The back channel jumping pattern is connected to one of the first driving power line, the second driving power line, and the reference power line.
According to claim 18,
a second thin film transistor disposed between a data line supplying a data signal and the gate pattern of the first thin film transistor; and
The organic light emitting display device further includes a third thin film transistor disposed between the reference power line and the organic light emitting element.

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