KR20190048557A - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an organic light-emitting diode (OLED) display device, which can increase an aperture ratio of sub-pixels by reducing a non-aperture region by a signal wiring. According to an embodiment, each of the sub-pixels includes: an aperture region which overlaps a light-emitting region of each light-emitting device; and a non-aperture region in which a pixel circuit and signal wirings not overlapping the aperture region are positioned. A data line of each of the signal wirings is positioned between adjacent pixel circuits of the sub-pixels and includes a main portion and a plurality of fine patterns overlapping an aperture region of each light-emitting device. The plurality of fine patterns overlapping the aperture region of light-emitting device are connected in a parallel structure in the non-aperture region to be connected to the main portion. Each of the plurality of fine patterns of the data line is smaller than the main portion of the data line and has a line width within a specific range not recognized.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display device capable of increasing the aperture ratio of a subpixel by reducing a non-aperture region by signal wiring.

Display devices that display images using digital image data include liquid crystal displays (LCDs) using liquid crystals, OLED display devices using organic light emitting diodes (OLEDs), electrophoretic particles And an electrophoretic display (EPD), which is a typical example.

Among them, OLED display devices have advantages of high brightness, low driving voltage, ultra thin film, and free shape by using a self-luminous element that emits an organic light emitting layer by recombination of electrons and holes.

Each sub-pixel of the OLED display has an OLED element and a pixel circuit for driving the OLED element. The storage capacitor connected between the gate electrode and the source electrode of a driving thin film transistor (hereinafter, TFT) in the pixel circuit is connected to the data voltage supplied from the data line through the first switching TFT and the data voltage supplied from the reference line To the driving voltage. The driving TFT controls the driving current flowing from the power supply line to the OLED element according to the driving voltage charged in the capacitor, and the OLED element generates light proportional to the driving current value.

The OLED display device can be classified into a bottom emission structure and a top emission structure according to the direction in which the light generated from the OLED device proceeds. Since the OLED element of the bottom emission structure emits light through the aperture region which does not overlap with the pixel circuit and the signal lines, each subpixel has an aperture region corresponding to the emission region of the OLED element, Non-aperture region.

However, although the size of each subpixel decreases with increasing resolution in a bottom emission OLED display device, since there is a minimum separation distance for pattern separation between adjacent signal wirings in the same layer, the non-aperture region occupies There is a problem that the specific gravity increases and the opening area of the OLED element in each sub pixel decreases.

When the aperture region of the OLED element (i.e., the aperture ratio) is reduced in each sub-pixel, not only the luminance is reduced but also the current stress applied to the OLED element is increased, shortening the lifetime of the OLED element.

Therefore, there is a need to increase the aperture ratio of the subpixel by reducing the area of the non-aperture region to improve the display performance and lifetime of the OLED display of the bottom emission structure.

The present invention provides an OLED display device capable of increasing the aperture ratio of a subpixel by reducing a non-aperture region by signal wiring.

In an OLED display device according to an embodiment, each of the plurality of subpixels includes an aperture region overlapping a light emitting region of each light emitting element, a pixel circuit not overlapping the aperture region, and a non-aperture region in which a plurality of signal wires are located do. Each data line of the plurality of signal lines includes a main portion and a plurality of fine patterns overlapping the opening regions of the respective light emitting elements, which are located between pixel circuits of adjacent subpixels. A plurality of fine patterns overlapping the opening regions of the respective light emitting elements are connected in a parallel structure in the non-opening region and connected to the main portion. Each of the plurality of fine patterns of the data line is smaller than the main portion of the data line and has a line width within a specific range not recognized.

The plurality of subpixels include first to fourth subpixels arranged in parallel in the first direction and emitting light of different colors. The signal wirings located in the non-aperture region extend in the first direction and are connected in common to the pixel circuits of the first to fourth subpixels, and a plurality of gate lines connected in common to the pixel circuits of the first to fourth subpixels, One of the reference lines extending in the second direction and commonly connected to the pixel circuits of the first to fourth sub-pixels, and a second reference line extending in the second direction outside the first sub- A plurality of power supply lines connected to the pixel circuits of the first and second subpixels and extending in the second direction outside the fourth subpixel and connected to the third and fourth subpixels, The main portion of each of the first and second data lines extending in the second direction and the main portion of each of the third and fourth data lines extending in the second direction between the pixel circuits of the third and fourth sub- .

The aperture region of each subpixel is defined by the bank insulating film located in the non-aperture region. The bank insulating film is located between the opening regions of the first and second subpixels and between the opening regions of the third and fourth subpixels in the absence of the data line.

The first through fourth aperture regions of the first through fourth subpixels may have the same length in the second direction, but may have different widths in the second direction.

The first through fourth subpixels may correspond to red, white, blue, and green subpixels, respectively. The second aperture region of the white subpixel or the third aperture region of the blue subpixel may be wider than the first aperture region of the red subpixel and the fourth aperture region of the green subpixel.

The widths of the first to fourth opening regions of the red, white, blue, and green subpixels are set to be equal to the widths of the first opening region of the white subpixel, the third opening region of the blue subpixel, And the fourth opening region of the second opening region.

The first aperture region of the red subpixel overlaps with the red color filter, the third aperture region of the blue subpixel overlaps with the blue color filter, the fourth aperture region of the green subpixel overlaps with the green color filter, , And a plurality of fine patterns respectively located in the third and fourth aperture regions overlap with the red, blue, and green color filters, respectively.

The intervals between the plurality of fine patterns located in the respective opening regions of the first to fourth sub-pixels may be equal to each other.

A transparent electrode may be applied to the plurality of fine patterns located in the respective opening regions of the first to fourth sub-pixels.

The OLED display device according to an exemplary embodiment may form a parallel connection structure by dividing a portion of the data line, which is parallel to the opening region of each subpixel, into a plurality of minute patterns that are difficult to perceive and form a plurality of fine patterns, Thereby making it possible to reduce the non-opening area caused by the data line while maintaining the electrical characteristics of the data line.

Accordingly, the OLED display device according to an embodiment can increase the aperture ratio of each subpixel because it can reduce the non-aperture area by the data line and increase the aperture area of each subpixel as the non-aperture area is reduced have.

In addition, when a plurality of fine patterns overlapping the opening regions of the respective subpixels are formed as transparent electrodes, reduction in transmittance due to the fine patterns can be prevented.

Therefore, in the OLED display device according to the embodiment, the non-aperture region due to the signal wiring decreases and the aperture ratio of each sub-pixel increases, so that the display performance can be improved by the luminance increase, It is possible to increase the lifetime of the OLED device.

1 is a block diagram schematically showing a configuration of an OLED display device according to an embodiment of the present invention.
FIG. 2 is a diagram schematically showing the configuration of four subpixels according to an embodiment of the present invention. Referring to FIG.
3 is an equivalent circuit diagram illustrating the configuration of each subpixel according to an embodiment of the present invention.
4 is a diagram schematically showing a planar configuration of four subpixels according to an embodiment of the present invention.
5 is a cross-sectional view of the R and W subpixels shown in FIG. 4, taken along line I-I '.

FIG. 1 is a block diagram schematically showing a configuration of an OLED display device according to an embodiment of the present invention. FIG. 2 is a block diagram schematically showing the configuration of four subpixels according to an embodiment, 1 is an equivalent circuit diagram illustrating a configuration of each subpixel according to an embodiment.

The OLED display device shown in FIG. 1 includes a panel 1100, a gate driver 1200, a data driver 1300, a timing controller 1400, a memory 1500, a gamma voltage generator 1700, a power supply unit 1600, And the like.

The power supply unit 1600 supplies driving voltages necessary for driving the OLED display device, that is, the panel 1100, the gate driver 1200, the data driver 1300, the timing controller 1400, The memory 1500, the gamma voltage generator 1700, and the like. For example, the power supply unit 1600 supplies the digital circuit driving voltage supplied to the timing controller 1400 and the data driver 1300 and the like, the analog circuit driving voltage supplied to the data driver 1300, (Gate high voltage) VGH (gate high voltage) and gate off voltage VGL (gate low voltage) supplied to the driver 1200 and outputs a plurality of driving voltages EVDD and EVSS And a reference voltage, and supplies the reference voltage to the panel 1100 through the data driver 1300.

The timing controller 1400 receives image data and input timing control signals from the host system. The host system can be any one of a system of a portable terminal such as a computer, a TV system, a set-top box, a tablet or a cellular phone. The input timing control signals may include a dot clock, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like.

The timing controller 1400 controls the timing of driving the data driver 1300 using input timing control signals supplied from the host system and timing setting information (start timing, pulse width, etc.) Signals to the data driver 1300 and generates and supplies a plurality of gate control signals for controlling the driving timing of the gate driver 1200 to the gate driver 1200. [

The timing controller 1400 can perform various image processing such as luminance correction, image quality correction, and the like for reducing power consumption of the image data supplied from the host system. The timing controller 1400 compensates the image data by applying a compensation value for the characteristic deviation of each subpixel stored in the memory 1500, and supplies the compensated image data to the data driver 1300.

On the other hand, when the timing controller 1400 is in a sensing mode at least at any desired time such as a power-on time, a vertical blanking period, and a power-off time, (Threshold voltage of the driving TFT, mobility, threshold voltage of the OLED element, and the like) and update the compensation value for the characteristic deviation of each subpixel stored in the memory 1500 using the sensing result.

The gamma voltage generator 1700 generates a reference gamma voltage set including a plurality of reference gamma voltages having different voltage levels and supplies a reference gamma voltage set to the data driver 1300. [

The data driver 1300 converts the image data supplied from the timing controller 1400 into an analog data signal according to the data control signal supplied from the timing controller 1400 and supplies the analog data signal to the data lines of the panel 1100. The data driver 1300 subdivides the reference gamma voltage set supplied from the gamma voltage generator 1700 into a plurality of gradation voltages corresponding to the gradation values of the data. The data driver 1300 uses the subdivided gradation voltages to convert the digital data into an analog data voltage and supplies the data voltage to each of the data lines of the panel 1100. [ The data driver 1300 supplies the reference voltage Vref supplied from the voltage supply unit 1600 to the reference lines of the panel 1100 under the control of the timing controller 1400.

The data driver 1300 supplies a sensing data voltage to a data line to drive each sub pixel and, when the sensing mode is under the control of the timing controller 1400, May be sensed as a voltage through a reference line, converted into digital sensing data, and provided to the timing controller 1400.

The data driver 1300 includes a plurality of data ICs and may be mounted on a circuit film such as a COF to be bonded to the panel 1100 in TAB fashion or mounted on the panel 1100 in a COG fashion.

The gate driver 1200 drives the gate lines of the panel 1100 individually using a plurality of gate control signals supplied from the timing controller 1400. The gate driver 1200 supplies a pulse of the gate-on voltage VGH to the gate line during the driving period of the gate line, and supplies the gate-off voltage VGL to the gate line during the non-driving period of the gate line . The gate driver 1200 supplies a scan pulse to the scan gate line and a sense pulse to the sense gate line.

The gate driver 1200 is composed of a plurality of gate ICs and is individually mounted on a circuit film such as a COF (Chip On Film) or the like to be bonded to the panel 1100 by TAB (Tape Automatic Bonding) (Not shown). The gate driver 1200 is formed on the substrate together with the thin film transistor array constituting the pixel array of the panel 1100 so that the gate driver 1200 is embedded in a non-display area of one side or both sides of the panel 1100 in a GIP (Gate In Panel) .

The panel 1100 displays an image through a pixel array in which the sub-pixels SP are arranged in a matrix form. The basic pixel can be composed of at least three subpixels capable of white representation by color mixing among white (W), red (R), green (G) and blue (B) subpixels. For example, the basic pixel may be subpixels of R / G / B combination, subpixels of W / R / G combination, subpixels of B / W / R combination, subpixels of G / Or a combination of W / R / G / B combinations of subpixels.

Each subpixel SP includes an aperture region in which a light emitting region of an OLED element (light emitting element) having a bottom light emitting structure is located, and a non-aperture region occupied by a pixel circuit and a signal wiring that do not overlap with the aperture region.

In particular, one embodiment includes a power supply line extending in a second direction that intersects a first direction of a gate line, a data line, and a sub-drain region by reducing a non-aperture region by a data line of relatively small (capacitance) The aperture ratio of the pixel can be increased.

Specifically, a part of the data line parallel to the opening region of the subpixel is divided into a plurality of minute patterns that are difficult to recognize and formed into a parallel connection structure, and a plurality of fine patterns are overlapped with the opening region corresponding to the light emitting region of the OLED element, It is possible to reduce the non-opening area caused by the data line while maintaining the electrical characteristics of the data line. In addition, when a plurality of fine patterns are formed as transparent electrodes, reduction in transmittance due to a fine pattern can be prevented.

Accordingly, the aperture ratio of the subpixel can be increased because the aperture region of the subpixel can be increased instead of the non-aperture region by the data line.

2, each of the first to fourth sub-pixels SP1, SP2, SP3, and SP4 includes an opening region 10R, 10W, 10B, and 10G in which the light emitting region of the OLED element is located, 10W, 10B, and 10G). In the non-aperture region 20, signal lines that do not overlap with the pixel circuits 30 and the aperture regions 10R, 10W, 10B, and 10G connected to the OLED elements are located.

The first to fourth sub-pixels SP1, SP2, SP3, and SP4 may be sub-pixels that emit light of different colors. For example, the first through fourth sub-pixels SP1, SP2, SP3, and SP4 may be R subpixels, W subpixels, B subpixels, and G subpixels, respectively. The first to fourth sub-pixels SP1, SP2, SP3, and SP4 all include white OLED elements that emit white light, and the aperture regions 10R, 10B, and 10G of the R, G, The R, G, and B color filters can be individually applied to the R, G, and B light, respectively, and the opening area 10W of the W sub pixel can emit W light without the color filter.

the first and second gate lines GLn1 and GLn2 of the nth horizontal line extend in the first direction and are connected in common to the first to fourth subpixels SP1, SP2, SP3, and SP4. The first and second gate lines GLn1 and GLn2 may be integrated into one gate line.

The first through fourth sub-pixels SP1, SP2, SP3 and SP4 arranged in the first direction between the two power supply lines PL are connected to the first through fourth data lines DL1, DL2, DL3, Connected in common to one reference line RL1, and dividedly connected to two power supply lines PL. The data lines DL1, DL2, DL3 and DL4 have relatively small loads (capacitances) because the number of subpixels connected to the power supply line PL and the reference line RL1 is small.

The power supply line PL, the reference line RL1 and the data lines DL1, DL2, DL3 and DL4 extend in a second direction orthogonal to the first direction. The first and second subpixels SP1 and SP2 are connected in common to the power supply line PL on the left side and the third and fourth subpixels SP3 and SP4 are connected in common to the power supply line PL on the right side. have. One reference line RL1 commonly connected to the first to fourth sub-pixels SP1, SP2, SP3 and SP4 may be located between the second and third sub-pixels SP2 and SP4.

Each of the data lines DL1, DL2, DL3 and DL4 is located between the adjacent pixel circuits 30 and includes the main portion 40 and the opening regions 10R, 10W, 10B, and 10G, and has a plurality of fine patterns 50 that are hard to recognize, and a plurality of fine patterns 50 are connected in parallel for each sub-pixel. The first line width of the main portion 40 of each data line DL is larger than the second line width of each of the plurality of fine patterns 50. [

Each of the plurality of fine patterns 50 overlapping the opening regions 10R, 10W, 10B, and 10G of the sub-pixels SP1, SP2, SP3, and SP4 is formed in a range difficult to recognize, The reduction of transmittance due to the plurality of fine patterns 50 in the opening regions 10R, 10W, 10B, and 10G can be minimized. On the other hand, when the plurality of fine patterns 50 are formed as transparent electrodes, the decrease of the transmittance of the opening regions 10R, 10W, 10B, and 10G due to the fine patterns 50 can be improved.

Each of the first and second data lines DL1 and DL2 individually connected to the pixel circuits 30 of the first and second subpixels SP1 and SP2 includes first and second subpixels SP1 and SP2, And a plurality of fine patterns 50 overlapping with the opening regions 10R and 10W of the first and second sub pixels SP1 and SP2, do. Thus, the data line is not present between the opening regions 10R and 10W of the first and second sub-pixels SP1 and SP2, so that the non-aperture region 20 is reduced. Instead, the first and second sub- The opening ratio can be increased by increasing the widths W1 and W2 of the opening regions 10R and 10W of the first and second regions SP1 and SP2.

The third and fourth data lines DL3 and DL4 respectively connected to the pixel circuits 30 of the third and fourth subpixels SP3 and SP4 are respectively connected to the third and fourth subpixels SP3 and SP4, And a plurality of fine patterns 50 overlapping with the opening regions 10B and 10G of the third and fourth subpixels SP3 and SP4 do. Thus, the data line is not present between the aperture regions 10B and 10G of the third and fourth subpixels SP3 and SP4, so that the non-aperture region 20 is reduced, and instead of the third and fourth subpixels SP3 and SP4, It is possible to increase the aperture ratio by increasing the widths W3 and W4 of the aperture regions 10B and 10G of the first and second aperture regions SP3 and SP4. The intervals D1 between the plurality of fine patterns 50 in the first to fourth sub-pixels SP1, SP2, SP3 and SP4 may be equal to each other.

The widths W1 and W2 in the first direction are the same as the lengths L in the second direction of the opening regions 10R, 10W, 10B and 10G of the first to fourth sub-pixels SP1, SP2, SP3 and SP4. W3 and W4 are different from each other, the areas of the opening regions 10R, 10W, 10B and 10G of the first to fourth sub-pixels SP1, SP2, SP3 and SP4 may be different from each other.

For example, the width W1 of the W subpixel (SP1) opening region 10W can be set relatively large for the overall luminance enhancement of the OLED display. The width W2 of the aperture region 10B of the B subpixel SP3, which is known to have a short lifetime compared to other subpixels, can be set relatively large. The width W1 of the opening area 10W of the W sub pixel SP1 can be further extended toward the opening area 10R of the R sub pixel SP2. The width W3 of the opening region 10B of the B subpixel SP3 can be further extended toward the opening region 10G of the G subpixel SP4. The width W4 of the opening region 10G of the G subpixel SP4 can be minimized to match the color temperature. The widths W1, W2, W3 and W4 of the opening regions 10R, 10W, 10B and 10G of the first to fourth sub-pixels SP1, SP2, SP3 and SP4 are small in the order W2> W3> W4> W1 Can be.

3, each sub-pixel SP includes an OLED element 600 connected between a high potential power supply (first driving voltage) line PL and a low potential driving voltage (EVSS) line And a pixel circuit including at least a first and a second switching TFTs ST1 and ST2 and a driving TFT DT and a storage capacitor Cst to independently drive the OLED element 300. [ On the other hand, since the pixel circuit has various configurations other than the configuration of FIG. 3, various configurations can be applied.

The switching TFTs ST1 and ST2 and the driving TFT DT may be an amorphous silicon (a-Si) TFT, a poly-Si TFT, an oxide TFT, an organic TFT or the like have.

The OLED element 300 has an anode connected to the source node N2 of the driving TFT DT, a cathode connected to the EVSS line PW2, and an organic light emitting layer between the anode and the cathode. The anode is independent for each subpixel, but the cathode may be a common electrode shared by all the subpixels. When a drive current is supplied from the drive TFT DT, electrons from the cathode are injected into the organic light-emitting layer, holes from the anode are injected into the organic light-emitting layer, and electrons and holes recombine in the organic light- By emitting phosphors, light of brightness proportional to the current value of the drive current is generated.

The first switching TFT ST1 is driven by a scan pulse SCAN supplied from the gate driver 200 (Fig. 1) to the gate line GLn1 and is supplied from the data driver 300 (Fig. 1) to the data line DL And supplies the data voltage Vdata to the gate node N1 of the driving TFT DT.

The second switching TFT ST2 is driven by a sense pulse SENSE supplied from the gate driver 200 (Fig. 1) to the other gate line GLn2 and is supplied from the data driver 300 (Fig. 1) to the reference line RL. And supplies the reference voltage Vref supplied to the source terminal N2 of the driving TFT DT.

The storage capacitor Cst connected between the gate node N1 and the source node N2 of the driving TFT DT is connected to the gate node N1 and the source node N2 through the first and second switching TFTs ST1 and ST2. The first and second switching TFTs ST1 and ST2 are turned off when the difference voltage between the data voltage Vdata and the reference voltage Vref supplied to the first and second switching TFTs N1 and N2 is charged to the driving voltage Vgs of the driving TFT DT, And holds the charged driving voltage Vgs during the light emission period.

The driving TFT DT controls the current supplied from the EVDD line PL in accordance with the driving voltage Vgs supplied from the storage capacitor Cst and supplies the driving current determined by the driving voltage Vgs to the OLED element 300 Thereby causing the OLED element 300 to emit light.

On the other hand, when the sub-pixel SP is in the sensing mode, the driving TFT DT supplies the sensing data voltage Vdata, which is supplied through the data line DL and the first switching TFT ST1, And a reference voltage (Vref) supplied through the second switching TFT (ST2). The pixel current reflecting the electrical characteristics (threshold voltage, mobility) of the driving TFT DT is charged to the line capacitor of the reference line RL which is floating through the second switching TFT ST2. The data driver 300 (FIG. 1) may sample the voltage charged in the reference line RL and convert it into sensing data of each subpixel SP and provide it to the timing controller 400 (FIG. 1).

FIG. 4 is a plan view schematically showing a planar configuration of four subpixels according to an embodiment of the present invention. FIG. 5 is a cross-sectional view of a driving TFT DT and an opening region 10R of the R subpixel shown in FIG. Sectional view of the opening region 10W of the sub-pixel cut along the line I-I '.

4 and 5, each of the R, W, B, and G subpixels disposed between the two power supply lines PL includes an opening region 10R, 10W, 10B (overlapping with the light emitting region of the OLED element 300) And a non-aperture region 20 in which signal lines that do not overlap with the pixel regions 30 and the aperture regions 10R, 10W, 10B, and 10G are connected to the OLED elements 300. [

The pixel circuit 30 of each of the R, W, B and G subpixels includes a power line PL, a first electrode of each OLED element 300, a driving TFT DT and data lines DL1, DL2, DL3, A first switching TFT ST1 connected between each of the source lines DL1 and DL4 and the gate electrode of the driving TFT DT and connected to the first gate line GLn1 and a second switching TFT ST2 connected between the reference line RL1 and the source electrode of the driving TFT DT A second switching TFT ST2 connected to the second gate line GLn2 and a first storage electrode connected to the gate electrode of the driving DT DT and a second storage electrode connected to the source electrode overlap And a formed storage capacitor Cst.

The driving TFT DT of the R and W subpixels is commonly connected to the left power supply line PL and the first switching TFT ST1 of each of the R and W subpixels is connected between the pixel circuits 30 of the R and W subpixels And is separately connected to the main portion 40 of the arranged first and second data lines DL1 and DL2. The driving TFT DT of the B and G subpixels is commonly connected to the right power supply line PL and the first switching TFT ST1 of each of the B and G subpixels is connected between the pixel circuits 30 of the B and G subpixels And is separately connected to the main portion 40 of the arranged third and fourth data lines DL3 and DL4. The second switching TFT ST2 of the R, W, R and G subpixels is commonly connected to the reference line RL1 disposed between the W and B subpixels.

A plurality of fine patterns 50 overlapped with the respective opening regions 10R, 10W, 10B and 10G of the R, W, R and G sub-pixels in the data lines DL1, DL2, DL3 and DL4, Are connected in parallel in the non-aperture region (20) of the subpixel. Each of the plurality of fine patterns 50 has a line width of 3 mu m or less which is hard to recognize, so that the transmittance reduction in the aperture regions 10R, 10W, 10B, and 10G due to the plurality of fine patterns 50 can be minimized. When the plurality of fine patterns 50 are formed as transparent electrodes, the reduction of transmittance by the fine patterns 50 can be improved.

There is no data line in the interval between the aperture regions 10R and 10W of the R and W subpixels and the interval between the aperture regions 10B and 10G of the B and G subpixels so that the width of the non- The aperture ratio of each sub-pixel can be increased by increasing the width of the aperture regions 10R, 10W, 10B, and 10G.

The opening regions 10R, 10W, 10B, and 10G of the R, W, R, and G subpixels have the same length in the second direction, 10G may have different areas. The widths of the aperture regions 10R, 10W, 10B and 10G of the R, W, R and G subpixels can be made smaller in the order of W> B> R> G subpixels.

4 and 5, a buffer layer 130 is disposed on a first substrate 110 and first and second switching TFTs ST1 and ST2, a driving TFT DT, A pixel circuit 30 including a capacitor Cst is located.

The driving TFT DT includes a semiconductor pattern 210, a gate insulating film 220, a gate electrode 230, an interlayer insulating film 240, a source electrode 250 and a drain electrode 260. Each of the first and second switching TFTs ST1 and ST2 may have the same vertical cross-sectional structure as the driving TFT DT.

A structure in which an organic insulating layer and an inorganic insulating layer are alternately stacked to block external moisture or gas to be introduced from the outside, a structure in which a silicon oxide (SiOx), a silicon nitride (SiNx), aluminum oxide (AlOx), or the like may be further disposed.

A light shielding metal layer may be further interposed between the first substrate 100 and the buffer layer 130 to block light from entering the semiconductor pattern 210 of the driving TFT DT.

The semiconductor pattern 210 is positioned between the lower substrate 110 and the buffer layer 130. The semiconductor pattern 210 may comprise a semiconductor material such as amorphous silicon or polycrystalline silicon. The semiconductor pattern 120 may include an oxide semiconductor including at least one of In, Ga, Zn, Al, Sn, Zr, Hf, Cd, Ni and Cu. The source region and the drain region of the semiconductor pattern 210 may be exposed by plasma, ultraviolet (UV), or etchant to remove some of the oxygen and be made conductive.

A gate insulating film 220 is formed on the semiconductor pattern 210 and a gate electrode 230 and a gate line GL are formed on the gate insulating film 220. The gate insulating film 220 may include silicon oxide and / or silicon nitride.

The gate electrode 230 overlaps the channel region of the semiconductor pattern 210 with the gate insulating film 220 interposed therebetween. The gate electrode 230 may include at least one metal material such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W)

The interlayer insulating layer 240 is formed in a structure covering the semiconductor pattern 210 and the gate electrode 230 and includes contact holes exposing the source region of the semiconductor pattern 210 and contact holes exposing the drain region. The interlayer insulating film 240 may include silicon oxide or silicon nitride.

A source / drain metal pattern including a source electrode 260 and a drain electrode 250, a data line DL, a reference line RL, and a power source line PL is formed on the interlayer insulating layer 240. The source electrode 260 and the drain electrode 250 are connected to the source region and the drain region of the semiconductor pattern 210 through the contact holes of the interlayer insulating film 240, respectively. A plurality of fine patterns 50 in the data line DL are positioned to overlap with the opening regions 10R, 10W, 10B, and 10G. The source / drain metal pattern may include at least one metal such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W) The source / drain metal pattern may further include a transparent conductive layer, and a plurality of fine patterns 50 among the data lines DL overlapping the opening regions 10R, 10W, 10B, and 10G may be a transparent conductive layer Can be formed.

A lower protective film 140 is formed to cover the pixel circuit 30 including the driving TFT DT and an overcoat layer 150 is formed on the lower protective film 140 to remove the step of the pixel circuit 30 and provide a flat surface. . The lower protective film 140 includes silicon oxide and / or silicon nitride, and may have a multilayer structure. The overcoat layer 150 may comprise an organic insulating material.

B, and G color filters CF overlapping the opening regions 10R, 10B, and 10G of the R, B, and G subpixels are positioned between the lower protective film 140 and the overcoat layer 150, There is no color filter. The R, B and G color filters CF overlap with the plurality of fine patterns 50 of the data lines DL overlapping the opening regions 10R, 10B and 10G of the R, B and G subpixels .

On the overcoat layer 150, the first electrode 310 of the OLED element 300, which is independently positioned for each sub-pixel, is formed. The first electrode 62 may be an anode electrode connected to the source electrode 260 of the driving TFT DT via the contact holes 150h and 140h passing through the overcoat layer 150 and the lower protective film 140 . The first electrode 310 may be formed of a transparent conductive material. The first electrode 62 may be a transparent electrode including ITO and IZO.

A bank insulating layer 160 is formed on the overcoat layer 150 where the first electrode 310 is formed to define the opening regions 10R, 10W, 10B and 10G of the respective subpixels. The bank insulating film 160 may include an organic insulating material. The bank insulating layer 160 may include an overcoat layer 150 and other materials.

 A light emitting stack 320 and a second electrode 330 are stacked on the bank insulating layer 160 and the first electrode 310. The light emitting stack 320 of the R, W, B and G subpixels may be connected to each other and the second electrodes 330 of the R, W, B and G subpixels may be connected to each other.

The light emitting stack 320 includes a light emitting material layer (EML) including a light emitting material. The light emitting stack 320 may include a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer ; EIL). ≪ / RTI >

The red, green and blue subpixels of the red, green, blue and green subpixels emit white light and the red, green and blue subpixels respectively emit red, green and blue subpixels overlapping the aperture regions 10R, 10B and 10G. And emit R, B, and G light through each of the CFs.

The second electrode 330 is a cathode electrode and is formed of a metal having a high reflectivity. The OLED element 300 has a bottom emission structure in which light generated by the emission stack 320 is emitted through the lower substrate 110 via the first electrode 310, the color filter CF, and the like.

An upper protective layer 170 may be formed on the OLED element 300 to prevent damage to the OLED element 300 due to external impact and moisture. The upper protective film 170 may have a multilayer structure including an insulating material. For example, the upper protective film 170 may be a structure in which an organic film containing an organic material is located between inorganic films containing an inorganic material.

An encapsulating layer 180 may be disposed on the upper protective layer 170 and a second substrate 120 may be further disposed on the encapsulation layer 180. The second substrate 120 may be bonded to the lower substrate 110 on which the OLED elements 300 are formed by the sealing layer 180 including an adhesive material. The sealing layer 180 may be a multi-layer structure. For example, the encapsulation layer 180 may include a first encapsulation layer 181 and a second encapsulation layer 182. The sealing layer 180 can prevent the penetration of moisture. For example, the second sealing layer 182 may include a moisture absorbing material 182p. The moisture permeating from the outside can be collected by the moisture absorbent 182p. The first sealing layer 181 can relieve stress caused by expansion of the moisture absorbing material 182p. The second substrate 120 may include a metal such as aluminum (Al), iron (Fe), and nickel (Ni).

As described above, the OLED display device according to an embodiment differs from the OLED display device according to an embodiment in that a part of each data line is overlapped with the opening regions 10R, 10W, 10B, and 10G of the R, W, 50), it is possible to maintain the electrical characteristics of the data lines at an equal level, and to maintain the electrical characteristics of the data lines between the aperture regions 10R, 10W of the R, W subpixels and the aperture regions 10B, The widths of the opening regions 10R, 10W, 10B, and 10G can be increased because there is no data line between the pixel electrodes 10G, 10G.

Accordingly, the OLED display device according to the embodiment can reduce the non-aperture area by the data line and increase the aperture areas 10R, 10W, 10B, and 10G of each sub-pixel as the non-aperture area is reduced The aperture ratio of each subpixel can be increased.

In addition, when a plurality of fine patterns 50 overlapping the opening regions 10R, 10W, 10B, and 10G of the respective subpixels are formed as transparent electrodes, reduction in transmittance due to the fine patterns can be prevented.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10R, 10W, 10B, 10G: aperture region 20: non-aperture region
30: pixel circuit 40: data line main part
20: data line fine patterns 300: OLED element (light emitting element)

Claims (9)

A plurality of sub-pixels disposed in the panel,
Each of the plurality of subpixels includes an aperture region overlapping with a light emitting region of each light emitting element, a non-aperture region in which a pixel circuit and a plurality of signal wires that do not overlap with the aperture region are located,
Wherein each data line of the plurality of signal lines includes a main portion and a plurality of fine patterns overlapping the opening region of each light emitting element,
A plurality of fine patterns overlapping the opening regions of the light emitting devices are connected in parallel in the non-opening region to be connected to the main portion,
Wherein each of the plurality of fine patterns has a line width smaller than that of the main portion and has a line width within a specific range not recognized. The method according to claim 1,
Wherein the plurality of subpixels include first through fourth subpixels arranged side by side in a first direction and emitting light of different colors,
The signal wirings located in the non-
A plurality of gate lines extended in the first direction and connected in common to the pixel circuits of the first through fourth sub-pixels,
A first reference line extending in a second direction orthogonal to the first direction between the second and third subpixels and commonly connected to the pixel circuits of the first through fourth subpixels,
Pixels extending outside the first subpixel in the second direction and connected to the pixel circuits of the first and second subpixels and extending in the second direction outside the fourth subpixel, A plurality of power supply lines connected to the fourth subpixel,
A main portion of each of the first and second data lines extending in the second direction between pixel circuits of the first and second subpixels,
And a main portion of each of the third and fourth data lines extending in the second direction between the pixel circuits of the third and fourth sub-pixels. The method of claim 2,
Wherein an opening region of each subpixel is defined by a bank insulating film located in the non-opening region,
Wherein the bank insulating film is positioned between the opening regions of the first and second subpixels and between the opening regions of the third and fourth subpixels in the absence of the data line. The method of claim 2,
Wherein the first through fourth aperture regions of the first through fourth subpixels have the same length in the second direction, and the widths of the first direction and the second direction are different from each other. The method of claim 4,
The first through fourth subpixels correspond to red, white, blue, and green subpixels, respectively,
The second aperture region of the white subpixel or the third aperture region of the blue subpixel is wider than the first aperture region of the red subpixel and the fourth aperture region of the green subpixel. The method of claim 5,
Wherein the widths of the first to fourth aperture regions of the red, white, blue, and green subpixels are the same as the widths of the first aperture region of the white subpixel, the third aperture region of the blue subpixel, And a fourth aperture region of the green subpixel. The method of claim 5,
The first aperture region of the red subpixel overlaps with the red color filter,
The third aperture region of the blue subpixel overlaps the blue color filter,
The fourth aperture region of the green subpixel overlaps with the green color filter,
Wherein the plurality of fine patterns respectively located in the first, third, and fourth opening regions overlap with the respective red, blue, and green color filters with at least one insulating film interposed therebetween. The method of claim 4,
Wherein the intervals between the plurality of fine patterns located in the respective opening regions of the first to fourth sub-pixels are equal to each other. The method of claim 4,
And the transparent electrodes are applied to the plurality of fine patterns located in the respective opening regions of the first to fourth sub-pixels.

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