KR102346544B1 - Thin Film Transistor Substrate And Display Using The Same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate in which different types of thin film transistors are disposed on the same substrate and a display device using the same. A display device according to the present invention includes a first thin film transistor, a second thin film transistor, a first intermediate insulating film, a second intermediate insulating film, and a third intermediate insulating film. The first thin film transistor includes a polycrystalline semiconductor layer, a first gate electrode disposed on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, and is disposed in a first region. The second thin film transistor includes an oxide semiconductor layer, a second gate electrode disposed on the oxide semiconductor layer, a second source electrode, and a second drain electrode, and is disposed in a second region. The first intermediate insulating film covers the first gate electrode, is disposed under the oxide semiconductor layer, and includes an oxide film. The second intermediate insulating film is selectively disposed on the first intermediate insulating film in a first region except for the second region, and includes a nitride film. The third intermediate insulating film covers the first and second gate electrodes on the second intermediate insulating film, and includes an oxide film.

Description

Thin Film Transistor Substrate And Display Using The Same

The present invention relates to a thin film transistor substrate in which different types of thin film transistors are disposed on the same substrate and a display device using the same.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. The display device field has rapidly changed to a thin, light, and large-area Flat Panel Display Device (FPD) that replaces a bulky cathode ray tube (CRT). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED), etc.

In the case of a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device that are actively driven, a thin film transistor substrate is included in which thin film transistors allocated in pixel regions arranged in a matrix manner are disposed. A liquid crystal display device (LCD) displays an image by adjusting the light transmittance of liquid crystal using an electric field. An organic light emitting display device displays an image by forming an organic light emitting element in pixels arranged in a matrix manner.

The organic light emitting diode display is a self-luminous device that emits light by itself, and has advantages in that the response speed is fast and the luminous efficiency, luminance, and viewing angle are large. In particular, in an organic light emitting diode display (OLED) using the characteristics of an organic light emitting diode having excellent energy efficiency, a passive matrix type organic light emitting diode display (PMOLED) and It is roughly classified into an active matrix type organic light emitting diode display (AMOLED).

As personal electronic devices are actively developed, display devices are also being developed as products with excellent portability and/or wearability. As such, in order to be applied to a portable or wearable device, a display device with low power consumption is required. There is a limit in realizing low power consumption with the technologies related to display devices developed so far.

An object of the present invention is to provide a thin film transistor substrate having two or more types of thin film transistors on the same substrate and a display device using the same, as the invention was devised to solve the problems of the prior art. Another object of the present invention is to provide a thin film transistor substrate in which two or more types of thin film transistors are formed through an optimized manufacturing process and a minimized mask process, and a display device using the same.

In order to achieve the above object, a display device according to the present invention includes a first thin film transistor, a second thin film transistor, a first intermediate insulating film, a second intermediate insulating film, and a third intermediate insulating film. The first thin film transistor includes a polycrystalline semiconductor layer, a first gate electrode disposed on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, and is disposed in a first region. The second thin film transistor includes an oxide semiconductor layer, a second gate electrode disposed on the oxide semiconductor layer, a second source electrode, and a second drain electrode, and is disposed in a second region. The first intermediate insulating film covers the first gate electrode, is disposed under the oxide semiconductor layer, and includes an oxide film. The second intermediate insulating film is selectively disposed on the first intermediate insulating film in a first region except for the second region, and includes a nitride film. The third intermediate insulating film covers the first and second gate electrodes on the second intermediate insulating film, and includes an oxide film.

For example, the display device further includes a first gate insulating layer and a second gate insulating layer. The first gate insulating film covers the polycrystalline semiconductor layer. The second gate insulating film is interposed between the oxide semiconductor layer and the first gate electrode.

For example, the first source electrode is disposed on the third intermediate insulating film, and through a first source contact hole penetrating the third intermediate insulating film, the second intermediate insulating film, the first intermediate insulating film, and the first gate insulating film. connected to one side. The first drain electrode is disposed on the third intermediate insulating film, and through a first drain contact hole penetrating the third intermediate insulating film, the second intermediate insulating film, the first intermediate insulating film, and the first gate insulating film, the other side of the polycrystalline semiconductor layer and connected The second source electrode is disposed on the third intermediate insulating layer and is connected to one side of the oxide semiconductor layer through a second source contact hole penetrating the third intermediate insulating layer. The second drain electrode is disposed on the third intermediate insulating layer and is connected to the other side of the oxide semiconductor layer through a second drain contact hole penetrating the third intermediate insulating layer.

For example, the first source electrode is disposed on the third intermediate insulating film, and includes an upper source contact hole penetrating the third intermediate insulating film, and one side of the second intermediate insulating film, the first intermediate insulating film, the first gate insulating film, and the polycrystalline semiconductor layer. It is connected to the etched side of the one side through the lower source contact hole passing through it. The first drain electrode is disposed on the third intermediate insulating film, the upper drain contact hole passes through the third intermediate insulating film, and the second intermediate insulating film, the first intermediate insulating film, the first gate insulating film, and the polycrystalline semiconductor layer passing through the other side. It is connected to the etched side of the other side through the lower drain contact hole. The second source electrode is disposed on the third intermediate insulating layer and is connected to the etched side of the one side through a second source contact hole passing through the third intermediate insulating layer and one side of the oxide semiconductor layer. The second drain electrode is disposed on the third intermediate insulating layer and is connected to the etched side of the other side through a second drain contact hole penetrating the other side of the third intermediate insulating layer and the oxide semiconductor layer.

For example, the size of the upper source contact hole is larger than that of the lower source contact hole to include the lower source contact hole. The size of the upper drain contact hole is larger than that of the lower drain contact hole to include the lower drain contact hole.

For example, the second thin film transistor is a switching element for selecting a pixel. The first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor.

For example, the display device further includes a driving circuit. At least one of the first thin film transistor and the second thin film transistor is included in the pixel. At least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.

For example, the driving circuit includes a data driver, a multiplexer, and a gate driver. The data driver outputs a data voltage. The multiplexer distributes the data voltage from the data driver to the data lines. The gate driver outputs a scan pulse to the gate wiring. At least one of the first thin film transistor and the second thin film transistor is included in any one of the multiplexer and the gate driver.

In addition, the display device according to the present invention includes a first semiconductor layer, a first gate insulating film, a first gate electrode, a first intermediate insulating film, a second semiconductor layer, a second intermediate insulating film, a second gate electrode, a third intermediate insulating film, It includes a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode. A first semiconductor layer, comprising polycrystalline semiconductor material, is disposed in the first region. The first gate insulating film covers the first semiconductor layer. The first gate electrode overlaps the first semiconductor layer on the first gate insulating film. The first intermediate insulating film covers the first gate electrode and includes an oxide film. A second semiconductor layer, comprising an oxide semiconductor material, is disposed in the second region over the first intermediate insulating film. The second intermediate insulating film is disposed in the first region except for the second region on the first intermediate insulating film, and includes a nitride film. The second gate electrode overlaps the second gate insulating film on the second semiconductor layer. The third intermediate insulating film covers the second intermediate insulating film and the second gate electrode, and includes an oxide film. The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the third intermediate insulating film.

For example, the first source electrode is connected to one side of the first semiconductor layer through a first source contact hole penetrating the third intermediate insulating layer, the second intermediate insulating layer, the first intermediate insulating layer, and the first gate insulating layer. The first drain electrode is connected to the other side of the first semiconductor layer through a first drain contact hole penetrating the third intermediate insulating film, the second intermediate insulating film, the first intermediate insulating film, and the first gate insulating film. The second source electrode is connected to one side of the second semiconductor layer through a second source contact hole penetrating the third intermediate insulating layer. The second drain electrode is connected to the other side of the second semiconductor layer through a second drain contact hole penetrating the third intermediate insulating layer.

For example, the first source electrode may include an upper source contact hole penetrating the third intermediate insulating film, and a lower source contact hole penetrating one side of the second intermediate insulating film, the first intermediate insulating film, the first gate insulating film, and the first semiconductor layer. It is connected to the etched side of one side through the The first drain electrode is connected through an upper drain contact hole penetrating the third intermediate insulating film, and a lower drain contact hole penetrating the second intermediate insulating film, the first intermediate insulating film, the first gate insulating film, and the other side of the first semiconductor layer. It is connected to the etched side of the side. The second source electrode is connected to the etched side of the third intermediate insulating layer and the second semiconductor layer through a second source contact hole passing through one side portion. The second drain electrode is connected to the etched side of the other side through a second drain contact hole penetrating the other side of the third intermediate insulating layer and the second semiconductor layer.

For example, the size of the upper source contact hole is larger than that of the lower source contact hole to include the lower source contact hole. The size of the upper drain contact hole is larger than that of the lower drain contact hole to include the lower drain contact hole.

For example, the first semiconductor layer, the first gate electrode, the first source electrode, and the first drain electrode are included in the first thin film transistor. The second semiconductor layer, the second gate electrode, the second source electrode, and the second drain electrode are included in the second thin film transistor.

For example, the second thin film transistor is a switching element for selecting a pixel. The first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor.

For example, the display device further includes a driving circuit. At least one of the first thin film transistor and the second thin film transistor is included in the pixel. At least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.

For example, the driving circuit includes a data driver, a multiplexer, and a gate driver. The data driver outputs a data voltage. The multiplexer distributes the data voltage from the data driver to the data lines. The gate driver outputs a scan pulse to the gate wiring. At least one of the first thin film transistor and the second thin film transistor is included in any one of the multiplexer and the gate driver.

The thin film transistor substrate and the display device using the same according to the present invention may have a feature that the other thin film transistors compensate for the disadvantages of one thin film transistor by forming two different types of thin film transistors on the same substrate. In particular, it is possible to provide a display device suitable for portable and/or wearable devices by reducing power consumption by providing a thin film transistor having low-speed driving characteristics.

1 is a cross-sectional view showing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention;
2 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to the first embodiment of the present invention.
3 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.
4 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.
5 is a block diagram schematically showing the configuration of a display device according to a first application example of the present invention.
6 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display, which is a type of horizontal electric field type, according to a second application example of the present invention.
FIG. 7 is a cross-sectional view of the thin film transistor substrate shown in FIG. 6 taken along line II';
8 is a plan view showing the structure of one pixel in an active matrix organic light emitting diode display according to a third application example of the present invention.
9 is a cross-sectional view showing the structure of the active matrix organic light emitting diode display device taken along the cut line II-II' in FIG. 8;
10 is an enlarged plan view showing a schematic structure of an organic light emitting diode display device according to a fourth application example of the present invention.
11 is a cross-sectional view showing the structure of an organic light emitting diode display according to a fourth application example of the present invention, taken along the cut line III-III' in FIG. 10;

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of writing the specification, and may be different from the component names of the actual product.

A thin film transistor substrate for a flat panel display according to the present invention includes a first thin film transistor disposed in a first region and a second thin film transistor disposed in a second region on a glass substrate. The substrate may include a display area and a non-display area. In the display area, a plurality of pixel areas are arranged in a matrix manner. Display elements for a display function are disposed in the pixel area. The non-display area is disposed around the display area, and driving elements for driving the display elements formed in the pixel area may be disposed.

Here, the first area may be a part of the non-display area, and the second area may be a part of the display area. In this case, the first thin film transistor and the second thin film transistor may be disposed far apart. Alternatively, both the first area and the second area may be included in the display area. In particular, when a plurality of thin film transistors are included in a single pixel area, the first thin film transistor and the second thin film transistor may be disposed adjacent to each other.

Polycrystalline semiconductor material has high mobility (100 cm2/Vs or more), low energy consumption, and excellent reliability, so it can be applied to a gate driver and/or a multiplexer (MUX) for driving devices that drive thin film transistors for display devices. have. Alternatively, it is preferable to apply it as a driving thin film transistor in a pixel in an organic light emitting diode display device. Since the oxide semiconductor material has a low off-current, it is suitable for a switching thin film transistor having a short on-time and a long off-time. In addition, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low-speed driving and/or low power consumption. As described above, by simultaneously disposing two different types of thin film transistors on the same substrate, a thin film transistor substrate exhibiting an optimal effect can be obtained.

When the semiconductor layer is formed of a polycrystalline semiconductor material, an impurity implantation process and a high-temperature heat treatment process are required. On the other hand, when the semiconductor layer is formed of an oxide semiconductor material, the process is performed at a relatively low temperature. Therefore, it is preferable to first form the polycrystalline semiconductor layer, which is subjected to the process under severe conditions, and then form the oxide semiconductor layer later.

In addition, in the manufacturing process, since the properties of the polycrystalline semiconductor material are deteriorated when voids exist, a process of filling the voids with hydrogen through a hydrogenation process is required. On the other hand, in the oxide semiconductor material, since the pores without covalent bonding can serve as carriers, a process for stabilizing the pores while retaining the pores to some extent is required. These two processes may be performed through a subsequent heat treatment process under 350°C to 380°C.

In order to perform the hydrogenation process, a nitride film including a large amount of hydrogen particles is interposed on the polycrystalline semiconductor material. Since the nitride film contains a large amount of hydrogen in a material used in manufacturing, a significant amount of hydrogen is also included in the layered nitride film itself. In a heat treatment process, hydrogen diffuses into the polycrystalline semiconductor material. As a result, the polycrystalline semiconductor layer can achieve stabilization. During the heat treatment process, hydrogens should not diffuse into the oxide semiconductor material in excessive amounts. Therefore, it is preferable to interpose an oxide film between the nitride film and the oxide semiconductor material. After performing the heat treatment process, the oxide semiconductor material may remain unaffected by hydrogen to achieve device stabilization.

In the following description, for convenience, the first thin film transistor is a thin film transistor for a driving element formed in the non-display area, and the second thin film transistor is a thin film transistor for a display element disposed in a pixel area of the display area. However, the present invention is not limited thereto, and in the case of an organic light emitting diode display, both the first thin film transistor and the second thin film transistor may be disposed in the pixel area of the display area. In particular, the first thin film transistor including the polycrystalline semiconductor material may be applied to the driving thin film transistor, and the second thin film transistor including the oxide semiconductor material may be applied to the switching thin film transistor.

<First embodiment>

A first embodiment of the present invention will be described with reference to FIG. 1 . 1 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention. Here, the present invention will be mainly described with a cross-sectional view that can clearly show the characteristics of the invention, and for convenience, a plan view structure is not shown in drawings.

Referring to FIG. 1 , a thin film transistor substrate for a flat panel display according to a first embodiment of the present invention includes a first thin film transistor T1 and a second thin film transistor T2 disposed on a substrate SUB. The first and second thin film transistors T1 and T2 may be disposed to be spaced apart or disposed adjacent to each other. Alternatively, two thin film transistors may be overlapped.

A buffer layer BUF is stacked on the entire surface of the substrate SUB. In some cases, the buffer layer BUF may be omitted. Alternatively, the buffer layer BUF may have a structure in which a plurality of thin film layers are stacked. Here, for convenience, it is described as a single layer. In addition, a light blocking layer may be selectively further provided only in a necessary portion between the buffer layer BUF and the substrate SUB. The light blocking layer may be formed for the purpose of preventing external light from being introduced into the semiconductor layer of the thin film transistor disposed thereon.

A first semiconductor layer A1 is disposed on the buffer layer BUF. The first semiconductor layer A1 includes a channel region of the first thin film transistor T1 . The channel region is defined as a region where the first gate electrode G1 and the first semiconductor layer A1 overlap. Since the first gate electrode G1 overlaps the central portion of the first thin film transistor T1 , the central portion of the first thin film transistor T1 becomes the channel region. Both sides of the channel region are regions doped with impurities, and are defined as a first source region SA1 and a first drain region DA1.

When the first thin film transistor T1 is a thin film transistor for a driving element, it is preferable to have characteristics suitable for performing high-speed driving processing. For example, a P-MOS or N-MOS type thin film transistor may be used, or a C-MOS type thin film transistor including both may be provided. The thin film transistors of the P-MOS, N-MOS and/or C-MOS type preferably include a polycrystalline semiconductor material such as poly-silicon. In addition, the first thin film transistor T1 preferably has a top-gate structure.

A first gate insulating layer GI1 is stacked on the entire surface of the substrate SUB on which the first semiconductor layer A1 is disposed. The first gate insulating layer GI1 may be formed of silicon nitride (SiNx) or silicon oxide (SiOx). In the case of the first gate insulating layer GI1, it is preferable to have a thickness of about 1,000 Å to 1,500 Å in consideration of device stability and characteristics. When the first gate insulating layer GI1 is formed of silicon nitride (SiNx), a large amount of hydrogen may be included in the first gate insulating layer GI1 due to a manufacturing process. These hydrogens may diffuse to the outside of the first gate insulating layer GI1 in a subsequent process, so that the first gate insulating layer GI1 is preferably formed of a silicon oxide material.

In the first semiconductor layer A1 including the polycrystalline silicon material, hydrogen diffusion may have a positive effect. However, a negative effect may be given to the second thin film transistor T2 having properties different from those of the first thin film transistor T1 . Therefore, when thin film transistors using different materials are formed on the same substrate as in the present invention, it is more preferable to use silicon oxide (SiOx), which does not have a special effect on the device. In some cases, unlike the case described in the first embodiment, the gate insulating layer GI may be formed as thick as 2,000 Å to 4,000 Å. In this case, when the first gate insulating layer GI1 is formed of silicon nitride (SiNx), the degree of hydrogen diffusion may be severe. Accordingly, in consideration of various cases, the first gate insulating layer GI1 is preferably formed of silicon oxide (SiOx).

A first gate electrode G1 is disposed on the first gate insulating layer GI1 . The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer A1 . A first intermediate insulating layer ILD1 is stacked to cover the first gate electrode G1 . The first intermediate insulating layer ILD1 is stacked on the first gate electrode G1 to cover the entire surface of the substrate SUB. In addition, the first intermediate insulating film ILD1 is preferably formed of an oxide film SIO including silicon oxide (SiOx).

A second intermediate insulating layer ILD2 is formed on the first intermediate insulating layer ILD2 . In particular, it is preferable that the second intermediate insulating layer ILD2 is selectively disposed only in the first region in which the first thin film transistor T1 is disposed. More specifically, the second intermediate insulating layer ILD2 is preferably patterned to have a shape covering the upper portion of the first gate electrode G1 . In particular, the second intermediate insulating layer ILD2 is for hydrogenation of the first semiconductor layer A1 including polysilicon by diffusing hydrogen contained therein through a subsequent heat treatment process, and includes silicon nitride (SiNx). It is preferable to include a nitride film (SIN) containing

In the second region where the second intermediate insulating layer ILD2 is not disposed, the second thin film transistor T2 is disposed. That is, in the second region, the second semiconductor layer A2 is formed on the first intermediate insulating layer ILD1 . The second semiconductor layer A2 includes a channel region of the second thin film transistor T2 . When the second thin film transistor T2 is a thin film transistor for a display element, it is preferable to have characteristics suitable for performing display function processing. Examples include oxide semiconductor materials such as Indium Gallium Zinc Oxide (IGZO), Indium Gallium Oxide (IGO), and Indium Zinc Oxide (IZO). it is preferable The oxide semiconductor material has a low off-current characteristic, and thus a voltage holding period of a pixel is long, so it is suitable for a display device requiring low-speed driving and low power consumption. In addition, in the present invention, in order to achieve high resolution and low power consumption at the same time, the second thin film transistor T2 also has the same top-gate structure as the first thin film transistor T1 .

Accordingly, the second gate insulating layer GI2 and the second gate electrode G2 are overlapped on the central portion of the second semiconductor layer A2 . A central portion of the second semiconductor layer A2 overlapping the second gate electrode G2 with the second gate insulating layer GI2 interposed therebetween is defined as a channel region. In addition, both sides of the channel region are defined as a second source region SA2 and a second drain region DA2, respectively. Here, since the second gate insulating layer GI2 is in direct contact with the second semiconductor layer A2 including an oxide semiconductor material, it is preferable to include an oxide insulating material such as silicon oxide (SiOx), which hardly generates hydrogen.

A third intermediate insulating layer ILD3 is stacked on the entire surface of the substrate SUB on which the second gate electrode G2 is formed. The third intermediate insulating layer ILD3 also has a stacked structure on the second semiconductor layer A2 including an oxide semiconductor material. Accordingly, it is preferable that the third intermediate insulating layer ILD3 also include an oxide insulating material such as silicon oxide (SiOx), which hardly generates hydrogen.

The second intermediate insulating layer ILD2 is for performing hydrogenation of the first semiconductor layer A1 including polysilicon by diffusing hydrogen contained therein through a subsequent heat treatment process. On the other hand, the first intermediate insulating layer ILD1 prevents hydrogen emitted from the second intermediate insulating layer ILD2, which is the nitride layer SIN, from diffusing too much into the semiconductor material of the second thin film transistor T2 by a subsequent heat treatment process. it is to do

For example, it is preferable that hydrogen emitted from the second intermediate insulating layer ILD2 serving as the nitride layer SIN diffuses into the first semiconductor layer A1 disposed therebelow with the gate insulating layer GI interposed therebetween. Accordingly, the second intermediate insulating layer ILD2 is preferably stacked on the gate insulating layer GI to be close to the first semiconductor layer A1 . On the other hand, it is desirable to prevent excessive diffusion of hydrogen emitted from the second intermediate insulating layer ILD2 that is the nitride layer SIN into the semiconductor material of the second thin film transistor T2 formed thereon. Accordingly, the second intermediate insulating layer ILD2 serving as the nitride layer SIN is selectively disposed in the first region in which the first thin film transistor T1 is disposed, except for the second region in which the second thin film transistor T2 is disposed. It is preferable to be

In consideration of the manufacturing process, the total thickness of the first intermediate insulating layer ILD1 to the third intermediate insulating layer ILD3 may be 3,000 Å to 6,000 Å. Accordingly, the thickness of each of the first intermediate insulating layer ILD1 , the second intermediate insulating layer ILD2 , and the third intermediate insulating layer ILD3 is preferably 1,000 Å to 2,000 Å. In addition, in order for hydrogen in the second intermediate insulating film ILD2, which is the nitride film SIN, to diffuse as much as possible to the first semiconductor layer A1, while affecting the second semiconductor layer A2 as little as possible, the oxide film SIO ) of the first intermediate insulating film ILD1 and the third intermediate insulating film ILD3 are preferably thicker than the second intermediate insulating film ILD2 of the nitride film SIN.

Source-drain electrodes are disposed on the third intermediate insulating layer ILD3 . The first source electrode S1 and the first drain electrode D1 are spaced apart from each other by a predetermined distance with respect to the first gate electrode G1 to face each other. The first source electrode S1 is connected to the first source area SA1, which is one side of the first semiconductor layer A1 exposed through the first source contact hole SH1. The first source contact hole SH1 passes through the third intermediate insulating layer ILD3 , the second intermediate insulating layer ILD2 , the first intermediate insulating layer ILD1 , and the first gate insulating layer GI1 to form the first semiconductor layer A1 . The first source area SA1, which is one side of the , is exposed. The first drain electrode D1 is connected to the first drain area DA1 which is the other side of the first semiconductor layer A1 exposed through the first drain contact hole DH1. The first drain contact hole DH1 passes through the third intermediate insulating layer ILD3 , the second intermediate insulating layer ILD2 , the first intermediate insulating layer ILD1 , and the first gate insulating layer GI1 to form the first semiconductor layer A1 . The first drain area DA1, which is the other side of the , is exposed.

The second source electrode S2 and the second drain electrode D2 are spaced apart from each other by a predetermined distance with respect to the second gate electrode G2 to face each other. The second source electrode S2 is connected to the second source area SA2 , which is one side of the second semiconductor layer A2 exposed through the second source contact hole SH2 . The second source contact hole SH2 penetrates the third intermediate insulating layer ILD3 to expose the second source area SA2 that is one side of the second semiconductor layer A2 . The second drain electrode D2 is connected to the second drain area DA2 which is the other side of the second semiconductor layer A2 exposed through the second drain contact hole DH2. The second drain contact hole DH2 passes through the third intermediate insulating layer ILD3 to expose the second drain region DA2 that is the other side of the second semiconductor layer A2 .

A passivation layer PAS covers the first thin film transistor T1 and the second thin film transistor T2 . Thereafter, a contact hole exposing the first drain electrode D1 and/or the second drain electrode D2 may be further formed by patterning the passivation layer PAS. In addition, a pixel electrode contacting the first drain electrode D1 and/or the second drain electrode D2 through a contact hole may be further included on the passivation layer PAS. Here, for convenience, only parts showing the structure of the thin film transistors representing the main features of the present invention are shown and described.

As described above, in the thin film transistor substrate for a flat panel display according to the first embodiment of the present invention, the first thin film transistor T1 including the polycrystalline semiconductor material and the second thin film transistor T2 including the oxide semiconductor material are the same It has a structure formed on the substrate SUB.

The first semiconductor layer A1 including the polycrystalline semiconductor material of the first thin film transistor T1 is disposed under the first gate electrode G1 , and the second semiconductor layer A1 including the oxide semiconductor material of the second thin film transistor T2 is The semiconductor layer A2 is disposed on the first gate electrode G1 . Accordingly, by first forming the first semiconductor layer A1 formed at a relatively high temperature and then forming the second semiconductor layer A2 formed at a relatively low temperature later, the oxide semiconductor material is exposed to a high temperature state during the manufacturing process It has a structure that can avoid the situation.

In addition, during the heat treatment of the second semiconductor layer A2 including the oxide semiconductor material, the hydrogen treatment process may be simultaneously performed on the first semiconductor layer A1 including the polycrystalline semiconductor material. To this end, the second intermediate insulating layer ILD2 serving as the nitride layer SIN is selectively formed in the first region in which the first thin film transistor T1 is disposed except for the second region in which the second thin film transistor T2 is disposed. do.

A hydrogenation process of diffusing hydrogen contained in the second intermediate insulating layer ILD2 , which is a nitride layer SIN, into the first semiconductor layer A1 through a heat treatment process is required due to a manufacturing process characteristic. In addition, a heat treatment process for stabilizing the second semiconductor layer A2 including the oxide semiconductor material is also required. The hydrogenation process may be performed after laminating the second intermediate insulating layer ILD2 on the first semiconductor layer A1 , and the heat treatment process may be performed after forming the second semiconductor layer A2 .

According to the first embodiment of the present invention, since the second intermediate insulating layer ILD2 serving as the nitride layer SIN is selectively stacked on the first semiconductor layer A1 portion, hydrogen is the second semiconductor layer including the oxide semiconductor material. (A2) has a structure that does not diffuse excessively. Accordingly, in the structure according to the first embodiment of the present invention, the hydrogenation process may be simultaneously performed in the heat treatment process for stabilizing the oxide semiconductor material.

Hereinafter, a method of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention will be described with further reference to FIG. 2 . 2 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to the first embodiment of the present invention.

A buffer layer BUF is deposited on the substrate SUB. Although not illustrated in the drawings, a light blocking layer may be formed in a necessary portion before depositing the buffer layer BUF. (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer BUF, and crystallization is performed to make poly-silicon. A first semiconductor layer A1 is formed by patterning the polysilicon material using a first mask process. (S110)

A first gate insulating layer GI1 is formed by depositing an insulating material such as silicon oxide on the entire surface of the substrate SUB on which the first semiconductor layer A1 is formed. The gate insulating film GI is preferably formed of silicon oxide. The thickness of the gate insulating layer GI is preferably 1,000 Å to 1,500 Å. (S120)

A gate metal material is deposited on the first gate insulating layer GI1 and patterned by a second mask process to form a first gate electrode G1. The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer A1 . (S200)

Using the first gate electrode G1 as a mask, impurities are implanted into the lower first semiconductor layer A1 to define a doped region including the source region SA and the drain region DA. The definition process of the doped region may be slightly different according to P-MOS, N-MOS, or C-MOS. For example, in the case of an N-MOS type thin film transistor, a high concentration doping region may be formed first, and then a low concentration doped region may be formed later. A heavily doped region may be defined by using the photoresist pattern of the first gate electrode G1 having a size larger than that of the first gate electrode G1 . A low density doping area (LDD) may be defined between the heavily doped region and the first gate electrode G1 by removing the photoresist and using the first gate electrode G1 as a mask. The impurity-doped region is not shown in the drawings for convenience. (S210)

A first intermediate insulating layer ILD1 is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 is formed. In particular, it is preferable to stack the first intermediate insulating layer ILD1 by depositing an oxide layer SIO such as silicon oxide (SiOx). In consideration of the manufacturing process, the first intermediate insulating layer ILD1 is deposited to a thickness of 1,000 Å to 2,000 Å. (S300)

A nitride layer such as silicon nitride (SiNx) is deposited on the first intermediate insulating layer ILD1. A second intermediate insulating layer ILD2 is formed by patterning the nitride layer by a third mask process. The nitride film for the purpose of hydrogen diffusion is deposited to a thickness of 1,000 Å to 2,000 Å in consideration of the degree of hydrogen diffusion. In particular, the second intermediate insulating layer ILD2 is preferably formed to selectively cover the first region in which the first semiconductor layer A1 is disposed, except for the second region in which the second thin film transistor T2 is disposed. do. (S310)

An oxide semiconductor material is deposited on the second intermediate insulating layer ILD2, in particular, on the oxide layer SIO. In particular, the oxide semiconductor material is preferably disposed directly on the oxide film SIO so as not to directly contact the nitride film SIN containing a large amount of hydrogen. The oxide semiconductor material includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Gallium Oxide (IGO), and Indium Zinc Oxide (IZO). A second semiconductor layer A2 is formed by patterning the oxide semiconductor material by a fourth mask process. The second semiconductor layer A2 is disposed in the second region where the second thin film transistor T2 is to be formed. (S400)

Subsequent heat treatment of the substrate SUB on which the second semiconductor layer A2 is formed is performed to perform a hydrogenation treatment of the first semiconductor layer A1 including polycrystalline silicon and heat treatment of the second semiconductor layer A2 including an oxide semiconductor material do it at the same time The subsequent heat treatment process is performed at a temperature of 350 °C to 380 °C. At this time, hydrogen contained in the second intermediate insulating film ILD2, which is the nitride film SIN, diffuses in a large amount to the first semiconductor layer A1, while it is separated from the nitride film SIN by a considerable distance into the second semiconductor layer A2. The amount of diffusion is limited. In some cases, the hydrogenation process of the first semiconductor layer A1 and the heat treatment process of the second semiconductor layer A2 may be separately performed. In this case, the hydrogenation process is performed immediately after the process S310 of forming the second intermediate insulating layer ILD2 , and the second semiconductor layer A2 is heat-treated through a subsequent heat treatment process. (S410)

An insulating material such as silicon oxide (SiOx) and a gate metal material are continuously deposited on the entire surface of the substrate SUB on which the second semiconductor layer A2 is formed. A second gate insulating layer GI2 and a second gate electrode G2 are formed by patterning the insulating material and the gate metal material through a fifth mask process. The second gate electrode G2 is disposed to overlap the central portion of the second semiconductor layer A2 with the second gate insulating layer GI2 interposed therebetween. In the process of forming the second gate electrode G2 , both sides of the second semiconductor layer A2 except for the central portion are exposed, and these portions form the second source region SA2 and the second drain region DA2 , respectively. is defined That is, an impurity-doped region may be defined together in the second semiconductor layer A2 through the etching process of the second gate electrode G2 . (S500)

A third intermediate insulating layer ILD3 is deposited on the entire surface of the substrate SUB on which the second gate electrode G2 is formed. The third intermediate insulating layer ILD3 is stacked very closely to the second semiconductor layer A2 . Therefore, it is preferable to form the oxide film (SIO) such as silicon oxide (SiOx) with little hydrogen generation. (S600)

The third intermediate insulating layer ILD3 is patterned by a sixth mask process to form second contact holes. In the second contact holes, the second source contact hole SH2 exposing the second source region SA2 that is one side of the second semiconductor layer A2 and the second drain region that is the other side of the second semiconductor layer A2 . and a second drain contact hole DH2 exposing the DA2. (S610)

In the seventh mask process, the third intermediate insulating layer ILD3 , the second intermediate insulating layer ILD2 , the first intermediate insulating layer ILD1 , and the gate insulating layer GI are patterned to form first contact holes. In the first contact holes, the first source contact hole SH1 exposing the first source area SA1 which is one side of the first semiconductor layer A1 and the first drain area DA1 which is the other side of the first semiconductor layer A1 are exposed. 1 includes a drain contact hole DH1. The pattern process for forming the first contact holes may be achieved by continuously performing the sixth mask process for forming the second contact holes. (S700)

Here, the second contact holes are formed by patterning only the third intermediate insulating layer ILD3 , while the first contact holes are the third intermediate insulating layer ILD3 , the second intermediate insulating layer ILD2 , the first intermediate insulating layer ILD1 , and the gate. All of the insulating film GI is formed by patterning. That is, since the thicknesses of the layers to be patterned were different from each other, they were formed through different mask processes. In some cases, after forming the second contact holes, the first contact holes may be formed in a continuous process. In this case, the number of mask processes can be reduced by one.

Source-drain on the third intermediate insulating layer ILD3 in which the first source contact hole SH1 , the first drain contact hole DH1 , the second source contact hole SH2 , and the second drain contact hole DH2 are formed Deposit metal. A first source electrode S1 , a first drain electrode D1 , and a second source electrode S2 and a second drain electrode D2 are formed by patterning the source-drain metal by an eighth mask process. The first source electrode S1 is connected to the first source area SA1, which is one side of the first semiconductor layer A1, through the first source contact hole SH1. The first drain electrode D1 is connected to the first drain region DA1, which is the other side of the first semiconductor layer A1, through the first drain contact hole DH1. The second source electrode S2 is connected to the second source area SA2, which is one side of the second semiconductor layer A2, through the second source contact hole SH2. The second drain electrode D2 is connected to the second drain region DA2, which is the other side of the second semiconductor layer A2, through the second drain contact hole DH2. (S800)

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the source-drain electrodes are formed. Although not illustrated, a contact hole exposing a portion of the first and second drain electrodes D1 and D2 may be further formed by patterning the passivation layer PAS later. (S900)

<Second embodiment>

Hereinafter, a second embodiment of the present invention will be described with reference to FIG. 3 . 3 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.

The second embodiment of the present invention has the same basic configuration as the first embodiment. If there is a difference, there is a difference in the shape of the contact hole connecting the source-drain electrodes to the semiconductor layer. In particular, the number of insulating layers to be etched between the contact holes of the first thin film transistor and the contact holes of the second thin film transistor is greatly different. If they are formed at the same time, one of them may be over-etched or excessively exposed to an etchant, thereby damaging the device. To avoid this, it is desirable to use different mask processes. Also, in the first embodiment, each contact hole is formed by a different mask process, but one contact hole is formed by a single mask process. In the second embodiment, by forming one contact hole in a process separated from each other, the exposure time to the etchant was maintained the same.

Due to the process difference, in the second embodiment, the contact hole may have a double structure having a step difference. In particular, in the case of the first source-drain contact holes SH1 and DH1 passing through the first gate insulating layer GI1 , the first intermediate insulating power ILD1 , the second intermediate insulating layer ILD2 , and the third intermediate insulating layer ILD3 . , a lower contact hole in which the first gate insulating layer GI1 is patterned with the first intermediate insulating power ILD1 and the second intermediate insulating layer ILD2 at the same time, and an upper contact hole where the third intermediate insulating layer ILD3 is patterned. have.

More specifically, the first thin film transistor T1 formed in the first region includes the first semiconductor layer A1, the first gate electrode G1, the first source electrode S1, and the first drain electrode ( D1). The first source electrode S1 is connected to the first source area SA1, which is one side of the first semiconductor layer A1, through the first source contact hole SH1. The first source contact hole SH1 is a lower source contact hole SHb passing through the first source area SA1 , the first gate insulating layer GI1 , the first intermediate insulating layer ILD1 , and the second intermediate insulating layer ILD2 . ) and an upper source contact hole SHa penetrating through the third intermediate insulating layer ILD3. In particular, the first source electrode S1 is connected to and in contact with the etched side surface of the first source area SA1 .

Similarly, the first drain electrode D1 is connected to the first drain area DA1 which is the other side of the first semiconductor layer A1 through the first drain contact hole DH1. The first drain contact hole DH1 is a lower drain contact hole DHb passing through the first drain region DA1 , the first gate insulating layer GI1 , the first intermediate insulating layer ILD1 , and the second intermediate insulating layer ILD2 . ) and an upper drain contact hole DHa penetrating through the third intermediate insulating layer ILD3. In particular, the first drain electrode D1 is connected to and in contact with the etched side surface of the first drain region DA1 .

Meanwhile, the second thin film transistor T2 formed in the second region includes a second semiconductor layer A2 , a second gate electrode G2 , a second source electrode S2 , and a second drain electrode D2 . . The second source electrode S2 is connected to the second source area SA2, which is one side of the second semiconductor layer A2, through the second source contact hole SH2. The second source contact hole SH2 passes through the second source area SA2 and the third intermediate insulating layer ILD3 . In particular, the second source electrode S2 is connected to and in contact with the etched side surface of the second source area SA2 .

Similarly, the second drain electrode D2 is connected to the second drain region DA2 which is one side of the second semiconductor layer A2 through the second drain contact hole DH2. The second drain contact hole DH2 passes through the second drain region DA2 and the third intermediate insulating layer ILD3 . In particular, the second drain electrode D2 is connected to and in contact with the etched side surface of the second drain region DA2 .

Thin films etched in the contact holes formed in the first thin film transistor T1 and the contact holes formed in the second thin film transistor T2 are different from each other. In order not to adversely affect the device in the process of etching different thicknesses, it is configured to have different shapes as described above. That is, the lower contact holes of the first thin film transistor T1 are first formed, and the contact holes of the second thin film transistor T2 and the upper contact holes of the first thin film transistor T1 are formed together. This process will be looked at in detail in the description of the manufacturing process below.

Since other components are the same as those of the first embodiment, detailed descriptions are omitted. Hereinafter, a process of manufacturing the thin film transistor substrate for a flat panel display according to the second embodiment will be described. Here too, since it is almost the same as that of the first embodiment, the same description without an important meaning is omitted. 4 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.

A buffer layer BUF is deposited on the substrate SUB. (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer BUF, and crystallization is performed to make poly-silicon. A first semiconductor layer A1 is formed by patterning the polysilicon material using a first mask process. (S110)

A gate insulating layer GI is formed by depositing an insulating material such as silicon oxide on the entire surface of the substrate SUB on which the first semiconductor layer A1 is formed. The gate insulating layer GI is preferably formed of silicon oxide having a thickness of about 1,000 Å to 1,500 Å. (S120)

A gate metal material is deposited on the gate insulating layer GI and patterned by a second mask process to form a first gate electrode G1. The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer A1 . (S200)

Using the first gate electrode G1 as a mask, impurities are implanted into the lower first semiconductor layer A1 to define a doped region including the first source region SA1 and the first drain region DA1. do. (S210)

A first intermediate insulating layer ILD1 is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 is formed. In particular, it is preferable to stack the first intermediate insulating layer ILD1 by depositing an oxide layer SIO such as silicon oxide (SiOx). In consideration of the manufacturing process, the first intermediate insulating layer ILD1 is deposited to a thickness of 1,000 Å to 2,000 Å. (S300)

A nitride layer such as silicon nitride (SiNx) is deposited on the first intermediate insulating layer ILD1. A second intermediate insulating layer ILD2 is formed by patterning the nitride layer by a third mask process. Considering the degree of hydrogen diffusion, the nitride film is deposited to a thickness of 1,000 Å to 2,000 Å. (S310)

In the fourth mask process, lower contact holes are formed by patterning the second intermediate insulating layer ILD2 , the first intermediate insulating layer ILD1 , and the first gate insulating layer GI1 . The lower contact holes include a lower source contact hole SHb and a lower drain contact hole DHb. Here, the lower source contact hole SHb and the lower drain contact hole DHb pass through the second intermediate insulating layer ILD2 , the first intermediate insulating layer ILD1 , and the first gate insulating layer GI1 . The first source area SA1 and the first drain area DA1 of the layer A1 are exposed. That is, the first source area SA1 and the first drain area DA1 are not passed through yet. (S400)

An oxide semiconductor material is deposited on the second intermediate insulating layer ILD2 that is the oxide layer SIO. In particular, the oxide semiconductor material is preferably disposed directly on the oxide film SIO so as not to directly contact the nitride film SIN containing a large amount of hydrogen. A second semiconductor layer A2 is formed by patterning the oxide semiconductor material by a fifth mask process. The second semiconductor layer A2 is disposed in the second region where the second thin film transistor T2 is to be formed. (S500)

Subsequent heat treatment of the substrate SUB on which the second semiconductor layer A2 is formed is performed to perform a hydrogenation treatment of the first semiconductor layer A1 including polycrystalline silicon and heat treatment of the second semiconductor layer A2 including an oxide semiconductor material do it at the same time The subsequent heat treatment process is performed at a temperature of 350 °C to 380 °C. At this time, hydrogen contained in the second intermediate insulating film ILD2, which is the nitride film SIN, diffuses in a large amount to the first semiconductor layer A1, while it is separated from the nitride film SIN by a considerable distance into the second semiconductor layer A2. The amount of diffusion is limited. In some cases, the hydrogenation process of the first semiconductor layer A1 and the heat treatment process of the second semiconductor layer A2 may be separately performed. In this case, the hydrogenation process is performed immediately after the process S310 of forming the second intermediate insulating layer ILD2 , and the second semiconductor layer A2 is heat-treated through a subsequent heat treatment process. (S510)

An insulating material such as silicon oxide (SiOx) and a gate metal material are continuously deposited on the entire surface of the substrate SUB on which the second semiconductor layer A2 is formed. A second gate insulating layer GI2 and a second gate electrode G2 are formed by patterning the insulating material and the gate metal material through a sixth mask process. The second gate electrode G2 is disposed to overlap the central portion of the second semiconductor layer A2 with the second gate insulating layer GI2 interposed therebetween. In the process of forming the second gate electrode G2 , the second source area SA2 and the second drain area DA2 are defined together. (S600)

A third intermediate insulating layer ILD3 is deposited on the entire surface of the substrate SUB on which the second gate electrode G2 is formed. The third intermediate insulating layer ILD3 is stacked very closely to the second semiconductor layer A2 . Therefore, it is preferable to form the oxide film (SIO) such as silicon oxide (SiOx) with little hydrogen generation. (S700)

The third intermediate insulating layer ILD3 , the second semiconductor layer A2 , and the first semiconductor layer A1 are patterned by a seventh mask process to form first and second contact holes. In the first thin film transistor T1 , an upper source contact hole SHa and an upper drain contact hole DHa having larger sizes are formed to expose the lower source contact hole SHb and the lower drain contact hole DHb, respectively. . Then, the etching process is continuously performed to etch the first source area SA1 and the first drain area DA1 exposed to the lower source contact hole SHb and the lower drain contact hole DHb, respectively, to obtain a first source contact. The hole SH1 and the first drain contact hole DH1 are completed.

At the same time, in the second thin film transistor T2 , the third intermediate insulating layer ILD3 , the second source contact hole SH2 passing through the second source region SA2 , and the third intermediate insulating layer ILD3 and the second A second drain contact hole DH2 passing through the drain area DA2 is formed. In both the first thin film transistor T1 and the second thin film transistor T2 , since the third intermediate insulating layer ILD3 and the semiconductor layer are etched, a phenomenon in which one part is overexposed to the etchant does not occur. (S710)

Source-drain on the third intermediate insulating layer ILD3 in which the first source contact hole SH1 , the first drain contact hole DH1 , the second source contact hole SH2 , and the second drain contact hole DH2 are formed Deposit metal. A first source electrode S1 , a first drain electrode D1 , and a second source electrode S2 and a second drain electrode D2 are formed by patterning the source-drain metal by an eighth mask process. The first source electrode S1 is connected to the etched side surface of the first source area SA1 through the first source contact hole SH1 . The first drain electrode D1 is connected to the etched side surface of the first drain region DA1 through the first drain contact hole DH1. The second source electrode S2 is connected to the etched side surface of the second source area SA2 through the second source contact hole SH2 . In addition, the second drain electrode D2 is connected to the etched side surface of the second drain region DA2 through the second drain contact hole DH2. (S800)

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the source-drain electrodes are formed. Although not illustrated, a contact hole exposing a portion of the first and second drain electrodes D1 and D2 may be further formed by patterning the passivation layer PAS later. (S900)

< 1st application example >

The thin film transistor substrate having the different thin film transistors described so far can be applied to various flat panel display devices. As suggested in the present invention, advantages that can be obtained when thin film transistors having different characteristics are formed on a single substrate are diverse. Hereinafter, with reference to FIG. 5 , the display device using the thin film transistor substrate according to the first application example of the present invention will be described in detail about what characteristics and what advantages can be expected. 5 is a block diagram schematically showing the configuration of a display device according to a first application example of the present invention.

One or more of the first and second thin film transistors T1 and T2 may be thin film transistors formed in each of the pixels of the display panel 100 to switch data voltages written to the pixels or to drive the pixels. In the case of an organic light emitting diode display, the second thin film transistor T2 may be applied as a switch element of a pixel, and the first thin film transistor T1 may be applied as a driving element, but is not limited thereto. The first and second thin film transistors T1 and T2 may be combined and applied as one switch element or one driving element.

In order to reduce power consumption in a mobile device or a wearable device, a low-speed driving method of lowering a frame rate has been attempted. In this case, the frame frequency of a still image or an image having a late data update period may be lowered. However, if the frame rate is lowered, a phenomenon in which the luminance flickers whenever the data voltage is changed, or a flicker phenomenon in which the luminance flickers at the data update cycle due to a prolonged voltage discharge time of the pixel may be seen. When the first and second thin film transistors T1 and T2 of the present invention are applied to the pixel, the flicker problem during low-speed driving can be solved.

When the data update period is long during low-speed driving, the amount of leakage current of the switch thin film transistor increases. The leakage current of the switch thin film transistor causes a drop in the voltage of the storage capacitor STG and the gate-source voltage of the driving thin film transistor. In the present invention, the second thin film transistor, which is an oxide transistor, can be applied as a switch thin film transistor of a pixel. Since the oxide transistor has a low off-current, a voltage drop between the storage capacitor and the gate electrode of the driving thin film transistor can be prevented. Accordingly, the present invention can prevent flicker when driving at a low speed.

When the first thin film transistor, which is a polysilicon transistor, is applied as a driving thin film transistor of a pixel, the amount of current supplied to the organic light emitting diode can be increased because electron mobility is high. Accordingly, according to the present invention, by applying the second thin film transistor T2 to the switch element of the pixel and the first thin film transistor T1 to the driving element of the pixel, power consumption can be significantly reduced and image quality deterioration can be prevented.

The present invention is effective for application to a mobile device or a wearable device because image quality deterioration can be prevented when a low-speed driving method is applied to reduce power consumption. For example, the portable electronic watch may update data on the display screen in units of 1 second to reduce power consumption. The frame frequency at this time is 1 Hz. According to the present invention, excellent image quality without flicker can be realized even using a driving frequency close to 1 Hz or a still image. The present invention can significantly reduce power consumption without degrading image quality by significantly lowering the frame rate of a still image on a standby screen of a mobile device or a wearable device. As a result, the present invention can improve portability by improving the picture quality of a mobile device or a wearable device and extending the battery life. According to the present invention, power consumption can be greatly reduced without degradation of image quality even in an E-Book with a very long data update cycle.

At least one of the first and second thin film transistors T1 and T2 is built into a driving circuit, for example, at least one of the data driver 200 , the multiplexer MUX 210 , and the gate driver 300 in FIG. 5 . A driving circuit can be configured. This driving circuit writes data to the pixel. In addition, one of the first and second thin film transistors T1 and T2 may be formed in the pixel and the other may be formed in the driving circuit. The data driver 200 converts the data of the input image into a data voltage and outputs it. The multiplexer 210 reduces the number of output channels of the data driver 200 by time division distribution of the data voltage from the data driver 200 to the plurality of data lines DL. The gate driver 300 outputs a scan signal (or gate signal) synchronized with the data voltage to the gate line GL to sequentially select pixels in which data of the input image is written in line units. In order to reduce the number of output channels of the gate driver 300 , a multiplexer (not shown) may be added between the gate driver 300 and the gate lines GL. The multiplexer 210 and the gate driver 300 may be directly formed on the thin film transistor substrate together with the pixel array as shown in FIG. 5 . The multiplexer 210 and the gate driver 300 are disposed in the non-display area NA as shown in FIG. 5 , and the pixel array is disposed in the display area AA.

The display device of the present invention can be applied to any display device requiring a thin film transistor, such as an active display device using a thin film transistor, for example, a liquid crystal display device, an organic light emitting diode display device, and an electrophoretic display device. Hereinafter, application examples of the display device to which the thin film transistor substrate according to the present invention is applied will be described with further reference to the drawings.

< 2nd application example >

6 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display, which is a type of horizontal electric field type, according to a second application example of the present invention. FIG. 7 is a cross-sectional view of the thin film transistor substrate shown in FIG. 6 taken along the perforated line I-I'.

The thin film transistor substrate having the metal oxide semiconductor layer shown in FIGS. 6 and 7 includes a gate line GL and a data line DL crossing a lower substrate SUB with a gate insulating layer GI interposed therebetween, and the intersection thereof. A thin film transistor T formed for each part is provided. In addition, a pixel area is defined by the cross structure of the gate line GL and the data line DL.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S, and a gate A semiconductor layer (A) overlapping the gate electrode (G) on the insulating layer (GI) and having a channel region between the source electrode (S) and the drain electrode (D) is included.

A gate pad GP for receiving a gate signal from the outside is disposed at one end of the gate line GL. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 passing through the gate insulating layer GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 penetrating the first and second passivation layers PA1 and PA2 . Meanwhile, a data pad DP for receiving a pixel signal from the outside is disposed at one end of the data line DL. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH penetrating the first passivation layer PA1 and the second passivation layer PA2 .

In the pixel area, the pixel electrode PXL and the common electrode COM are disposed with the second passivation layer PA2 interposed therebetween to form a fringe field. The common electrode COM may be connected to the common line CL arranged in parallel with the gate line GL. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL. As another method, the common electrode COM may have a shape disposed on the entire surface of the substrate SUB except for a portion where the drain contact hole DH is disposed. That is, the common electrode COM may function to shield the data line DL by covering the upper layer of the data line DL.

The positions and shapes of the common electrode COM and the pixel electrode PXL may have various shapes according to a design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that changes frequently according to video data to be implemented is applied to the pixel electrode PXL. Accordingly, a parasitic capacitance may be generated between the data line DL and the pixel electrode PXL. Since such a parasitic capacitance may cause a problem in image quality, it is preferable to arrange the common electrode COM first and the pixel electrode PXL on the uppermost layer.

That is, after forming the planarization layer PAC by thickly stacking an organic material having a low dielectric constant on the first passivation layer PA1 covering the data line DL and the thin film transistor T, the common electrode COM is formed. Then, after the second passivation layer PA2 covering the common electrode COM is formed, the pixel electrode PXL overlapping the common electrode COM is formed on the second passivation layer PA2 . In this structure, since the pixel electrode PXL is spaced apart by the data line DL, the first passivation layer PA1, the planarization layer PAC, and the second passivation layer PA2, the data line DL and the pixel electrode PXL In between, the parasitic capacity can be reduced. However, the present invention is not limited thereto, and in some cases, the pixel electrode PXL may be disposed first, and the common electrode COM may be disposed on the uppermost layer.

The common electrode COM has a rectangular shape corresponding to the shape of the pixel area, and the pixel electrode PXL has a plurality of line segment shapes. In particular, the pixel electrode PXL has a structure that vertically overlaps with the common electrode COM with the second passivation layer PA2 interposed therebetween. Accordingly, a fringe field is formed between the pixel electrode PXL and the common electrode COM. Liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate rotate due to dielectric anisotropy by the fringe field type electric field. In addition, the transmittance of light passing through the pixel region varies according to the degree of rotation of the liquid crystal molecules to realize grayscale.

6 and 7 illustrating the second application example of the present invention, for convenience, the structure of the thin film transistor T in the liquid crystal display is only schematically illustrated. The structures of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, when low-speed driving is required, the second thin film transistor T2 having an oxide semiconductor layer may be applied. When low power consumption is required, the first thin film transistor T1 having a polycrystalline semiconductor layer may be applied. Alternatively, both the first and second thin film transistors T1 and T2 may be provided and configured to be connected to each other to complement each other.

< 3rd application example >

8 is a plan view showing the structure of one pixel in a matrix organic light emitting diode display according to a third application example of the present invention. 9 is a cross-sectional view showing the structure of the active matrix organic light emitting diode display device taken along the cut line II-II' in FIG. 8 .

8 and 9 , the active matrix organic light emitting diode display includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor, and an organic light emitting diode OLE connected to the driving thin film transistor DT. includes

The switching thin film transistor ST is disposed on the substrate SUB at an intersection of the gate line GL and the data line DL. The switching thin film transistor ST has a function of selecting a pixel by supplying a data voltage from the data line DL to the gate electrode DG and the storage capacitor STG of the driving thin film transistor DT in response to a scan signal do The switching thin film transistor ST includes a gate electrode SG branching from the gate line GL, a semiconductor layer SA, a source electrode SS, and a drain electrode SD. In addition, the driving thin film transistor DT drives the organic light emitting diode OLE of the pixel selected by the switching thin film transistor ST by controlling the current flowing through the organic light emitting diode OLE of the pixel according to the gate voltage.

The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor layer DA, a source electrode DS connected to the driving current line VDD, and a drain and an electrode DD. The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE. An organic light emitting layer OL is interposed between the anode electrode ANO and the cathode electrode CAT. The cathode electrode CAT is connected to the base line VSS.

Referring to FIG. 9 for a closer look, the gate electrodes SG and DG of the switching thin film transistor ST and the driving thin film transistor DT are disposed on the substrate SUB of the active matrix organic light emitting diode display device. have. In addition, the gate insulating layer GI covers the gate electrodes SG and DG. The semiconductor layers SA and DA are disposed on a portion of the gate insulating layer GI overlapping the gate electrodes SG and DG. On the semiconductor layers SA and DA, the source electrodes SS and DS and the drain electrodes SD and DD are disposed to face each other with a predetermined interval therebetween. The drain electrode SD of the switching thin film transistor ST contacts the gate electrode DG of the driving thin film transistor DT through the drain contact hole DH passing through the gate insulating layer GI. A protective film PAS covering the switching thin film transistor ST and the driving thin film transistor DT having such a structure is stacked on the entire surface.

A color filter CF is disposed in a portion corresponding to the region of the anode electrode ANO. The color filter CF preferably has as wide an area as possible. For example, it is preferable to have a shape overlapping many regions of the data line DL, the driving current line VDD, and the gate line GL of the previous stage. As described above, the surface of the substrate on which the switching thin film transistor ST, the driving thin film transistor DT, and the color filters CF are disposed is not flat and the level difference is severe. The organic light emitting layer OL must be laminated on a flat surface so that light emission can be uniformly and uniformly emitted. Therefore, a planarization film (PAC) or an overcoat layer (OC) is laminated on the entire surface of the substrate for the purpose of flattening the surface of the substrate.

And the anode electrode ANO of the organic light emitting diode OLE is disposed on the overcoat layer OC. Here, the anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the pixel contact hole PH formed in the overcoat layer OC and the passivation layer PAS.

On the substrate on which the anode electrode ANO is disposed, the bank BA is disposed on the area where the switching thin film transistor ST, the driving thin film transistor DT, and various wirings DL, GL, and VDD are disposed to define a pixel area. (or bank pattern) is arranged. The anode electrode ANO exposed by the bank BA becomes a light emitting area. An organic light emitting layer OL is stacked on the anode ANO exposed by the bank BA. In addition, a cathode electrode CAT is sequentially stacked on the organic light emitting layer OL. When the organic light emitting layer OL is made of an organic material emitting white light, a color assigned to each pixel is displayed by the color filter CF positioned below. The organic light emitting diode display having the structure as shown in FIG. 9 becomes a bottom emission display device emitting light in a downward direction.

A storage capacitor (or 'Storage Capacitance') STG is disposed between the gate electrode DG and the anode electrode ANO of the driving thin film transistor DT. The storage capacitor STG is connected to the driving thin film transistor DT so that a voltage applied to the gate electrode DG of the driving thin film transistor DT by the switching thin film transistor ST is stably maintained.

By applying the thin film transistor substrate as described above, it is possible to realize a high-quality active display device. In particular, in order to have better driving characteristics, it is preferable that the semiconductor layer of the thin film transistor is formed of a metal oxide semiconductor material.

The metal oxide semiconductor material has a characteristic that its characteristics are rapidly deteriorated when it is voltage driven in a state in which it is exposed to light. Accordingly, it is desirable to have a structure capable of blocking light entering from the outside at the upper and lower portions of the semiconductor layer. In the case of the thin film transistor substrate described above, the thin film transistor preferably has a bottom gate structure. That is, light entering from the bottom may be blocked to some extent by the gate electrode G, which is a metal material.

As described above, in a thin film transistor substrate for a flat panel display device, a plurality of pixel regions arranged in a matrix manner are disposed so far. In addition, at least one thin film transistor is disposed in each of the unit pixel areas. That is, it has a structure in which a plurality of thin film transistors are distributed over the entire area of the substrate. Since the respective structures of the plurality of pixels must be used for the same purpose and have the same quality and properties, they are formed with the same structure.

However, in some cases, it may be necessary to have different characteristics of the thin film transistors. For example, in the case of an organic light emitting diode display, a switching thin film transistor ST and a driving thin film transistor DT are included in one pixel area. Since the purpose of the switching thin film transistor ST and the driving thin film transistor DT are different from each other, the required characteristics are also different. To this end, it can be designed to have the same structure and the same semiconductor channel layer but have different sizes to suit each function. Alternatively, if necessary, a compensation thin film transistor may be further provided to supplement the function or performance.

8 and 9 for explaining the third application example of the present invention, for convenience, only the structures of the thin film transistors ST and DT of the organic light emitting diode display are schematically illustrated. However, the structures of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, the second thin film transistor T2 having an oxide semiconductor layer may be applied to the switching thin film transistor ST. The first thin film transistor T1 having a polycrystalline semiconductor layer may be applied to the driving thin film transistor DT. As described above, while providing both the first and second thin film transistors T1 and T2 , the disadvantages of the other thin film transistors can be complemented by mutual advantages.

< 4th application example >

In another case, a thin film transistor substrate in which a driving element is embedded in a non-display area of a display device may be used. Hereinafter, a case in which the driving element is directly formed on the display panel will be described in detail with reference to FIGS. 10 and 11 .

10 is an enlarged plan view showing a schematic structure of an organic light emitting diode display device according to a fourth application example of the present invention. 11 is a cross-sectional view showing the structure of an organic light emitting diode display according to a fourth application example of the present invention, taken along the cut line III-III' in FIG. 10 . Here, a thin film transistor substrate for a flat panel display having a built-in driving element will be described, and a detailed description of the thin film transistor and organic light emitting diode disposed in the display area will be omitted.

First, with reference to FIG. 10, the structure on a plane is demonstrated. The organic light emitting diode display with a built-in gate driver (GIP) according to a fourth application example of the present invention has a ratio between a display area AA displaying image information and various elements for driving the display area AA. and a substrate SUB divided by a display area NA. A plurality of pixel areas PA arranged in a matrix manner is defined in the display area AA. In FIG. 10 , the pixel areas PA are indicated by dotted lines.

For example, the pixel areas PA may be defined as an NxM rectangle. However, it is not necessarily limited to this method, and may be arranged in various ways. Each pixel area may have the same size or may have different sizes. In addition, three sub-pixels representing RGB (red, green, blue) colors may be regularly arranged as one unit. In the simplest structure, the pixel areas PA have a cross structure of a plurality of gate lines GL running in a horizontal direction and a plurality of data lines DL and driving current lines VDD running in a vertical direction. can be defined as

A data driver (or Data Driving Integrated Circuit) (DIC) for supplying a signal corresponding to image information to the data lines DL in the non-display area NA, which is defined on the outer periphery of the pixel area PA; A gate driver (or, a gate driving integrated circuit) (GIP) for supplying a scan signal to the gate wirings GL may be disposed. In the case of high resolution higher than the VGA level, in which the number of data lines DL and driving current lines VDD increases, the data driver DIC is mounted outside the substrate SUB, and the data driver DIC ) instead of data connection pads may be arranged.

In order to simplify the structure of the display device, the gate driver GIP is preferably directly formed on one side of the substrate SUB. In addition, a base line Vss for supplying a base voltage is disposed at the outermost portion of the substrate SUB. The ground wiring Vss is preferably disposed to receive a ground voltage supplied from the outside of the substrate SUB, and to supply the ground voltage to both the data driver DIC and the gate driver GIP. For example, the electrical wiring Vss is connected to the data driver DIC to be separately mounted on the upper side of the substrate SUB, and the gate driver GIP is disposed on the left and/or right side of the substrate SUB. It can be arranged as if wrapping the substrate from the outside of the.

In each pixel area PA, an organic light emitting diode, which is a key component of an organic light emitting diode display, and thin film transistors for driving the organic light emitting diode are disposed. The thin film transistors may be disposed in the thin film transistor area TA defined at one side of the pixel area PA. The organic light emitting diode includes an anode electrode ANO, a cathode electrode CAT, and an organic light emitting layer OL interposed between the two electrodes. The area that actually emits light is determined by the area of the organic light emitting layer overlapping the anode electrode ANO.

The anode electrode ANO has a shape occupying a portion of the pixel area PA and is connected to the thin film transistor disposed in the thin film transistor area TA. An organic light emitting layer OL is stacked on the anode ANO, and an area where the anode ANO and the organic light emitting layer OL overlap is determined as an actual light emitting area. The cathode electrode CAT is formed as a single body so as to cover at least the area of the display area AA in which the pixel areas PA are disposed on the organic light emitting layer OL.

The cathode electrode CAT crosses the gate driver GIP and contacts the base line Vss disposed on the outer side of the substrate SUB. That is, the base voltage is applied to the cathode electrode CAT through the base line Vss. The cathode electrode CAT receives the base voltage, the anode electrode ANO receives the image voltage, and light is emitted from the organic light emitting layer OL by the voltage difference therebetween to display image information.

With further reference to FIG. 11 , a cross-sectional structure of an organic light emitting diode display according to a fourth application example of the present invention will be described in more detail. A non-display area NA in which the gate driver GIP and the base wiring Vss are disposed on the substrate SUB, and the switching thin film transistor ST, the driving thin film transistor DT, and the organic light emitting diode OLE are disposed A display area AA is defined.

The gate driver GIP may include a thin film transistor formed together in the process of forming the switching thin film transistor ST and the driving thin film transistor DT. The switching thin film transistor ST disposed in the pixel area PA includes a gate electrode SG, a gate insulating layer GI, a channel layer SA, a source electrode SS, and a drain electrode SD. In addition, the driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a gate insulating layer GI, a channel layer DA, a source electrode DS, and a drain electrode ( DD) is included.

A passivation layer PAS and a planarization layer PL are sequentially stacked on the thin film transistors ST and DT. An isolated rectangular anode electrode ANO occupying only a certain portion of the pixel area PA is disposed on the planarization layer PL. The anode electrode ANO contacts the drain electrode DD of the driving thin film transistor DT through a contact hole penetrating the passivation layer PAS and the planarization layer PL.

A bank BA defining a light emitting area is disposed on the substrate on which the anode electrode ANO is formed. The bank BA has a shape exposing most of the anode electrode ANO. An organic light emitting layer OL is stacked on the anode electrode ANO exposed by the bank BA pattern. A cathode electrode CAT made of a transparent conductive material is stacked on the bank BA and the organic light emitting layer OL. Accordingly, the organic light emitting diode OLE including the anode electrode ANO, the organic light emitting layer OL and the cathode electrode CAT is disposed.

The organic light emitting layer OL may emit white light, and a color may be expressed using a separately formed color filter CF. In this case, the organic light emitting layer OL is preferably stacked to cover at least all of the display area AA.

The cathode electrode CAT preferably covers the display area AA and the non-display area NA so as to be in contact with the base line Vss disposed on the outer side of the substrate SUB beyond the gate driver GIP. Accordingly, the ground voltage may be applied to the cathode electrode CAT through the ground line Vss.

Meanwhile, the base wiring Vss may be formed of the same material as the gate electrode G and on the same layer. In this case, it may contact the cathode electrode CAT through a contact hole penetrating the passivation layer PAS covering the base line Vss and the gate insulating layer GI. Alternatively, the base wiring Vss may be formed of the same material as the source-drain electrodes SS-SD and DS-DD on the same layer. In this case, the base line Vss may contact the cathode electrode CAT through a contact hole penetrating the passivation layer PAS.

10 and 11 illustrating the fourth application example of the present invention, for convenience, the thin film transistors ST and DT of the organic light emitting diode display and the thin film transistor structures of the gate driving device GIP are only schematically illustrated. The structures of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, the second thin film transistor T2 having an oxide semiconductor layer may be applied to the switching thin film transistor ST. The first thin film transistor T1 having a polycrystalline semiconductor layer may be applied to the driving thin film transistor DT. In addition, the first thin film transistor T1 having a polycrystalline semiconductor layer may be applied to the gate driver GIP. If necessary, the gate driver GIP may include a C-MOS type thin film transistor having both a P-MOS type and an N-MOS type.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

GL: gate wiring PAS: protective film
DL: data wire VDD: drive current wire
PA: pixel area T: thin film transistor
AA: display area NA: non-display area
G: gate electrode A: semiconductor layer
S: source electrode D: drain electrode
GI: gate insulating film ILD1: first intermediate insulating film
ILD2: second intermediate insulating film ILD3: third intermediate insulating film
SIN: nitride film SIO: oxide film

Claims (16)

a first thin film transistor comprising a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode disposed on the polycrystalline semiconductor layer, the first thin film transistor being disposed in a first region;
A second thin film transistor comprising an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode disposed over the oxide semiconductor layer, the second thin film transistor being disposed in a second region;
a first intermediate insulating layer covering the first gate electrode and disposed under the oxide semiconductor layer, the first intermediate insulating layer including an oxide layer;
a second intermediate insulating film selectively disposed on the first intermediate insulating film in the first region except for the second region, the second intermediate insulating film including a nitride film; and
a third intermediate insulating film covering the first gate electrode and the second gate electrode on the second intermediate insulating film, and including an oxide film;
The first source electrode is disposed on the third intermediate insulating layer, and is connected to one side of the polycrystalline semiconductor layer through a first source contact hole;
the first drain electrode is disposed on the third intermediate insulating layer and is connected to the other side of the polycrystalline semiconductor layer through a first drain contact hole;
The second source electrode is disposed on the third intermediate insulating layer and is connected to one side of the oxide semiconductor layer through a second source contact hole,
The second drain electrode is disposed on the third intermediate insulating layer, and is connected to the other side of the oxide semiconductor layer through a second drain contact hole.
The method of claim 1,
a first gate insulating film covering the polycrystalline semiconductor layer; and
and a second gate insulating layer interposed between the oxide semiconductor layer and the first gate electrode.
3. The method of claim 2,
the first source contact hole passes through the third intermediate insulating layer, the second intermediate insulating layer, the first intermediate insulating layer, and the first gate insulating layer;
the first drain contact hole passes through the third intermediate insulating layer, the second intermediate insulating layer, the first intermediate insulating layer, and the first gate insulating layer;
the second source contact hole passes through the third intermediate insulating layer;
The second drain contact hole passes through the third intermediate insulating layer.
3. The method of claim 2
The first source contact hole may include an upper source contact hole penetrating the third intermediate insulating film, and a lower source penetrating the second intermediate insulating film, the first intermediate insulating film, the first gate insulating film, and one side of the polycrystalline semiconductor layer. a contact hole, wherein the first source electrode is connected to an etched side surface of the one side portion through the first source contact hole;
The first drain contact hole may include an upper drain contact hole penetrating the third intermediate insulating film, and a lower portion penetrating the second intermediate insulating film, the first intermediate insulating film, the first gate insulating film, and the other side of the polycrystalline semiconductor layer. a drain contact hole, wherein the first drain electrode is connected to an etched side surface of the other side portion through the first drain contact hole;
The second source contact hole penetrates through one side of the third intermediate insulating layer and the oxide semiconductor layer, and the second source electrode is connected to the etched side of the one side through the second source contact hole,
The second drain contact hole penetrates through the third intermediate insulating layer and the other side of the oxide semiconductor layer, and the second drain electrode is connected to the etched side of the other side through the second drain contact hole. .
5. The method of claim 4,
The upper source contact hole is larger than the lower source contact hole to include the lower source contact hole,
The size of the upper drain contact hole is larger than that of the lower drain contact hole to include the lower drain contact hole.
The method of claim 1,
The second thin film transistor is a switching element for selecting a pixel,
The first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor.
a first thin film transistor comprising a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode disposed on the polycrystalline semiconductor layer, the first thin film transistor being disposed in a first region;
A second thin film transistor comprising an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode disposed over the oxide semiconductor layer, the second thin film transistor being disposed in a second region;
a first intermediate insulating layer covering the first gate electrode and disposed under the oxide semiconductor layer, the first intermediate insulating layer including an oxide layer;
a second intermediate insulating film selectively disposed on the first intermediate insulating film in the first region except for the second region, the second intermediate insulating film including a nitride film;
a third intermediate insulating layer on the second intermediate insulating layer, the third intermediate insulating layer covering the first gate electrode and the second gate electrode, and including an oxide layer; and
comprising a driving circuit;
One of the first thin film transistor and the second thin film transistor is included in the driving circuit, and the other is included in the pixel.
8. The method of claim 7,
The driving circuit is
a data driver outputting a data voltage;
a multiplexer that distributes the data voltage from the data driver to data lines; and
a gate driver outputting a scan pulse to a gate wiring;
Any one of the first thin film transistor and the second thin film transistor is included in any one of the multiplexer and the gate driver.
a first semiconductor layer comprising a polycrystalline semiconductor material disposed in a first region;
a first gate insulating layer covering the first semiconductor layer;
a first gate electrode overlapping the first semiconductor layer on the first gate insulating layer;
a first intermediate insulating layer covering the first gate electrode and including an oxide layer;
a second semiconductor layer comprising an oxide semiconductor material and disposed in a second region over the first intermediate insulating layer;
a second intermediate insulating film disposed on the first intermediate insulating film in the first region except for the second region, the second intermediate insulating film including a nitride film;
a second gate electrode overlapping the second semiconductor layer with a second gate insulating layer interposed therebetween;
a third intermediate insulating film covering the second intermediate insulating film and the second gate electrode and including an oxide film; and
a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode disposed on the third intermediate insulating layer;
The first source electrode is connected to one side of the first semiconductor layer through a first source contact hole,
The first drain electrode is connected to the other side of the first semiconductor layer through a first drain contact hole,
The second source electrode is connected to one side of the second semiconductor layer through a second source contact hole,
The second drain electrode is connected to the other side of the second semiconductor layer through a second drain contact hole.
10. The method of claim 9,
the first source contact hole passes through the third intermediate insulating layer, the second intermediate insulating layer, the first intermediate insulating layer, and the first gate insulating layer;
the first drain contact hole passes through the third intermediate insulating layer, the second intermediate insulating layer, the first intermediate insulating layer, and the first gate insulating layer;
the second source contact hole passes through the third intermediate insulating layer;
The second drain contact hole passes through the third intermediate insulating layer.
10. The method of claim 9
The first source contact hole may include an upper source contact hole penetrating the third intermediate insulating film, and a lower portion penetrating the second intermediate insulating film, the first intermediate insulating film, the first gate insulating film, and one side of the first semiconductor layer. a source contact hole, wherein the first source electrode is connected to an etched side surface of the one side portion through the first source contact hole;
The first drain contact hole may include an upper drain contact hole penetrating the third intermediate insulating film, and penetrating the second intermediate insulating film, the first intermediate insulating film, the first gate insulating film, and the other side of the first semiconductor layer. a lower drain contact hole, wherein the first drain electrode is connected to an etched side surface of the other side through the first drain contact hole;
The second source contact hole penetrates through one side of the third intermediate insulating layer and the second semiconductor layer, and the second source electrode is connected to the etched side of the one side through the second source contact hole,
The second drain contact hole penetrates through the other side portions of the third intermediate insulating layer and the second semiconductor layer, and the second drain electrode is connected to the etched side surface of the other side through the second drain contact hole. .
12. The method of claim 11,
The upper source contact hole is larger than the lower source contact hole to include the lower source contact hole,
The size of the upper drain contact hole is larger than that of the lower drain contact hole to include the lower drain contact hole.
10. The method of claim 9,
The first semiconductor layer, the first gate electrode, the first source electrode, and the first drain electrode are included in a first thin film transistor,
The second semiconductor layer, the second gate electrode, the second source electrode, and the second drain electrode are included in a second thin film transistor.
14. The method of claim 13,
The second thin film transistor is a switching element for selecting a pixel,
The first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor.
a first semiconductor layer comprising a polycrystalline semiconductor material disposed in a first region;
a first gate insulating layer covering the first semiconductor layer;
a first gate electrode overlapping the first semiconductor layer on the first gate insulating layer;
a first intermediate insulating layer covering the first gate electrode and including an oxide layer;
a second semiconductor layer comprising an oxide semiconductor material and disposed in a second region over the first intermediate insulating layer;
a second intermediate insulating film disposed on the first intermediate insulating film in the first region except for the second region, the second intermediate insulating film including a nitride film;
a second gate electrode overlapping the second semiconductor layer with a second gate insulating layer interposed therebetween;
a third intermediate insulating film covering the second intermediate insulating film and the second gate electrode and including an oxide film;
a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode disposed on the third intermediate insulating layer; and
comprising a driving circuit;
The first semiconductor layer, the first gate electrode, the first source electrode, and the first drain electrode are included in a first thin film transistor,
the second semiconductor layer, the second gate electrode, the second source electrode, and the second drain electrode are included in a second thin film transistor;
One of the first thin film transistor and the second thin film transistor is included in the driving circuit, and the other is included in the pixel.
16. The method of claim 15,
The driving circuit is
a data driver outputting a data voltage;
a multiplexer that distributes the data voltage from the data driver to data lines; and
a gate driver outputting a scan pulse to a gate wiring;
Any one of the first thin film transistor and the second thin film transistor is included in any one of the multiplexer and the gate driver.

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