KR102370322B1 - Thin Film Transistor Substrate And Display Using The Same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate in which different types of thin film transistors are disposed on the same substrate and a display device using the same. A display device according to the present invention includes a first semiconductor layer, a second semiconductor layer, a first gate electrode, a second gate electrode, a first source region and a first drain region, a second source region and a second drain region, and an intermediate insulating layer. , a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode. The first gate electrode is stacked on the central portion of the first semiconductor layer with the first gate insulating film interposed therebetween. The second gate electrode is stacked on the central portion of the second semiconductor layer with the second gate insulating film interposed therebetween. A first source region and a first drain region are stacked on both sides of the central portion of the first semiconductor layer and include an oxide semiconductor material. The intermediate insulating film covers the first semiconductor layer, the second semiconductor layer, the first gate electrode, and the second gate electrode. And the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the intermediate insulating layer.

Description

Thin Film Transistor Substrate And Display Using The Same

The present invention relates to a thin film transistor substrate in which different types of thin film transistors are disposed on the same substrate and a display device using the same.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. The display device field has rapidly changed to a thin, light, and large-area Flat Panel Display Device (FPD) that replaces a bulky cathode ray tube (CRT). Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device. : ED), etc.

In the case of a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device that are actively driven, a thin film transistor substrate is included in which thin film transistors allocated in pixel regions arranged in a matrix manner are disposed. A liquid crystal display device (LCD) displays an image by adjusting the light transmittance of liquid crystal using an electric field. An organic light emitting display device displays an image by forming an organic light emitting element in pixels arranged in a matrix manner.

The organic light emitting diode display is a self-luminous device that emits light by itself, and has advantages in that the response speed is fast and the luminous efficiency, luminance, and viewing angle are large. In particular, in an organic light emitting diode display (OLED) using the characteristics of an organic light emitting diode with excellent energy efficiency, a passive matrix type organic light emitting diode display (PMOLED) and It is roughly classified into an active matrix type organic light emitting diode display (AMOLED).

As personal electronic devices are actively developed, display devices are also being developed as products with excellent portability and/or wearability. As such, in order to be applied to a portable or wearable device, a display device with low power consumption is required. There is a limit in realizing low power consumption with the technologies related to display devices developed so far.

An object of the present invention is to provide a thin film transistor substrate having two or more types of thin film transistors on the same substrate and a display device using the same, as the invention was devised to solve the problems of the prior art. Another object of the present invention is to provide a thin film transistor substrate in which two or more types of thin film transistors are formed through an optimized manufacturing process and a minimized mask process, and a display device using the same.

In order to achieve the above object, a display device according to the present invention includes a first semiconductor layer, a second semiconductor layer, a first gate electrode, a second gate electrode, a first source region and a first drain region, a second source region, and It includes a second drain region, an intermediate insulating layer, a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode. The first semiconductor layer includes a polycrystalline semiconductor material. The second semiconductor layer includes an oxide semiconductor material. The first gate electrode is stacked on the central portion of the first semiconductor layer with the first gate insulating film interposed therebetween. The second gate electrode is stacked on the central portion of the second semiconductor layer with the second gate insulating film interposed therebetween. A first source region and a first drain region are stacked on both sides of the central portion of the first semiconductor layer and include an oxide semiconductor material. A second source region and a second drain region are defined on both sides of the second semiconductor layer central portion. The intermediate insulating film covers the first semiconductor layer, the second semiconductor layer, the first gate electrode, and the second gate electrode. And the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the intermediate insulating layer.

For example, the first semiconductor layer, the first gate electrode, the first source region, the first drain region, the first source electrode, and the first drain electrode are included in the first thin film transistor. The second semiconductor layer, the second gate electrode, the second source region, the second drain region, the second source electrode, and the second drain electrode are included in the second thin film transistor.

In one example, it further includes a driving circuit. At least one of the first thin film transistor and the second thin film transistor is included in the pixel. At least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.

In one example, the driving circuit includes a driving unit, a multiplexer, and a gate driving unit. The data driver outputs a data voltage. The multiplexer distributes the data voltage from the data driver to the data lines. The gate driver outputs a scan pulse to the gate wiring. And at least one of the first thin film transistor and the second thin film transistor is included in any one of the multiplexer and the gate driver.

For example, the second thin film transistor is a switching element for selecting a pixel. The first thin film transistor is a driving element for driving the pixel selected by the second thin film transistor.

For example, the first source electrode passes through the intermediate insulating layer and contacts the first source region. The first drain electrode penetrates the intermediate insulating film and contacts the first drain region. The second source electrode penetrates the intermediate insulating film and contacts the second source region. The second drain electrode penetrates the intermediate insulating film and contacts the second drain region.

For example, the first gate insulating layer and the second gate insulating layer form one thin film layer including a material in the same layer. The first semiconductor layer and the second semiconductor layer are disposed over the same layer.

In one example, the first semiconductor layer is disposed under the first gate insulating film. A second semiconductor layer is disposed over the first gate insulating film. The first source region penetrates the first gate insulating layer and contacts one side of the first semiconductor layer. The first drain region penetrates the first gate insulating film and contacts the other side of the first semiconductor layer.

The thin film transistor substrate and the display device using the same according to the present invention may have a feature that the other thin film transistors compensate for the disadvantages of one thin film transistor by forming two different types of thin film transistors on the same substrate. In particular, by providing a thin film transistor having a low off-current characteristic, a display device suitable for portable and/or wearable devices can be provided by realizing low-speed driving and reducing power consumption.

1 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention.
2 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to the first embodiment of the present invention.
3 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.
4 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.
5 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a third embodiment of the present invention.
6 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a third embodiment of the present invention.
7 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a third embodiment of the present invention.
8 is a block diagram schematically showing the configuration of a display device according to a first application example of the present invention.
9 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display, which is a type of horizontal electric field type, according to a second application example of the present invention.
FIG. 10 is a cross-sectional view of the thin film transistor substrate shown in FIG. 9 taken along line II';
11 is a plan view showing the structure of one pixel in an active matrix organic light emitting diode display according to a third application example of the present invention;
FIG. 12 is a cross-sectional view showing the structure of an active matrix organic light emitting diode display taken along the cut line II-II' in FIG. 11;
13 is an enlarged plan view showing a schematic structure of an organic light emitting diode display device according to a fourth application example of the present invention.
14 is a cross-sectional view showing the structure of an organic light emitting diode display according to a fourth application example of the present invention, taken along the cut line III-III' in FIG. 13;

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of ease of writing the specification, and may be different from the component names of the actual product.

A thin film transistor substrate for a flat panel display according to the present invention includes a first thin film transistor disposed in a first region and a second thin film transistor disposed in a second region on a glass substrate. The substrate may include a display area and a non-display area. In the display area, a plurality of pixel areas are arranged in a matrix manner. Display elements for a display function are disposed in the pixel area. The non-display area is disposed around the display area, and driving elements for driving the display elements formed in the pixel area may be disposed.

Here, the first area may be a part of the non-display area, and the second area may be a part of the display area. In this case, the first thin film transistor and the second thin film transistor may be disposed far apart. Alternatively, both the first area and the second area may be included in the display area. In particular, when a plurality of thin film transistors are included in a single pixel area, the first thin film transistor and the second thin film transistor may be disposed adjacent to each other.

Polycrystalline semiconductor material has high mobility (100 cm2/Vs or more), low energy consumption, and excellent reliability, so it can be applied to a gate driver and/or a multiplexer (MUX) for driving devices that drive thin film transistors for display devices. there is. Alternatively, it is preferable to apply it as a driving thin film transistor in a pixel in an organic light emitting diode display device. Since the oxide semiconductor material has a low off-current, it is suitable for a switching thin film transistor having a short on-time and a long off-time. In addition, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low-speed driving and/or low power consumption. As described above, by simultaneously disposing two different types of thin film transistors on the same substrate, a thin film transistor substrate exhibiting an optimal effect can be obtained.

When the semiconductor layer is formed of a polycrystalline semiconductor material, an impurity implantation process and a high-temperature heat treatment process are required. On the other hand, when the semiconductor layer is formed of an oxide semiconductor material, the process is performed at a relatively low temperature. Therefore, it is preferable to first form the polycrystalline semiconductor layer, which is subjected to the process under severe conditions, and then form the oxide semiconductor layer later. In addition, in order to simplify the manufacturing process, it is preferable that both the first thin film transistor including the polycrystalline semiconductor layer and the second thin film transistor including the oxide semiconductor layer have the same structure. For example, it is preferable that the first gate electrode and the second gate electrode are formed of the same metal material on the same layer, and the first source-drain electrode and the second source-drain electrode are also formed of the same metal material on the same layer. . In particular, in order to secure the characteristics of the semiconductor device, it is preferable to form a top-gate structure capable of accurately defining a channel region.

In the following description, for convenience, the first thin film transistor is a thin film transistor for a driving element formed in the non-display area, and the second thin film transistor is a thin film transistor for a display element disposed in a pixel area of the display area. However, the present invention is not limited thereto, and in the case of an organic light emitting diode display, both the first thin film transistor and the second thin film transistor may be disposed in the pixel area of the display area. In particular, the first thin film transistor including the polycrystalline semiconductor material may be applied to the driving thin film transistor, and the second thin film transistor including the oxide semiconductor material may be applied to the switching thin film transistor.

In addition, when the gate driving device is formed in the non-display area, it may be implemented as a C-MOS type thin film transistor including a polycrystalline semiconductor layer. That is, both the P-MOS type and N-MOS type thin film transistors including the polycrystalline semiconductor layer are formed in the gate driver in the non-display area. In this case, the N-MOS type requires a number of mask processes to form a low-density doped region. Here, the N-MOS type thin film transistor including a polycrystalline semiconductor layer may be configured as a heterogeneous thin film transistor in which a thin film transistor including an oxide semiconductor layer is replaced. Then, since the low-density doped region can be excluded, there is an advantage in that the number of mask processes can be reduced.

<First embodiment>

A first embodiment of the present invention will be described with reference to FIG. 1 . 1 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention. Here, the present invention will be mainly described with a cross-sectional view that can clearly show the characteristics of the invention, and for convenience, a plan view structure is not shown in drawings.

Referring to FIG. 1 , a thin film transistor substrate for a flat panel display according to a first embodiment of the present invention includes a first thin film transistor T1 and a second thin film transistor T2 disposed on a substrate SUB. The first and second thin film transistors T1 and T2 may be disposed to be spaced apart or disposed adjacent to each other. Alternatively, two thin film transistors may be overlapped.

A buffer layer BUF is stacked on the entire surface of the substrate SUB. In some cases, the buffer layer BUF may be omitted. Alternatively, the buffer layer BUF may have a structure in which a plurality of thin film layers are stacked. Here, for convenience, it is described as a single layer. In addition, a light blocking layer may be selectively further provided only in a necessary portion between the buffer layer BUF and the substrate SUB. The light blocking layer may be formed for the purpose of preventing external light from being introduced into the semiconductor layer of the thin film transistor disposed thereon.

A first semiconductor layer is disposed on the buffer layer BUF in a region where the first thin film transistor T1 is disposed. When the first thin film transistor T1 is a thin film transistor for a driving element, it is preferable to have characteristics suitable for performing high-speed driving processing. For example, a P-MOS or N-MOS type thin film transistor including a polycrystalline semiconductor material may be used, or a C-MOS type thin film transistor including both may be provided. The first semiconductor layer includes a first channel region A1 constituting the first thin film transistor T1 . The first channel region A1 is defined as a region where the first gate electrode G1 and the first semiconductor layer overlap. Since the first gate electrode G1 overlaps the central portion of the first semiconductor layer, the central portion of the first semiconductor layer becomes the first channel region A1 .

In addition, on the buffer layer BUF, which is the same layer as the first semiconductor layer, a second semiconductor layer is disposed in a region where the second thin film transistor T2 is disposed. The second semiconductor layer includes an oxide semiconductor material. Examples include oxide semiconductor materials such as Indium Gallium Zinc Oxide (IGZO), Indium Gallium Oxide (IGO) and Indium Zinc Oxide (IZO). it is preferable The oxide semiconductor material has a low off-current characteristic, and thus a voltage holding period of a pixel is long, so it is suitable for a display device requiring low-speed driving and low power consumption.

The second semiconductor layer includes a second channel region A2 constituting the second thin film transistor T2 . The second channel region A2 is defined as a region where the second gate electrode G2 and the second semiconductor layer overlap. Since the second gate electrode G2 overlaps the central portion of the second semiconductor layer, the central portion of the second semiconductor layer becomes the second channel region A2 .

The first semiconductor layer comprises a polycrystalline semiconductor material and the second semiconductor layer comprises an oxide semiconductor material. The process of forming the polycrystalline semiconductor layer requires a high-temperature process compared to the process of forming the oxide semiconductor layer. Therefore, the polycrystalline semiconductor layer is formed first, and then the oxide semiconductor layer is formed later. Both side portions of the second channel region A2 , which are the central portion of the oxide semiconductor layer, are conductive regions, and are defined as a second source region SA2 and a second drain region DA2 . Using this process feature, a first source region SA1 and a first drain region DA1 made of a conductive oxide semiconductor material are stacked on upper surfaces of both sides of the polycrystalline semiconductor layer.

The first gate electrode G1 and the second gate electrode G2 overlap each of the first channel region A1 and the second channel region A2 with the gate insulating layer GI interposed therebetween. An intermediate insulating layer ILD covers the entire substrate SUB on the first gate electrode G1 and the second gate electrode G2 . A first source electrode S1 , a first drain electrode D1 , and a second source electrode S2 and a second drain electrode D2 are disposed on the intermediate insulating layer ILD.

The first source electrode S1 and the second drain electrode D1 contact the first source region SA1 and the first drain region DA1 made of an oxide semiconductor material stacked on a polycrystalline semiconductor material, respectively. The second source electrode S2 and the second drain electrode D2 contact the second source area SA2 and the second drain area DA2 made of a polycrystalline semiconductor material, respectively. Accordingly, the first thin film transistor T1 and the second thin film transistor T2 are completed.

A passivation layer PAS is stacked on the first thin film transistor T1 and the second thin film transistor T2 to cover the entire substrate SUB. When the heterogeneous thin film transistors made of different materials having different characteristics are formed on the same substrate, the polycrystalline semiconductor material is first formed and the oxide semiconductor material is formed later, thereby securing the respective characteristics of the device. By separating and forming the semiconductor layers in this separate process, heterogeneous thin film transistors can be formed with the same structure. Accordingly, many components of the first thin film transistor T1 and the second thin film transistor T2 may be formed on the same layer and with the same material.

Hereinafter, a method of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention will be described with further reference to FIG. 2 . 2 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to the first embodiment of the present invention.

A buffer layer BUF is deposited on the substrate SUB. Although not illustrated in the drawings, a light blocking layer may be formed in a necessary portion before depositing the buffer layer BUF. (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer BUF, and crystallization is performed to make poly-silicon. A first semiconductor layer is formed by patterning the polycrystalline silicon material in a first mask process. If necessary, a hydrogenation process may be performed to fill voids that may exist in the polycrystalline semiconductor material with hydrogen particles to stabilize and improve device characteristics. (S110)

A metal oxide semiconductor material is deposited on the buffer layer BUF on which the first semiconductor layer is formed, and patterned by a second mask process to form a second semiconductor layer. At this time, a second semiconductor layer is also laminated on the surfaces of both sides of the first channel region A1 in the first semiconductor layer. (S200)

A gate insulating layer GI is deposited as an insulating material on the substrate SUB on which the first semiconductor layer and the second semiconductor layer are formed. Here, the gate insulating layer GI is preferably formed of silicon oxide. The thickness of the gate insulating layer GI is preferably 1,000 Å to 2,000 Å. (S300)

A gate metal material is deposited on the gate insulating layer GI and patterned by a third mask process to form a gate electrode. In particular, the first gate electrode G1 and the second gate electrode G2 are simultaneously formed. The first gate electrode G1 is disposed to overlap the first channel region A1, which is a central region of the first semiconductor layer. The second gate electrode G2 is disposed to overlap the second channel region A2 that is the central region of the second semiconductor layer. In the mask process of forming the first gate electrode G1 and the second gate electrode G2 , the gate insulating layer GI disposed thereunder is also etched in the same shape as the gate electrodes G1 and G2 . In this process, a second semiconductor layer stacked on top of the first semiconductor layer exposed to both sides of the first gate electrode G1 is made conductive so that the first source area SA1 and the first drain area DA1 are formed. is defined Similarly, the second semiconductor layer exposed on both sides of the second gate electrode G2 is made into a conductor to define a second source area SA2 and a second drain area DA2 . (S310)

An intermediate insulating layer ILD is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 and the second gate electrode G2 are formed. The intermediate insulating layer ILD may include a nitride layer and/or an oxide layer. Considering the manufacturing process, it is preferable to deposit the intermediate insulating layer ILD to have a total thickness of 2,000 Å to 6,000 Å. (S400)

A contact hole exposing the first source area SA1 and the first drain area DA1 and the second source area SA2 and the second drain area DA2 by patterning the intermediate insulating layer ILD by a fourth mask process form them These contact holes are for connecting a source-drain electrode to be formed later with the source-drain regions. (S410)

A source-drain metal is deposited on the intermediate insulating layer ILD in which the contact holes are formed. A first source electrode S1 , a first drain electrode D1 , and a second source electrode S2 and a second drain electrode D2 are formed by patterning the source-drain metal using a fifth mask process. The first source electrode S1 is in contact with the first source area SA1. The first drain electrode D1 contacts the first drain area DA1. The second source electrode S2 contacts the second source region SA2 , and the second drain electrode D2 contacts the second drain region DA2 . (S500)

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the source-drain electrodes are formed. Although not illustrated, a contact hole exposing a portion of the first and second drain electrodes D1 and D2 may be further formed by patterning the passivation layer PAS later. (S600)

In the first embodiment, the first gate electrode G1 and the second gate electrode G2 are formed on the same layer using the same material. In the process of patterning the first gate electrode G1 and the second gate electrode G2, an oxide semiconductor material is made a conductor to define a channel region. In the case of a polycrystalline semiconductor layer, a doping process defines a channel region. However, in the first embodiment, without applying a doping process, an oxide semiconductor material is stacked on the polycrystalline semiconductor layer, and then the oxide semiconductor material is made into a conductor to define a channel region. Accordingly, the first gate electrode G1 and the second gate electrode G2 may be formed on the same layer using the same material.

<Second embodiment>

Hereinafter, a second embodiment of the present invention will be described with reference to FIG. 3 . 3 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.

In the first embodiment, a conductive oxide semiconductor layer is disposed on both sides of the channel region of the polycrystalline semiconductor layer to define the channel region. That is, the polycrystalline semiconductor layer has a structure in which a doped region does not exist. Accordingly, a resistance problem may occur in the connection structure between the source-drain electrode and the polycrystalline semiconductor layer.

In the second embodiment, a structure of a thin film transistor substrate including heterogeneous thin film transistors that can further solve the disadvantages that may occur in the first embodiment is proposed. Referring to FIG. 3 , a thin film transistor substrate for a flat panel display according to a second embodiment of the present invention includes a first thin film transistor T1 and a second thin film transistor T2 disposed on a substrate SUB. The first and second thin film transistors T1 and T2 may be disposed to be spaced apart or disposed adjacent to each other. Alternatively, two thin film transistors may be overlapped.

In the second embodiment, the first thin film transistor T1 is formed first, and the second thin film transistor T2 is formed later. In this case, in order to simplify the manufacturing process, the source-drain electrodes are used in the same layer and of the same material. In particular, since the first thin film transistor T1 has a structure in which the step difference is severely separated from the second thin film transistor T2 , the source-drain electrode may not be smoothly connected in the first thin film transistor T1 . In order to prevent this, by connecting the conductive semiconductor material layer of the second thin film transistor in the middle, an ohmic contact is secured.

A buffer layer BUF is stacked on the entire surface of the substrate SUB. The buffer layer BUF may be formed in the same manner as in the first embodiment. As such, detailed descriptions of the same components as those of the previous embodiment will be omitted.

A first semiconductor layer is disposed on the buffer layer BUF. The first semiconductor layer includes a first channel region A1 constituting the first thin film transistor T1 . The first channel region A1 is defined as a region where the first gate electrode G1 and the first semiconductor layer overlap. Since the first gate electrode G1 overlaps the central portion of the first semiconductor layer, the central portion of the first semiconductor layer becomes the first channel region A1 . Both sides of the first channel region A1 are doped with impurities, and are defined as a first source region SA1 and a first drain region DA1.

A first gate insulating layer GI1 is stacked on the entire surface of the substrate SUB on which the first semiconductor layer is disposed. The first gate insulating layer GI1 is preferably formed of silicon oxide (SiOx). In the case of the first gate insulating layer GI1, it is preferable to have a thickness of about 1,000 Å to 2,000 Å in consideration of device stability and characteristics.

A first gate electrode G1 is disposed on the first gate insulating layer GI1 . The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer. A region overlapping the first gate electrode G1 in the first semiconductor layer is defined as a first channel region A1 by doping the impurities using the first gate electrode G1 as a mask. Both sides doped with impurities are defined as a first source area SA1 and a first drain area DA1, respectively.

A first intermediate insulating layer ILD1 is stacked to cover the first gate electrode G1 . The first intermediate insulating layer ILD1 may have a multilayer structure in which a nitride layer including silicon nitride (SiNx) and an oxide layer including silicon oxide (SiOx) are alternately stacked. In particular, since the nitride film is preferably disposed close to the polycrystalline semiconductor layer, it is preferable that the nitride film is laminated on the lower layer and the oxide film is stacked on the upper layer. The nitride film is for performing hydrogenation treatment of the first semiconductor layer including polycrystalline silicon by diffusing hydrogen contained therein through a subsequent heat treatment process. On the other hand, the oxide film is to prevent too much diffusion of hydrogen emitted from the nitride film by a subsequent heat treatment process into the oxide semiconductor material of the second thin film transistor T2.

Considering the manufacturing process, it is preferable that the total thickness of the first intermediate insulating layer ILD1 has a thickness of 2,000 Å to 6,000 Å. Therefore, the thickness of each of the nitride film and the oxide film is preferably 1,000 Å to 3,000 Å. In addition, in order for hydrogen in the nitride film to diffuse to the first semiconductor layer and to have as little influence as possible to the second semiconductor layer, the oxide film is preferably thicker than the gate insulating film GI. In particular, the oxide film is used to control the diffusion degree of hydrogen emitted from the nitride film, and the oxide film is preferably thicker than the nitride film.

A second semiconductor layer is disposed on the first intermediate insulating layer ILD1 . The second semiconductor layer includes a second channel region A2 constituting the second thin film transistor T2 . When the second thin film transistor T2 is a thin film transistor for a display device, it is preferable to include an oxide semiconductor material to have properties suitable for performing display function processing.

Made of the same material as the second semiconductor layer, a first sub-source region SA1 ′ and a first sub-drain region connected to the first source region SA1 and the first drain region DA1 of the first semiconductor layer ( DA1') is further formed. The first sub-source region SA1 ′ is connected through a contact hole penetrating the first intermediate insulating layer ILD1 and the first gate insulating layer GI1 to expose the first source region SA1 . The first sub-drain region DA1 ′ is connected through a contact hole penetrating the first intermediate insulating layer ILD1 and the first gate insulating layer GI1 to expose the first drain region DA1 .

The second semiconductor layer includes a second channel region A2 constituting the second thin film transistor T2 . The second channel region A2 is defined as a region where the second gate electrode G2 and the second semiconductor layer overlap. Since the second gate electrode G2 overlaps the central portion of the second semiconductor layer, the central portion of the second semiconductor layer becomes the second channel region A2 . Both side portions of the second channel area A2 are conductive areas, and are defined as a second source area SA2 and a second drain area DA2 .

The second gate electrode G2 overlaps the second channel region A2 with the second gate insulating layer GI2 interposed therebetween. In particular, the second gate insulating layer GI2 is patterned to have the same shape and size as the second gate electrode G2 . As a result, portions of the second semiconductor layer that do not overlap the second gate electrode G2 are conductive. For example, the second source region SA2 , the second drain region DA2 , the first sub-source region SA1 ′, and the first sub-drain region DA1 ′ include a conductive oxide semiconductor material. .

A second intermediate insulating layer ILD2 is stacked on the second gate electrode G2 to cover the entire surface of the substrate SUB. Source-drain electrodes are formed on the upper surface of the second intermediate insulating layer ILD2 . For example, the first source electrode S1 and the first drain electrode D1 constituting the first thin film transistor T1 and the second source electrode S2 and the second constituting the second thin film transistor T2 are A drain electrode D2 is formed. The first source electrode S1 is connected to the first sub-source area SA1', and the first drain electrode D1 is connected to the first sub-drain area DA1'. In addition, the second source electrode S2 is connected to the second source region SA2 , and the second drain electrode D2 is connected to the second drain region DA2 .

A passivation layer PAS is stacked on the source-drain electrodes to cover the entire substrate SUB. When the heterogeneous thin film transistors made of different materials having different characteristics are formed on the same substrate, the polycrystalline semiconductor material is first formed and the oxide semiconductor material is formed later, thereby securing the respective characteristics of the device. Compared with the first embodiment, since the gate electrode is formed on different layers, the manufacturing process may be more complicated. However, since the polycrystalline semiconductor layer and the oxide semiconductor layer have a structure that is further spaced apart, the characteristics of different devices each can be stabilized.

Hereinafter, a method of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention will be described with further reference to FIG. 4 . 4 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.

A buffer layer BUF is deposited on the substrate SUB. Although not illustrated in the drawings, a light blocking layer may be formed in a necessary portion before depositing the buffer layer BUF. (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer BUF, and crystallization is performed to make poly-silicon. A first semiconductor layer is formed by patterning the polycrystalline silicon material in a first mask process. (S110)

A first gate insulating layer GI1 is formed by depositing an insulating material such as silicon oxide on the entire surface of the substrate SUB on which the first semiconductor layer is formed. The first gate insulating layer GI1 is preferably formed of silicon oxide. The thickness of the first gate insulating layer GI1 is preferably 1,000 Å to 2,000 Å. Apply gate metal material in succession. A first gate electrode G1 is formed by patterning the gate metal by a second mask process. The first gate electrode G1 is disposed to overlap the central portion of the first semiconductor layer. Thereafter, a doped region including the first source region SA1 and the first drain region DA1 is defined by implanting impurities into the first semiconductor layer disposed thereunder using the first gate electrode G1 as a mask. .

The definition process of the doped region may be slightly different according to P-MOS, N-MOS, or C-MOS. For example, in the case of an N-MOS type thin film transistor, a high concentration doping region may be formed first, and then a low concentration doped region may be formed later. A heavily doped region may be defined by using the photoresist pattern of the first gate electrode G1 having a size larger than that of the first gate electrode G1 . A low density doping area (LDD) may be defined between the heavily doped region and the first gate electrode G1 by removing the photoresist and using the first gate electrode G1 as a mask. In addition, a C-MOS thin film transistor in which the first thin film transistor T1 is a P-MOS type thin film transistor and the second thin film transistor T2 is an N-MOS type thin film transistor may be implemented. (S200)

A first intermediate insulating layer ILD1 is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 is formed. When forming the first intermediate insulating layer ILD1 as a double layer, it is preferable to first deposit a nitride layer and then sequentially stack an oxide layer. The nitride film may contain a large amount of hydrogen therein during the manufacturing process. Considering the manufacturing process, it is preferable to deposit the first intermediate insulating layer ILD1 to have a total thickness of 2,000 Å to 6,000 Å. Accordingly, the nitride film for the purpose of hydrogen diffusion is deposited to a thickness of 1,000 Å to 3,000 Å in consideration of the degree of hydrogen diffusion. The oxide layer is preferably deposited to a thickness of 1,000 Å to 3,000 Å to prevent diffusion of hydrogen particles emitted from the nitride layer into the oxide semiconductor material to be disposed thereon. The thickness of the oxide film and the nitride film can be appropriately selected in consideration of the degree of hydrogen diffusion and device characteristics. For example, in order to prevent excessive diffusion of hydrogen, the nitride film is preferably thinner than the oxide film.

A contact hole is formed by patterning the first intermediate insulating layer ILD1 and the first gate insulating layer GI1 by a third mask process. In particular, contact holes exposing the first source area SA1 and the first drain area DA1 are formed. (S300)

An oxide semiconductor material is deposited on the first intermediate insulating layer ILD1. The oxide semiconductor material includes at least one of Indium Gallium Zinc Oxide (IGZO), Indium Gallium Oxide (IGO), and Indium Zinc Oxide (IZO). A second semiconductor layer is formed by patterning the oxide semiconductor material by a fourth mask process. In addition, a first sub-source area SA1' connected to the first source area SA1 and a first sub-drain area DA1' connected to the first drain area DA1 are further formed through the contact hole. do. (S400)

A second gate insulating layer GI2 is deposited as an insulating material on the entire surface of the substrate SUB on which the second semiconductor layer is formed. The second gate insulating layer GI2 may also be formed of the same material as the first gate insulating layer GI1 and have the same thickness. (S500)

A gate material is continuously applied on the second gate insulating layer GI2. A second gate electrode G2 is formed by simultaneously patterning the gate material and the second gate insulating layer GI2 by a fifth mask process. At this time, as the second gate insulating layer GI2 is etched, a portion of the second semiconductor layer is exposed and becomes a conductor. That is, the second source area SA2 and the second drain area DA2 exposed on both sides of the second gate electrode G2 are conductive. Similarly, the first sub-source area SA1' and the first sub-drain area DA1' are also conductive. (S510)

A second intermediate insulating layer ILD2 is deposited as an insulating material on the entire surface of the substrate SUB on which the second gate electrode G2 is formed. The second intermediate insulating layer ILD2 is patterned by a sixth mask process to form contact holes. For example, the contact holes may include a conductive second source area SA2 and a second drain area DA2, and a first conductive sub-source area SA1' and a first sub-drain area DA1'. to expose (S600)

A metal material is deposited on the second intermediate insulating layer ILD2 and patterned by a seventh mask process to form source-drain electrodes. For example, a first source electrode S1 , a first drain electrode D1 , a second source electrode S2 , and a second drain electrode D2 are formed. The first source electrode S1 is connected to the first sub-source area SA1' through a contact hole. The first drain electrode D1 is connected to the first sub-drain area DA1' through a contact hole. The second source electrode S2 is connected to the second source area SA2 through a contact hole. In addition, the second drain electrode D2 is connected to the second drain region DA2 through a contact hole. (S700)

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the source-drain electrodes are formed. Although not illustrated, a contact hole exposing a portion of the first and second drain electrodes D1 and D2 may be further formed by patterning the passivation layer PAS later. (S800)

<Third embodiment>

Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 5 . 5 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a third embodiment of the present invention.

The third embodiment of the present invention is substantially the same as the first embodiment in consideration of both structural features and manufacturing processes. If there is a difference, in the first embodiment, the channel region is defined by the conducting process, whereas in the third embodiment, the channel region is defined by the doping process. In the case of the third embodiment, it can be advantageously applied when two different types of thin film transistors have a structure in which they are directly connected.

Referring to FIG. 5 , a buffer layer BUF is coated on a substrate SUB. A first semiconductor layer including a polycrystalline semiconductor material is coated on the buffer layer BUF. The first semiconductor layer is formed in both the region where the first thin film transistor T1 is disposed and the region where the second thin film transistor T2 is disposed. In the first thin film transistor T1 , the first semiconductor layer is not formed in the channel region, whereas in the second thin film transistor T2 , the channel region is included. This is because the first thin film transistor T1 forms a channel region with a polycrystalline semiconductor material, while the second thin film transistor T2 forms a channel region with an oxide semiconductor material.

Accordingly, a second semiconductor layer including an oxide semiconductor material is disposed between the first semiconductor layers formed in the region where the second thin film transistor T2 is disposed and separated from both sides. In particular, both sides of the second semiconductor layer are preferably connected by being stacked with the first semiconductor layer.

A gate insulating layer GI is stacked over the entire surface of the substrate SUB on the first semiconductor layer and the second semiconductor layer. A first gate electrode G1 and a second gate electrode G2 are formed on the gate insulating layer GI. The first gate electrode G1 is disposed to overlap the central region of the first semiconductor layer formed in the region where the first thin film transistor T1 is disposed. The second gate electrode G2 is disposed to overlap a central region of the second semiconductor layer in which the second thin film transistor T2 is disposed.

The first gate electrode G1 overlaps the first channel region A1 with the gate insulating layer GI interposed therebetween. A first source area SA1 and a first drain area DA1 doped with impurities are defined on both sides of the first channel area A1 . The second gate electrode G2 also overlaps the second channel region A2 with the gate insulating layer GI interposed therebetween. Both side portions of the second channel region A2 are in surface contact with the first semiconductor layer. In addition, both sides of the second channel region A2 and the first semiconductor layer are also doped with impurities to define a second source region SA2 and a second drain region DA2 .

An intermediate insulating layer ILD is deposited on the first gate electrode G1 and the second gate electrode G2 to cover the entire substrate SUB. A first source electrode S1 constituting the first thin film transistor T1 and a second drain electrode D2 constituting the second thin film transistor T2 are disposed on the intermediate insulating layer ILD. The first source electrode S1 is connected to the first source region SA1 through a contact hole passing through the intermediate insulating layer ILD and the gate insulating layer GI. The second drain electrode D2 is connected to the second drain region DA2 through a contact hole passing through the intermediate insulating layer ILD and the gate insulating layer GI.

Here, the first drain region DA1 of the first thin film transistor T1 and the second source region SA2 of the second thin film transistor T2 are formed as a single body, thereby forming a structure in which the two thin film transistors are connected in series. have Accordingly, there is a structure in which it is not necessary to form the first drain electrode and the first source electrode.

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the first thin film transistor T1 and the second thin film transistor T2 are formed.

Hereinafter, a process of manufacturing the thin film transistor substrate for a flat panel display according to the third embodiment will be described with reference to FIG. 6 . Here too, since it is almost the same as that of the first embodiment, the same description without an important meaning is omitted. 6 is a flowchart illustrating a process of manufacturing a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a third embodiment of the present invention.

A buffer layer BUF is deposited on the substrate SUB. (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer BUF, and crystallization is performed to make poly-silicon. A first semiconductor layer is formed by patterning the polycrystalline silicon material in a first mask process. The first semiconductor layer includes a first channel region A1 constituting the first thin film transistor T1 . Also, the first semiconductor layer includes a doped region of the second thin film transistor T2. (S110)

A metal oxide semiconductor material is deposited on the buffer layer BUF on which the first semiconductor layer is formed, and patterned by a second mask process to form a second semiconductor layer. The second semiconductor layer includes a channel region of the second thin film transistor T2. In particular, the first semiconductor layers disposed in the region of the second thin film transistor T2 and spaced apart from each other on both sides of the channel region are formed to be connected to each other. (S200)

A gate insulating layer GI is deposited as an insulating material on the substrate SUB on which the first semiconductor layer and the second semiconductor layer are formed. (S300)

A gate metal material is deposited on the gate insulating layer GI and patterned by a third mask process to form a gate electrode. In particular, the first gate electrode G1 and the second gate electrode G2 are simultaneously formed. The first gate electrode G1 is disposed to overlap the first channel region A1, which is a central region of the first semiconductor layer. The second gate electrode G2 is disposed to overlap the second channel region A2 that is the central region of the second semiconductor layer. Using the first gate electrode G1 and the second gate electrode G2 as a mask, impurities are doped into the lower first semiconductor layer and the second semiconductor layer. Accordingly, in the first semiconductor layer exposed to both sides of the first gate electrode G1 , a first source region SA1 and a first drain region DA1 that are doped with impurities are defined. Similarly, the second semiconductor layer and the first semiconductor layer exposed to both sides of the second gate electrode G2 are also doped with impurities to define a second source region SA2 and a second drain region DA2 . (S310)

An intermediate insulating layer ILD is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 and the second gate electrode G2 are formed. (S400)

Contact holes exposing the first source area SA1 and the second drain area DA2 are formed by patterning the intermediate insulating layer ILD by a fourth mask process. These contact holes are for connecting a source-drain electrode to be formed later with the source-drain regions. (S410)

A source-drain metal is deposited on the intermediate insulating layer ILD in which the contact holes are formed. A first source electrode S1 and a second drain electrode D2 are formed by patterning the source-drain metal by a fifth mask process. The first source electrode S1 is in contact with the first source area SA1. The second drain electrode D2 contacts the second drain area DA2. (S500)

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the source-drain electrodes are formed. Although not illustrated, a contact hole exposing a portion of the second drain electrode D2 may be further formed by patterning the passivation layer PAS later. (S600)

A third embodiment of the present invention provides a thin film transistor substrate including two different thin film transistors and having a structure in which they are connected to each other. In particular, the first thin film transistor T1 including the polycrystalline semiconductor material and the second thin film transistor T2 including the oxide semiconductor material have a structure connected to each other in series. For example, in a liquid crystal display, when it is necessary to significantly reduce the off-current Ioff, an oxide semiconductor material having a low off-current Ioff may be applied to the second thin film transistor T2.

Alternatively, the method may be applied to a case in which the gate driver is directly formed around the pixel area of the display panel. For example, a C-MOS type may be formed by directly connecting a P-MOS thin film transistor including a polycrystalline semiconductor material and an N-MOS thin film transistor including an oxide semiconductor material.

<Fourth embodiment>

Hereinafter, a fourth embodiment of the present invention will be described with reference to FIG. 7 . 7 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a fourth embodiment of the present invention.

The fourth embodiment presents a structure slightly different from that of a thin film transistor including different thin film transistors. For example, when connecting two identical thin film transistors, the characteristics may be improved by connecting them via semiconductor materials having different characteristics. For example, when two thin film transistors including a polycrystalline semiconductor material are connected in series, the off-current (Ioff) characteristic may be improved by interposing an oxide semiconductor material in the middle.

The fourth embodiment of the present invention is substantially the same as the third embodiment in consideration of both the structural features and the manufacturing process. The difference lies in that in the third embodiment, different types of thin film transistors are connected in series with each other, whereas in the fourth embodiment, thin film transistors of the same type are connected via a semiconductor material having different characteristics.

Referring to FIG. 7 , a buffer layer BUF is coated on a substrate SUB. A first semiconductor layer including a polycrystalline semiconductor material is coated on the buffer layer BUF. The first semiconductor layer is formed in both the region where the first thin film transistor T1 is disposed and the region where the second thin film transistor T2 is disposed.

Both the first thin film transistor T1 and the second thin film transistor T2 form a channel region using a polycrystalline semiconductor material. Accordingly, the first semiconductor layer is disposed to include a channel region of each of the first thin film transistor T1 and the second thin film transistor T2 .

A second semiconductor layer OX including an oxide semiconductor material is formed on the substrate SUB on which the first semiconductor layer is formed. In particular, it has a structure connecting the first semiconductor layer disposed on the first thin film transistor T1 and the first semiconductor layer disposed on the second thin film transistor T2 .

A gate insulating layer GI is stacked over the entire surface of the substrate SUB on the first semiconductor layer and the second semiconductor layer. A first gate electrode G1 and a second gate electrode G2 are formed on the gate insulating layer GI. The first gate electrode G1 is disposed to overlap the central region of the first semiconductor layer formed in the region where the first thin film transistor T1 is disposed. The second gate electrode G2 is disposed to overlap the central region of the first semiconductor layer formed in the region where the second thin film transistor T2 is disposed.

The first gate electrode G1 and the second gate electrode G2 respectively overlap the first channel region A1 and the second channel region A2 with the gate insulating layer GI interposed therebetween. A first source area SA1 and a first drain area DA1 doped with impurities are defined on both sides of the first channel area A1 . A second source area SA2 and a second drain area DA2 that are also doped with impurities are defined on both sides of the second channel area A2 . The first drain area DA1 and the second source area SA2 are connected by the second semiconductor layer OX. The second semiconductor layer OX is also doped with impurities.

An intermediate insulating layer ILD is deposited on the first gate electrode G1 and the second gate electrode G2 to cover the entire substrate SUB. A first source electrode S1 constituting the first thin film transistor T1 and a second drain electrode D2 constituting the second thin film transistor T2 are disposed on the intermediate insulating layer ILD. The first source electrode S1 is connected to the first source region SA1 through a contact hole passing through the intermediate insulating layer ILD and the gate insulating layer GI. The second drain electrode D2 is connected to the second drain region DA2 through a contact hole passing through the intermediate insulating layer ILD and the gate insulating layer GI.

Here, the first drain region DA1 of the first thin film transistor T1 has a structure connected in series with the second source region SA2 of the second thin film transistor T2 via the oxide semiconductor layer OX. Accordingly, there is a structure in which it is not necessary to form the first drain electrode and the first source electrode.

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the first thin film transistor T1 and the second thin film transistor T2 are formed. Since the manufacturing process is the same as that of the third embodiment, a description of the process is omitted.

< 1st application example >

The thin film transistor substrate having the different thin film transistors described so far can be applied to various flat panel display devices. As suggested in the present invention, advantages that can be obtained when thin film transistors having different characteristics are formed on a single substrate are diverse. Hereinafter, with reference to FIG. 8 , the characteristics of the display device using the thin film transistor substrate according to the first application example of the present invention and what advantages can be expected will be described in detail. 8 is a block diagram schematically showing the configuration of a display device according to a first application example of the present invention.

One or more of the first and second thin film transistors T1 and T2 may be thin film transistors formed in each of the pixels of the display panel 100 to switch data voltages written to the pixels or to drive the pixels. In the case of an organic light emitting diode display, the second thin film transistor T2 may be applied as a switch element of a pixel, and the first thin film transistor T1 may be applied as a driving element, but is not limited thereto. The first and second thin film transistors T1 and T2 may be combined and applied as one switch element or one driving element.

In order to reduce power consumption in a mobile device or a wearable device, a low-speed driving method of lowering a frame rate has been attempted. In this case, the frame frequency of a still image or an image having a late data update period may be lowered. However, if the frame rate is lowered, a phenomenon in which the luminance flickers whenever the data voltage is changed, or a flicker phenomenon in which the luminance flickers at the data update cycle due to a prolonged voltage discharge time of the pixel may be seen. When the first and second thin film transistors T1 and T2 of the present invention are applied to the pixel, the flicker problem during low-speed driving can be solved.

When the data update period is long during low-speed driving, the amount of leakage current of the switch thin film transistor increases. The leakage current of the switch thin film transistor causes a drop in the voltage of the storage capacitor STG and the gate-source voltage of the driving thin film transistor. In the present invention, the second thin film transistor, which is an oxide transistor, can be applied as a switch thin film transistor of a pixel. Since the oxide transistor has a low off-current, a voltage drop between the storage capacitor and the gate electrode of the driving thin film transistor can be prevented. Accordingly, the present invention can prevent flicker when driving at a low speed.

When the first thin film transistor, which is a polysilicon transistor, is applied as a driving thin film transistor of a pixel, the amount of current supplied to the organic light emitting diode can be increased because electron mobility is high. Accordingly, according to the present invention, by applying the second thin film transistor T2 to the switch element of the pixel and the first thin film transistor T1 to the driving element of the pixel, power consumption can be significantly reduced and image quality deterioration can be prevented.

The present invention is effective for application to a mobile device or a wearable device because image quality deterioration can be prevented when a low-speed driving method is applied to reduce power consumption. For example, the portable electronic watch may update data on the display screen in units of 1 second to reduce power consumption. The frame frequency at this time is 1 Hz. According to the present invention, excellent image quality without flicker can be realized even using a driving frequency close to 1 Hz or a still image. The present invention can significantly reduce power consumption without degrading image quality by significantly lowering the frame rate of a still image on a standby screen of a mobile device or a wearable device. As a result, the present invention can improve portability by improving the picture quality of a mobile device or a wearable device and extending the battery life. According to the present invention, power consumption can be greatly reduced without degradation of image quality even in an E-Book with a very long data update cycle.

At least one of the first and second thin film transistors T1 and T2 is built into a driving circuit, for example, at least one of the data driver 200 , the multiplexer MUX 210 , and the gate driver 300 in FIG. 8 . A driving circuit can be configured. This driving circuit writes data to the pixel. In addition, one of the first and second thin film transistors T1 and T2 may be formed in the pixel and the other may be formed in the driving circuit. The data driver 200 converts the data of the input image into a data voltage and outputs it. The multiplexer 210 reduces the number of output channels of the data driver 200 by time division distribution of the data voltage from the data driver 200 to the plurality of data lines DL. The gate driver 300 outputs a scan signal (or gate signal) synchronized with the data voltage to the gate line GL to sequentially select pixels in which data of the input image is written in line units. In order to reduce the number of output channels of the gate driver 300 , a multiplexer (not shown) may be added between the gate driver 300 and the gate lines GL. The multiplexer 210 and the gate driver 300 may be directly formed on the thin film transistor substrate together with the pixel array as shown in FIG. 8 . The multiplexer 210 and the gate driver 300 are disposed in the non-display area NA as shown in FIG. 8 , and the pixel array is disposed in the display area AA.

The display device of the present invention can be applied to any display device requiring a thin film transistor, such as an active display device using a thin film transistor, for example, a liquid crystal display device, an organic light emitting diode display device, and an electrophoretic display device. Hereinafter, application examples of the display device to which the thin film transistor substrate according to the present invention is applied will be described with further reference to the drawings.

< 2nd application example >

9 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display, which is a type of horizontal electric field type, according to a second application example of the present invention. 10 is a cross-sectional view of the thin film transistor substrate shown in FIG. 9 taken along the perforated line I-I'.

The thin film transistor substrate having the metal oxide semiconductor layer shown in FIGS. 9 and 10 includes a gate line GL and a data line DL crossing a lower substrate SUB with a gate insulating layer GI interposed therebetween, and the intersection thereof. A thin film transistor T formed for each part is provided. In addition, a pixel area is defined by the cross structure of the gate line GL and the data line DL.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S, and a gate A semiconductor layer (A) overlapping the gate electrode (G) on the insulating layer (GI) and having a channel region between the source electrode (S) and the drain electrode (D) is included.

A gate pad GP for receiving a gate signal from the outside is disposed at one end of the gate line GL. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 passing through the gate insulating layer GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 penetrating the first and second passivation layers PA1 and PA2 . Meanwhile, a data pad DP for receiving a pixel signal from the outside is disposed at one end of the data line DL. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH penetrating the first passivation layer PA1 and the second passivation layer PA2 .

In the pixel area, the pixel electrode PXL and the common electrode COM are provided with the second passivation layer PA2 interposed therebetween to form a fringe field. The common electrode COM may be connected to the common line CL arranged in parallel with the gate line GL. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL. As another method, the common electrode COM may have a shape disposed on the entire surface of the substrate SUB except for a portion where the drain contact hole DH is disposed. That is, the common electrode COM may function to shield the data line DL by covering the upper layer of the data line DL.

The positions and shapes of the common electrode COM and the pixel electrode PXL may have various shapes according to a design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that changes frequently according to video data to be implemented is applied to the pixel electrode PXL. Accordingly, a parasitic capacitance may be generated between the data line DL and the pixel electrode PXL. Since such a parasitic capacitance may cause a problem in image quality, it is preferable to arrange the common electrode COM first and the pixel electrode PXL on the uppermost layer.

That is, after forming the planarization layer PAC by thickly stacking an organic material having a low dielectric constant on the first passivation layer PA1 covering the data line DL and the thin film transistor T, the common electrode COM is formed. Then, after the second passivation layer PA2 covering the common electrode COM is formed, the pixel electrode PXL overlapping the common electrode COM is formed on the second passivation layer PA2 . In this structure, since the pixel electrode PXL is spaced apart by the data line DL, the first passivation layer PA1, the planarization layer PAC, and the second passivation layer PA2, the data line DL and the pixel electrode PXL In between, the parasitic capacity can be reduced. However, the present invention is not limited thereto, and in some cases, the pixel electrode PXL may be disposed first, and the common electrode COM may be disposed on the uppermost layer.

The common electrode COM has a rectangular shape corresponding to the shape of the pixel area, and the pixel electrode PXL has a plurality of line segment shapes. In particular, the pixel electrode PXL has a structure that vertically overlaps with the common electrode COM with the second passivation layer PA2 interposed therebetween. Accordingly, a fringe field is formed between the pixel electrode PXL and the common electrode COM. Liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate rotate due to dielectric anisotropy by the fringe field type electric field. In addition, the transmittance of light passing through the pixel region varies according to the degree of rotation of the liquid crystal molecules to realize grayscale.

9 and 10 illustrating the second application example of the present invention, for convenience, the structure of the thin film transistor T in the liquid crystal display is only schematically illustrated. The structures of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, when low-speed driving is required, the second thin film transistor T2 having an oxide semiconductor layer may be applied. When low power consumption is required, the first thin film transistor T1 having a polycrystalline semiconductor layer may be applied. Alternatively, both the first and second thin film transistors T1 and T2 may be provided and configured to be connected to each other to complement each other.

< 3rd application example >

11 is a plan view showing the structure of one pixel in a matrix organic light emitting diode display according to a third application example of the present invention. 12 is a cross-sectional view showing the structure of the active matrix organic light emitting diode display device taken along the cut line II-II' in FIG. 11 .

11 and 12 , the active matrix organic light emitting diode display includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor, and an organic light emitting diode OLE connected to the driving thin film transistor DT. includes

The switching thin film transistor ST is disposed on the substrate SUB at an intersection of the gate line GL and the data line DL. The switching thin film transistor ST has a function of selecting a pixel by supplying a data voltage from the data line DL to the gate electrode DG and the storage capacitor STG of the driving thin film transistor DT in response to a scan signal do The switching thin film transistor ST includes a gate electrode SG branching from the gate line GL, a semiconductor layer SA, a source electrode SS, and a drain electrode SD. In addition, the driving thin film transistor DT drives the organic light emitting diode OLE of the pixel selected by the switching thin film transistor ST by controlling the current flowing through the organic light emitting diode OLE of the pixel according to the gate voltage.

The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor layer DA, a source electrode DS connected to the driving current line VDD, and a drain and an electrode DD. The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE. An organic light emitting layer OL is interposed between the anode electrode ANO and the cathode electrode CAT. The cathode electrode CAT is connected to the base line VSS.

12 , the gate electrodes SG and DG of the switching thin film transistor ST and the driving thin film transistor DT are disposed on the substrate SUB of the active matrix organic light emitting diode display device. there is. In addition, the gate insulating layer GI covers the gate electrodes SG and DG. The semiconductor layers SA and DA are disposed on a portion of the gate insulating layer GI overlapping the gate electrodes SG and DG. On the semiconductor layers SA and DA, the source electrodes SS and DS and the drain electrodes SD and DD are disposed to face each other with a predetermined interval therebetween. The drain electrode SD of the switching thin film transistor ST contacts the gate electrode DG of the driving thin film transistor DT through the drain contact hole DH passing through the gate insulating layer GI. A protective film PAS covering the switching thin film transistor ST and the driving thin film transistor DT having such a structure is stacked on the entire surface.

A color filter CF is disposed in a portion corresponding to the region of the anode electrode ANO. The color filter CF preferably has as wide an area as possible. For example, it is preferable to have a shape overlapping many regions of the data line DL, the driving current line VDD, and the gate line GL of the previous stage. As described above, the surface of the substrate on which the switching thin film transistor ST, the driving thin film transistor DT, and the color filters CF are disposed is not flat and the level difference is severe. The organic light emitting layer OL must be laminated on a flat surface so that light emission can be uniformly and uniformly emitted. Therefore, a planarization film (PAC) or an overcoat layer (OC) is laminated on the entire surface of the substrate for the purpose of flattening the surface of the substrate.

And the anode electrode ANO of the organic light emitting diode OLE is disposed on the overcoat layer OC. Here, the anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the pixel contact hole PH formed in the overcoat layer OC and the passivation layer PAS.

On the substrate on which the anode electrode ANO is disposed, the bank BA is disposed on the area where the switching thin film transistor ST, the driving thin film transistor DT, and various wirings DL, GL, and VDD are disposed to define a pixel area. (or bank pattern) is arranged. The anode electrode ANO exposed by the bank BA becomes a light emitting area. An organic light emitting layer OL is stacked on the anode ANO exposed by the bank BA. In addition, a cathode electrode CAT is sequentially stacked on the organic light emitting layer OL. When the organic light emitting layer OL is made of an organic material emitting white light, a color assigned to each pixel is displayed by the color filter CF positioned below. The organic light emitting diode display having the structure shown in FIG. 12 becomes a bottom emission display device that emits light in a downward direction.

A storage capacitor (or 'Storage Capacitance') STG is disposed between the gate electrode DG and the anode electrode ANO of the driving thin film transistor DT. The storage capacitor STG is connected to the driving thin film transistor DT so that a voltage applied to the gate electrode DG of the driving thin film transistor DT by the switching thin film transistor ST is stably maintained.

By applying the thin film transistor substrate as described above, it is possible to realize a high-quality active display device. In particular, in order to have better driving characteristics, it is preferable that the semiconductor layer of the thin film transistor is formed of a metal oxide semiconductor material.

The metal oxide semiconductor material has a characteristic that its characteristics are rapidly deteriorated when it is voltage driven in a state in which it is exposed to light. Accordingly, it is desirable to have a structure capable of blocking light entering from the outside at the upper and lower portions of the semiconductor layer. In the case of the thin film transistor substrate described above, the thin film transistor preferably has a bottom gate structure. That is, light entering from the bottom may be blocked to some extent by the gate electrode G, which is a metal material.

As described above, in a thin film transistor substrate for a flat panel display device, a plurality of pixel regions arranged in a matrix manner are disposed so far. In addition, at least one thin film transistor is disposed in each of the unit pixel areas. That is, it has a structure in which a plurality of thin film transistors are distributed over the entire area of the substrate. Since the respective structures of the plurality of pixels must be used for the same purpose and have the same quality and properties, they are formed with the same structure.

However, in some cases, it may be necessary to have different characteristics of the thin film transistors. For example, in the case of an organic light emitting diode display, a switching thin film transistor ST and a driving thin film transistor DT are included in one pixel area. Since the purpose of the switching thin film transistor ST and the driving thin film transistor DT are different from each other, the required characteristics are also different. To this end, it can be designed to have the same structure and the same semiconductor channel layer but have different sizes to suit each function. Alternatively, if necessary, a compensation thin film transistor may be further provided to supplement the function or performance.

11 and 12 for explaining the third application example of the present invention, for convenience, only the structures of the thin film transistors ST and DT of the organic light emitting diode display are schematically illustrated. However, the structures of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, the second thin film transistor T2 having an oxide semiconductor layer may be applied to the switching thin film transistor ST. The first thin film transistor T1 having a polycrystalline semiconductor layer may be applied to the driving thin film transistor DT. As described above, while providing both the first and second thin film transistors T1 and T2 , the disadvantages of the other thin film transistors can be complemented by mutual advantages.

< 4th application example >

In another case, a thin film transistor substrate in which a driving element is embedded in a non-display area of a display device may be used. Hereinafter, a case in which the driving element is directly formed on the display panel will be described in detail with reference to FIGS. 13 and 14 .

13 is a plan enlarged view showing a schematic structure of an organic light emitting diode display device according to a fourth application example of the present invention. 14 is a cross-sectional view showing the structure of an organic light emitting diode display according to a fourth application example of the present invention, taken along the cut line III-III' in FIG. 13 . Here, a thin film transistor substrate for a flat panel display having a built-in driving element will be described, and a detailed description of the thin film transistor and organic light emitting diode disposed in the display area will be omitted.

First, with reference to FIG. 13, the structure on a plane is demonstrated. The organic light emitting diode display with a built-in gate driver (GIP) according to the fourth application example of the present invention has a ratio between a display area AA displaying image information and various elements for driving the display area AA. and a substrate SUB divided by a display area NA. A plurality of pixel areas PA arranged in a matrix manner is defined in the display area AA. In FIG. 13 , the pixel areas PA are indicated by dotted lines.

For example, the pixel areas PA may be defined as an NxM rectangle. However, it is not necessarily limited to this method, and may be arranged in various ways. Each of the pixel areas may have the same size or may have different sizes. In addition, three sub-pixels representing RGB (red, green, blue) colors may be regularly arranged as one unit. In the simplest structure, the pixel areas PA have a cross structure of a plurality of gate lines GL running in a horizontal direction and a plurality of data lines DL and driving current lines VDD running in a vertical direction. can be defined as

A data driver (or Data Driving Integrated Circuit) (DIC) for supplying a signal corresponding to image information to the data lines DL in the non-display area NA, which is defined on the outer periphery of the pixel area PA; A gate driver (or, a gate driving integrated circuit) (GIP) for supplying a scan signal to the gate wirings GL may be disposed. In the case of high resolution higher than the VGA level, in which the number of data lines DL and driving current lines VDD increases, the data driver DIC is mounted outside the substrate SUB, and the data driver DIC ) instead of data connection pads may be arranged.

In order to simplify the structure of the display device, the gate driver GIP is preferably directly formed on one side of the substrate SUB. In addition, a base line Vss for supplying a base voltage is disposed at the outermost portion of the substrate SUB. The ground wiring Vss is preferably disposed to receive a ground voltage supplied from the outside of the substrate SUB, and to supply the ground voltage to both the data driver DIC and the gate driver GIP. For example, the electrical wiring Vss is connected to the data driver DIC to be separately mounted on the upper side of the substrate SUB, and the gate driver GIP is disposed on the left and/or right side of the substrate SUB. It can be arranged as if wrapping the substrate from the outside of the.

In each pixel area PA, an organic light emitting diode, which is a key component of an organic light emitting diode display, and thin film transistors for driving the organic light emitting diode are disposed. The thin film transistors may be disposed in the thin film transistor area TA defined at one side of the pixel area PA. The organic light emitting diode includes an anode electrode ANO, a cathode electrode CAT, and an organic light emitting layer OL interposed between the two electrodes. The area that actually emits light is determined by the area of the organic light emitting layer overlapping the anode electrode ANO.

The anode electrode ANO has a shape occupying a portion of the pixel area PA and is connected to the thin film transistor disposed in the thin film transistor area TA. An organic light emitting layer OL is stacked on the anode ANO, and an area where the anode ANO and the organic light emitting layer OL overlap is determined as an actual light emitting area. The cathode electrode CAT is formed as a single body so as to cover at least the area of the display area AA in which the pixel areas PA are disposed on the organic light emitting layer OL.

The cathode electrode CAT crosses the gate driver GIP and contacts the base line Vss disposed on the outer side of the substrate SUB. That is, the base voltage is applied to the cathode electrode CAT through the base line Vss. The cathode electrode CAT receives the base voltage, the anode electrode ANO receives the image voltage, and light is emitted from the organic light emitting layer OL by the voltage difference therebetween to display image information.

With further reference to FIG. 14 , a cross-sectional structure of an organic light emitting diode display according to a fourth application example of the present invention will be described in more detail. A non-display area NA in which the gate driver GIP and the base wiring Vss are disposed on the substrate SUB, and the switching thin film transistor ST, the driving thin film transistor DT, and the organic light emitting diode OLE are disposed A display area AA is defined.

The gate driver GIP may include a thin film transistor formed together in the process of forming the switching thin film transistor ST and the driving thin film transistor DT. The switching thin film transistor ST disposed in the pixel area PA includes a gate electrode SG, a gate insulating layer GI, a channel layer SA, a source electrode SS, and a drain electrode SD. In addition, the driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a gate insulating layer GI, a channel layer DA, a source electrode DS, and a drain electrode ( DD) is included.

A passivation layer PAS and a planarization layer PL are sequentially stacked on the thin film transistors ST and DT. An isolated rectangular anode electrode ANO occupying only a certain portion of the pixel area PA is disposed on the planarization layer PL. The anode electrode ANO contacts the drain electrode DD of the driving thin film transistor DT through a contact hole penetrating the passivation layer PAS and the planarization layer PL.

A bank BA defining a light emitting area is disposed on the substrate on which the anode electrode ANO is formed. The bank BA has a shape exposing most of the anode electrode ANO. An organic light emitting layer OL is stacked on the anode electrode ANO exposed by the bank BA pattern. A cathode electrode CAT made of a transparent conductive material is stacked on the bank BA and the organic light emitting layer OL. Accordingly, the organic light emitting diode OLE including the anode electrode ANO, the organic light emitting layer OL and the cathode electrode CAT is disposed.

The organic light emitting layer OL may emit white light, and a color may be expressed using a separately formed color filter CF. In this case, the organic light emitting layer OL is preferably stacked to cover at least all of the display area AA.

The cathode electrode CAT preferably covers the display area AA and the non-display area NA so as to be in contact with the base line Vss disposed on the outer side of the substrate SUB beyond the gate driver GIP. Accordingly, the ground voltage may be applied to the cathode electrode CAT through the ground line Vss.

Meanwhile, the base wiring Vss may be formed of the same material as the gate electrode G and on the same layer. In this case, it may contact the cathode electrode CAT through a contact hole penetrating the passivation layer PAS covering the base line Vss and the gate insulating layer GI. Alternatively, the base wiring Vss may be formed of the same material as the source-drain electrodes SS-SD and DS-DD on the same layer. In this case, the base line Vss may contact the cathode electrode CAT through a contact hole penetrating the passivation layer PAS.

13 and 14 for explaining the fourth application example of the present invention, for convenience, the thin film transistors ST and DT of the organic light emitting diode display and the thin film transistor structures of the gate driving device GIP are only schematically shown. The structures of the first or second thin film transistors T1 and T2 described in the first to second embodiments of the present invention may be applied. For example, the second thin film transistor T2 having an oxide semiconductor layer may be applied to the switching thin film transistor ST. The first thin film transistor T1 having a polycrystalline semiconductor layer may be applied to the driving thin film transistor DT. In addition, the first thin film transistor T1 having a polycrystalline semiconductor layer may be applied to the gate driver GIP. If necessary, the gate driver GIP may include a C-MOS type thin film transistor having both a P-MOS type and an N-MOS type.

Those skilled in the art from the above description will be able to see that various changes and modifications are possible without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be defined by the claims.

GL: gate wiring PAS: protective film
DL: data wire VDD: drive current wire
PA: pixel area T: thin film transistor
AA: display area NA: non-display area
G: gate electrode A: semiconductor layer
S: source electrode D: drain electrode
GI: gate insulating film ILD: intermediate insulating film

Claims (8)

a first semiconductor layer comprising a polycrystalline semiconductor material;
a second semiconductor layer comprising an oxide semiconductor material;
a first gate electrode stacked on a central portion of the first semiconductor layer with a first gate insulating layer interposed therebetween;
a second gate electrode stacked on a central portion of the second semiconductor layer with a second gate insulating layer interposed therebetween;
a first source region and a first drain region stacked on both sides of the first semiconductor layer;
a second source region and a second drain region defined on both sides of the second semiconductor layer;
an intermediate insulating layer covering the first semiconductor layer, the second semiconductor layer, the first gate electrode, and the second gate electrode; And
a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode disposed on the intermediate insulating layer;
The display device of claim 1, wherein the oxide semiconductor material is formed into a conductor in the first source region, the first drain region, the second source region, and the second drain region.
The method of claim 1,
the first semiconductor layer, the first gate electrode, the first source region, the first drain region, the first source electrode, and the first drain electrode are included in a first thin film transistor;
The second semiconductor layer, the second gate electrode, the second source region, the second drain region, the second source electrode, and the second drain electrode are included in a second thin film transistor.
3. The method of claim 2,
Further comprising a driving circuit,
At least one of the first thin film transistor and the second thin film transistor is included in a pixel,
At least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.
4. The method of claim 3,
The driving circuit is
a data driver outputting a data voltage;
a multiplexer that distributes the data voltage from the data driver to data lines; And
a gate driver outputting a scan pulse to a gate wiring;
At least one of the first thin film transistor and the second thin film transistor is included in any one of the multiplexer and the gate driver.
3. The method of claim 2,
The second thin film transistor is a switching element for selecting a pixel,
The first thin film transistor is a driving element for driving the pixel selected by the second thin film transistor.
The method of claim 1,
the first source electrode passes through the intermediate insulating layer and contacts the first source region;
the first drain electrode passes through the intermediate insulating layer and contacts the first drain region;
the second source electrode passes through the intermediate insulating layer and contacts the second source region;
The second drain electrode penetrates the intermediate insulating layer and contacts the second drain region.
The method of claim 1,
The first gate insulating film and the second gate insulating film form one thin film layer including a material in the same layer,
The first semiconductor layer and the second semiconductor layer are disposed on the same layer.
The method of claim 1,
The first semiconductor layer is disposed under the first gate insulating layer,
the second semiconductor layer is disposed on the first gate insulating layer;
the first source region passes through the first gate insulating layer and contacts one side of the first semiconductor layer;
The first drain region penetrates the first gate insulating layer and contacts the other side of the first semiconductor layer.

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