KR102454382B1 - Thin Film Transistor Substrate And Display Using The Same - Google Patents

Abstract

The present invention provides a display device including a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor is disposed on the substrate and includes a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode. The second thin film transistor is disposed on the substrate to be spaced apart from the first thin film transistor, and includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second gate electrode are disposed spaced apart from each other in the same layer on the upper surface of the gate insulating film. First and second intermediate insulating layers in which a nitride layer and an oxide layer are sequentially stacked are disposed on upper surfaces of the first gate electrode and the second gate electrode. A dummy semiconductor layer formed in an island shape between the substrate and the oxide semiconductor layer and a buffer layer positioned on the dummy semiconductor layer are included.

Description

Thin Film Transistor Substrate And Display Using The Same

The present invention relates to a thin film transistor substrate in which different types of thin film transistors are disposed on the same substrate and a display device using the same.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. The display device field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) replacing a bulky cathode ray tube (CRT). Display devices include a Liquid Crystal Display Device (LCD), a Plasma Display Panel (PDP), an Organic Light Emitting Display Device (OLED), and an Electrophoretic Display Device: ED), etc.

In the case of a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device that are actively driven, a thin film transistor substrate is included in which thin film transistors allocated in pixel regions arranged in a matrix manner are disposed. A liquid crystal display device (LCD) displays an image by controlling the light transmittance of liquid crystal using an electric field. An organic light emitting display device displays an image by forming an organic light emitting element in pixels arranged in a matrix manner.

The organic light emitting display device is a self-luminous device that emits light by itself, and has advantages of fast response speed, luminous efficiency, luminance, and large viewing angle. In particular, in an organic light emitting diode display (OLED) using the characteristics of an organic light emitting diode with excellent energy efficiency, a passive matrix type organic light emitting diode display (PMOLED) and an active matrix It is roughly classified into an Active Matrix type Organic Light Emitting Diode display (AMOLED) type.

As personal electronic devices are actively developed, display devices are also being developed into products with excellent portability and/or wearability. As such, in order to be applied to a portable or wearable device, a display device with low power consumption is required. The technologies related to the display device developed so far have a limit in realizing low power consumption.

SUMMARY OF THE INVENTION The present invention for solving the problems of the background art is to provide a display device including two or more kinds of thin film transistors including different materials on the same substrate. Another object of the present invention is to provide a display device in which a thin film transistor for a driving device including a polycrystalline semiconductor material and a thin film transistor for a display device including an oxide semiconductor material are disposed on the same substrate. Another object of the present invention is to provide a display device including two or more types of thin film transistors, which include different materials and have different structures, using a minimum mask process and a minimum manufacturing process. Another object of the present invention is to provide a display device capable of improving device characteristics.

As a means for solving the above problems, the present invention provides a display device including a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor is disposed on the substrate and includes a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode. The second thin film transistor is disposed on the substrate to be spaced apart from the first thin film transistor, and includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second gate electrode are disposed spaced apart from each other in the same layer on the upper surface of the gate insulating film. First and second intermediate insulating layers in which a nitride layer and an oxide layer are sequentially stacked are disposed on upper surfaces of the first gate electrode and the second gate electrode. A dummy semiconductor layer formed in an island shape between the substrate and the oxide semiconductor layer and a buffer layer positioned on the dummy semiconductor layer are included.

The buffer layer is disposed on the entire surface of the substrate or is formed in an island shape corresponding to the dummy semiconductor layer.

In the second thin film transistor, the second source electrode and the second drain electrode are positioned on the oxide semiconductor layer, or the oxide semiconductor layer is positioned on the second source electrode and the second drain electrode.

The present invention also provides a display device including a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor is disposed on the substrate and includes a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode. The second thin film transistor is disposed on the substrate to be spaced apart from the first thin film transistor, and includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode and the second gate electrode are disposed on different layers, and the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed spaced apart from each other on the same layer. A dummy semiconductor layer formed in an island shape between the substrate and the oxide semiconductor layer, an island shape insulated from the dummy semiconductor layer, electrically connected to the second source electrode, located on the same layer as the first gate electrode, and an oxide semiconductor layer and an insulated metal electrode layer.

The first thin film transistor is positioned on the first intermediate insulating layer and is positioned in a region that does not overlap the first gate electrode, and a data line made of the same layer and the same material as that of the second gate electrode is further disposed.

The first thin film transistor includes a first gate electrode positioned on the first intermediate insulating film, a metal electrode layer positioned under the first gate electrode, and a first source electrode, a first drain electrode, and a second source positioned on the second intermediate insulating film. and a dummy source-drain electrode made of the same layer and material as the electrode and the second drain electrode and electrically connecting the first gate electrode and the metal electrode layer.

The thin film transistor substrate and the display device using the same according to the present invention may have a feature in that two different types of thin film transistors are formed on the same substrate, so that the other thin film transistor compensates for the disadvantages of one thin film transistor. In particular, it is possible to provide a display device suitable for portable and/or wearable devices by reducing power consumption by providing a thin film transistor having low-speed driving characteristics.

1 is a cross-sectional view showing a thin film transistor substrate for a display device including different types of thin film transistors according to a first embodiment of the present invention;
2 to 5 are cross-sectional views illustrating a process of manufacturing a thin film transistor substrate for a display device including different types of thin film transistors according to a second embodiment of the present invention.
6 and 7 are cross-sectional views and process flow charts illustrating a process of manufacturing a thin film transistor substrate for a display device including different types of thin film transistors according to a third embodiment of the present invention.
8 and 9 are cross-sectional views and process flow charts illustrating a process of manufacturing a thin film transistor substrate for a display device including different types of thin film transistors according to a fourth embodiment of the present invention.
10 is a block diagram schematically showing the configuration of a display device according to a first application example of the present invention.
11 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display, which is a type of horizontal electric field type, according to a second application example of the present invention.
FIG. 12 is a cross-sectional view of the thin film transistor substrate shown in FIG. 11 taken along line II';
13 is a plan view illustrating the structure of one pixel in an active matrix organic light emitting diode display according to a third application example of the present invention;
FIG. 14 is a cross-sectional view illustrating the structure of an active matrix organic light emitting diode display taken along the cut line II-II' in FIG. 13;
15 is an enlarged plan view showing a schematic structure of an organic light emitting display device according to a fourth application example of the present invention.
16 is a cross-sectional view showing the structure of an organic light emitting diode display according to a fourth application example of the present invention, taken along the cut line III-III' in FIG. 15;

Hereinafter, with reference to the accompanying drawings, a preferred embodiment of the present invention will be described. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the component names used in the following description may be selected in consideration of the ease of writing the specification, and may be different from the component names of the actual product.

<First embodiment>

An embodiment of the present invention includes first and second thin film transistors disposed in a first region on a substrate and a third thin film transistor disposed in the second region. The substrate may include a display area and a non-display area. In the display area, a plurality of pixel areas are arranged in a matrix manner or the like. Display elements for a display function are disposed in the pixel area. The non-display area may be disposed around the display area, and driving elements for driving the display elements formed in the pixel area may be disposed.

Polycrystalline semiconductor material has high mobility (100cm2/Vs or more), low energy consumption, and excellent reliability, so it can be applied to a gate driver and/or a multiplexer (MUX) for driving devices that drive thin film transistors for display devices. have. Alternatively, it is preferable to apply it as a driving thin film transistor in a pixel in an organic light emitting display device. Since the oxide semiconductor material has a low off-current, it is suitable for a switching thin film transistor having a short on-time and a long off-time. In addition, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low-speed driving and/or low power consumption. In this way, by simultaneously disposing the thin film transistor for a driving element and the thin film transistor for a display element, which have different properties, on the same substrate, a thin film transistor substrate having optimum efficiency can be obtained.

When the semiconductor layer is formed of a polycrystalline semiconductor material, an impurity implantation process and a high-temperature heat treatment process are required. On the other hand, when the semiconductor layer is formed of an oxide semiconductor material, the process is performed at a relatively low temperature. Therefore, it is preferable to first form the polycrystalline semiconductor layer, which is subjected to the process under severe conditions, and then to form the oxide semiconductor layer later. To this end, it is preferable that the first thin film transistor including the polycrystalline semiconductor material has a top-gate structure, and the second thin film transistor including the oxide semiconductor material has a bottom-gate structure.

In addition, in the manufacturing process, since properties of the polycrystalline semiconductor material are deteriorated when voids exist, a process of filling the voids with hydrogen through a hydrogenation process is required. On the other hand, in the oxide semiconductor material, since the pores without covalent bonding can serve as carriers, a process for stabilizing the pores while retaining the pores is required. These two processes can be formed through a subsequent heat treatment process performed under 350 ~ 380 ℃.

In order to perform the hydrogenation process, a nitride film including a large amount of hydrogen particles is interposed on the polycrystalline semiconductor material. In a heat treatment process, hydrogen diffuses into the polycrystalline semiconductor material. As a result, the polycrystalline semiconductor layer can achieve stabilization. During the heat treatment process, hydrogens should not diffuse into the oxide semiconductor material. Therefore, it is preferable to interpose an oxide film between the nitride film and the oxide semiconductor material. After performing the heat treatment process, the oxide semiconductor material remains unaffected by hydrogen, so device stabilization can be achieved.

Here, the first area may be a part of the non-display area, and the second area may be a part of the display area. In this case, the first and second thin film transistors and the third thin film transistor may be disposed far apart. Alternatively, both the first area and the second area may be included in the display area. In particular, when a plurality of thin film transistors are included in a single pixel area, the first and second thin film transistors and the third thin film transistor may be disposed adjacent to each other.

In the following description, for convenience, the first and second thin film transistors are thin film transistors for driving elements formed in the non-display area, and the third thin film transistors are thin film transistors for display elements disposed in the pixel area of the display area. . However, it is not limited thereto. In addition, hereinafter, for convenience, two thin film transistors are formed in the non-display area and one thin film transistor is formed in the pixel area of the display area as an example, but the number thereof is not limited thereto.

A thin film transistor made of a polycrystalline semiconductor material may be applied to a driving thin film transistor, and a thin film transistor made of an oxide semiconductor material may be applied to a switching thin film transistor. In addition, the mask process described below refers to a photolithography process including photomask alignment, exposure, development, and etching processes.

A first embodiment of the present invention will be described with reference to FIG. 1 . 1 is a cross-sectional view illustrating a thin film transistor substrate for a display device including different types of thin film transistors according to a first embodiment of the present invention. Here, a sectional view that can clearly show the characteristics of the invention will be mainly described, and for convenience, a plan view structure is not shown in drawings.

Referring to FIG. 1 , a thin film transistor substrate for a display device according to a first embodiment of the present invention includes a first thin film transistor T1 , a second thin film transistor T2 , and a second thin film transistor T2 and a first thin film transistor T1 spaced apart from each other on a substrate SUB. 3 includes a thin film transistor T3. The first to third thin film transistors T1 to T3 may be spaced apart considerably apart, or may be disposed relatively adjacent to each other and spaced apart from each other.

A first semiconductor layer A1 , SA1 , DA1 , a second semiconductor layer A2 , SA2 , DA2 , and a dummy semiconductor layer LS are formed on the substrate SUB. The first semiconductor layers A1 , SA1 , and DA1 include a channel region A1 , a source region SA1 , and a drain region DA1 of the first thin film transistor T1 , and the second semiconductor layer A2 includes the second semiconductor layer A2 . 2 The thin film transistor T2 includes a channel region A2 , a source region SA2 , and a drain region DA2 . The channel region, source region and drain region are defined by ion doping. On the other hand, the dummy semiconductor layer LS is formed of the same semiconductor material as the first semiconductor layers A1 , SA1 , DA1 and the second semiconductor layers A2 , SA2 , DA2 , but a light blocking layer that blocks light incident from the outside It is formed in the form of an island to perform only its role.

When the first and second thin film transistors T1 and T2 are thin film transistors for driving elements, they preferably have characteristics suitable for performing high-speed driving processing. For example, the first and second thin film transistors T1 and T2 may be implemented as C-MOS type thin film transistors including P-MOS and N-MOS type thin film transistors. In this case, the first thin film transistor T1 corresponding to the P-MOS type includes a channel region A1, a source region SA1, and a drain region DA1, while the second thin film transistor T1 corresponding to the N-MOS type is included. T2 includes a channel region A2 , a source region SA2 , a drain region DA2 , and an impurity region LDD. The impurity region LDD is formed by an ion doping process that defines the type of semiconductor layer. The impurity region LDD of the second thin film transistor T2 corresponding to the N-MOS type generally refers to a low density doping region (LDD).

Such thin film transistors preferably include a polycrystalline semiconductor material such as poly-silicon. In addition, in the case of these thin film transistors, it is preferable to have a top-gate structure. The first semiconductor layer (A1, SA1, DA1), the second semiconductor layer (A2, SA2, DA2) and the dummy semiconductor layer (LS) are to deposit an amorphous silicon (a-Si) material, and perform dehydrogenation and crystallization. As a result, it becomes poly-silicon.

A buffer layer BUF is deposited on the surface of the substrate SUB on which the dummy semiconductor layer LS is formed. After the buffer layer BUF is formed on the entire surface of the substrate SUB, only a region corresponding to the dummy semiconductor layer LS is removed, leaving an island shape.

A third semiconductor layer A3 is formed on the region overlapping the buffer layer BUF. The third semiconductor layer A3 includes a channel region, a source region, and a drain region of the third thin film transistor T3 . When the third thin film transistor T3 is a thin film transistor for a display element, it is preferable to have characteristics suitable for performing display function processing. For example, it is preferred to include an oxide semiconductor material (eg, IGZO, etc.). When the oxide semiconductor material is included, it is preferable to have a top-gate structure capable of forming a gate electrode in a single process together with the subsequent first and second thin film transistors T1 and T2 .

A gate insulating layer GI is deposited on the entire surface of the substrate SUB on which the first semiconductor layers A1 , SA1 , DA1 , the second semiconductor layers A2 , SA2 , DA2 and the third semiconductor layer A3 are formed. The gate insulating layer GI is preferably formed of silicon oxide (SiOx).

A first gate electrode G1 , a second gate electrode G2 , and a third gate electrode G3 are formed on the gate insulating layer GI. The first gate electrode G1 is disposed to overlap the channel region A1 of the first semiconductor layers A1 , SA1 , and DA1 . The second gate electrode G2 is disposed to overlap the channel region A2 of the second semiconductor layers A2 , SA2 , and DA2 . The third gate electrode G3 is disposed to overlap the channel region of the third semiconductor layer A3 . Since the first to third gate electrodes G1 to G3 are formed of the same material on the same layer and are formed by the same mask, a manufacturing process may be simplified.

A first intermediate insulating layer ILD1 and a second intermediate insulating layer ILD2 are deposited on the entire surface of the substrate SUB on which the first to third gate electrodes G1 to G3 are formed. In particular, the first and second intermediate insulating layers ILD1 and ILD2 have a double-layer or more structure in which an oxide layer SIO including silicon oxide (SiOx) and a nitride layer SIN including silicon nitride (SiNx) are sequentially stacked. it is preferable Here, as a minimum component for convenience, a double-layer structure in which a nitride film SIN is stacked on an oxide film SIO will be described.

Source-drain electrodes S1 , S2 , S3 , D1 , D2 , and D3 of the first to third thin film transistors T1 to T3 are formed on the substrate SUB on which the second intermediate insulating layer ILD2 is formed. The first source electrode S1 and the first drain electrode D1 are spaced apart from each other by a predetermined distance with respect to the first gate electrode G1 to face each other. The first source electrode S1 is connected to the source region SA1 of the first semiconductor layers A1 , SA1 , and DA1 exposed through the first source contact hole. The first source contact hole penetrates the intermediate insulating layers ILD1 and ILD2 and the gate insulating layer GI to expose one side of the source region SA1 of the first semiconductor layers A1 , SA1 and DA1. The first drain electrode D1 is connected to the drain region DA1 of the first semiconductor layers A1 , SA1 , and DA1 exposed through the drain contact hole. The drain contact hole penetrates the intermediate insulating layers ILD1 and ILD2 and the gate insulating layer GI to expose the drain region DA1 of the first semiconductor layers A1 , SA1 and DA1 .

The second source electrode S2 and the second drain electrode D2 are also spaced apart from each other by a predetermined distance in the same manner as above, and the source region SA1 and the drain region DA2 of the second semiconductor layers A2 , SA2 , and DA2 . is connected to In addition, the third source electrode S3 and the third drain electrode D3 are also spaced apart from each other by a predetermined distance in the same manner as above, and are connected to the source region and the drain region of the third semiconductor layer A3 .

A passivation layer PAS is deposited on the substrate SUB on which the source-drain electrodes S1 , S2 , S3 , D1 , D2 , and D3 of the first to third thin film transistors T1 to T3 are formed. Thereafter, a contact hole exposing the first drain electrode D1 , the second drain electrode D2 , and/or the third drain electrode D3 may be further formed by patterning the passivation layer PAS.

In addition, on the passivation layer PAS, a reflective plate, a color filter, and a pixel electrode in contact with the first drain electrode D1, the second drain electrode D2, and/or the third drain electrode D3 exposed through the contact hole; A planarization film or the like may be further formed. The thin film transistor substrate for a display device is implemented as a display device such as a liquid crystal display device or an organic light emitting display device according to the shape of an electrode or structure formed after the pixel electrode. However, for convenience of description, only parts showing the structure of the thin film transistors representing the main features of the present invention are illustrated and described herein.

As described above, the thin film transistor substrate for a display device according to the first embodiment of the present invention includes the first and second thin film transistors T1 and T2 including a polycrystalline semiconductor material and the third thin film transistor T3 including an oxide semiconductor material. ) has a structure formed on the same substrate SUB. In particular, the gate electrode constituting the first and second thin film transistors T1 and T2 and the gate electrode constituting the third thin film transistor T3 have a structure in which the same material is formed on the same layer.

The first embodiment described above has effects of low power consumption (Low Frequency) and low voltage (Oxide Saturation characteristic) by applying an oxide TFT to the display area AA, and the non-display area NA (eg: By applying a polysilicon thin film transistor (Poly-Silicon or LTPS TFT) to the GIP circuit of the gate driver or the MUX circuit of the data driver), it has the effect of satisfying the function requiring high mobility.

Also, in the first embodiment, since the gate electrodes and the source-drain electrodes constituting different types of thin film transistors are not separated from each other (formed on different layers) but are formed on the same layer, the mask is increased (added) in the manufacturing process. has the effect of preventing

<Second embodiment>

Hereinafter, a method of manufacturing a thin film transistor substrate for a display device including different types of thin film transistors according to a second embodiment of the present invention will be described with further reference to FIGS. 2 to 5 . 2 to 5 are cross-sectional views illustrating a process of manufacturing a thin film transistor substrate for a display device including different types of thin film transistors according to a second embodiment of the present invention.

Different types of thin film transistors according to the second embodiment of the present invention, unlike the first embodiment, are implemented in a combination of a coplanar structure and an inverted coplanar structure. Meanwhile, hereinafter, for convenience, two thin film transistors are formed in the non-display area and one thin film transistor is formed in the pixel area of the display area as an example, but the number thereof is not limited thereto.

A first semiconductor layer A1 , SA1 , DA1 , a second semiconductor layer A2 , SA2 , DA2 , and a dummy semiconductor layer LS are formed on the substrate SUB. The first semiconductor layers A1 , SA1 , and DA1 include a channel region A1 , a source region SA1 , and a drain region DA1 of the first thin film transistor T1 , and the second semiconductor layer A2 includes the second semiconductor layer A2 . 2 The thin film transistor T2 includes a channel region A2 , a source region SA2 , and a drain region DA2 . The channel region, source region and drain region are defined by ion doping. On the other hand, the dummy semiconductor layer LS is formed of the same semiconductor material as the first semiconductor layers A1 , SA1 , DA1 and the second semiconductor layers A2 , SA2 , DA2 , but only serves to block light incident from the outside. It is formed in the shape of an island.

When the first and second thin film transistors T1 and T2 to be formed in the non-display area NA thereafter are thin film transistors for driving elements, it is desirable to have characteristics suitable for performing high-speed driving processing. For example, the first and second thin film transistors T1 and T2 may be implemented as C-MOS type thin film transistors including P-MOS and N-MOS type thin film transistors. In this case, the first thin film transistor T1 corresponding to the P-MOS type includes a channel region A1, a source region SA1, and a drain region DA1, while the second thin film transistor T1 corresponding to the N-MOS type is included. T2 includes a channel region A2 , a source region SA2 , a drain region DA2 , and an impurity region LDD. The impurity region LDD is formed by an ion doping process that defines the type of semiconductor layer. The impurity region LDD of the second thin film transistor T2 corresponding to the N-MOS type generally refers to a low density doping region (LDD).

Such thin film transistors preferably include a polycrystalline semiconductor material such as poly-silicon. In addition, in the case of these thin film transistors, it is preferable to have a top-gate structure.

On the entire surface of the substrate SUB on which the first semiconductor layers A1 , SA1 , DA1 , the second semiconductor layers A2 , SA2 , DA2 and the dummy semiconductor layer LS are formed, the first intermediate insulating layer ILD1 and the second An intermediate insulating layer ILD2 is deposited. In particular, the first and second intermediate insulating layers ILD1 and ILD2 have a double-layer or more structure in which an oxide layer SIO including silicon oxide (SiOx) and a nitride layer SIN including silicon nitride (SiNx) are sequentially stacked. it is preferable Here, as a minimum component for convenience, a double-layer structure in which a nitride film SIN is stacked on an oxide film SIO will be described.

The first and second intermediate insulating layers ILD1 and ILD2 formed in the non-display area NA remain as they are, and only the second intermediate insulating layer ILD2 formed in the display area AA is removed. The first intermediate insulating layer ILD1 formed in the display area AA serves as a buffer layer BUF that electrically separates the electrode and the dummy semiconductor layer LS to be formed later. Accordingly, the first intermediate insulating layer ILD1 formed in the display area AA is referred to as a buffer layer BUF.

Contact holes SH1 and SH2 for electrical contact between the source-drain electrodes and the source-drain regions in the first and second intermediate insulating layers ILD1 and ILD2 formed in the non-display area NA through a photo process using a halftone mask. , DH1, DH2).

Polysilicon of the first semiconductor layers A1 and DA1 and the second semiconductor layers A2 and DA2 exposed through the contact holes SH1, SH2, DH1, DH2 of the non-display area NA through a high-temperature heat treatment process Hydrogenation (a process that fills the less-bonded spaces with hydrogen through activation. Unlike activation, it proceeds at a lower temperature and is affected by time rather than temperature, so it is more effective the longer you do it). In this case, in the non-display area NA, the H2 source present in the second intermediate insulating layer ILD2 of the nitride layer SIN including the silicon nitride (SiNx) may diffuse into the polysilicon layer. On the other hand, in the display area AA, since the second intermediate insulating layer ILD2 is completely removed, the density of H2 as the first intermediate insulating layer ILD1 serving as a buffer does not increase.

Source-drain electrodes S1 , S2 , S3 , D1 , D2 , and D3 are formed on the substrate SUB on which the first and second intermediate insulating layers ILD1 and ILD2 are formed. The first source electrode S1 and the first drain electrode D1 are spaced apart from each other by a predetermined distance and disposed to face each other. The first source electrode S1 is connected to the source region SA1 of the first semiconductor layers A1 , SA1 , and DA1 exposed through the first source contact hole SH1 . The first source contact hole SH1 penetrates the intermediate insulating layers ILD1 and ILD2 to expose one side of the source region SA1 of the first semiconductor layers A1 , SA1 , and DA1 . The first drain electrode D1 is connected to the drain region DA1 of the first semiconductor layers A1 , SA1 , and DA1 exposed through the first drain contact hole DH1 . The first drain contact hole DH1 penetrates the intermediate insulating layers ILD1 and ILD2 to expose the drain region DA1 of the first semiconductor layers A1 , SA1 and DA1 .

The second source electrode S2 and the second drain electrode D2 are also spaced apart from each other by a predetermined distance in the same manner as above, and the source region SA1 and the drain region DA2 of the second semiconductor layers A2 , SA2 , and DA2 . is connected to Unlike this, the third source electrode S3 and the third drain electrode D3 are disposed to be spaced apart from each other by a predetermined distance. As described above, since the source-drain electrodes S1 , S2 , S3 , D1 , D2 , and D3 are formed of the same material on the same layer and are formed by the same mask, the manufacturing process may be simplified.

A third semiconductor layer A3 is formed on the substrate SUB on which the third source electrode S3 and the third drain electrode D3 are formed. The third semiconductor layer A3 includes a channel region, a source region, and a drain region of the third thin film transistor T3 . When the third thin film transistor T3 is a thin film transistor for a display element, it is preferable to have characteristics suitable for performing display function processing. For example, it is preferred to include an oxide semiconductor material (eg, IGZO, etc.). When the oxide semiconductor material is included, it is preferable to have a top-gate structure capable of forming a gate electrode in a single process together with the subsequent first and second thin film transistors T1 and T2 .

A gate insulating layer GI is deposited on the entire surface of the substrate SUB on which the source-drain electrodes S1 , S2 , S3 , D1 , D2 , and D3 are formed. The gate insulating layer GI is preferably formed of silicon oxide (SiOx). In the case of the gate insulating layer GI, it is preferable to have a thickness of about 1,000 to 1,500 Å in consideration of device stability and characteristics.

A first gate electrode G1 , a second gate electrode G2 , and a third gate electrode G3 are formed on the gate insulating layer GI. The first gate electrode G1 is disposed to overlap the channel region A1 of the first semiconductor layers A1 , SA1 , and DA1 . The second gate electrode G2 is disposed to overlap the channel region A2 of the second semiconductor layers A2 , SA2 , and DA2 . The third gate electrode G3 is disposed to overlap the channel region of the third semiconductor layer A3 . Since the first to third gate electrodes G1 to G3 are formed of the same material on the same layer and are formed by the same mask, a manufacturing process may be simplified.

A passivation layer PAS is deposited on the entire surface of the substrate SUB on which the first to third gate electrodes G1 to G3 are formed. The passivation layer PAS is preferably formed of silicon oxide (SiOx).

Thereafter, a contact hole exposing the first drain electrode D1 , the second drain electrode D2 , and/or the third drain electrode D3 may be further formed by patterning the passivation layer PAS. In addition, on the passivation layer PAS, a reflective plate, a color filter, and a pixel electrode in contact with the first drain electrode D1, the second drain electrode D2, and/or the third drain electrode D3 exposed through the contact hole; A planarization film or the like may be further formed. However, for convenience, only parts showing the structure of the thin film transistors representing the main features of the present invention are illustrated and described herein.

As described above, the thin film transistor substrate for a display device according to the second embodiment of the present invention includes the first and second thin film transistors T1 and T2 including a polycrystalline semiconductor material and the third thin film transistor T3 including an oxide semiconductor material. ) has a structure formed on the same substrate SUB. In particular, the gate electrodes constituting the first and second thin film transistors T1 and T2 , the source-drain electrodes and the gate electrodes constituting the third thin film transistor T3 , and the source-drain electrodes are formed on the same layer using the same material. have a structure

The second embodiment described above is advantageous in manufacturing a high-resolution panel because the capacitor can be reduced due to the low-speed driving capability and low off-current of the oxide thin film transistor. And it is advantageous to achieve a narrow bezel with high mobility and good reliability of the polysilicon thin film transistor. In addition, both polycrystalline silicon and oxide thin film transistors can be manufactured with similar structures, and since the gate electrode, the gate insulating film, and the source-drain electrode are formed on the same layer, a metal-to-metal contact process is unnecessary, which is advantageous for mask reduction. In addition, since the semiconductor layer of the oxide thin film transistor is formed after a high temperature process (activation, hydrogenation) of the polysilicon thin film transistor, deterioration of the device can be prevented. In addition, since there is no silicon nitride under the semiconductor layer of the oxide thin film transistor, deterioration of the device can be prevented. And since CMOS is implemented with polysilicon thin film transistors, it is advantageous to reduce power consumption.

<Third embodiment>

A thin film transistor substrate for a display device according to an embodiment of the present invention includes a first thin film transistor disposed in a first region and a second thin film transistor disposed in a second region on the substrate. The substrate may include a display area and a non-display area. In the display area, a plurality of pixel areas are arranged in a matrix manner or the like. Display elements for a display function are disposed in the pixel area. The non-display area may be disposed around the display area, and driving elements for driving the display elements formed in the pixel area may be disposed.

Here, the first area may be a part of the non-display area, and the second area may be a part of the display area. In this case, the first thin film transistor and the second thin film transistor may be disposed far apart. Alternatively, both the first area and the second area may be included in the display area. In particular, when a plurality of thin film transistors are included in a single pixel area, the first thin film transistor and the second thin film transistor may be disposed adjacent to each other.

In the following description, for convenience, the first thin film transistor is a thin film transistor for a driving element formed in the non-display area, and the second thin film transistor is a thin film transistor for a display element disposed in a pixel area of the display area. However, it is not limited thereto. In addition, hereinafter, one thin film transistor is formed in each of the non-display area and the pixel area of the display area as an example for convenience, but the number thereof is not limited thereto.

Hereinafter, a method of manufacturing a thin film transistor substrate for a display device including different types of thin film transistors according to a third embodiment of the present invention will be described with further reference to FIGS. 6 and 7 . 6 and 7 are cross-sectional views and process flowcharts illustrating a process of manufacturing a thin film transistor substrate for a display device including different types of thin film transistors according to a third embodiment of the present invention.

6 and 7 , a thin film transistor substrate for a display device according to a third exemplary embodiment of the present invention includes a first thin film transistor T1 and a second thin film transistor T2 disposed on the substrate SUB to be spaced apart from each other. ) is included. The first and second thin film transistors T1 and T2 may be spaced apart considerably apart, or may be disposed relatively adjacent to each other and spaced apart from each other.

A buffer layer BUF is deposited on the substrate SUB (S100). The buffer layer BUF may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The buffer layer BUF serves to improve adhesion between the layer to be formed later and the substrate SUB, and this may be omitted.

The first semiconductor layers A1 , SA1 , DA1 and the dummy semiconductor layer A12 are formed on the substrate SUB on which the buffer layer BUF is formed ( S110 ). A semiconductor layer material is deposited on the buffer layer BUF and patterned by a first mask process to form first semiconductor layers A1 , SA1 , DA1 and a dummy semiconductor layer A12 .

The first semiconductor layers A1 , SA1 and DA1 include a channel region A1 , a source region SA1 , and a drain region DA1 of the first thin film transistor T1 , and the dummy semiconductor layer A12 includes the first Although it is formed of the same semiconductor material as the semiconductor layers A1 , SA1 and DA1 , it is formed in an island shape to only serve to block light incident from the outside. The channel region, source region and drain region are defined by ion doping.

The first thin film transistor T1 including the first semiconductor layers A1 , SA1 and DA1 may include a polycrystalline semiconductor material such as poly-silicon. In addition, the first thin film transistor T1 preferably has a top-gate structure. The first semiconductor layers A1 , SA1 , and DA1 become poly-silicon by depositing an amorphous silicon (a-Si) material and performing dehydrogenation and crystallization. On the other hand, the dummy semiconductor layer A12 serving as a light blocking layer may exist in an amorphous silicon (a-Si) state without being crystallized.

A first gate insulating layer GI1 is deposited on the surface of the substrate SUB on which the first semiconductor layers A1 , SA1 , DA1 and the dummy semiconductor layer A12 are formed ( S120 ). The first gate insulating layer GI1 serves as a gate insulating layer in the non-display area NA, but functions as a lower buffer layer in the display area AA.

First and second metal electrode layers G1 and LS are formed on the first gate insulating layer GI1 (S200). A metal material (eg, MoTi) is formed on the first gate insulating layer GI1 and patterned by a second mask process to form first and second metal electrode layers G1 and LS. Using the first metal electrode layer G1 as a mask, ions are doped into the lower first semiconductor layers A1 , SA1 , and DA1 .

The first metal electrode layer G1 is disposed to overlap the channel region A1 of the first semiconductor layers A1 , SA1 , and DA1 . The second metal electrode layer LS is disposed to overlap the dummy semiconductor layer A12 . The first metal electrode layer G1 serves as a gate electrode, a gate pad, and a gate wiring of the first thin film transistor T1 . On the other hand, the second metal electrode layer LS serves as a light blocking layer like the dummy semiconductor layer A12 .

The dummy semiconductor layer A12 is present to prevent (block) a problem that light incident from the outside is incident on the inside (oxide semiconductor layer), but it is at a distance from the oxide semiconductor layer formed later. Therefore, the second metal electrode layer LS is positioned close to the oxide semiconductor layer in order to assist the light blocking ability of the dummy semiconductor layer A12 . To this end, the second metal electrode layer LS may have a size similar to or corresponding to that of the dummy semiconductor layer A12, but is not limited thereto.

A first intermediate insulating layer ILD1 is deposited on the entire surface of the substrate SUB on which the first and second metal electrode layers G1 and LS are formed (S210). The first intermediate insulating layer ILD1 is selected as a nitride layer SIN including silicon nitride (SiNx).

A second semiconductor layer A2 is formed on the first intermediate insulating layer ILD1 on which the second metal electrode layer LS is formed ( S220 ). An oxide semiconductor material (eg, IGZO) is formed on the first intermediate insulating layer ILD1 and patterned by a third mask process to form a second semiconductor layer A2 and heat treatment is performed.

A second gate insulating layer GI2 is deposited on the second semiconductor layer A2 and heat-treated ( S310 ). The second gate insulating layer GI2 is preferably formed of silicon oxide (SiOx). In the case of the second gate insulating layer GI2, it is preferable to have a thickness of about 1,000 to 1,500 Å in consideration of device stability and characteristics.

Third and fourth metal electrode layers DL and G2 are formed on the second gate insulating layer GI2 ( S400 ). A metal material (eg, Cu) is formed on the second gate insulating layer GI2 and patterned by a fourth mask process to form third and fourth metal electrode layers DL and G2 .

The third metal electrode layer DL does not overlap the first metal electrode layer G1 but is disposed to be positioned in a region adjacent to the first semiconductor layers A1 , SA1 , and DA1 . The fourth metal electrode layer G2 is disposed to overlap the second semiconductor layer A2. The third metal electrode layer DL serves as a data line connected to the source electrode of the first thin film transistor T1 . On the other hand, the fourth metal electrode layer G2 becomes a gate electrode of the second thin film transistor T2.

A second intermediate insulating layer ILD2 is deposited on the first intermediate insulating layer ILD1 on which the third and fourth metal electrode layers DL and G2 are formed ( S500 ). The second intermediate insulating layer ILD2 is selected as an oxide layer SIO including silicon oxide (SiOx). A portion of the first semiconductor layers A1, SA1, DA1, a portion of the second semiconductor layer A2, and a portion of the third metal electrode layer DL by forming the second intermediate insulating layer ILD2 and patterning it by a fifth mask process and a contact hole exposing a portion of the second metal electrode layer LS.

First source-drain electrodes S1 and D1 and second source-drain electrodes S2 and D2 (integrated source-drain electrodes) are formed on the second intermediate insulating layer ILD2 ( S600 ). A source-drain material is formed on the second intermediate insulating layer ILD2 and patterned by a sixth mask process to form the first source-drain electrodes S1 and D1 and the second source-drain electrodes S2 and D2 (integrated source-drain). electrode) is formed.

The first source electrode S1 is connected to the source region SA1 of the third metal electrode layer DL and the first semiconductor layers A1, SA1, and DA1, and the first drain electrode D1 is connected to the first semiconductor layer ( It is connected to the drain region DA1 of A1, SA1, and DA1. The first source-drain electrodes S1 and D1 become source-drain electrodes of the first thin film transistor T1.

The second source electrode S2 is connected to the source region of the second metal electrode layer LS and the second semiconductor layer A2 , and the second drain electrode D2 is connected to the drain region of the second semiconductor layer A2 . do. The second source-drain electrodes S2 and D2 become source-drain electrodes of the second thin film transistor T2. As described above, since the source-drain electrodes are formed of the same material on the same layer and are formed by the same mask, the manufacturing process can be simplified.

A passivation layer PAS is deposited on the second intermediate insulating layer ILD2 on which the first source-drain electrodes S1 and D1 and the second source-drain electrodes S2 and D2 are formed ( S610 ). Thereafter, a contact hole exposing the first drain electrode D1 and/or the second drain electrode D2 may be further formed by patterning the passivation layer PAS.

In addition, a reflective plate, a color filter, a planarization layer, etc. may be further formed on the passivation layer PAS along with the pixel electrode in contact with the first drain electrode D1 and/or the second drain electrode D2 exposed through the contact hole. have. The thin film transistor substrate for a display device is implemented as a display device such as a liquid crystal display device or an organic light emitting display device according to the shape of an electrode or structure formed after the pixel electrode. However, for convenience of description, only parts showing the structure of the thin film transistors representing the main features of the present invention are illustrated and described herein.

As described above, in the thin film transistor substrate for a display device according to the third embodiment of the present invention, the first thin film transistor T1 including the polycrystalline semiconductor material and the second thin film transistor T2 including the oxide semiconductor material are the same substrate ( SUB) has a structure formed on it. In particular, the data line constituting the first thin film transistor T1 and the gate electrode constituting the second thin film transistor T2 have a structure in which the same material is formed on the same layer. In addition, the source-drain electrode constituting the first thin film transistor T1 and the source-drain electrode constituting the second thin film transistor T2 have a structure in which the same material is formed on the same layer.

The third embodiment described above has effects of low power consumption (Low Frequency) and low voltage (Oxide Saturation characteristic) by applying an oxide thin film transistor (Oxide TFT) to the display area AA, and the non-display area NA (eg: By applying a polysilicon thin film transistor (Poly-Silicon or LTPS TFT) to the GIP circuit of the gate driver or the MUX circuit of the data driver), it has the effect of satisfying the function requiring high mobility.

And in the third embodiment, since the gate electrodes and the source-drain electrodes constituting different types of thin film transistors are not separated from each other (formed on different layers) but are formed on the same layer, the mask is increased (added) in the manufacturing process. has the effect of preventing

<Fourth embodiment>

Hereinafter, a method of manufacturing a thin film transistor substrate for a display device including different types of thin film transistors according to a fourth embodiment of the present invention will be described with further reference to FIGS. 8 and 9 . 8 and 9 are cross-sectional views and process flowcharts illustrating a process of manufacturing a thin film transistor substrate for a display device including different types of thin film transistors according to a fourth embodiment of the present invention.

Meanwhile, in FIG. 8 , a plan view (a) and a cross-sectional view (b) are shown together in order to clearly show a part different from the third embodiment. In addition, hereinafter, one thin film transistor is formed in each of the non-display area and the pixel area of the display area as an example for convenience, but the number thereof is not limited thereto.

8 and 9 , in the thin film transistor substrate for a display device according to the fourth embodiment of the present invention, a first thin film transistor T1 and a second thin film transistor T2 are disposed on the substrate SUB to be spaced apart from each other. ) is included. The first and second thin film transistors T1 and T2 may be spaced apart considerably apart, or may be disposed relatively adjacent to each other and spaced apart from each other.

A buffer layer BUF is deposited on the substrate SUB (S100). The buffer layer BUF may be formed of a single layer or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx). The buffer layer BUF serves to improve adhesion between the layer to be formed later and the substrate SUB, and this may be omitted.

The first semiconductor layers A1 , SA1 , DA1 and the dummy semiconductor layer A12 are formed on the substrate SUB on which the buffer layer BUF is formed ( S110 ). A semiconductor layer material is deposited on the buffer layer BUF and patterned by a first mask process to form first semiconductor layers A1 , SA1 , DA1 and a dummy semiconductor layer A12 .

The first semiconductor layers A1 , SA1 and DA1 include a channel region A1 , a source region SA1 , and a drain region DA1 of the first thin film transistor T1 , and the dummy semiconductor layer A12 includes the first It is formed of the same semiconductor material as the semiconductor layers A1 , SA1 , and DA1 , but serves only to block light incident from the outside. The channel region, source region and drain region are defined by ion doping.

The first thin film transistor T1 including the first semiconductor layers A1 , SA1 and DA1 may include a polycrystalline semiconductor material such as poly-silicon. In addition, the first thin film transistor T1 preferably has a top-gate structure. The first semiconductor layers A1 , SA1 , and DA1 become poly-silicon by depositing an amorphous silicon (a-Si) material and performing dehydrogenation and crystallization. On the other hand, the dummy semiconductor layer A12 serving as a light blocking layer may exist in an amorphous silicon (a-Si) state without being crystallized.

A first gate insulating layer GI1 is deposited on the surface of the substrate SUB on which the first semiconductor layers A1 , SA1 , DA1 and the dummy semiconductor layer A12 are formed ( S120 ). The first gate insulating layer GI1 serves as a gate insulating layer in the non-display area NA, but functions as a lower buffer layer in the display area AA.

First and second metal electrode layers GP and LS are formed on the first gate insulating layer GI1 ( S200 ). A metal material (eg, MoTi) is formed on the first gate insulating layer GI1 and patterned by a second mask process to form first and second metal electrode layers GP and LS. Using the first metal electrode layer GP as a mask, ions are doped into the lower first semiconductor layers A1 , SA1 , and DA1 .

The first metal electrode layer GP is disposed to overlap the channel region A1 of the first semiconductor layers A1 , SA1 , and DA1 . The second metal electrode layer LS is disposed to overlap the dummy semiconductor layer A12 . The first metal electrode layer GP serves as a gate electrode of the first thin film transistor T1 but is formed in an island shape. Therefore, the gate electrode is electrically connected to the gate wiring by a subsequent process. On the other hand, the second metal electrode layer LS serves as a light blocking layer like the dummy semiconductor layer A12 . That is, the embodiment of the present invention has a double light blocking layer.

The dummy semiconductor layer A12 is present to prevent (block) a problem that light incident from the outside is incident on the inside (oxide semiconductor layer), but it is at a distance from the oxide semiconductor layer formed later. Therefore, the second metal electrode layer LS is positioned close to the oxide semiconductor layer in order to assist the light blocking ability of the dummy semiconductor layer A12 . To this end, the second metal electrode layer LS may have a size similar to or corresponding to that of the dummy semiconductor layer A12, but is not limited thereto.

A first intermediate insulating layer ILD1 is deposited on the entire surface of the substrate SUB on which the first and second metal electrode layers GP and LS are formed (S210). The first intermediate insulating layer ILD1 is selected as a nitride layer SIN including silicon nitride (SiNx).

A second semiconductor layer A2 is formed on the first intermediate insulating layer ILD1 on which the second metal electrode layer LS is formed ( S220 ). An oxide semiconductor material (eg, IGZO) is formed on the first intermediate insulating layer ILD1 and patterned by a third mask process to form a second semiconductor layer A2 and heat treatment is performed.

A second gate insulating layer GI2 is deposited on the second semiconductor layer A2 and heat-treated ( S310 ). The second gate insulating layer GI2 is preferably formed of silicon oxide (SiOx). In the case of the second gate insulating layer GI2, it is preferable to have a thickness of about 1,000 to 1,500 Å in consideration of device stability and characteristics.

Third and fourth metal electrode layers G1 and G2 are formed on the second gate insulating layer GI2 (S400). A metal material (eg, Cu) is formed on the second gate insulating layer GI2 and patterned by a fourth mask process to form third and fourth metal electrode layers G1 and G2.

The third metal electrode layer G1 is disposed adjacent to the first metal electrode layer GP. Specifically, the third metal electrode layer G1 should be disposed in a region that can be electrically connected to the first metal electrode layer GP in a subsequent process. To this end, when the first metal electrode layer GP is disposed to be elongated in the vertical direction, the third metal electrode layer G1 may be disposed to be elongated in the horizontal direction (refer to FIG. 8A ).

The fourth metal electrode layer G2 is disposed to overlap the second semiconductor layer A2. The third metal electrode layer G1 becomes a gate electrode of the first thin film transistor T1 , and the fourth metal electrode layer G2 becomes a gate electrode of the second thin film transistor T2 . As described above, since the gate electrodes are formed by the same mask, the manufacturing process can be simplified.

A second intermediate insulating layer ILD2 is deposited on the first intermediate insulating layer ILD1 on which the third and fourth metal electrode layers G1 and G2 are formed ( S500 ). The second intermediate insulating layer ILD2 is selected as an oxide layer SIO including silicon oxide (SiOx). A portion of the first semiconductor layer A1, SA1, DA1, a portion of the second semiconductor layer A2, and a portion of the third metal electrode layer G1 by forming the second intermediate insulating layer ILD2 and patterning it by a fifth mask process , a contact hole exposing a portion of the first metal electrode layer GP and a portion of the second metal electrode layer LS is formed.

First source-drain electrodes S1 and D1 , second source-drain electrodes S2 and D2 , and dummy source-drain electrodes SD (integrated source-drain electrodes) are formed on the second intermediate insulating layer ILD2 . (S600). A source-drain material is formed on the second intermediate insulating layer ILD2 and patterned by a sixth mask process to form the first source-drain electrodes S1 and D1, the second source-drain electrodes S2 and D2, and the dummy source-drain An electrode SD (integrated source-drain electrode) is formed.

The first source electrode S1 is connected to the source region SA1 of the third metal electrode layer G1 and the first semiconductor layers A1, SA1 and DA1 through the first contact hole SH1, and a first drain electrode D1 is connected to the drain region DA1 of the first semiconductor layers A1 , SA1 and DA1 through the second contact hole DH1 . The first source-drain electrodes S1 and D1 become source-drain electrodes of the first thin film transistor T1.

The second source electrode S2 is connected to the source region of the second metal electrode layer LS and the second semiconductor layer A2 through the third contact hole SH2 , and the second drain electrode D2 has a fourth contact It is connected to the drain region of the second semiconductor layer A2 through the hole DH2. The second source-drain electrodes S2 and D2 become source-drain electrodes of the second thin film transistor T2. Since the second metal electrode layer LS is electrically connected to the second source electrode S2, it is electrically more stable than when it is in a floating state and can serve as a light blocking layer.

The dummy source-drain electrode SD is connected to the first metal electrode layer GP and the third metal electrode layer G1 through the fifth contact hole GH. The first metal electrode layer GP and the third metal electrode layer G1 are electrically connected to each other by the dummy source-drain electrode SD. That is, the dummy source-drain electrode SD serves as a connection electrode electrically connecting the first metal electrode layer GP and the third metal electrode layer G1.

A passivation layer PAS is deposited on the second intermediate insulating layer ILD2 on which the first source-drain electrodes S1 and D1, the second source-drain electrodes S2 and D2, and the dummy source-drain electrode SD are formed ( S610). Thereafter, a contact hole exposing the first drain electrode D1 and/or the second drain electrode D2 may be further formed by patterning the passivation layer PAS.

In addition, a reflective plate, a color filter, a planarization layer, etc. may be further formed on the passivation layer PAS along with the pixel electrode in contact with the first drain electrode D1 and/or the second drain electrode D2 exposed through the contact hole. have. The thin film transistor substrate for a display device is implemented as a display device such as a liquid crystal display device or an organic light emitting display device according to the shape of an electrode or structure formed after the pixel electrode. However, for convenience of description, only parts showing the structure of the thin film transistors representing the main features of the present invention are illustrated and described herein.

Meanwhile, an external light blocking layer OLS may be further formed on the outer surface of the substrate SUB. The external light blocking layer OLS is made of an opaque material and has an area large enough to cover the entire region occupied by the first thin film transistor T1 . The external light-shielding layer OLS may be selected as an appliance made of plastic or the like or a black-based tape, but is not limited thereto.

As described above, in the thin film transistor substrate for a display device according to the fourth embodiment of the present invention, the first thin film transistor T1 including the polycrystalline semiconductor material and the second thin film transistor T2 including the oxide semiconductor material are the same substrate ( SUB) has a structure formed on it. In particular, the gate electrode constituting the first thin film transistor T1 and the gate electrode constituting the second thin film transistor T2 have a structure in which the same material is formed on the same layer. In addition, the source-drain electrode constituting the first thin film transistor T1 and the source-drain electrode constituting the second thin film transistor T2 have a structure in which the same material is formed on the same layer. Moreover, it has a structure which has a double light-shielding layer.

The fourth embodiment described above has effects of low power consumption (Low Frequency) and low voltage (Oxide Saturation characteristic) by applying an oxide TFT to the display area AA, and the non-display area NA (eg: By applying a polysilicon thin film transistor (Poly-Silicon or LTPS TFT) to the GIP circuit of the gate driver or the MUX circuit of the data driver), it has the effect of satisfying the function requiring high mobility.

And in the fourth embodiment, since the gate electrodes and the source-drain electrodes constituting different types of thin film transistors are not separated from each other (formed on different layers) but are formed on the same layer, the mask is increased (added) in the manufacturing process. has the effect of preventing

As described above, the thin film transistor substrate and the display device using the same according to the present invention may have a feature that the other thin film transistors compensate for the disadvantages of one thin film transistor by forming two different types of thin film transistors on the same substrate. In particular, it is possible to provide a display device suitable for portable and/or wearable devices by reducing power consumption by providing a thin film transistor having low-speed driving characteristics.

Hereinafter, application examples of the thin film transistors of the first to fourth embodiments described above will be described.

10 is a block diagram schematically showing the configuration of a display device according to a first application example of the present invention, and FIG. 11 is a fringe field type liquid crystal display device of a horizontal electric field type according to a second application example of the present invention. It is a plan view showing a thin film transistor substrate having an oxide semiconductor layer included, FIG. 12 is a cross-sectional view of the thin film transistor substrate shown in FIG. 11 taken along the perforated line I-I', and FIG. 13 is an active according to a third application example of the present invention It is a plan view showing the structure of one pixel in the matrix organic light emitting diode display, FIG. 14 is a cross-sectional view showing the structure of the active matrix organic light emitting display device cut along the perforated line II-II' in FIG. 13, and FIG. 15 is a fourth application of the present invention It is a plan enlarged view showing a schematic structure of an organic light emitting diode display according to an example, and FIG. 16 is a view taken along the cut line III-III' in FIG. 15 showing the structure of an organic light emitting display device according to a fourth application example of the present invention. It is a cross section.

<First application example>

As shown in FIG. 10 , one or more of the aforementioned thin film transistors may be thin film transistors formed in each of the pixels of the panel 100 to switch data voltages written to the pixels or to drive the pixels. In the case of an organic light emitting diode display, the first thin film transistor located in the non-display area may be applied as a driving element, and the second thin film transistor located in the display area may be applied as a switch element of a pixel, but is not limited thereto. For example, in the embodiments, the thin film transistor is divided into a display area and a non-display area and is positioned in a divided form as an example, but these may be combined and applied as one switch element or one driving element (eg CMOS TFT). Because.

In order to reduce power consumption in a mobile device or a wearable device corresponding to a small size among display devices, a low-speed driving method of lowering a frame rate has been attempted. In this case, the frame frequency of a still image or an image having a slow data update period may be lowered. However, when the frame rate is lowered, a phenomenon in which the luminance flickers whenever the data voltage is changed, or a flicker phenomenon in which the luminance flickers in response to the data update period due to a prolonged discharge time of the pixel voltage may be observed. However, if the thin film transistors described in the embodiments of the present invention are applied to the pixel, the flicker problem during low-speed driving can be solved.

When the data update period is long during low-speed driving, the amount of leakage current of the switch thin film transistor increases. The leakage current of the switch thin film transistor causes a drop in the voltage of the storage capacitor and the low voltage between the gate and the source of the driving thin film transistor. According to the present invention, the second thin film transistor, which is an oxide transistor, can be applied as a switch thin film transistor of a pixel. Since the oxide transistor has a low off-current, it is possible to prevent a decrease in the gate-source potential of the storage capacitor and the driving thin film transistor. Accordingly, the present invention can prevent flicker when driving at a low speed.

Since the first thin film transistor, which is a polysilicon transistor, has high electron mobility, when it is applied as a driving thin film transistor of a pixel, the amount of current supplied to the organic light emitting diode can be increased. Accordingly, according to the present invention, by applying the second thin film transistor to the switch element of the pixel and the first thin film transistor to the driving element of the pixel, power consumption can be greatly reduced and image quality deterioration can be prevented.

The present invention is effective for application to a mobile device or a wearable device because image quality deterioration can be prevented when a low-speed driving method is applied to reduce power consumption. For example, the portable electronic watch may update data on the display screen in units of 1 second to reduce power consumption. In this case, the frame frequency is 1 Hz. According to the present invention, excellent image quality without flicker can be realized even using a driving frequency close to 1 Hz or a still image. The present invention greatly reduces the frame rate of a still image on a standby screen of a mobile device or a wearable device, thereby significantly reducing power consumption without degrading image quality. As a result, the present invention can improve portability by improving the picture quality of a mobile device or a wearable device and extending the battery life. According to the present invention, power consumption can be greatly reduced without deterioration of image quality even in an E-Book with a very long data update cycle.

At least one of the first and second thin film transistors may be embedded in a driving circuit, for example, at least one of the data driver 200 , the multiplexer MUX 210 , and the gate driver 300 to configure the driving circuit. Also, one of the first and second thin film transistors may be formed in the pixel and the other one may be formed in the driving circuit. The data driver 200 converts the data of the input image into a data voltage and outputs it. The multiplexer 210 reduces the number of output channels of the data driver 200 by time division distribution of the data voltage from the data driver 200 to the plurality of data lines DL. The gate driver 300 outputs a scan signal (or gate signal) synchronized with the data voltage to sequentially select pixels in which data of the input image is written in line units. In order to reduce the number of output channels of the gate driver 300 , a multiplexer (not shown) may be added between the gate driver 300 and the gate lines DL. Meanwhile, the multiplexer 210 and the gate driver 300 are disposed in the non-display area NA, and the pixel array is disposed in the display area AA.

<Second application example>

11 and 12 , a thin film transistor substrate having a metal oxide semiconductor layer includes a gate line GL and a data line DL crossing the lower substrate SUB with the gate insulating layer GI interposed therebetween. , a thin film transistor T formed at each intersection thereof. In addition, a pixel area is defined by the cross structure of the gate line GL and the data line DL.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D facing the source electrode S, and a gate When overlapping the gate electrode G on the insulating layer GI, the semiconductor layer A having a channel region between the source electrode S and the drain electrode D is included.

A gate pad GP for receiving a gate signal from the outside is disposed at one end of the gate line GL. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 penetrating the gate insulating layer GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 penetrating the first passivation layer PA1 and the second passivation layer PA2 . Meanwhile, a data pad DP for receiving a pixel signal from the outside is disposed at one end of the data line DL. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH penetrating the first passivation layer PA1 and the second passivation layer PA2 .

In the pixel area, the pixel electrode PXL and the common electrode COM are provided with the second passivation layer PA2 interposed therebetween to form a fringe field. The common electrode COM may be connected to the common line CL arranged in parallel with the gate line GL. The common electrode COM receives a reference voltage (or a common voltage) for driving the liquid crystal through the common line CL. Alternatively, the common electrode COM may have a shape disposed on the entire surface of the substrate SUB except for a portion where the drain contact hole DH is disposed. That is, the common electrode COM may function to shield the data line DL by covering the upper layer of the data line DL.

The positions and shapes of the common electrode COM and the pixel electrode PXL may have various shapes according to a design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that changes frequently according to video data to be implemented is applied to the pixel electrode PXL. Accordingly, a parasitic capacitance may be generated between the data line DL and the pixel electrode PXL. Since such a parasitic capacitance may cause a problem in image quality, it is preferable to arrange the common electrode COM first and the pixel electrode PXL on the uppermost layer.

That is, after forming the planarization layer PAC by thickly stacking an organic material having a low dielectric constant on the first passivation layer PA1 covering the data line DL and the thin film transistor T, the common electrode COM is formed. Then, after the second passivation layer PA2 covering the common electrode COM is formed, the pixel electrode PXL overlapping the common electrode COM is formed on the second passivation layer PA2 . In this structure, since the pixel electrode PXL is spaced apart by the data line DL, the first passivation layer PA1, the planarization layer PAC, and the second passivation layer PA2, the data line DL and the pixel electrode PXL It is possible to reduce the parasitic capacity in between. However, the present invention is not limited thereto, and in some cases, the pixel electrode PXL may be disposed first, and the common electrode COM may be disposed on the uppermost layer.

The common electrode COM has a rectangular shape corresponding to the shape of the pixel area, and the pixel electrode PXL has a plurality of line segment shapes. In particular, the pixel electrode PXL has a structure that vertically overlaps the common electrode COM with the second passivation layer PA2 interposed therebetween. Accordingly, a fringe field is formed between the pixel electrode PXL and the common electrode COM. Liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate rotate due to dielectric anisotropy by the fringe field type electric field. In addition, the transmittance of light passing through the pixel region varies according to the degree of rotation of the liquid crystal molecules to realize grayscale.

In the drawings for explaining the second application example of the present invention, the structure of the thin film transistor in the liquid crystal display is only schematically shown for convenience. However, the structures of the thin film transistors described in the first to fourth embodiments of the present invention may be applied. For example, when low-speed driving is required, a thin film transistor having an oxide semiconductor layer may be applied. When low power consumption is required, a thin film transistor having a polycrystalline semiconductor layer may be applied. Alternatively, the thin film transistors may be configured to be connected to each other and configured to complement each other.

<Third application example>

13 and 14 , the active matrix organic light emitting diode display includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor, and an organic light emitting diode connected to the driving thin film transistor DT ( OLE).

The switching thin film transistor ST is disposed on the substrate SUB at a portion where the gate line GL and the data line DL intersect. The switching thin film transistor ST has a function of selecting a pixel by supplying a data voltage from the data line DL to the gate electrode DG and the storage capacitor STG of the driving thin film transistor DT in response to a scan signal do The switching thin film transistor ST includes a gate electrode SG branching from the gate line GL, a semiconductor layer SA, a source electrode SS, and a drain electrode SD. The driving thin film transistor DT drives the organic light emitting diode OLE of the pixel selected by the switching thin film transistor ST by controlling the current flowing through the organic light emitting diode OLE of the pixel according to the gate voltage.

The driving thin film transistor DT has a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor layer DA, a source electrode DS connected to the driving current line VDD, and a drain and an electrode DD. The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE. An organic light emitting layer OL is interposed between the anode electrode ANO and the cathode electrode CAT. The cathode electrode CAT is connected to the base line VSS.

Gate electrodes SG and DG of the switching thin film transistor ST and the driving thin film transistor DT are disposed on the substrate SUB of the active matrix organic light emitting diode display. In addition, the gate insulating layer GI covers the gate electrodes SG and DG. The semiconductor layers SA and DA are disposed on a portion of the gate insulating layer GI overlapping the gate electrodes SG and DG. On the semiconductor layers SA and DA, the source electrodes SS and DS and the drain electrodes SD and DD are disposed to face each other with a predetermined interval therebetween. The drain electrode SD of the switching thin film transistor ST contacts the gate electrode DG of the driving thin film transistor DT through the drain contact hole DH passing through the gate insulating layer GI. A protective film PAS covering the switching thin film transistor ST and the driving thin film transistor DT having such a structure is stacked on the entire surface.

A color filter CF is disposed in a portion corresponding to the region of the anode electrode ANO. The color filter CF preferably has as wide an area as possible. For example, it is preferable to have a shape overlapping with many regions of the data line DL, the driving current line VDD, and the gate line GL of the previous stage. As described above, the surface of the substrate on which the switching thin film transistor ST, the driving thin film transistor DT, and the color filters CF are disposed is not flat and the level difference is severe. The organic light emitting layer OL should be laminated on a flat surface so that light emission can be uniformly and evenly emitted. Accordingly, a planarization film (PAC) or an overcoat layer (OC) is laminated on the entire surface of the substrate for the purpose of flattening the surface of the substrate.

And the anode electrode ANO of the organic light emitting diode OLE is disposed on the overcoat layer OC. Here, the anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the pixel contact hole PH formed in the overcoat layer OC and the passivation layer PAS.

On the substrate on which the anode electrode ANO is disposed, the bank BA is disposed on the region where the switching thin film transistor ST, the driving thin film transistor DT, and various wirings DL, GL, and VDD are disposed to define a pixel area. (or bank pattern) is arranged. The anode electrode ANO exposed by the bank BA becomes a light emitting area. An organic light emitting layer OL is stacked on the anode ANO exposed by the bank BA. In addition, a cathode electrode CAT is sequentially stacked on the organic light emitting layer OL. When the organic light emitting layer OL is made of an organic material emitting white light, a color assigned to each pixel is displayed by the color filter CF positioned below. The organic light emitting display device having such a structure becomes a bottom emission display device that emits light in a downward direction.

A storage capacitor (or 'Storage Capacitance') STG is disposed between the gate electrode DG and the anode electrode ANO of the driving thin film transistor DT. The storage capacitor STG is connected to the driving thin film transistor DT so that a voltage applied to the gate electrode DG of the driving thin film transistor DT by the switching thin film transistor ST is stably maintained.

By applying the thin film transistor substrate as described above, it is possible to realize a high-quality active display device. In particular, in order to have better driving characteristics, it is preferable that the semiconductor layer of the thin film transistor is formed of a metal oxide semiconductor material.

The metal oxide semiconductor material has a characteristic that its characteristics are rapidly deteriorated when it is voltage driven in a state of being exposed to light. Accordingly, it is desirable to have a structure capable of blocking light entering from the outside in the upper and lower portions of the semiconductor layer. In the case of the thin film transistor substrate described above, the thin film transistor preferably has a bottom gate structure. That is, light entering from the bottom may be blocked to some extent by the gate electrode G, which is a metal material.

As described above, a plurality of pixel regions arranged in a matrix manner are arranged in a thin film transistor substrate for a display device so far. In addition, at least one thin film transistor is disposed in each of the unit pixel areas. That is, it has a structure in which a plurality of thin film transistors are distributed over the entire area of the substrate. Since the respective structures of the plurality of pixels must all be used for the same purpose and have the same quality and properties, they are formed with the same structure.

However, in some cases, it may be necessary to have different characteristics of the thin film transistors. For example, in the case of an organic light emitting diode display, a switching thin film transistor ST and a driving thin film transistor DT are included in one pixel area. Since the purpose of the switching thin film transistor ST and the driving thin film transistor DT are different from each other, the required characteristics are also different. To this end, it can be designed to have the same structure and the same semiconductor channel layer but have different sizes to suit each function. Alternatively, if necessary, a compensation thin film transistor may be further provided to supplement the function or performance.

In the drawings for explaining the third application example of the present invention, the structures of the thin film transistors ST and DT of the organic light emitting diode display are only schematically illustrated for convenience. However, the structures of the thin film transistors described in the first to fourth embodiments of the present invention may be applied. For example, a thin film transistor having an oxide semiconductor layer may be applied to the switching thin film transistor ST. As the driving thin film transistor DT, a thin film transistor having a polycrystalline semiconductor layer can be applied. In this way, the thin film transistors can complement each other's disadvantages with each other's advantages.

<Fourth application example>

As shown in FIGS. 15 and 16 , after the structure on a plane is described, the structure on a cross section will be described. An organic light emitting diode display including a driving element (GIP) according to a fourth application example of the present invention includes a display area AA displaying image information and a non-display area in which various elements for driving the display area AA are disposed. It includes a substrate SUB divided into regions NA. A plurality of pixel areas PA arranged in a matrix manner is defined in the display area AA.

For example, the pixel areas PA may be defined as an NxM rectangle. However, it is not necessarily limited to this method, and may be arranged in various ways. Each pixel area may have the same size or may have different sizes. In addition, three sub-pixels representing RGB (red, green, blue) colors may be regularly arranged as one unit. In the simplest structure, the pixel areas PA have a cross structure of a plurality of gate lines GL running in a horizontal direction and a plurality of data lines DL and driving current lines VDD running in a vertical direction. can be defined as

A data driver (or Data Driving Integrated Circuit) (DIC) for supplying a signal corresponding to image information to the data lines DL in the non-display area NA, which is defined on the outer periphery of the pixel area PA; A gate driver (or, a gate driving integrated circuit) (GIP) for supplying a scan signal to the gate wirings GL may be disposed. In the case of high resolution higher than the VGA level, in which the number of data lines DL and driving current lines VDD increases, the data driver DIC is mounted on the outside of the substrate SUB, and the data driver DIC ) instead of data connection pads may be arranged.

In order to simplify the structure of the display device, the gate driver GIP is preferably directly formed on one side of the substrate SUB. In addition, a base line Vss for supplying a base voltage is disposed at the outermost portion of the substrate SUB. It is preferable that the ground wiring Vss is arranged to receive a ground voltage supplied from the outside of the substrate SUB and supply the ground voltage to both the data driver DIC and the gate driver GIP. For example, the electrical wiring Vss is connected to the data driver DIC to be separately mounted on the upper side of the substrate SUB, and the gate driver GIP is disposed on the left and/or right side of the substrate SUB. It may be disposed as if wrapping the substrate from the outside of the.

In each pixel area PA, an organic light emitting diode, which is a key component of an organic light emitting diode display, and thin film transistors for driving the organic light emitting diode are disposed. The thin film transistors may be disposed in the thin film transistor area TA defined at one side of the pixel area PA. The organic light emitting diode includes an anode electrode ANO, a cathode electrode CAT, and an organic light emitting layer OL interposed between the two electrodes. The area that actually emits light is determined by the area of the organic light emitting layer overlapping the anode electrode ANO.

The anode electrode ANO has a shape that occupies a portion of the pixel area PA and is connected to the thin film transistor disposed in the thin film transistor area TA. An organic light emitting layer OL is stacked on the anode ANO, and an area where the anode ANO and the organic light emitting layer OL overlap is determined as an actual light emitting area. The cathode electrode CAT is formed as a single body so as to cover at least an area of the display area AA in which the pixel areas PA are disposed on the organic light emitting layer OL.

The cathode electrode CAT crosses the gate driver GIP and contacts the base line Vss disposed on the outer side of the substrate SUB. That is, the ground voltage is applied to the cathode electrode CAT through the ground line Vss. The cathode electrode CAT receives the base voltage, the anode electrode ANO receives the image voltage, and the organic light emitting layer OL emits light by the voltage difference therebetween to display image information.

The non-display area NA in which the gate driver GIP and the base wiring Vss are disposed on the substrate SUB, and the switching thin film transistor ST, the driving thin film transistor DT, and the organic light emitting diode OLE are disposed on the substrate SUB. A display area AA is defined.

The gate driver GIP may include a thin film transistor formed together in the process of forming the switching thin film transistor ST and the driving thin film transistor DT. The switching thin film transistor ST disposed in the pixel area PA includes a gate electrode SG, a gate insulating layer GI, a channel layer SA, a source electrode SS, and a drain electrode SD. In addition, the driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a gate insulating layer GI, a channel layer DA, a source electrode DS, and a drain electrode ( DD).

A passivation layer PAS and a planarization layer PL are sequentially stacked on the thin film transistors ST and DT. An isolated rectangular anode electrode ANO occupying only a certain portion of the pixel area PA is disposed on the planarization layer PL. The anode electrode ANO contacts the drain electrode DD of the driving thin film transistor DT through a contact hole penetrating the passivation layer PAS and the planarization layer PL.

A bank BA defining a light emitting area is disposed on the substrate on which the anode electrode ANO is formed. The bank BA has a shape exposing most of the anode electrode ANO. An organic light emitting layer OL is stacked on the anode electrode ANO exposed by the bank BA pattern. A cathode electrode CAT made of a transparent conductive material is stacked on the bank BA and the organic light emitting layer OL. Accordingly, the organic light emitting diode OLE including the anode electrode ANO, the organic light emitting layer OL and the cathode electrode CAT is disposed.

The organic light emitting layer OL may emit white light, and a color may be expressed using a separately formed color filter CF. In this case, the organic light emitting layer OL is preferably stacked to cover at least all of the display area AA.

The cathode electrode CAT preferably covers the display area AA and the non-display area NA so as to be in contact with the base line Vss disposed on the outer side of the substrate SUB beyond the gate driver GIP. Accordingly, the ground voltage may be applied to the cathode electrode CAT through the ground line Vss.

Meanwhile, the base wiring Vss may be formed of the same material as the gate electrode G and on the same layer. In this case, the cathode electrode CAT may be in contact with the passivation layer PAS covering the base line Vss and the contact hole penetrating the gate insulating layer GI. Alternatively, the base wiring Vss may be formed of the same material as the source-drain electrodes SS-SD and DS-DD on the same layer. In this case, the base line Vss may contact the cathode electrode CAT through a contact hole penetrating the passivation layer PAS.

In the drawings for explaining the fourth application example of the present invention, for convenience, the thin film transistors ST and DT of the organic light emitting diode display and the thin film transistor structures of the gate driving device GIP are only schematically illustrated. However, the structures of the thin film transistors described in the first to fourth embodiments of the present invention may be applied. For example, a thin film transistor having an oxide semiconductor layer may be applied to the switching thin film transistor ST. As the driving thin film transistor DT, a thin film transistor having a polycrystalline semiconductor layer can be applied. In addition, a thin film transistor having a polycrystalline semiconductor layer may be applied to the gate driver GIP. If necessary, the gate driver GIP may include a C-MOS type thin film transistor having both a P-MOS type and an N-MOS type.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention can be changed to other specific forms by those skilled in the art to which the present invention pertains without changing the technical spirit or essential features of the present invention. It will be appreciated that this may be practiced. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. In addition, the scope of the present invention is indicated by the claims to be described later rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention.

GL: gate wiring
DL: data wire VDD: drive current wire
PA: pixel area T1 to T3: thin film transistor
AA: display area NA: non-display area
G1, G2, G3: gate electrode A1, A2, A3: semiconductor layer
S1, S2, S3: source electrode D1, D2, D3: drain electrode
GI, GI1, GI2: gate insulating film ILD1, ILD2: intermediate insulating film
PAS: Shield

Claims (6)

Board;
a first thin film transistor disposed on the substrate and including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and
a second thin film transistor disposed on the substrate to be spaced apart from the first thin film transistor and including an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode;
the first gate electrode and the second gate electrode are disposed spaced apart from each other in the same layer on the upper surface of the gate insulating film;
The first thin film transistor is
a first intermediate insulating layer disposed on the substrate and covering the polycrystalline semiconductor layer, a second intermediate insulating layer disposed on the first intermediate insulating layer, the first source electrode disposed on the second intermediate insulating layer, and the first a drain electrode, a gate insulating layer disposed on the second intermediate insulating layer and covering the first source electrode and the first drain electrode, and the first gate electrode disposed on the gate insulating layer,
The second thin film transistor is
A display device comprising: a dummy semiconductor layer formed in an island shape between the substrate and the oxide semiconductor layer; and the first intermediate insulating layer disposed on the dummy semiconductor layer. delete According to claim 1,
In the second thin film transistor, the oxide semiconductor layer is positioned on the second source electrode and the second drain electrode. Board;
a first thin film transistor disposed on the substrate and including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and
a second thin film transistor disposed on the substrate to be spaced apart from the first thin film transistor and including an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode;
The first gate electrode and the second gate electrode are disposed on different layers,
the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed to be spaced apart from each other in the same layer;
A dummy semiconductor layer formed in an island shape between the substrate and the oxide semiconductor layer is formed in an island shape insulated from the dummy semiconductor layer, is electrically connected to the second source electrode, and is disposed on the same layer as the first gate electrode. and a metal electrode layer insulated from the oxide semiconductor layer. 5. The method of claim 4,
wherein the first thin film transistor is disposed on a first intermediate insulating layer and a data line is further disposed in a region that does not overlap the first gate electrode. Board;
a first thin film transistor disposed on the substrate and including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and
a second thin film transistor disposed on the substrate to be spaced apart from the first thin film transistor and including an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode;
The first gate electrode and the second gate electrode are disposed on different layers,
the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed to be spaced apart from each other in the same layer;
The first thin film transistor
the first gate electrode positioned on the first intermediate insulating layer;
a gate metal electrode layer positioned under the first intermediate insulating film;
The first gate electrode is positioned on a second intermediate insulating film covering the first intermediate insulating film and made of the same layer and material as the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode. and a dummy source-drain electrode electrically connecting the gate metal electrode layer to the display device.

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