CN115938284A - Display panel and display device - Google Patents
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- CN115938284A CN115938284A CN202211413967.3A CN202211413967A CN115938284A CN 115938284 A CN115938284 A CN 115938284A CN 202211413967 A CN202211413967 A CN 202211413967A CN 115938284 A CN115938284 A CN 115938284A
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- 239000000758 substrate Substances 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 239000010703 silicon Substances 0.000 claims description 19
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000002834 transmittance Methods 0.000 abstract description 51
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- 238000005452 bending Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
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- 206010070834 Sensitisation Diseases 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
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Abstract
The invention discloses a display panel and a display device, wherein the display panel comprises: a substrate; a plurality of pixel driving circuits; the plurality of pixel driving circuits comprise a first pixel driving circuit and a second pixel driving circuit which are adjacently arranged along a first direction; a plurality of first power signal lines extending along the second direction and arranged in sequence along the first direction; the first direction intersects the second direction; the first power supply signal line is connected with the corresponding pixel driving circuit; the first pixel driving circuit and the second pixel driving circuit share one first power supply signal line, and the first power supply signal line is positioned between the first pixel driving circuit and the second pixel driving circuit; the pixel driving circuit includes a plurality of transistors; the transistor comprises an active layer and a grid electrode which is insulated from the active layer; the active layer of at least one transistor includes an oxide semiconductor. The technical scheme provided by the invention can optimize the pixel driving circuit and improve the light transmittance of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a display device.
Background
The organic light-emitting diode (OLED) display panel has the advantages of simple manufacturing process, low power consumption, light weight, fast response speed, wide viewing angle, high resolution, wide temperature characteristic and the like, and has a wide market application prospect.
At present, due to the extremely high screen ratio of the display panel, brand new visual experience and sensory impact are brought to people, and the display panel becomes a competitive pursuit target of display panel manufacturers. Set up photosensitive element often when needs set up photosensitive element and set up under the screen to see through display panel and acquire ambient light source and carry out sensitization control, realize comprehensive screen effect.
However, the structure of the pixel driving circuit for driving the OLED to emit light is complex, which causes the peripheral circuit for driving the pixel driving circuit to work to become very complex, and the display panel cannot meet the high-transmittance requirement, for example, when the photosensitive element is an off-screen camera, the photographing effect of the off-screen camera is poor.
Disclosure of Invention
The embodiment of the invention provides a display panel and a display device, which are used for optimizing a pixel driving circuit and improving the light transmittance of the display panel.
In a first aspect, an embodiment of the present invention provides a display panel, including: a substrate;
a plurality of pixel driving circuits; the plurality of pixel driving circuits comprise a first pixel driving circuit and a second pixel driving circuit which are adjacently arranged along a first direction;
a plurality of first power signal lines extending in a second direction and arranged in sequence in the first direction; the first direction intersects the second direction; the first power supply signal line is connected with the corresponding pixel driving circuit;
wherein the first pixel driving circuit and the second pixel driving circuit share one first power supply signal line, and the first power supply signal line is located between the first pixel driving circuit and the second pixel driving circuit;
the pixel driving circuit includes a plurality of transistors; the transistor comprises an active layer and a grid electrode which is arranged in an insulated mode with the active layer; the active layer of at least one of the transistors includes an oxide semiconductor.
In a second aspect, an embodiment of the present invention further provides a display device, including the display panel provided in any embodiment of the present invention.
In the invention, when pixel driving circuits arranged in an array are formed on a substrate, a first pixel driving circuit and a second pixel driving circuit are adjacently arranged along a first direction, the adjacent first pixel driving circuit and the adjacent second pixel driving circuit share one first power signal line, and the first power signal line extends along a second direction and is arranged between the first pixel driving circuit and the second pixel driving circuit. The arrangement of sharing a first power signal line between adjacent pixel drive circuits along the first direction, and a first power signal line is arranged for each pixel drive circuit, so that the wiring of the first power signal line can be effectively saved, the complexity of the pixel drive circuits is reduced, the light transmission area of the whole or partial pixel drive circuits is increased, a high-transmittance area is formed, the light transmission effect is better, transparent display can be realized in the high-transmittance area or a photosensitive device under a screen is arranged, and the design requirement of a display screen with diversified and attractive appearance of a user is met. In addition, in the embodiment, no matter the first pixel driving circuit or the second pixel driving circuit, the active layer of at least one of the transistors includes an oxide semiconductor, and the oxide semiconductor has higher light transmittance compared with a silicon semiconductor, so that the light transmittance of the pixel driving circuit is further enhanced, and the light transmittance requirement of a user on the high-transmittance region is met.
Drawings
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 2 is an enlarged view of a portion of the area A1 in FIG. 1;
FIG. 3 is a schematic diagram of a display panel according to the prior art;
fig. 4 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;
FIG. 5 is another enlarged partial view of the area A1 in FIG. 1;
FIG. 6 is another enlarged partial view of the area A1 in FIG. 1;
FIG. 7 is another enlarged partial view of the area A1 in FIG. 1;
FIG. 8 is another enlarged partial view of the area A1 in FIG. 1;
FIG. 9 is an enlarged partial view of the area A2 in FIG. 3;
FIG. 10 is a schematic diagram of the pixel driving circuit shown in FIG. 9;
fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
It should be understood that although the terms first, second, etc. may be used to describe the pixel driving circuits, the scan lines, the transistors, etc. in the embodiments of the present application, these pixel driving circuits, the scan lines, the transistors, etc. should not be limited to these terms. These terms are only used to distinguish pixel driving circuits, scanning lines, transistors, and the like from one another. For example, the first transistor may also be referred to as a second transistor, and similarly, the second transistor may also be referred to as a first transistor without departing from the scope of embodiments of the present application.
With the increasing demand of a user for high transmittance in a high transmittance region, an embodiment of the present invention mainly performs a re-layout and design on a driving circuit of a display panel to obtain a higher light transmittance without affecting the overall loading, as shown in fig. 1 and fig. 2, where fig. 1 is a schematic structural diagram of a display panel provided in an embodiment of the present invention, and fig. 2 is a schematic partial enlarged diagram of a region A1 in fig. 1, and an embodiment of the present invention provides a display panel, including: a substrate 11;
a plurality of pixel drive circuits 121; the plurality of pixel driving circuits 121 include a first pixel driving circuit 121a and a second pixel driving circuit 121b adjacently arranged in the first direction X;
a plurality of first power source signal lines 13 extending in the second direction Y and arranged in sequence in the first direction X; the first direction X intersects the second direction Y; the first power supply signal line 13 is connected to the corresponding pixel drive circuit 121 (the connection relationship of the first power supply signal line 13 to the corresponding pixel drive circuit 121 is not shown in fig. 1);
wherein the first pixel driving circuit 121a and the second pixel driving circuit 121b share one first power supply signal line 13, and the first power supply signal line 13 is located between the first pixel driving circuit 121a and the second pixel driving circuit 121b;
as shown in fig. 2, the pixel driving circuit 121 includes a plurality of transistors M (e.g., first transistors M1); the transistor M comprises an active layer B and a grid electrode G insulated from the active layer B; the active layer B of at least one transistor M includes an oxide semiconductor.
In the invention, when pixel driving circuits arranged in an array are formed on a substrate, a first pixel driving circuit and a second pixel driving circuit are adjacently arranged along a first direction, the adjacent first pixel driving circuit and the adjacent second pixel driving circuit share one first power signal line, and the first power signal line extends along a second direction and is arranged between the first pixel driving circuit and the second pixel driving circuit. The arrangement of sharing one first power signal wire between adjacent pixel driving circuits along the first direction, one first power signal wire is arranged for each pixel driving circuit, wiring of the first power signal wires can be effectively saved, the complexity of the pixel driving circuits is reduced, the light transmission area of the whole or partial pixel driving circuits is increased, a high-transmittance area is formed, the light transmission effect is good, transparent display can be achieved in the high-transmittance area or a photosensitive device under a screen is arranged, and the design requirement of a display screen with diversified and attractive appearance of a user is met. In addition, in the embodiment, no matter the first pixel driving circuit or the second pixel driving circuit, the active layer of at least one transistor in the transistors includes an oxide semiconductor, and the oxide semiconductor has higher light transmittance compared with a silicon semiconductor, so that the light transmittance of the pixel driving circuit is further enhanced, and the light transmittance requirement of a user on a high-transmittance region is met.
The above is the core idea of the present invention, and the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiment of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
As shown in fig. 1 and 2, the display panel includes a substrate 11 and a pixel 12 provided on the substrate 11, and the pixel 12 includes a light emitting device 122 and a pixel driving circuit 121 that drives the light emitting device 122 to emit light. The pixel driving circuit 121 is capable of generating a driving current to drive the light emitting device 122 so that the light emitting device 122 emits light in response to the driving current, displaying luminance to be displayed. The light emitting device 122 is a current type device, such as an organic light emitting device OLED, a micro light emitting diode Mirco LED or Mini LED, and the like, and the specific type of the light emitting device 122 in this embodiment is not particularly limited.
As shown in fig. 1, the display panel includes a display area AA and a non-display area NA at least partially surrounding the display area AA in a plane parallel to the substrate 11. A plurality of pixel driving circuits 121 may be disposed in the display area AA. In this embodiment, the pixel driving circuits 121 may be sequentially arranged along the first direction X, and the pixel driving circuits 121 may include a first pixel driving circuit 121a and a second pixel driving circuit 121b. The first pixel driving circuit 121a and the second pixel driving circuit 121b are adjacently disposed in the first direction X.
The display panel further includes a first power signal line 13, and the first power signal lines 13 may extend in a second direction Y and be sequentially arranged in a first direction X, the first direction X intersecting the second direction Y, and optionally, the first direction X and the second direction Y are perpendicular to each other. The first power supply signal line 13 is connected to the corresponding pixel driving circuit 121 for supplying the first power supply signal PVDD to the corresponding pixel driving circuit 121. The connection of the pixel driving circuits 121 to the corresponding first power supply signal lines 13 is not shown in fig. 1, but in general, the first power supply signal lines 13 are used to supply the first power supply signals to the pixel driving circuits 121 adjacent in the extending direction thereof. In the present embodiment, one first power supply signal line 13 is provided in a region between each pair of adjacent first and second pixel driving circuits 121a and 121b. The first power supply signal line 13 may supply a first power supply signal to the first pixel driving circuit 121a and the second pixel driving circuit 121b, respectively. As shown in fig. 3, fig. 3 is a schematic structural diagram of a display panel in the prior art, compared to a scheme in which each pixel driving circuit corresponds to one first power signal line in the same row of pixel driving circuits in the prior art. The display panel includes a display area AA 'and a non-display area NA'. In the row direction X ', each pixel 12' corresponds to one first power signal line 13', and each pixel driving circuit 121' corresponds to one first power signal line 13', and in this embodiment, the adjacent first pixel driving circuit 121a and the second pixel driving circuit 121b share one first power signal line 13, so that the embodiments of the present invention effectively save the number of the first power signal lines 13, effectively reduce the wiring complexity of the pixel driving circuits, increase the light transmittance of the pixel driving circuits, and facilitate the implementation of a high transmittance region for the setting of the photosensitive elements or the design of transparent display.
The pixel driving circuit 121 is generally formed by interconnecting a plurality of transistors M, each of which is provided with an active layer B and a gate electrode G spaced from the active layer B by an insulating layer, the active layer B of each transistor M overlying its corresponding gate electrode G in a plane parallel to the substrate 11, thereby forming a conductive channel such that each transistor M functions as a switching tube. It is to be noted that, in the present embodiment, the active layer B of at least one transistor M in the pixel driving circuit 121 includes an oxide semiconductor. As shown in fig. 2, for example, each pixel driving circuit 121 may include 7 transistors M, and in the present embodiment, the material of the active layer B of one or more transistors M of the 7 transistors M is provided as an oxide semiconductor. In the prior art, the active layer of the transistor of the pixel driving circuit in the display panel is generally selected to be a silicon semiconductor. For example, for a transistor in LTPS process, the active layer is selected to be low temperature polysilicon. In this application, the active layer B of a part of the transistors includes an oxide semiconductor. Illustratively, part of the transistors adopt an IGZO process, and the active layer of the transistors can be indium tin oxide. It should be noted that the light transmittance of the oxide semiconductor is higher than that of the silicon semiconductor, for example, the light transmittance of the indium tin oxide can reach 95%, and the light transmittance of the low-temperature polysilicon can only reach 85%, so in this embodiment, the active layer B of a part of the transistors in the pixel driving circuit 121 is set as the oxide semiconductor, which can further increase the light transmittance of the pixel driving circuit, is beneficial to forming a high-transmittance region meeting the user requirement, and improves the detection effect of the photosensitive element under the screen.
On the basis of the above embodiment, with continued reference to fig. 1 and 2, the display panel may further include: a plurality of data lines 14 extending in the second direction Y and arranged in sequence in the first direction X; the data line 14 includes a first data line 141 and a second data line 142; the first data line 141 is connected to the first pixel driving circuit 121 a; the second data line 142 is connected to the second pixel driving circuit 121b; the first data line 141 is located at a side of the first pixel driving circuit 121a close to the first power supply signal line 13; the second data line 142 is located at a side of the second pixel driving circuit 121b close to the first power supply signal line 13; the pixel drive circuit 121 includes: a first transistor M1, the first transistor M1 including a first active layer B1 and a first gate electrode G1; the first transistor M1 is used to provide a driving current for the light emitting device 122; a second transistor M2, the second transistor M2 including a second active layer B2 and a second gate electrode G2; a first end of the second active layer B2 is connected to the corresponding data line 14; a second end of the second active layer B2 is connected to a first end of the first active layer B1; in a plane parallel to the substrate 11, the first data line 141 covers the second active layer B2; and/or, the second data line 142 covers the second active layer B2.
As shown in fig. 1, the display panel further includes a data line 14, the data line 14 extends along the second direction Y for providing a data signal Vdata to the corresponding pixel driving circuit 121, in this embodiment, the data line 14 providing the data signal Vdata to the first pixel driving circuit 121a is referred to as a first data line 141, and the data line 14 providing the data signal Vdata to the second pixel driving circuit 121b is referred to as a second data line 142. As shown in fig. 1, the first data line 141 is disposed on a side of the first pixel driving circuit 121a close to the first power signal line 13, and the second data line 142 is disposed on a side of the second pixel driving circuit 121b close to the first power signal line 13, that is, in an area between the first pixel driving circuit 121a and the second pixel driving circuit 121b, the first data line 141, the first power signal line 13, and the second data line 142 are sequentially arranged.
Fig. 4 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention, and referring to fig. 2 and fig. 4, both the first pixel driving circuit 121a and the second pixel driving circuit 121b include a first transistor M1 and a second transistor M2. The first transistor M1 includes a first active layer B1 and a first gate G1, the first gate G1 covering the first active layer B1 at the plane of the substrate 11. It should be noted that, in this embodiment, each transistor M includes an active layer, and even the adjacent transistors M can be connected by the active layer, the arrangement range of the active layer can be larger, but only the gate portion covered by the active layer of the current transistor M is taken as the gate of the current transistor M, for example, the gate portion covered by the first active layer B1 is the first gate G1, and the gate portion covered by the second active layer B2 is the second gate G2. No matter the first pixel driving circuit 121a or the second pixel driving circuit 121B, the first end of the second active layer B2 is connected to the corresponding data line 14 through the via hole K1, and the second end of the second active layer B2 is connected to the first end of the first active layer B1, as shown in fig. 2, the second end of the second active layer B2 is directly connected to the first end of the first active layer B1 through the active layer without passing through the via hole, as shown in fig. 2, the first data line 141 may cover the second active layer B2 in a plane parallel to the substrate 11, so that the planar area of the pixel driving circuit occupied by the first data line 141 and the second active layer B2 is further reduced, the area of the light-transmitting region in the pixel driving circuit is increased, and the display panel with high transmittance is obtained. Alternatively, the second data line 142 may cover the second active layer B2, and the area of the light-transmitting region in the pixel driving circuit may be increased. On this basis, the first data line 141 can be controlled to cover the second active layer B2 of the first pixel driving circuit 121a, and the second data line 142 can be controlled to cover the second active layer B2 of the second pixel driving circuit 121B, so as to increase the area of the light-transmitting region in the first pixel driving circuit 121a and the second pixel driving circuit 121B to a greater extent, and obtain a high-quality high-transmittance region.
With continued reference to fig. 2 and 4, optionally, the display panel may further include: a plurality of reset signal lines Vref extending in the first direction X and arranged in sequence in the second direction Y; the pixel driving circuit 121 further includes: a third transistor M3, the third transistor M3 including a third active layer B3 and a third gate electrode G3; a first end of the third active layer B3 is connected to the first gate G1; a second end of the third active layer B3 is connected to a second end of the first active layer B1; a fourth transistor M4, the fourth transistor M4 including a fourth active layer B4 and a fourth gate electrode G4; a first end of the fourth active layer B4 is connected to the reset signal line Vref; a second end of the fourth active layer B4 is connected to a first end of the third active layer B3; the first active layer B1 and the second active layer B2 are disposed at the same layer and include a silicon semiconductor; the third active layer B3 and the fourth active layer B4 are disposed at the same layer and include an oxide semiconductor.
The pixel driving circuit 121 includes a third transistor M3 and a fourth transistor M4 in addition to the first transistor M1 and the second transistor M2. Similarly, the third transistor M3 includes a third active layer B3 and a third gate electrode G3, and the fourth transistor M4 includes a fourth active layer B4 and a fourth gate electrode G4. A first terminal of the third active layer B3 of the third transistor M3 is connected to the first gate electrode G1, and a second terminal thereof is connected to a second terminal of the first active layer B1. A first end of the fourth active layer B4 of the fourth transistor is connected to the reset signal line Vref through the via hole K2, and a second end thereof is connected to a first end of the third active layer B3 and also to the first gate G1 of the first transistor M1. It should be noted that in the present embodiment, the active layers of the first transistor M1 and the second transistor M2 are silicon semiconductors, and the first active layer B1 and the second active layer B2 can be disposed in the same layer. The active layers of the third transistor M3 and the fourth transistor M4 are oxide semiconductors, and the third active layer B3 and the fourth active layer B4 are disposed at the same layer. Since the active layers of the first transistor M1 and the third transistor M3 are located at different film layers, the second terminal of the first active layer B1 may be connected to the second terminal of the third active layer B3 through a via hole. The active layers of the third transistor M3 and the fourth transistor M4 are both oxide semiconductors, and the light transmittance thereof is higher than that of silicon semiconductors, so that the light transmittance of the region where the third transistor M3 and the fourth transistor M4 are located is high, thereby improving the light transmittance of the display panel as a whole. In addition, compared with a silicon semiconductor, the active layer of the oxide semiconductor reduces the leakage current of the corresponding transistor, which is beneficial to improving the accuracy of pixel display and improving the display effect of the whole display panel. In this embodiment, the active layer materials of the third transistor M3 and the fourth transistor M4 for controlling the driving transistor (the first transistor M1) are set as oxide semiconductors, which is beneficial to reducing the leakage current of the third transistor M3 and the fourth transistor M4, improving the accuracy of turning on and off the first transistor M1, and finally improving the accuracy of the driving current of the light emitting device.
With continued reference to fig. 2, optionally, a first end of the third active layer B3 is in communication with the first gate G1 through a first crossover 15; the second end of the third active layer B3 is connected to the second end of the first active layer B1 through a second flying lead 16. The first end of the third active layer B3 is connected to the first gate G1 through the first crossover 15, and the line change between the silicon semiconductor layer and the oxide semiconductor layer is completed through the second crossover 16. The first crossover 15 and the second crossover 16 both occupy a smaller area as much as possible, or at least partially overlap with other film layers as much as possible, so that the influence of the first crossover 15 and the second crossover 16 on the light transmittance is avoided. As shown in fig. 2, the first span line 15 is obliquely pulled and overlapped with the first gate G1 and other film layers as much as possible, so that the blocking of light is reduced, the second span line 15 is shorter, the occupation of a horizontal area can be reduced, and the light transmittance of the display panel is improved. Alternatively, the first and second flying leads 15, 16 may both be straight. The line segment is the shortest between the two points, in this embodiment, when the first end of the third active layer B3 is connected to the first gate G1, the linear first span line 15 is adopted, and when the second end of the third active layer B3 is connected to the second end of the first active layer B1, the linear second span line 16 is adopted, so that the bending setting of the first span line 15 is effectively reduced, the planar occupied area of the first span line 15 is further reduced, and the light transmittance of the display panel is improved.
With continued reference to fig. 2, optionally, the display panel may further include: a plurality of scanning lines extending along a first direction X and arranged in sequence along a second direction Y; the scanning line includes: a first scanning line S1, a second scanning line S2 and a third scanning line S3; the overlapping part of the first scanning line S1 and the second active layer B2 forms a second grid G2; the overlapping part of the second scanning line S2 and the fourth active layer B4 forms a fourth gate G4; the overlapping part of the third scanning line S3 and the third active layer B3 forms a third gate G3; in the pixel driving circuit, the reset signal line Vref, the second scan line S2, the first scan line S1, and the third scan line S3 are arranged in this order.
Because different active layer materials have different types of corresponding transistors, for example, a transistor made of silicon semiconductor material is often a P-type transistor and is turned on when a signal received by a gate is high, while a transistor made of oxide semiconductor material is often an N-type transistor and is turned on when a signal received by a gate is low. In this embodiment, each pixel driving circuit corresponds to a plurality of scan lines, extends along the first direction X and is sequentially arranged along the second direction Y, and each pixel driving circuit corresponds to a first scan line S1, a second scan line S2 and a third scan line S3. The gate of the transistor may be provided separately or may be formed in an overlapping portion of the scan line and the active layer. Illustratively, for the first transistor M1, the first gate electrode G1 is a separate structure, and for the second transistor M2, the third transistor M3 and the fourth transistor M4, the gate electrodes thereof are connected to the scan lines, so that the overlapping portion of the first scan line S1 and the second active layer B2 forms the second gate electrode G2, the overlapping portion of the third scan line S3 and the third active layer B3 forms the third gate electrode G3, and the overlapping portion of the second scan line S2 and the fourth active layer B4 forms the fourth gate electrode G4. In the second direction Y, the reset signal line Vref, the second scan line S2, the first scan line S1, and the third scan line S3 are sequentially arranged, as shown in fig. 2, the second scan line S2 is located on a side of the first scan line S1 away from the third scan line S3, the first transistor M1 is disposed close to the third scan line S3, the second transistor M2 needs to be connected to the first transistor M1 through the second active layer B2, the first scan line S1 forming the second gate G2 is closer to the third scan line S3, and the second active layer B2 of the silicon semiconductor material is advantageously disposed shorter. Compared with the second transistor M2, the third scan line S3 forms the third gate G3, the third transistor M3 is disposed close to the third scan line S3, and the second scan line S2 forming the fourth gate G4 is disposed farther from the third scan line S3, the fourth transistor M4 is disposed farther from the third transistor M3, and the active layer of the oxide semiconductor material between the fourth transistor M4 and the third transistor M3 is disposed longer, but because the light transmittance of the oxide semiconductor material is higher than that of the silicon semiconductor material, the active layer of the oxide semiconductor material of the present embodiment is disposed longer, and the active layer of the silicon semiconductor material is disposed shorter, so compared with the scheme that the first scan line S1 is disposed on the side of the second scan line S2 away from the third scan line S3, the present embodiment reduces the disposition length of the silicon semiconductor material as much as possible, increases the disposition length of the oxide semiconductor material, is beneficial to increase the light transmittance of the entire display panel as a whole, obtains a high-quality high-transmittance region of the display panel, and meets the requirement of a user for the high-transmittance region.
With continued reference to fig. 2, optionally, a first distance d1 is formed between the reset signal line Vref and the second scan line S2; a second space d2 is formed between the second scanning line S2 and the first scanning line S1; a third distance d3 is formed between the first scanning line S1 and the third scanning line S3; the third distance d3 is greater than the first distance d1, and the third distance d3 is greater than the second distance d2.
In this embodiment, the reset signal line Vref, the second scan line S2, the first scan line S1, and the third scan line S3 are sequentially arranged, where a first distance d1 exists between the reset signal line Vref and the second scan line S2, a second distance d2 exists between the second scan line S2 and the first scan line S1, and a third distance d3 exists between the first scan line S1 and the third scan line S3, and the distance in this embodiment refers to a gap between two signal lines, as shown in fig. 2, that is, a distance between edges of the two signal lines closest to each other. d3 > d1, and d3 > d2, then form great clearance between first scanning line S1 and the third scanning line S3, then this embodiment can emphasize first scanning line S1 and third scanning line S3 and reduce the setting of signal line and rete structure to form the higher high-transmittance region of luminousness between first scanning line S1 and third scanning line S3, more easily realize the transparent display of display panel, satisfy user' S high-transmittance demand.
Optionally, in an area between the first scan line S1 and the third scan line S3, the active layers from the second end of the third active layer B3 to the first end of the fourth active layer B4 extend along the second direction Y.
In the pixel driving circuit, the third transistor M3 is disposed adjacent to the first scan line S1, the fourth transistor M4 is disposed adjacent to the third scan line S3, and when the third transistor M3 is connected to the first end of the fourth active layer B4 of the fourth transistor M4 through the second end of the third active layer B3, it is directly connected through the active layer in the same layer as the third active layer B3 and the fourth active layer B4. In order to reduce the occupied area of the active layers from the second end of the third active layer B3 to the first end of the fourth active layer B4, the active layers may extend along the second direction Y, so as to reduce the bending along the first direction X as much as possible, thereby improving the light transmittance of the gap between the first scan line S1 and the third scan line S3. Optionally, if the third active layer B3 and the fourth active layer B4 are both made of an oxide semiconductor, the active layer from the second end of the third active layer B3 to the first end of the fourth active layer B4 is also made of an oxide semiconductor, and the oxide semiconductor has higher light transmittance than a silicon semiconductor, so that the light transmittance of the gap between the first scan line S1 and the third scan line S3 is further improved.
As shown in fig. 2, the first data line 141, the first power signal line 13, and the second data line 142 may be sequentially arranged, or in order to further reduce the width occupied by the three signal lines along the first direction X and increase the light transmittance of the pixel driving circuit, if the three signal lines are not disposed on the same layer, the signal lines between different layers may be disposed on the plane of the substrate 11 in an overlapping manner. As shown in fig. 5 and 6, fig. 5 is another partial enlarged schematic view of a region A1 in fig. 1, fig. 6 is another partial enlarged schematic view of the region A1 in fig. 1, and optionally, the first power signal line 13 and the first data line 141 at least partially overlap in a plane parallel to the substrate 11; and/or, the first power signal line 13 and the second data line 142 at least partially overlap. In this embodiment, the first data line 141 and the second data line 142 may be disposed in the same layer, the first power signal line 13 is disposed in another film layer, and referring to fig. 5, the first power signal line 13 may at least partially overlap the first data line 141 in a plane parallel to the substrate 11, and a schematic diagram of the partial overlap is shown in fig. 5, but of course, the first power signal line 13 may also completely cover the first data line 141, or, referring to fig. 6, the first power signal line 13 may at least partially overlap the second data line 142 in a plane parallel to the substrate 11, and similarly, a schematic diagram of the partial overlap is shown in fig. 6, and the first power signal line 13 may also completely cover the second data line 142, which is not particularly limited in this embodiment. The above-mentioned solutions can reduce the planar area of the display panel occupied by the first data line 141, the first power signal line 13, and the second data line 142 on the whole, so as to save space for arranging the high-transmittance region. Even more, the first power signal line 13 may overlap with both the first data line 141 and the second data line 142 to further reduce the planar area of the display panel occupied by the first data line 141, the first power signal line 13, and the second data line 142. It should be noted that, in order to clearly show the overlapping relationship between the data line 14 and the first power supply signal line 13, fig. 5 and 6 are intentionally widened to illustrate the width of the first power supply signal line 13 for clarity of film layer relationship, but in the present embodiment, the width of the first power supply signal line 13 in fig. 2, 5 and 6 is not changed, and the overlapping relationship between the first power supply signal line 13 and the data line 14 in fig. 5 and 6 is existed in comparison with fig. 2, because the gap between the first data line 141 and the second data line 142 is reduced, so that the overall occupied width of the first data line 141, the first power supply signal line 13 and the second data line 142 in the first direction X is reduced as a whole.
As shown in fig. 7, fig. 7 is another partially enlarged schematic view of the area A1 in fig. 1, and optionally, the projection of the first power signal line 13 covers the first data line 141 and the second data line 142 in a plane parallel to the substrate 11. When the first power signal line 13 may overlap with both the first data line 141 and the second data line 142, such that the first power signal line 13 covers both the first data line 141 and the second data line 142, the planar area of the display panel occupied by the first power signal line 141, the first power signal line 13, and the second data line 142 is further reduced, and the layout design of the pixel driving circuit is used to save space and improve the transmittance of the display panel without affecting the voltage drop of each signal, such as the voltage drop of the first power signal, the first data signal, and the second data signal, so as to maintain the original light emitting performance of the display panel.
When the projection of the first power signal line 13 covers the first data line 141 and the second data line 142, in addition to the covering relationship shown in fig. 7, as shown in fig. 8, fig. 8 is another partially enlarged schematic view of the area A1 in fig. 1, and optionally, the first power signal line 13 includes: a first portion 131, a second portion 132, and at least one connecting portion 133; the first portion 131 and the second portion 132 each extend in the second direction Y; the connection portion 133 connects the first portion 131 and the second portion 132; in a plane parallel to the substrate 11, the projection of the first portion 131 covers the first data line 141, and the projection of the second portion 132 covers the second data line 142. In this embodiment, the first power signal line 13 may further include a hollow structure, so that the first power signal line 13 covers the first data line 141 and the second data line 142 at the same time, but does not cover the gap between the first data line 141 and the second data line 142, thereby further increasing the light-transmitting area of the pixel driving circuit. Specifically, as shown in fig. 8, the first power supply signal line 13 includes a first portion 131, a second portion 132, and at least one connection portion 133, the first portion 131 covers the first data line 141, the second portion 132 covers the second data line 142, and the first portion 131 and the second portion 132 have the same potential and are connected through the connection portion 133.
Optionally, in this embodiment, the connection portion 133 is at least partially overlapped with other film layers of the pixel driving circuit, for example, as shown in fig. 8, because other film layers are connected to the first power signal line 13 through the via structure, the connection portion 133 may be disposed at a position where the via structure is disposed, so as to not occupy other regions where the film layer structure is not disposed, and improve the light-transmitting area of the pixel driving circuit. Optionally, the number of the connecting portions 133 may be multiple, so as to enhance the connection relationship between the first portion 131 and the second portion 132, improve the electrical potential stability on the first portion 131 and the second portion 132, and improve the display effect of the display panel.
With continued reference to fig. 8, alternatively, the adjacent first and second pixel driving circuits 121a and 121b are symmetrically disposed with respect to the first power supply signal line 13 therebetween in the first direction X. In order to facilitate the layout of the pixel driving circuits, the adjacent first pixel driving circuit 121a and the second pixel driving circuit 121b may be configured to be symmetrical with respect to the straight line where the first power signal line 13 is located, which is beneficial to concentrate the light-transmitting area and reduce the difficulty of circuit layout.
With continuing reference to fig. 2 and 4, optionally, the display panel may further include: a plurality of light emission control signal lines EMIT extending in a first direction X and arranged in sequence in a second direction Y; the pixel driving circuit further includes: the storage capacitor, the first pole Cb1 of the storage capacitor is multiplexed as the first grid G1; the second pole Cb2 of the storage capacitor is connected to the first power signal line 13; a fifth transistor M5 including a fifth active layer B5 and a fifth gate electrode G5; a first end of the fifth active layer B5 is connected to the first power signal line 13; a second end of the fifth active layer B5 is connected to a second end of the second active layer B2; a sixth transistor M6 including a sixth active layer B6 and a sixth gate electrode G6; a first end of the sixth active layer B6 is connected to a second end of the first active layer B1; a second end of the sixth active layer B6 is connected to a first end of the light emitting device 122; a seventh transistor M7 including a seventh active layer B7 and a seventh gate electrode G7; a first end of the seventh active layer B7 is connected to the reset signal line Vref; a second end of the seventh active layer B7 is connected to the first end of the light emitting device 122; the first, second, fifth, sixth, and seventh active layers B1, B2, B5, B6, and B7 are disposed at the same layer and include a silicon semiconductor; the overlapping portion of the light emission control signal line EMIT and the sixth active layer B6 forms a sixth gate G6; the overlapping portion of the light emission control signal line EMIT and the fifth active layer B5 forms a fifth gate electrode G5; the overlapping portion of the first scan line S1 and the seventh active layer B7 forms a seventh gate electrode G7.
Optionally, along the first direction X, the second poles Cb2 of the storage capacitors of every two adjacent pixel driving circuits are connected to form an auxiliary signal line 17; in each pixel driving circuit, the auxiliary signal line 17 is provided on the side of the third scanning line S3 away from the first scanning line S1; the light emission control signal line EMIT is provided on a side of the auxiliary signal line 17 away from the third scan line S3; a third distance d3 is formed between the first scanning line S1 and the third scanning line S3; a fourth interval d4 is formed between the light emission control signal line EMIT and the third scanning line S3; the third spacing d3 is greater than the fourth spacing d4.
The pixel driving circuit further comprises a storage capacitor, the storage capacitor comprises a first pole Cb1 and a second pole Cb2 which are oppositely arranged, the first pole Cb1 of the storage capacitor is connected with the gate of the first transistor M1, the first pole Cb1 of the storage capacitor can be used as the first gate G1, the second pole Cb2 of the storage capacitor is connected with the first power signal line 13, the second poles Cb2 of the storage capacitors of adjacent pixel driving circuits are connected along the first direction X to form an auxiliary signal line 17 extending along the first direction X, and the auxiliary signal line 17 can be connected with the first power signal line 13 through a through hole K3. The pixel driving circuit further includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. The fifth transistor M5 includes a fifth active layer B5 and a fifth gate electrode G5, the sixth transistor M6 includes a sixth active layer B6 and a sixth gate electrode G6, the seventh transistor M7 includes a seventh active layer B7 and a seventh gate electrode G7, an overlapping portion of the light emission control signal line EMIT and the sixth active layer B6 forms the sixth gate electrode G6, an overlapping portion of the light emission control signal line EMIT and the fifth active layer B5 forms the fifth gate electrode G5, and an overlapping portion of the first scan line S1 and the seventh active layer B7 forms the seventh gate electrode G7. Among them, the fifth transistor M5 and the sixth transistor M6 can form a driving current path sequentially with the first power supply signal line 13, the first transistor M1, and the first terminal (anode) of the light emitting device 122. The seventh transistor M7 is configured to connect the emission control signal line EMIT and an anode of the light emitting device 122, and is configured to reset the anode of the light emitting device 122 at a non-light emitting device, so as to improve the display accuracy of the light emitting device 122, and a cathode of the light emitting device 122 may be connected to the second power signal PVEE. In summary, as shown in fig. 2, each pixel driving circuit includes 7 transistors, wherein the signal lines are arranged in order of a reset signal line Vref, a second scan line S2, a first scan line S1, a third scan line S3, an auxiliary signal line 17, and a light emission control signal line EMIT, a fourth distance d4 exists between the light emission control signal line EMIT and the third scan line S3, and d3 > d4, a first transistor M1 with a larger volume is disposed between the third scan line S3 and the light emission control signal line EMIT, and a larger gap is reserved between the first scan line S1 and the third scan line S3 for light transmission region setting. The layout design is carried out on part or all of the pixel driving circuits in the display panel, so that high transmittance meeting the requirements of users can be formed, and the user experience is improved.
With continued reference to fig. 2, optionally, the first data line 141 at least partially overlaps the fifth active layer B5 of the first pixel driving circuit 121a in a plane parallel to the substrate 11; and/or, the second data line 142 at least partially overlaps the fifth active layer B5 of the second pixel driving circuit 121B. The fifth active layer B5 of the first pixel driving circuit 121a and the second pixel driving circuit 121B may be the same as the second active layer B2, extend along the second direction Y, and overlap with the corresponding data line 141, so as to further reuse the planar area of the pixel driving circuit on the plane of the substrate 11, increase the area of the transparent region, and improve the transmittance of the display panel.
With continued reference to fig. 2, optionally, the first terminal of the fifth active layer B5 of the first pixel driving circuit 121a is multiplexed as the first terminal of the fifth active layer B5 of the second pixel driving circuit 121B. The first end of the fifth active layer B5 of the first pixel driving circuit 121a or the second pixel driving circuit 121B is connected to the same signal line, i.e., the first power signal line 13. The fifth active layer B5 of the first pixel driving circuit 121a and the fifth active layer B5 of the second pixel driving circuit 121B share the first terminal, thereby saving the wiring of the fifth active layer B5, and the first pixel driving circuit 121a and the second pixel driving circuit 121B share one via hole K4 and the first power signal line 13, thereby further simplifying the manufacturing process of the pixel driving circuit.
On the basis of the above embodiments, the present embodiment compares the layout of the pixel driving circuit of the present disclosure with the layout of the pixel driving circuit in the prior art. Referring to fig. 9 and 10, fig. 9 is a partially enlarged schematic view of a region A2 in fig. 3, and fig. 10 is a schematic view of a structure of the pixel driving circuit in fig. 9. In the example of the prior art, each pixel drive circuit is also provided with 7 transistors, transistors M1 'to M7'. In contrast, one data line 14 'and one first power supply signal line 13' are provided for each pixel driving circuit along the first direction X, and the data line 14 'and the first power supply signal line 13' occupy a wider planar area compared to the embodiment of the present invention. In addition, in the second direction Y, the reset signal line Vref, the first scan line S1', the second scan line S2', and the emission control signal line EMIT are sequentially arranged, and 7 transistors are uniformly disposed between the scan lines, for example, a shielding layer 15 'is formed between the first scan line S1' and the second scan line S2', and is connected to the first power signal line 13' to form a capacitive shield, so as to reduce the influence of the data signal on the N1 node, and a transistor M1 'is disposed between the second scan line S2' and the emission control signal line EMIT. The pixel driving circuit has no dedicated light-transmitting region, and the high-transmittance region of the display panel in this embodiment cannot be formed. In addition, each transistor is an active layer made of a silicon semiconductor material, the light transmittance of the transistor is low, and in order to avoid leakage current of the transistor M3 'and the transistor M4', the transistor M3 'and the transistor M4' are arranged in a double-gate structure, so that the arrangement area of the active layer is further increased. In this embodiment, the active layers of the third transistor M3 and the fourth transistor M4 are both made of oxide semiconductor materials, so that the light transmittance is higher, and the third transistor M3 and the fourth transistor M4 made of oxide semiconductor materials have smaller leakage currents, and do not need to be arranged in a dual-gate structure, thereby reducing the arrangement area of the active layer and further improving the light transmittance. For pixel drive circuit among the prior art, pixel drive circuit in this embodiment is when not influencing pixel drive circuit normal drive current, from aspects such as circuit layout and technology setting, promotes the area in the light-permeable region among the pixel drive circuit greatly, promotes display panel's luminousness.
The embodiment of the invention also provides a display device. Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 11, the display device according to the embodiment of the present invention includes a display panel 200 according to any embodiment of the present invention. The display device may be a mobile phone as shown in fig. 11, or may be a computer, a television, an intelligent wearable device, and the like, which is not particularly limited in this embodiment.
The display device in the embodiment of the present invention includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding features, which are not described herein again.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (17)
1. A display panel, comprising: a substrate;
a plurality of pixel driving circuits; the plurality of pixel driving circuits comprise a first pixel driving circuit and a second pixel driving circuit which are adjacently arranged along a first direction;
the plurality of first power signal wires extend along a second direction and are sequentially arranged along the first direction; the first direction intersects the second direction; the first power supply signal line is connected with the corresponding pixel driving circuit;
wherein the first pixel driving circuit and the second pixel driving circuit share one first power signal line, and the first power signal line is located between the first pixel driving circuit and the second pixel driving circuit;
the pixel driving circuit includes a plurality of transistors; the transistor comprises an active layer and a grid electrode which is arranged in an insulated mode with the active layer; the active layer of at least one of the transistors includes an oxide semiconductor.
2. The display panel according to claim 1, characterized by further comprising: a plurality of data lines extending along the second direction and arranged in sequence along the first direction; the data lines include a first data line and a second data line; the first data line is connected with the first pixel driving circuit; the second data line is connected with the second pixel driving circuit; the first data line is positioned at one side of the first pixel driving circuit close to the first power supply signal line; the second data line is positioned at one side of the second pixel driving circuit close to the first power supply signal line;
the pixel driving circuit includes:
a first transistor including a first active layer and a first gate electrode; the first transistor is used for providing a driving current for the light-emitting device;
a second transistor including a second active layer and a second gate electrode; the first end of the second active layer is connected with the corresponding data line; the second end of the second active layer is connected with the first end of the first active layer;
the first data line covers the second active layer in a plane parallel to the substrate; and/or the presence of a gas in the gas,
the second data line covers the second active layer.
3. The display panel according to claim 2, further comprising: a plurality of reset signal lines extending along the first direction and arranged in sequence along a second direction;
the pixel driving circuit further includes:
a third transistor including a third active layer and a third gate electrode; a first end of the third active layer is connected with the first grid electrode; a second end of the third active layer is connected with a second end of the first active layer;
a fourth transistor including a fourth active layer and a fourth gate electrode; a first end of the fourth active layer is connected with the reset signal line; a second end of the fourth active layer is connected to a first end of the third active layer;
the first active layer and the second active layer are arranged on the same layer and comprise silicon semiconductors; the third active layer and the fourth active layer are disposed at the same layer and include an oxide semiconductor.
4. The display panel according to claim 3,
the first end of the third active layer is communicated with the first grid electrode through a first overline; the second end of the third active layer is connected with the second end of the first active layer through a second overline.
5. The display panel of claim 4, wherein the first and second flying leads are both linear.
6. The display panel according to claim 3, characterized by further comprising: a plurality of scanning lines extending along the first direction and arranged in sequence along the second direction;
the scan line includes: a first scanning line, a second scanning line and a third scanning line; the overlapping part of the first scanning line and the second active layer forms the second grid electrode; the overlapping part of the second scanning line and the fourth active layer forms the fourth grid electrode; the overlapping part of the third scanning line and the third active layer forms the third gate;
in the pixel driving circuit, the reset signal line, the second scanning line, the first scanning line, and the third scanning line are arranged in sequence.
7. The display panel according to claim 6, wherein a first space is formed between the reset signal line and the second scan line; a second space is formed between the second scanning line and the first scanning line; a third space is formed between the first scanning line and the third scanning line;
the third pitch is greater than the first pitch, and the third pitch is greater than the second pitch.
8. The display panel according to claim 6, wherein an active layer from the second end of the third active layer to the first end of the fourth active layer in a region between the first scan line and the third scan line extends in the second direction.
9. The display panel according to claim 2, wherein the first power supply signal line at least partially overlaps the first data line in a plane parallel to the substrate; and/or the presence of a gas in the gas,
the first power supply signal line at least partially overlaps the second data line.
10. The display panel according to claim 9, wherein a projection of the first power supply signal line in a plane parallel to the substrate covers the first data line and the second data line.
11. The display panel according to claim 10, wherein the first power supply signal line comprises: a first portion, a second portion, and at least one connection; the first portion and the second portion both extend in the second direction; the connecting part connects the first part and the second part;
in a plane parallel to the substrate, the projection of the first portion covers the first data line, and the projection of the second portion covers the second data line.
12. The display panel according to claim 1, wherein adjacent ones of the first pixel drive circuit and the second pixel drive circuit are symmetrically arranged with respect to a first power supply signal line therebetween in the first direction.
13. The display panel according to claim 6, further comprising: a plurality of light emission control signal lines extending in the first direction and arranged in sequence in the second direction;
the pixel driving circuit further includes:
a storage capacitor, a first pole of the storage capacitor being multiplexed as the first gate; a second pole of the storage capacitor is connected with the first power signal line;
a fifth transistor including a fifth active layer and a fifth gate electrode; a first end of the fifth active layer is connected to the first power signal line; a second end of the fifth active layer is connected with a second end of the second active layer;
a sixth transistor including a sixth active layer and a sixth gate electrode; a first end of the sixth active layer is connected with a second end of the first active layer; a second end of the sixth active layer is connected to a first end of the light emitting device;
a seventh transistor including a seventh active layer and a seventh gate electrode; a first end of the seventh active layer is connected to the reset signal line; a second end of the seventh active layer is connected with a first end of the light emitting device;
the first active layer, the second active layer, the fifth active layer, the sixth active layer and the seventh active layer are arranged at the same layer and comprise silicon semiconductors; the overlapping part of the light-emitting control signal line and the sixth active layer forms a sixth gate; the overlapping part of the light-emitting control signal line and the fifth active layer forms a fifth gate electrode; the overlapping part of the first scanning line and the seventh active layer forms a seventh gate electrode.
14. The display panel according to claim 13, wherein along the first direction, second poles of storage capacitors of every two adjacent pixel driving circuits are connected to form an auxiliary signal line;
in each pixel driving circuit, the auxiliary signal line is disposed on a side of the third scanning line away from the first scanning line; the light-emitting control signal line is arranged on one side of the auxiliary signal line far away from the third scanning line;
a third space is formed between the first scanning line and the third scanning line; a fourth space is formed between the light-emitting control signal line and the third scanning line; the third pitch is greater than the fourth pitch.
15. The display panel according to claim 13, wherein the first data line at least partially overlaps with a fifth active layer of the first pixel driving circuit in a plane parallel to the substrate; and/or the second data line at least partially overlaps with a fifth active layer of the second pixel driving circuit.
16. The display panel according to claim 13, wherein a first terminal of a fifth active layer of the first pixel driving circuit is multiplexed as a first terminal of a fifth active layer of the second pixel driving circuit.
17. A display device characterized by comprising the display panel according to any one of claims 1 to 16.
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