CN112038381A - Display panel and display device - Google Patents
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
- H10K59/65—OLEDs integrated with inorganic image sensors
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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Abstract
The invention describes a display panel and a display device. The display panel comprises a substrate base plate, a first display area and a second display area, wherein a first pixel is positioned in the first display area, a first pixel circuit is positioned in the second display area, the first pixel is electrically connected with the first pixel circuit through a connecting signal line, the connecting signal line comprises a first overlapping structure, and the orthographic projection of the first overlapping structure on the substrate base plate is at least partially overlapped with the orthographic projection of the second pixel circuit positioned in the second display area on the substrate base plate; the functional layer is located between the connecting signal line and the third metal layer and comprises a functional structure, the orthographic projection of the functional structure on the substrate at least partially covers the orthographic projection of the first overlapping structure on the substrate, and the functional structure has a fixed potential. The embodiment of the invention can increase the light transmittance of the display panel and improve the display effect.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device including the display panel.
Background
For electronic products, the arrangement of optical modules such as a front camera and the like can occupy the space of a certain display panel, thereby influencing the screen occupation ratio.
In order to achieve a truly comprehensive screen, researchers consider implementation schemes in which devices such as optical modules are disposed under the display panel screen. Set up optical module for example the camera in display panel's emitting device's below, be about to optical module set up in the display area, the position at optical module place can normally show, when needs use optical module, light penetrates display panel and reaches optical module and finally is utilized by optical module. In the scheme of the optical module under the screen, the common design is to reduce the pixel density of the area where the optical module is located so as to improve the light transmittance of the area where the optical module is located and further improve the light quantity received by the optical module. In order to ensure the effect of the optical module, the requirement for the light transmittance of the region is high, but the pixel density of the region is greatly reduced, which may affect the overall display effect of the display panel.
Disclosure of Invention
In view of the foregoing, the present invention provides a display panel and a display device including the display panel.
The present invention provides a display panel, comprising: a substrate base plate;
the display device comprises a first display area and a second display area, wherein the first display area comprises first pixels, the second display area comprises second pixels, a first pixel circuit and a second pixel circuit, and the first pixel circuit is electrically connected with the first pixels through connecting signal lines; the second pixel circuit is located between the first display region and the first pixel circuit along the extending direction of the connecting signal line; the connecting signal line comprises a first overlapping structure, and the orthographic projection of the first overlapping structure on the substrate base plate at least partially overlaps with the orthographic projection of the second pixel circuit on the substrate base plate;
the display panel comprises an active layer, a first metal layer, a second metal layer, a third metal layer and a functional layer which are arranged in a stacking mode along the direction perpendicular to the plane of the substrate base plate, and the functional layer is located between the connecting signal line and the third metal layer; the functional layer comprises a functional structure, and the orthographic projection of the functional structure on the substrate at least partially covers the orthographic projection of the first overlapped structure on the substrate; the functional structure has a fixed potential.
The invention also provides a display device comprising the display panel, which comprises any one of the display panels provided by the embodiment of the invention.
The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: according to the display panel provided by the embodiment of the invention, the first pixel circuit corresponding to the first pixel in the first display area is arranged in the second display area, and the first pixel circuit and the second pixel circuit are electrically connected through the connecting signal line, so that the driving signal of the first pixel circuit is transmitted to the first pixel, the normal display of the first pixel is controlled, the normal display of the first display area is ensured, the excessive occupied space of the first pixel circuit in the first display area is avoided, and the light transmittance of the first display area can be obviously improved. Meanwhile, by arranging the functional structure with the fixed potential in the functional layer at the orthographic projection overlapping position of the connecting signal line and the second pixel circuit, the coupling capacitance formed between the connecting signal line passing through the upper part of the second pixel circuit structure and the second pixel circuit structure can be reduced, the signal crosstalk of the coupling capacitance to the second pixel circuit is inhibited, the phenomenon that the brightness of the display panel is uneven due to signal coupling is effectively improved, the risk of split display is reduced, and the full-screen display with high image quality is realized.
Drawings
The drawings in the following description are for simplicity of explanation and it is apparent that the drawings in the following description are some embodiments of the present invention, and it is obvious for a person skilled in the art that other drawings can be obtained based on the drawings without inventive exercise.
FIG. 1 is a schematic top view of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic top view of a portion of a display panel according to an embodiment of the present invention;
FIG. 3 is an enlarged, partially schematic top view of the area B in FIG. 2 according to an embodiment of the present invention;
FIG. 4 is a schematic top view of a portion of another display panel according to an embodiment of the present invention;
FIG. 5 is an enlarged, partially schematic top view of region C of FIG. 4 in accordance with an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view taken along line A-A' of FIG. 3 in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of a second pixel circuit according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view taken along line B-B' of FIG. 8 in accordance with one embodiment of the present invention;
FIG. 10 is an enlarged, fragmentary, top view of the area A of FIG. 1 in accordance with one embodiment of the present invention;
FIG. 11 is a schematic top view of a portion of the method of FIG. 1 in accordance with another embodiment of the present invention;
FIG. 12 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 13 is a schematic cross-sectional view taken along line C-C' of FIG. 10 in accordance with one embodiment of the present invention;
FIG. 14 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 15 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 16 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 17 is a schematic structural diagram of another display panel according to an embodiment of the present invention;
FIG. 18 is a schematic top view of a portion of another display panel according to an embodiment of the present invention;
FIG. 19 is a schematic cross-sectional view taken along lines D-D 'and E-E' of FIG. 18 in accordance with one embodiment of the present invention;
FIG. 20 is a schematic cross-sectional view taken along line F-F' of FIG. 18 in accordance with one embodiment of the present invention;
FIG. 21 is a schematic top view of a portion of another display panel according to an embodiment of the present invention;
FIG. 22 is a schematic top view of a display device according to an embodiment of the invention;
FIG. 23 is a cross-sectional view of the Z-Z' position of FIG. 22 in accordance with one embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer and more comprehensible, the technical solutions of the present invention will be described in detail and in full below with reference to the drawings and the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be implemented in a number of ways different from those described herein and similar generalizations can be made by those skilled in the art without departing from the spirit of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Referring to fig. 1 and fig. 2, in which fig. 1 is a schematic top view of a display panel according to an embodiment of the present invention. As shown in fig. 1, the display panel 100 includes a first display area AA1 and a second display area AA2 arranged along a first direction D1, and fig. 2 is a partial enlarged view of the display panel according to an embodiment of the present invention, where the first display area AA1 includes first pixels 11, and the second display area includes second pixels 12, first pixel circuits 21, and second pixel circuits 22; the first pixel circuit 21 and the first pixel 11 are electrically connected through a connection signal line R1, and are configured to transmit a driving signal generated by the first pixel circuit 21 to the first pixel 11, so as to drive the first pixel 11 to perform light emitting display. Along the first direction D1, the second pixel circuit 22 is located between the first display area AA1 and the first pixel circuit 21, and the extending path of the connection signal line R1 passes over the second pixel circuit 22 and is electrically connected to the first pixel circuit 21, that is, there is an overlapping portion between the orthographic projection of the connection signal line R1 on the substrate and the orthographic projection of the second pixel circuit 22 on the substrate. Fig. 2 is a partial schematic view, and in the embodiment of the present invention, the shapes of the first display area AA1 and the second display area AA2 may be designed according to specific requirements, and may be any shape, such as a circle, a rectangle, a triangle, and the like. When displaying a screen, the first display area AA1 may be used to display an electric quantity graphic, a message notification graphic, a network status graphic, etc. alone, or may be used to implement a complete screen display together with the second display area AA 2. The number of the first display area AA1 and the second display area AA2 is not limited in the present application, and on the display panel, the number of the first display area AA1 and the second display area AA2 may be one or more, and the display panel is designed according to specific requirements, for example, when the display panel 100 is a front-mounted dual-camera display panel, the number of the first display area AA1 may be two, and the number of the second display area AA2 may be one, two or more. The "pixel circuit" in this embodiment is a pixel circuit which can drive a pixel to normally emit light, refers to a minimum repeating unit of a circuit structure which drives a corresponding pixel, and may be a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, or the like, where the "7T 1C circuit" refers to a pixel circuit in which the pixel circuit includes 7 thin film transistors and 1 capacitor. It should be noted that the same filling pattern in fig. 2 is only for showing the same connection state between the pixel circuits and the pixels, and is not used to limit the "first pixel circuit" and the "second pixel circuit". Alternatively, referring to fig. 4 and fig. 5, fig. 4 is a partial top view schematic diagram of another display panel according to an embodiment of the present invention, and fig. 5 is a partial enlarged top view schematic diagram of a region C in fig. 4. The number of the second display area AA2 may be multiple, and the second display area AA2 may be located on the left and right sides of the first display area AA1 or on the upper and lower sides of the first display area AA1, and is set according to actual requirements. That is, the second pixel circuit 22 may be electrically connected to the connection signal line R1, or may not be electrically connected to the connection signal line R1, depending on the circuit arrangement of a specific display panel.
Further, referring to fig. 3 and 6, the connection signal line R1 includes a first overlap structure RD, and an orthographic projection of the first overlap structure RD on the substrate base 10 at least partially overlaps with an orthographic projection of the second pixel circuit 22 on the substrate base 10. Along a direction perpendicular to the plane of the substrate 10, the display panel 100 further includes an active layer 20, a first metal layer 30, a second metal layer 40, a third metal layer 50, and a functional layer 60, which are sequentially stacked in an insulating manner, for facilitating understanding of the positional relationship among the film layers, please refer to fig. 6, fig. 6 is a schematic cross-sectional view taken along a-a' position in fig. 3, and the display panel 200 further includes the active layer 20, the first metal layer 30 located on a side of the active layer 20 away from the substrate 10, the second metal layer 40 located on a side of the first metal layer 30 away from the substrate 10, the third metal layer 50 located on a side of the second metal layer 40 away from the substrate 10, and the functional layer 60 located on a side of the third metal layer 50 away from the substrate 10. In an actual display panel, an insulating layer is usually further included between the metal layers, and the insulating layer separates the signal lines between the metal layers, and for convenience of representation, the illustration of the insulating layer between each metal layer and the metal layer is omitted in the cross-sectional view of fig. 6. The functional layer 60 comprises a functional structure SL, the orthographic projection of the functional structure SL on the substrate 10 at least partially overlaps the orthographic projection of the first overlap structure RD on the substrate 10, i.e. in a direction perpendicular to the plane of the display panel, the functional structure SL is located between the connection signal line R1 and the second pixel circuit 22, and the functional structure SL at least partially overlaps the first overlap structure RD between the connection signal line R1 and the second pixel circuit 22; and the functional structure SL has a fixed potential.
It can be understood that, often need reserve the great district of dodging that does not set up light-emitting pixel of an area for optical module such as leading camera among the current display panel, thereby realize normal work in order to ensure that these optical module can receive sufficient effective light, the design in district of dodging can additionally increase the area in the non-display area of display panel, be unfavorable for realizing full screen display, in order to improve the problem that dodge the district and occupy the display panel space, the people have proposed the direct idea that sets up optical module such as camera in the display area below of display panel. However, taking the schematic diagram provided in fig. 2 as an example, generally, an OLED pixel circuit capable of performing threshold compensation includes a plurality of transistors, a plurality of circuit lines and a capacitor structure, the routing is dense and the structure is complex, and in order to achieve high image quality display, a high ppi (pixel per inch) design is usually adopted for a display panel, the number of pixel circuits is increased accordingly, and the light shielding area is increased, so that the existing display panel design cannot meet the requirement of light transmittance for normal operation of the optical module. In order to realize a real full screen and ensure the normal operation of the optical module, the embodiment of the invention designs the first display area in the display panel, places the first pixel circuit 21 for driving the first pixel 11 to emit light in the second display area AA2, and realizes the signal transmission between the first pixel 11 and the first pixel circuit 11 only by connecting the signal line R1, thereby reducing the shielding area of the pixel circuit 21 and other wiring structures in the first display area AA1 to light, greatly improving the light transmittance of the first display area AA1, ensuring that when the optical module is arranged below the first display area AA1 of the display panel, the optical module can receive enough effective optical signals during working, realizing the function of the optical module, simultaneously avoiding the great reduction of the number of the pixels in the first display area, and ensuring the display of PPI.
It can be understood that when the OLED pixel circuit operates, coupling capacitors may exist between the plurality of transistors and the circuit connection wiring and the signal line, and the existence of the coupling capacitors may affect the voltage of the connection nodes between the transistors in the pixel circuit, so that the current value flowing to the pixel may change, and finally the display luminance of the pixel may deviate from the theoretical value or deviate from the required luminance, which may affect the display effect. In order to achieve high PPI, the conventional display panel has utilized the space of the display panel to the utmost, and therefore, the connection signal line R1 passes through the upper portion of the second pixel circuit 22, and generates a coupling capacitance with the lower portion of the second pixel circuit 22, especially when the connection signal line R1 overlaps with the gate signal line of the driving transistor, the gate voltage of the driving transistor is affected, so that the current value output by the second pixel circuit 22 is shifted to be larger, and the actual luminance of the pixel corresponding to the second pixel circuit 22 is different from the ideal luminance. When the number of the second pixels is large, the display split screen can be caused, and the visual display effect is influenced. In the embodiment of the present invention, by arranging the functional structure SL, the orthographic projection of the functional structure SL on the substrate 10 at least partially covers the orthographic projection of the first overlapping portion RD connected to the signal line R1 on the substrate 10, and the functional structure SL has a fixed potential, so that the coupling crosstalk between signal traces can be reduced, the stability of the pixel circuit can be improved, and thus, the real high-image-quality full-screen display can be realized. It will be appreciated that the functional structure SL has a fixed potential, i.e. the functional structure may comprise a metal (e.g. Al, Mo, etc.), ITO or other material with conductive capabilities. When the functional structure SL has a fixed potential, since the functional structure SL is located between the first overlap RD and the second pixel circuit 22, part of the electric field lines of the electric field generated by the connection signal line R1 may be terminated at the functional structure SL, that is, the functional structure SL may cut off the electric field generated by part of the connection signal line R1 or the signal line of the second pixel circuit 22, so that parasitic capacitance that suppresses coupling of the signal line connecting the signal line R1 and the second pixel circuit 22 may be realized.
Optionally, with continued reference to fig. 2, 3 and 7, the second pixel circuit 22 generally includes a fixed voltage signal line for transmitting a constant voltage signal, which may be a first power voltage signal line PVDD1 for providing a power voltage signal to the second pixel circuit 22, or an initialization signal line vref for providing an initialization signal. Optionally, the functional structure SL may be electrically connected to the first power voltage signal line PVDD1, or the functional structure SL may be electrically connected to the initialization signal line vref, so that the functional structure SL has a fixed potential, which can be implemented by using the existing signal routing of the display panel, and it is not necessary to additionally provide a separate fixed voltage signal line for the functional structure SL to provide a fixed voltage signal, thereby saving the wiring space of the panel, and simultaneously saving the port of the driving chip, which is easily compatible with the existing chip design.
Optionally, referring to fig. 3 and 7, fig. 7 is a schematic diagram of a pixel circuit structure corresponding to the second pixel circuit, the second pixel circuit 22 further includes a driving transistor TD, an initialization module T5, and a threshold capture module T4, the first node N1 is located between the initialization module T5 and the threshold capture module T4, and the first node N1 is electrically connected to a gate of the driving transistor TD through the first connecting trace FN to implement signal conduction. The first connection trace FN is located on the third metal layer 50, and the material thereof may include aluminum, titanium, molybdenum, etc. The third metal layer 50 may further include a source and a drain of a transistor, which is not limited in this application. The initialization module T5 is used to transmit the initialization signal vref to the first node N1 during the initialization phase to reset the first node N1, and the threshold capture module T4 is used to complete the threshold voltage capture and self-compensation of the driving transistor TD during the data signal writing phase. The initialization block T5 may include one or more transistors to perform its function, or the initialization block T5 may include other structures having signal on/off functions to transmit the initialization signal to the gate of the driving transistor TD, which is not limited in this application.
The second pixel circuit 22 further includes scan lines (a first scan line S1 and a second scan line S2) for transmitting scan signals, a data signal line data for transmitting a data signal data, and a first capacitor Cst; optionally, the scan line may be located in the first metal layer 30, the power line may be located in the third metal layer 50, and the two plates of the first capacitor Cst may be respectively located in the first metal layer 30 and the second metal layer 40, which is determined by the specific circumstances and is not limited in this embodiment. The driving current I generated by the driving transistor TD is determined by the source voltage of the driving transistor TD and the gate voltage of the driving transistor TD＝K×(VPVDD-Vdata-ΔV)2Wherein
Δ V is the parasitic capacitance magnitude of the coupling between the signal line and the first connection trace FN, in the light emitting stage, the source voltage of the driving transistor TD is the power voltage signal PVDD, and the gate is electrically connected to the first node N1 through the first connection trace FN, so that the gate potential of the driving transistor TD can be influenced by the first connection trace FN in addition to the coupling influence of other signal lines, thereby influencing the driving current magnitude of the driving transistor TD, causing the driving current value to shift, and influencing the pixel light emitting intensity.
Optionally, referring to fig. 8, in the embodiment of the present invention, the functional structure SL covers the first connection trace FN along a direction perpendicular to the plane of the substrate.
Since the functional structure SL has a fixed potential, on one hand, the functional structure SL covers the first connection line FN, so that the coupling capacitance between the first connection line FN and the connection signal line R1 passing through the upper side of the second pixel circuit 22 can be reduced, thereby preventing the potential of the first connection line FN from changing and affecting the gate voltage of the driving transistor; on the other hand, the functional structure SL covers the first connection trace FN, and can cut off a part of the data signal line data or an electric field generated between the first connection trace FN, and reduce the coupling capacitance between the signal line in the structure of the second pixel circuit 22 itself and the first connection trace FN, thereby preventing the display effect from being affected by the reduction of the pixel current due to the increase of the electric potential of the first node N1 and the driving transistor gate due to the coupling effect.
Referring to fig. 9, fig. 9 is a schematic cross-sectional view taken along a line B-B' in fig. 8 according to an embodiment of the present invention. The functional structure SL is electrically connected to the first power voltage signal line PVDD1, the functional structure SL has a fixed potential PVDD, the functional structure SL covers the first connection line FN, and the first connection line FN is electrically connected to the gate of the driving transistor TD, so that a capacitor C1 can be formed between the functional structure SL and the first connection line FN. The first capacitor Cst in the second pixel circuit 22 is used for stabilizing the voltage of the gate of the driving transistor, and when the first plate C11 of the first capacitor Cst is located on the first metal layer 20, the second plate C12 of the first capacitor Cst may be located on the second metal layer 30 and electrically connected to the first power voltage line PVDD1, so that the second plate C12 has a fixed potential PVDD. At this time, the capacitance of the gate electrode of the driving transistor TD may be increased, and the capacitor C1 and the first capacitor Cst act together to better stabilize the gate node voltage. It should be noted that, the "electrical connection" mentioned in the present application may be implemented by a via hole between two structures/signal lines, may also be implemented by a direct lap joint, or may be implemented by other ways of implementing electrical signal conduction or transmission, which is not limited in the present application.
Optionally, referring to fig. 1 and fig. 10, fig. 10 is a partially enlarged top view schematic diagram of a region a in fig. 1 according to an embodiment. The display panel 100 further includes a third display area AA3, and the third display area AA3 includes a plurality of third pixels 13 arranged in an array and a third pixel circuit 23 electrically connected to the third pixels 13. The pixel density of the third display area AA3 is greater than that of the first display area AA1, or the number of the third pixels 13 in the third display area AA3 is greater than that of the first pixels 11 in the first display area AA1 per unit area. The pixel density of the third display area AA3 is greater than that of the second display area AA2, or the number of the third pixels 13 in the third display area AA3 is greater than that of the second pixels 12 in the second display area AA2 per unit area. It will be appreciated that the third display area has the greatest pixel density.
With continued reference to fig. 7 and 10, when the functional structure SL is electrically connected to the first power voltage signal line PVDD1 and covers the first connection line FN, since a capacitor C1 is formed between the functional structure SL and the first connection line FN and can cooperate with the first capacitor Cst to increase the capacitance of the capacitor electrically connected to the gate of the driving transistor TD, optionally, the orthographic area S1 of the second pixel circuit 22 on the substrate 10 can be made smaller than the orthographic area S2 of the third pixel circuit 23 on the substrate 10, so as to reduce the occupied space of the first capacitor Cst in the second pixel circuit 22 and save the space of the second display area AA2 on the premise of ensuring the performance of the second pixel circuit 22, thereby facilitating the arrangement of more first pixel circuits 21 and second pixel circuits 22 in the second display area AA2, and as can be understood, more first pixel circuits 21 can be arranged, the number of the first pixels 11 in the first display area AA1 is increased, the pixel density of the first display area AA1 is increased, and the display effect is improved.
Further, when the second display area AA2 has enough space for placing the first pixel circuit 21, the ratio of the pixel density of the first display area AA1 to the pixel density of the third display area AA3 may be set to be greater than
The pixel density of the first display area AA1 may be set to be that of the third display area AA3
The display effect of the first display area AA1 may be improved. If the pixel density of the first display area AA1 is greatly reduced in order to secure the light transmittance of the first display area AA1, the luminance of the first display area AA1 may be significantly different from that of the third display area AA 3. Generally, in order to alleviate the difference in display brightness, the light emitting current of the first pixel 11 in the first display area AA1 is selected to be increased, but for the OLED display panel, the lifetime of the pixel is inversely proportional to the current magnitude per unit density, so that the lifetime of the first display area AA1 is significantly reduced by increasing the light emitting current to increase the brightness, thereby affecting the lifetime of the whole display panel. By adopting the technical scheme of the embodiment of the application, the space utilization rate is improved, the pixel density of the first display area AA1 can be increased, the display effect can be improved, and the service life of the display panel can be prolonged. Referring to fig. 11, one first pixel circuit 21 may be electrically connected to two first pixels 11 with the same light emitting color, and the two pixels are driven to emit light simultaneously, so that more first pixel circuits 21 may be disposed in the second display area AA2 while ensuring that the pixels in the first display area AA1 can emit light normally, thereby more first pixels 11 may be disposed in the first display area AA1, and the first pixel circuits may be further increasedThe pixel density of the display area AA1 is better to realize full-screen display. Similarly, one second pixel circuit 22 may be electrically connected to two second pixels 12 with the same light emitting color, and the two pixels may be driven to emit light at the same time, so that the number of the second pixel circuits 22 may be reduced, and the second display area AA2 may have enough space to place all the first pixel circuits 21 and the second pixel circuits 22. It is understood that the more pixels driven by one pixel circuit, the more the pixel density in the first display area AA1 can be increased, which is not limited in the present application.
Optionally, when the number of the second pixel circuits 22 in the second display area is multiple, for example, the number of the second pixel circuits 22 is two, the two functional structures SL may be electrically connected to each other and respectively electrically connected to the first power voltage lines PVDD in the respective second pixel circuits 22, and when the first power voltage lines PVDD are located in the third metal layer, the first power voltage lines PVDD are wired in parallel, so that the voltage drop of the power voltage lines may be reduced, the display luminance deviation caused by the voltage drop of the first power voltage lines PVDD is improved, and the display effect is improved.
Optionally, referring to fig. 12, the first power voltage line PVDD1 is located in the functional layer, that is, the first power voltage line PVDD1 is disposed in the same layer as the functional structure SL. Thus, the number of traces in the same metal layer in the display panel 100 can be reduced, thereby reducing the orthographic projection area of the second pixel circuit 22 on the substrate, making the space wiring more compact, and being beneficial to improving the PPI of the display panel.
Alternatively, with continuing reference to fig. 12 and 13, fig. 13 is a schematic cross-sectional view taken along the position C-C' in fig. 10, when the fixed potential of the functional structure SL is the power voltage signal PVDD and the functional structure SL and the first power voltage line PVDD1 are disposed in the same layer, the functional structure SL and the first power voltage line PVDD1 may be in direct contact with each other, or the functional structure SL and the first power voltage line PVDD 3526 are integrally formed, in other words, the first power voltage line PVDD1 includes the functional structure SL. With the design of this embodiment, it is equivalent to increase the line width of the first power voltage line PVDD1, and reduce the voltage drop of the first power voltage line PVDD1, thereby improving the display luminance deviation caused by the voltage drop. It is to be understood that the fixed voltage signal lines in the display panel are not limited to the first power voltage signal line PVDD1, and the case where the functional structure SL is connected to the first power voltage signal line PVDD1 is only illustrated here, and the signal lines to which the functional structure SL is connected are not limited. Optionally, the functional structure SL may be electrically connected to the initialization signal line vref, that is, the fixed voltage signal line multiplexes the initialization signal line vref in the second pixel circuit 22, and the initialization signal line vref also has a voltage drop problem, which may directly affect the reset condition of the gate node voltage of the driving transistor TD, and further affect the effect of writing the next frame data signal into the driving transistor TD.
Further, referring to fig. 14, when the functional structure SL is located in the functional layer, it is disposed on the same layer as the first power voltage line PVDD 1. The data signal line data is located on the third metal layer, the first connection wire FN is located on the third metal layer, and the data signal line data and the first connection wire FN are arranged in an insulated mode. In this case, since only the functional structure SL and the first power supply voltage line PVDD1 are provided in the functional layer, there is a sufficient wiring space, and the area of the functional structure SL can be appropriately increased to directly contact the functional structure SL with the first power supply voltage line PVDD, or in this case, the first power supply voltage line PVDD1 includes the functional structure SL. In the direction perpendicular to the plane of the substrate base plate 10, the first power voltage line PVDD1 covers both the first connection line FN and the data signal line data, and the first power voltage line PVDD1 can cut off part of the electric field lines between the data signal line data and the first connection line FN on the basis of improving the coupling crosstalk generated by the connection signal line R1 to the second pixel circuit 22. By adopting the technical scheme of the embodiment, the coupling crosstalk of the external wiring (the connection signal line R1) to the second pixel circuit 22 is improved, and meanwhile, the coupling crosstalk between the internal signal lines of the second pixel circuit 22 can be improved, so that the display effect is remarkably improved.
Further, the data signal line data of the second pixel circuit is located at a third metal layer, i.e., a different layer of the data signal line data and the first power voltage signal line PVDD 1. The orthographic projection of the first power supply voltage signal line PVDD1 on the substrate base plate 10 at least partially overlaps with the orthographic projection of the data signal line data on the substrate base plate 10, i.e., the first power supply voltage signal line at least partially overlaps the data signal line data along a direction perpendicular to the plane of the substrate base plate 10. By the design, the wiring space can be further saved.
Alternatively, referring to fig. 15, the functional structure SL covers the second display area AA2 along a direction perpendicular to the plane of the substrate base plate 10. When the functional structure SL completely covers the second display area AA2, the crosstalk of signals from the connection signal line R1 to the second pixel circuit 22 can be reduced, and the crosstalk of coupling between the signal lines inside the pixel circuit can be reduced.
Optionally, referring to fig. 16, fig. 16 is a schematic structural diagram of another display panel according to an embodiment of the present invention. The data signal line data is disposed in the same layer as the functional layer, that is, the data signal line data is disposed in the same layer as the functional structure SL, and a first insulating layer (not shown) is further included between the third metal layer 50 and the functional layer 60, and the first insulating layer may include silicon dioxide or a material with a smaller dielectric constant. The data line signal line data and the first connecting line FN are located on different layers, the space distance between the two signal lines is increased, the first insulating layer with a small dielectric constant is further arranged between the data line signal line data and the first connecting line FN, parasitic capacitance of coupling of the data line signal line data and the first connecting line FN can be greatly reduced, mutual crosstalk between the signal lines is favorably reduced, the first connecting line FN is prevented from being interfered to influence grid voltage of the first node N1 and the driving transistor TD, interference of grid signals of the driving transistor TD is reduced, and the display effect is improved.
Optionally, referring to fig. 17, the second pixel circuit includes a second power voltage line PVDD2, the second power voltage line PVDD2 is disposed on the third metal layer, the data signal line data is located in the functional layer, and an orthogonal projection of the second power voltage line PVDD2 on the substrate base plate 10 is located between an orthogonal projection of the data signal line data on the substrate base plate 10 and an orthogonal projection of the first connection line FN on the substrate base plate 10. Both the spatial distance between the data signal line data and the first connection line FN is increased, and the electric field lines generated by the data signal line data or the first connection line FN are terminated at the second power voltage line PVDD2, thereby suppressing the parasitic capacitance generated by the coupling between the signal lines. At this time, the connection structure SL may be electrically connected to the second power voltage line PVDD2 through the via H1, and the position of H1 is not limited, so that the second power voltage line PVDD2 and the functional structure SL may be electrically connected to each other.
Optionally, referring to fig. 18, fig. 18 is a partial top view of another first display area and a second display area according to an embodiment of the present invention, in which the connection signal line R1 includes a first sub-connection signal line R11 located in the first display area AA1 and a second sub-connection signal line R12 located in the second display area AA2, where the first sub-connection signal line R11 is a transparent trace. The material of the transparent trace may include ITO, IZO, etc., and the application is not limited herein.
Further, referring to fig. 19, fig. 19 is a schematic cross-sectional view taken along positions D-D 'and E-E' in fig. 18, in which the first pixel 11 includes a first electrode E1, the first electrode E1 includes a first transparent electrode E11, and the first sub-connection signal line SL1 is at the same layer as the first electrode. The first electrode E1 is a pixel anode formed by ITO-Ag-ITO stacking, the first transparent electrode E11 can be arranged on the same layer with any layer of ITO in the stacking structure, the process and the panel thickness can be saved, and signal transmission is achieved at the same time. Of course, the first electrode E1 may also be a pixel anode made of ITO, which has high light transmittance, and when the first electrode E1 does not include a reflective electrode, the light transmittance of the first display area AA1 may be further improved. The first pixel 11 includes a first electrode E1, a light emitting layer, and a second electrode E2 disposed in a direction perpendicular to the substrate base plate 10. In general, a pixel in an OLED display panel generally includes an anode, a light emitting layer, and a cathode, and constituent materials of the respective structures are determined as the case may be, unless otherwise specified. Note that, for convenience of describing the positional relationship and the connection relationship between each pixel and the pixel circuit, only a partial structural sectional view of the first pixel circuit 21 is shown in the drawing to refer to the pixel circuit.
Optionally, referring to fig. 18 and fig. 20, the second pixel circuit 22 is electrically connected to the second pixel 12 for providing a driving signal to the second pixel 12 located in the second display area AA 2. In the first display area AA1, the first pixels 11 are alternately arranged in the first direction D1 and the second direction D2, in the second display area AA2, the first pixel circuits 21 and the second pixel circuits 22 are alternately arranged in sequence in the first direction D1, the first pixel circuits and the second pixel circuits 22 are alternately arranged in sequence in the second direction D2, and the second pixels 12 are alternately arranged in the first direction D1 and the second direction D2, wherein the first direction D1 and the second direction D2 cross. Alternatively, the second display area AA2 may include a plurality of second pixel circuits 22 arranged in a multi-row and multi-column array, wherein the first direction D1 may be a row direction of the array arrangement, and the second direction D2 may be a column direction of the array arrangement. Note that, for convenience of describing the positional relationship and the connection relationship between each pixel and the pixel circuit, fig. 20 shows only a partial structural sectional view of the first pixel circuit 21 and the second pixel circuit 22 to refer to the pixel circuits.
Optionally, referring to fig. 21, the first pixel 11 may further include a first light-emitting color sub-pixel, a second light-emitting color sub-pixel, and a third light-emitting color sub-pixel, and the first pixel circuit 21 may further include a first sub-pixel circuit electrically connected to the first color sub-pixel, a second sub-pixel circuit electrically connected to the second color sub-pixel, and a third sub-pixel circuit electrically connected to the third color sub-pixel. The first light-emitting color sub-pixel, the second light-emitting color sub-pixel and the third light-emitting color sub-pixel may be one of red, green and blue, or may be other three colors capable of emitting white light in combination, which is selected according to specific situations, and the application does not limit the colors.
Alternatively, referring to fig. 21, the first pixel 11 includes a first pixel electrode P1, an orthographic projection of the first pixel electrode P1 on the substrate 10 is circular, and the first pixel electrode P1 may be an anode or a cathode of the first pixel 11, which is not limited in this application. In the prior art, when light passes through the gap between the signal lines in the first display area AA1 and when the edge of the first pixel 11 is a straight line, diffraction and superposition of diffraction are easy to occur, which may affect the imaging effect of the optical device under the first display area AA 1. In an alternative embodiment of the present invention, the first pixel electrode P1 is designed to be circular, i.e. the first pixel electrode P1 has an arc-shaped profile (arc-shaped edge), which destroys diffraction phenomenon generated by light passing through a straight edge. In the embodiment of the present application, the circle is a circle or a shape close to a circle, and in an actual process, due to the influence of factors such as process errors, the shape of an absolute circle may not be obtained, and a shape such as an ellipse close to a circle may be formed. The first pixel electrode P1 in fig. 21 is filled with different patterns to show that the first pixel electrode P1 corresponds to the first sub-pixel 11 with different light emission colors, and the first pixel electrode P1 is not limited to other patterns.
Optionally, with reference to fig. 21, the connection signal line R1 includes a third sub-connection signal line R13 and a fourth sub-connection signal line R14, the third sub-connection signal line R13 is located in the first display area AA1, the fourth sub-connection signal line is located in the second display area AA2, and the third sub-connection signal line R13 includes an arc line. The third sub-connecting signal line R13 is designed into an arc line, so that the phenomenon that a straight line edge appears in the first display area AA1 is avoided, the degree of diffraction of external ambient light after passing through the first display area AA1 can be reduced, the influence of diffraction phenomena on optical devices such as a camera is weakened, and the working effect of the optical devices is improved.
Based on the same inventive concept, the present application further provides a display apparatus, fig. 22 is a schematic diagram of the display apparatus provided in the embodiment of the present application, please refer to fig. 22, the display apparatus 200 includes the display panel 100 and the optical device CC provided in any of the above embodiments of the present application; referring to fig. 23, the first display area AA1 covers the optical device CC along a direction perpendicular to the plane of the substrate base plate 10. For an embodiment of the display device 200 provided in the embodiment of the present application, reference may be made to the above-mentioned embodiment of the display panel 100, and repeated descriptions are omitted. The display device 200 provided by the present application may be: any product or component with practical functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Optical device CC can be sensitization devices such as camera, fingerprint identification module. It should be noted that, in the embodiments of the display panel provided by the present invention, the technical features can be freely combined without conflict, and the present invention is not exhaustive.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (17)
1. A display panel, comprising:
a substrate base plate;
the display device comprises a first display area and a second display area, wherein the first display area and the second display area are arranged along a first direction, the first display area comprises first pixels, the second display area comprises second pixels, a first pixel circuit and a second pixel circuit, and the first pixel circuit and the first pixels are electrically connected through a connecting signal line; the second pixel circuit is located between the first display region and the first pixel circuit along the first direction; the connecting signal line comprises a first overlapping structure, and the orthographic projection of the first overlapping structure on the substrate base plate at least partially overlaps with the orthographic projection of the second pixel circuit on the substrate base plate;
the display panel comprises an active layer, a first metal layer, a second metal layer, a third metal layer and a functional layer which are arranged in a stacking mode along the direction perpendicular to the plane of the substrate base plate, and the functional layer is located between the connecting signal line and the third metal layer; the functional layer comprises a functional structure, and the orthographic projection of the functional structure on the substrate at least partially covers the orthographic projection of the first overlapped structure on the substrate; the functional structure has a fixed potential.
2. The display panel of claim 1, wherein the second pixel circuit includes a fixed voltage signal line for transmitting a constant voltage signal, the functional structure being electrically connected to the fixed voltage signal line.
3. The display panel of claim 1, wherein the second pixel circuit comprises a driving transistor, an initialization module, a threshold capture module, and a first node, the first node is between the initialization module and the threshold capture module, and the first node is electrically connected to a gate of the driving transistor through a first connection trace; the first connecting trace is located on the third metal layer;
and the functional structure covers the first connecting wire along the direction vertical to the plane of the substrate base plate.
4. The display panel according to claim 3, wherein the second pixel circuit further includes a first power supply voltage signal line and a first capacitor structure; the functional structure is electrically connected with the first power supply voltage signal line; the first electrode plate of the first capacitor structure is located on the first metal layer, the second electrode plate of the capacitor structure is located on the second metal layer, and the second electrode plate is electrically connected with the first power supply voltage signal line.
5. The display panel according to claim 4, wherein the first power supply voltage signal line is located in the functional layer.
6. The display panel of claim 5, wherein the second pixel circuit further comprises a data signal line, the data signal line is located in the third metal layer, and an orthographic projection of the first power supply voltage signal line on the substrate base at least partially overlaps an orthographic projection of the data signal line on the substrate base.
7. The display panel according to claim 4, further comprising a third display region including a plurality of third pixels arranged in an array and a third pixel circuit electrically connected to the third pixels, wherein a pixel density of the third display region is greater than a pixel density of the first display region, and a pixel density of the third display region is greater than a pixel density of the second display region.
8. The display panel according to claim 7, wherein a ratio of a pixel density of the first display region to a pixel density of the third display region is larger than
9. The display panel of claim 3, wherein the functional structure covers the second display area in a direction perpendicular to a plane in which the substrate base is located.
10. The display panel according to claim 1, wherein the second pixel circuit further includes a data signal line, and wherein the data signal line is located in the functional layer.
11. The display panel of claim 10, wherein the second pixel circuit further comprises a second supply voltage line, the second supply voltage line being located in the third metal layer, an orthogonal projection of the second supply voltage line at the substrate base being located between an orthogonal projection of the data signal line at the substrate base and an orthogonal projection of the first connection line at the substrate base.
12. The display panel according to claim 1, wherein the connection signal line comprises a first sub-connection signal line located in the first display area and a second sub-connection signal line located in the second display area, wherein the first sub-connection signal line is a transparent trace.
13. The display panel according to claim 12, wherein the first pixel includes a first electrode including a first transparent electrode, and the first sub-connection signal line is in the same layer as the first transparent electrode.
14. The display panel according to claim 1, wherein the second pixel circuit is electrically connected to the second pixel; in the first display area, the first pixels are arranged in a staggered mode along the first direction and the second direction; in the second display region, along the first direction, the first pixel circuits and the second pixel circuits are alternately arranged in sequence, along the second direction, the first pixel circuits and the second pixel circuits are alternately arranged in sequence, and the second pixels are alternately arranged along the first direction and the second direction; the second direction intersects the first direction.
15. The display panel according to claim 1, wherein the first pixel includes a first pixel electrode, and an orthogonal projection shape of the first pixel electrode on the substrate base plate is a circle.
16. The display panel according to claim 1, wherein the connection signal lines include a third sub-connection signal line and a fourth sub-connection signal line, the third sub-connection signal line being located in the first display region, the fourth sub-connection signal line being located in the second display region, wherein the third sub-connection signal line includes an arc line.
17. A display device comprising the display panel according to any one of claims 1 to 16, the display device further comprising an optical device, wherein the first display region covers the optical device in a direction perpendicular to a plane of the substrate base plate.
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