KR20160008047A - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an organic light emitting diode display device comprising: a first TFT which adjusts the current of an organic light emitting diode in accordance with the voltage of a first node; a second TFT which forms a current path between a second node and a data line to which data voltage is supplied in response to an n^th first scan pulse; a third TFT which is operated as a diode between the first node and the second node; a fourth TFT which supplies an initialization voltage to the first node in response to an (n-1)^th first scan pulse generated before the n^th first scan pulse; a fifth TFT which supplies the initialization voltage to the second node in response to an n^th second scan pulse overlapped with the (n-1)^th and n^th first scan pulses; and a capacitor which is formed between the first node and a high-potential power voltage line to which high-potential power voltage is supplied.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display.

Since the organic light emitting diode display device is a self-light emitting device, a separate light source such as a backlight is not required, which is advantageous for thinning, low power consumption, high contrast ratio, and high response speed. The pixel of the organic light emitting diode display device includes an organic light emitting diode (OLED) and a driving device for controlling the current flowing through the organic light emitting diode according to the gate voltage.

The threshold voltage Vth of a driving thin film transistor (hereinafter, referred to as "TFT") characteristic of the driving element can be made nonuniform when viewed from the whole screen of the organic light emitting diode display. The threshold voltage of the driving device may vary as the driving time of the pixel becomes longer due to gate bias stress. In order to sense the threshold voltage of the driving device and compensate for the change in the threshold voltage, an internal compensation circuit may be incorporated in the pixel. The internal compensation circuit senses a change in the characteristics of the driving element and adds the threshold voltage of the driving element to the data voltage to compensate the threshold voltage deviation. Such an internal compensation circuit lowers the aperture ratio of the pixel because it includes the switch elements and the capacitor.

The contrast ratio is deteriorated when the pixels emit light during the period of sensing and compensating for the characteristic deviation of the driving element. To this end, the internal compensation circuit may be supplied with an emission control signal for controlling the emission period of the organic light emitting diode. The scan driver circuit includes a first shift register for sequentially shifting the scan pulses, a second shift register for sequentially shifting the emission control signal, and an inverter for inverting the output of the second shift register . The scan pulse is synchronized with the data voltage of the input image and simultaneously selects pixels of one line in which data is written.

The scan driving circuit may be formed directly in the bezel region of the display panel. In this case, the pixel array and the scan driver circuit are formed on the same substrate surface in the display panel. The bezel region is the non-display region outside the pixel array. When the scan driver circuit is large, the bezel area of the display panel becomes large, so it is difficult to reduce the bezel area. In particular, if an inverter for inverting the emission control signal is added to the scan driver circuit, the scan driver circuit becomes large, which limits the bezel area.

The present invention provides an organic light emitting diode display device capable of compensating for a characteristic deviation of a driving device and compensating for a threshold voltage and a mobility of a TFT to improve an image quality.

The organic light emitting diode display device of the present invention includes a first TFT for controlling a current of an organic light emitting diode according to a voltage of a first node: data (n is a positive integer) A second TFT forming a current path between the line and the second node; A third TFT operating as a diode between the first node and the second node; a fourth TFT for supplying an initialization voltage to the first node in response to an (n-1) th first scan pulse generated prior to an n-th first scan pulse; A fifth TFT for supplying the initialization voltage to the second node in response to an n-th second scan pulse overlapping with the (n-1) -th and n-th first scan pulses; And a capacitor formed between the high potential power supply voltage line to which the high potential power supply voltage is supplied and the first node.

The organic light emitting diode display device according to another embodiment of the present invention includes a first TFT for adjusting a current of the organic light emitting diode according to a voltage of a first node: n (n is a positive integer) A second TFT which forms a current path between a second node and a data line to which a voltage is supplied; A third TFT operating as a diode between the first node and the second node; a fourth TFT for supplying an initialization voltage to the first node in response to an (n-1) th first scan pulse generated prior to an n-th first scan pulse; A fifth TFT for blocking a current path between the first TFT and the organic light emitting diode during an initialization period and a sampling period in response to a light emission control signal and connecting the current path for an emission period; And a capacitor formed between the high potential power supply voltage line to which the high potential power supply voltage is supplied and the first node.

The present invention reduces and simplifies the number of TFTs in the pixel's internal compensation circuitry and forms a capacitor below the supply voltage line. As a result, the present invention can compensate for threshold voltage variations and variations of pixels and minimize aperture ratio degradation of pixels due to the internal compensation circuitry.

1 is a block diagram showing an organic light emitting diode display device according to an embodiment of the present invention.
FIG. 2 is a plan view showing an example in which the scan driver shown in FIG. 1 is formed on the same substrate together with the pixel array.
3 is a circuit diagram showing pixels of an organic light emitting diode display device according to a first embodiment of the present invention.
4 is a waveform diagram showing a drive waveform of the pixel shown in FIG.
5 is a diagram illustrating an initialization period of a pixel shown in FIG.
FIG. 6 is a view illustrating a sampling period of the pixel shown in FIG. 3. FIG.
7 is a diagram illustrating a light emission period of the pixel shown in FIG.
FIGS. 8 and 9 are diagrams showing simulation results of the present invention. FIG.
10 is a circuit diagram showing pixels of an organic light emitting diode display device according to a second embodiment of the present invention.
11 is a waveform diagram showing a drive waveform of the pixel shown in FIG.
12 is a circuit diagram showing pixels of an organic light emitting diode display device according to a third embodiment of the present invention.
13 is a circuit diagram showing pixels of an organic light emitting diode display device according to a fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 and 2, the organic light emitting diode display of the present invention includes a display panel 100 in which pixels are arranged in a matrix, a data driver 102 for supplying a data voltage to the data lines 11, A scan driver 104 for sequentially supplying a selection pulse SEN to the scan lines 12 intersecting the data lines 11 and a timing controller 112 for controlling the data driver 102 and the scan driver 104. [ And a controller 106.

Each of the pixels of the display panel 100 is implemented as shown in FIG. Each of the pixels may be divided into red, green and blue subpixels for the color implementation, each of the pixels as shown in FIG. Each of the pixels may include a light emitting layer for generating white light and a color filter.

The data driver 102 converts the digital video data RGB of the input image received from the timing controller 106 into a gamma compensation voltage and supplies the gamma compensation voltage to the data lines 11.

The scan driver 104 sequentially supplies the first scan pulses SCANA1 to SCANA4 to the scan lines of the first scan line group and the second scan pulses SCANB1 to SCANB4 to the scan lines of the second scan line group, . The first and second scan pulses SCANA1 to SCANB4 are shown in FIG. The pulse widths of the second scan pulses SCANB1 to SCANB4 are two times larger than the first scan pulses SCANA1 to SCANA4. When the pulse widths of the first scan pulses SCANA1 to SCANA4 are approximately one horizontal period, the pulse widths of the second scan pulses SCANB1 to SCANB4 are two horizontal periods. When the TFTs of the pixels are p-type switch TFTs, the first and second scan pulses SCANA1-4 and SCANB1-4 are generated as pulses of a low logic voltage.

The scan driver 104 may be formed directly on the same substrate together with the pixel array. The scan driver 104 is formed in the bezel area BZ of the display panel. The scan driver 104 includes a first shift register SR1 for sequentially shifting the first scan pulses SCANA1 to SCANA4 and a second shift register SR2 for sequentially shifting the second scan pulses SCANB1 to SCANB4, . The timing controller 110 supplies the first start pulse Vst (A) and the first shift clocks CLK (A) to the first shift register SR1 to set the operation timing of the first shift register SR1 to . The timing controller 110 supplies the second start pulse Vst (B) and the second shift clocks CLK (B) to the first shift register SR1 to set the operation timing of the second shift register SR2 to . The pulse width of the second shift clocks CLK (B) is larger than that of the first shift clocks CLK (B) because the pulse widths of the second scan pulses SCANB1 to SCANB4 are two times larger than the first scan pulses SCANA1 to SCANA4. A) is two times wider than that.

Since the scan driver 104 does not need to generate the emission control signal, a shift register and an inverter for shifting the emission control signal EM are not required. Accordingly, the display panel of the present invention can realize a Narrow bezel because the size of the scan driver 104 is reduced.

The scan driver 104 may further generate the emission control signal EM as shown in FIG. In this case, a shift register for shifting the light emission control signal EM and an inverter for inverting the output of the shift register are included.

The timing controller 106 transfers digital video data (RGB) received from an external host system (not shown) to the data driver 102. The timing controller 106 controls the data driver (not shown) using timing signals received from the host system such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a dot clock CLK 102 and the scan driver 104. The timing control signals for controlling the operation timings of the scan driver 102 and the scan driver 104 are shown in FIG. The host system may be various information devices such as a navigation system, a set-top box, a DVD player, a Blu-ray player, a computer, a home theater system, a broadcast receiver, a phone system, or a home appliance system.

3 is a circuit diagram showing pixels of an organic light emitting diode display device according to a first embodiment of the present invention. 4 is a waveform diagram showing a drive waveform of the pixel shown in FIG.

Referring to FIGS. 3 and 4, each of the pixels of the display panel 100 includes first through fifth TFTs T1 through T5, a capacitor C, and an organic light emitting diode (OLED).

The TFTs T1 to T5 may be implemented as a p-type MOSFET (metal-oxide-semiconductor field-effect transistor). The TFTs T1 to T5 are not limited to p-type MOSFETs but may be implemented as n-type MOSFETs and CMOS (complementary metal semiconductor) TFTs. In the case where the TFTs T1 to T5 are implemented as an n-type MOSFET or a CMOS TFT, the scan pulses SCANAn and SCANAn-1 may be inverted in the driving waveform of FIG.

In Fig. 4, "SCANAn-1" is n (n is a positive integer) -1-th first scan pulse. "SCANAn" is the n-th first scan pulse generated following the (n-1) th first scan pulse SCANAn-1. Quot; SCANBn "is the n-th second scan pulse. When the pulse widths of the first scan pulses SCANn-1 and SCANn are one horizontal period, the pulse width of the second scan pulse SCANn is two horizontal periods. The pulse of the second scan pulse SCANAn is superposed on the (n-1) th and nth scan pulse (SCANAn-1, SCANn).

The first TFT T1 is a driving element for adjusting the current of the organic light emitting diode OLED according to the voltage of the first node N1, that is, the gate voltage. The first TFT T1 includes a source connected to the high potential power supply voltage line 13 to which the high potential power supply voltage VDD is supplied, a drain connected to the second node N2, and a gate connected to the first node N1 . The high-potential power supply voltage (VDD) is a voltage of 5V or more.

The second TFT T2 is a switch element which forms a current path between the data line 11 and the second node N2 in response to the n-th first scan pulse SCANAn. The second TFT T2 is connected to the source connected to the data line 11, the drain connected to the second node N2, and the nth first scan line 12a to which the nth first scan pulse SCANAn is supplied Gate.

The third TFT T3 operates as a diode between the first node TFT T1 and the second TFT T2. The source of the third TFT (T3) is connected to the drain of the second TFT (T2) through the second node (N2). The gate and the drain of the third TFT T3 are connected to the first node N1.

The fourth TFT T4 is a switch element for supplying the initialization voltage Vini to the first node N1 in response to the (n-1) th first scan pulse SCANAn-1. The fourth TFT T4 includes a source to which the initialization voltage Vini is supplied, a drain connected to the first node N1, and an (n-1) < th > And a gate connected to the scan line 12b. The initialization voltage Vini may be set to a voltage lower than the threshold voltage of the organic light emitting diode OLED, e.g., 2V to 3V, from the low potential power supply voltage VSS.

The fifth TFT T5 is a switch element for supplying the initializing voltage Vini to the third node N3 in response to the nth second scan pulse SCANBn. The fifth TFT T5 is connected to the source to which the initializing voltage Vini is supplied, the drain connected to the third node N3, and the nth second scan line 12c to which the nth second scan pulse SCANBn is supplied And a connected gate.

The capacitor C is formed between the high potential power supply voltage line 13 and the first node N1 to store the difference between the voltage of the first node N1 and the high potential power supply voltage VDD. The high-potential power-supply voltage VDD is supplied to the pixels through the high-potential power-supply voltage line 13. [ The capacitor C is formed below the high potential power supply voltage line 13, so that the aperture ratio of the pixel is not lowered.

The organic light emitting diode OLED emits light according to the current supplied through the first TFT T1 when the difference between the anode voltage and the cathode voltage is equal to or greater than the threshold voltage of the organic light emitting diode OLED. The organic light emitting diode OLED includes an anode connected to the third node N3 and a cathode connected to the low potential supply voltage VSS. The low potential power supply voltage source may be set to a low potential power supply voltage (VSS) of 0 V or lower, for example, a voltage of -5 V. A multilayer organic compound layer is formed between the anode and the cathode of the organic light emitting diode (OLED). The organic compound layer may include a hole injection layer (HIL) connected to the anode, a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL) Layer (Electron Injection layer, EIL).

Each of these pixels includes an internal compensation circuit for sensing the threshold voltage of the driving element and compensating the data voltage by the threshold voltage. The internal compensation circuit includes the third TFT (T3) and the capacitor (C), so that the circuit configuration is simplified and the aperture ratio of the pixel can be increased.

The operation of each of the pixels may be divided into an initialization period t1, a sampling period t2, and a light emission period t3. The initialization period t1 is a period for initializing the TFTs T1 to T5 of the pixels and the organic light emitting diode OLED. In the initialization period t1, the organic light emitting diode OLED does not emit light. The sampling period t2 stores Vdata-Vth in the capacitor C. "Vdata" is the data voltage of the input image. Vth is the threshold voltage of the first and third TFTs T1 and T3. The light emitting period t3 supplies a current to the organic light emitting diode OLED through the first TFT T1 according to the voltage Vdata-Vth.

FIG. 5 is a diagram showing an initialization period t1 of the pixel shown in FIG. 3. FIG. FIG. 6 is a diagram showing a sampling period t2 of the pixel shown in FIG. 3. FIG. FIG. 7 is a diagram showing a light emitting period t3 of the pixel shown in FIG.

Referring to FIG. 5, the (n-1) th first scan pulse SCANAn-1 and the nth second scan pulse SCANBn of the low logic voltage are generated in the initialization period t1. The fourth TFT T4 is turned on in response to the (n-1) -th first scan pulse SCANAn-1 in the initialization period t1. At the same time, the fifth TFT T5 is turned on in response to the n-th second scan pulse SCANBn in the initialization period t1. As a result, the voltages of the first and third nodes N1 and N3 are simultaneously initialized to the initializing voltage Vini. The organic light emitting diode OLED does not emit light because the difference between the initialization voltage Vini and the low potential power supply voltage VSS is smaller than its threshold voltage. When the organic light emitting diode OLED emits light in the initialization period t1, the luminance of the black gradation rises and the contrast ratio decreases.

In the initialization period t1, the n-th first scan pulse SCANAn is not generated. Therefore, the second TFT T4 maintains the off state during the initialization period t1. The gate voltages of the first and third TFTs T1 and T3 are initialized to the initializing voltage Vini during the initialization period t1 and remain off.

6, in the sampling period t2, the data voltage Vdata is supplied to the pixel through the data line 11, and the n-th first scan pulse (Vdata) of the low logic voltage synchronized with the data voltage Vdata SCANAn-1) is generated. At the sampling period t2, the n-th second scan pulse SCANBn of the low logic voltage is maintained. the voltage of the (n-1) th first scan line 12b is inverted to a high logic voltage during the sampling period t2. The second TFT T2 is turned on in response to the n-th first scan pulse SCANAn-1 during the sampling period t2. The third TFT T3 operates as a diode during the sampling period t2. Therefore, the voltage of the first node N1 changes to Vdata-Vth during the sampling period t2 and is charged to the data voltage Vdata compensated for by the turn-on voltage Vth. The voltage of the first node N1 is stored in the capacitor C so that the capacitor C is held for one frame period by sampling Vdata-Vth. The threshold voltage Vth is a threshold voltage of the third TFT T3 which operates as a diode. Since the third TFT T3 is substantially the same as the first TFT T1, the threshold voltage Vth of the third TFT T3 is equal to the threshold voltage Vth of the first TFT T1.

The fifth TFT T5 maintains the on state in response to the nth second scan pulse SCANBn during the sampling period t2 to fix the anode voltage of the organic light emitting diode OLED to the initialization voltage Vini. Therefore, the organic light emitting diode OLED remains off during the sampling period t2 and is not emitted.

The threshold voltages Vth of the first and third TFTs T1 and T3 must be equal to each other in order to correctly sample the threshold voltage Vth of the first TFT T1 as the driving element in the sampling period t2. The channel ratio (W / L, W: channel width, L: channel length) of the first and third TFTs T1 and T3 may be equal to or different from each other, This can be seen from the following equation (1) defining the threshold voltage (Vth) of the MOSFET. The threshold voltage (Vth) of the MOSFET depends on C _OX . Since the first and third TFTs T1 and T2 are adjacent in the pixel, there is no thickness deviation of the gate metal therebetween and there is no dielectric layer thickness variation under the gate metal, so that _Cox is the same. Therefore, the threshold voltages VTh of the first and third TFTs T1 and T2 are substantially the same regardless of the channel ratio W / L.

φ _MS : work function potential difference between metal and semiconductor

Q _OX : fixed charge on oxide surface

Q _d : positive charge in the ionosphere

C _OX : capacitance per unit area of gate

φ _f is the difference between the Fermi level Ei of the intrinsic semiconductor and the Fermi level Ef of the extrinsic semiconductor

2? _F : Internal potential barrier in thermal equilibrium state (PN junction)

Referring to FIG. 7, in the light emitting period t3, the voltage of the n-th first scan line 12a and the n-th second scan line 12c changes to a high logic voltage. The voltage of the (n-1) th first scan line 12b in the light emission period t3 maintains a high logic voltage. Therefore, the first TFT T1 supplies the current I _OLED to the organic light emitting diode OLED according to the gate voltage Vdata-Vth during the light emission period t3. The second to fifth TFTs T2 to T5 maintain the off state during the light emitting period t3. During the light emitting period t3, the current I _OLED flowing through the organic light emitting diode _OLED is expressed by Equation (2).

Here, 'k' is a constant value defined by the product of the mobility μ of the driving TFT DT and the parasitic capacitance Cox, 'L' is the channel length of the driving TFT DT, 'W' (DT).

The current I _OLED of the organic light emitting diode OLED is not affected by the threshold voltage Vth of the first TFT T1. Therefore, the organic light emitting diode display of the present invention can reduce the threshold voltage deviation of the driving device depending on the position of the pixel array or the brightness of the organic light emitting diode OLED in all pixels regardless of the threshold voltage change, Can be uniformly controlled.

Figures 8 and 9 show the simulation results of the present invention. 8, the threshold voltage of the first and third TFTs T1 and T3 and the horizontal axis is time (ms). In this simulation, when the threshold voltage Vth is changed by 0.5 V, the threshold voltage change? Vth is accurately detected at the sampling period t2. 9 shows the current IOLED of the organic light emitting diode OLED flowing according to the gradation of the input image data. As a result of the simulation, the pixels according to the present invention did not change the current characteristics of the organic light emitting diode (OLED) according to the gradation when the threshold voltage change (? Vth) varied by ± 1 V. Therefore, the present invention can express the gradation of the input image data irrespective of the threshold voltage change of the driving element.

The current IOLED of the organic light emitting diode OLED is not large. The first TFT T1 is a driving device for driving the organic light emitting diode OLED, and thus is designed to have a channel ratio (W / L) that meets the required current of the organic light emitting diode OLED. In the present invention, the channel length (L) of the first TFT (T1) is maximized within a range satisfying the required current of the organic light emitting diode (OLED), and the gradation of the input data is set to the high- (Vdata). Since the second, fourth, and fifth TFTs T2, T4, and T5 are the switch TFTs to which no voltage is applied and the voltage is applied, a minimum margin is set regardless of the channel ratio (W / L) Is designed. The channel ratio (W / L) of the second, fourth, and fifth TFTs T2, T4, and T5 may be designed to be the same.

10 and 11 are views showing pixels of an organic light emitting diode display device according to a second embodiment of the present invention.

10 and 11, each of the pixels of the display panel 100 includes first through fifth TFTs T1 through T4 and T51, a capacitor C, and an organic light emitting diode OLED do.

The TFTs T1 to T4 and T51 may be implemented as a p-type MOSFET (metal-oxide-semiconductor field-effect transistor). In comparison with the above-described first embodiment, the pixel shown in Fig. 10 is substantially the same as the pixel shown in Fig. 3 except for the control signal of the fifth TFT (T51).

The fifth TFT T51 cuts off the current path between the first TFT T1 and the organic light emitting diode OLED during the initialization period t1 and the sampling period t2 in response to the emission control signal EM, And is turned on during the light emission period t3 to connect the current path to supply current to the organic light emitting diode OLED. As a result, a current flows in the organic light emitting diode OLED through the first and fifth TFTs T1 and T5 during the light emitting period t3.

The fifth TFT T51 includes a gate to which the emission control signal EM is supplied, a source connected to the second node N2, and a drain connected to the anode of the organic light emitting diode OLED. The light emission control signal EM is generated with a high logic voltage during the initialization period t1 and the sampling period t2 and is generated as a low logic voltage during the light emission period.

The operation of each of the pixels is divided into an initialization period t1, a sampling period t2, and a light emission period t3. The operation of this pixel is substantially the same as that of the first embodiment described above, so a detailed description thereof will be omitted.

The pixel shown in Fig. 10 needs the emission control signal EM, but does not need the second scan pulse SCANBn. Therefore, the size factor of the scan driver 104 is not large.

12 is a circuit diagram showing pixels of an organic light emitting diode display device according to a third embodiment of the present invention.

12, each of the pixels of the display panel 100 includes first to fifth TFTs T1 to T4 and T5, first and second capacitors C1 and C2, and an organic light emitting diode OLED).

The TFTs T1 to T5 may be implemented as a p-type MOSFET (metal-oxide-semiconductor field-effect transistor). Compared with the first embodiment described above, the pixel shown in Fig. 12 is substantially the same as the pixel shown in Fig. 3, except that the second capacitor C2 is added.

The second capacitor C2 is provided between the second node N2 and the high potential power supply voltage line 13 to prevent the voltage change of the second node N2. The first capacitor C1 is formed between the high potential power supply voltage line 13 and the first node N1 and stores the difference between the voltage of the first node N1 and the high potential power supply voltage VDD. The first capacitor C is the same as the capacitor C of the first embodiment described above. Since the first and second capacitors C1 and C2 are formed below the high potential power supply voltage line 13, the aperture ratio of the pixel is not lowered. The capacitance of the first capacitor C1 may be lower than that of the second capacitor C2.

The operation of each of the pixels is divided into an initialization period t1, a sampling period t2, and a light emission period t3. The operation of this pixel is substantially the same as that of the first embodiment described above, so a detailed description thereof will be omitted.

13 is a circuit diagram showing pixels of an organic light emitting diode display device according to a fourth embodiment of the present invention.

13, each of the pixels of the display panel 100 includes first to fifth TFTs T1 to T4 and T5, first and second capacitors C1 and C2, and an organic light emitting diode OLED).

The TFTs T1 to T5 may be implemented as a p-type MOSFET (metal-oxide-semiconductor field-effect transistor). Compared with the first embodiment described above, the pixel shown in Fig. 13 is substantially the same as the pixel shown in Fig. 3 except that the second capacitor C2 is added and the control signal of the fifth TFT T51 is different.

The second capacitor C2 is provided between the second node N2 and the high potential power supply voltage line 13 to prevent the voltage change of the second node N2. The fifth TFT T51 cuts off the current path between the first TFT T1 and the organic light emitting diode OLED during the initialization period t1 and the sampling period t2 in response to the emission control signal EM, And supplies current to the organic light emitting diode OLED by connecting the current path during the light emitting period t3.

The operation of each of the pixels is divided into an initialization period t1, a sampling period t2, and a light emission period t3. The operation of this pixel is substantially the same as that of the first embodiment described above, so a detailed description thereof will be omitted.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

100: display panel 102: data driver
104: scan driver 106: timing controller
OLED: Organic light emitting diode C, C1, C1: Capacitor
T1 to T5, T51: TFT

Claims (12)

A first TFT for adjusting a current of the organic light emitting diode according to a voltage of the first node:
a second TFT which forms a current path between a data line and a second node to which a data voltage is supplied in response to the nth (n is a positive integer) first scan pulse;
A third TFT operating as a diode between the first node and the second node;
a fourth TFT for supplying an initialization voltage to the first node in response to an (n-1) th first scan pulse generated prior to an n-th first scan pulse;
A fifth TFT for supplying the initialization voltage to the second node in response to an n-th second scan pulse overlapping with the (n-1) -th and n-th first scan pulses; And
And a first capacitor formed between the first node and a high potential power supply line to which a high potential power supply voltage is supplied. The method according to claim 1,
Wherein the first TFT includes a source to which a high-potential power supply voltage is supplied, a drain connected to the second node, and a gate coupled to the first node,
The second TFT includes a source coupled to the data line, a drain coupled to the second node, and a gate to which the nth first scan pulse is supplied,
The third TFT includes a source connected to the drain of the second TFT through the second node, a gate connected to the first node and a drain,
The fourth TFT includes a source to which the initialization voltage is supplied, a drain connected to the first node, and a gate to which the (n-1) th first scan pulse is supplied,
Wherein the fifth TFT includes a source to which the initialization voltage is supplied, a drain connected to the third node, and a gate to which the nth second scan pulse is supplied. 3. The method according to claim 1 or 2,
And a second capacitor formed between the high potential power supply voltage line and the second node. The method according to claim 1,
During the initialization period, the (n-1) th first scan pulse and the (n) th second scan pulse are generated to simultaneously turn on the fourth and fifth TFTs,
And the voltages of the first and third nodes are simultaneously initialized to the initialization voltage. 5. The method of claim 4,
The data voltage is supplied to the data line during the sampling period, the n-th first scan pulse synchronized with the data voltage is generated,
During the sampling period, the second TFT is turned on and the voltage of the first node is supplied with the data voltage, which is subtracted by the threshold voltage of the third TFT, and is stored in the first capacitor. 6. The method of claim 5,
Following the sampling period, a current flows through the organic light emitting diode through the first TFT during a light emitting period,
And the second to fifth TFTs maintain an off state during the light emission period. A first TFT for adjusting a current of the organic light emitting diode according to a voltage of the first node:
a second TFT which forms a current path between a data line and a second node to which a data voltage is supplied in response to the nth (n is a positive integer) first scan pulse;
A third TFT operating as a diode between the first node and the second node;
a fourth TFT for supplying an initialization voltage to the first node in response to an (n-1) th first scan pulse generated prior to an n-th first scan pulse;
A fifth TFT for blocking a current path between the first TFT and the organic light emitting diode during an initialization period and a sampling period in response to a light emission control signal and connecting the current path for an emission period; And
And a first capacitor formed between the first node and a high potential power supply line to which a high potential power supply voltage is supplied. 8. The method of claim 7,
Wherein the first TFT includes a source to which a high-potential power supply voltage is supplied, a drain connected to the second node, and a gate coupled to the first node,
The second TFT includes a source coupled to the data line, a drain coupled to the second node, and a gate to which the nth first scan pulse is supplied,
The third TFT includes a source connected to the drain of the second TFT through the second node, a gate connected to the first node and a drain,
The fourth TFT includes a source to which the initialization voltage is supplied, a drain connected to the first node, and a gate to which the (n-1) th first scan pulse is supplied,
The fifth TFT includes a gate to which the emission control signal is supplied, a source connected to the second node, and a drain connected to the anode of the organic light emitting diode. 9. The method according to claim 7 or 8,
And a second capacitor formed between the high potential power supply voltage line and the second node. 8. The method of claim 7,
During the initialization period, the (n-1) th first scan pulse and the (n) th second scan pulse are generated to simultaneously turn on the fourth and fifth TFTs,
And the voltages of the first and third nodes are simultaneously initialized to the initialization voltage. 11. The method of claim 10,
The data voltage is supplied to the data line during the sampling period, the n-th first scan pulse synchronized with the data voltage is generated,
During the sampling period, the second TFT is turned on and the voltage of the first node is supplied with the data voltage, which is subtracted by the threshold voltage of the third TFT, and is stored in the first capacitor. 11. The method of claim 10,
Following the sampling period, the fifth TFT is turned on according to the emission control signal during a light emission period, and a current flows to the organic light emitting diode through the first and fifth TFTs,
And the second to fourth TFTs are kept off during the light emitting period.

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