KR102223495B1 - Organic Light Emitting Display - Google Patents

Abstract

The present invention includes one or more switch elements, a driving element for supplying current to an organic light emitting diode, and a pixel having a capacitor. Among the switch elements, the driving element or the switch element connected to the organic light emitting diode is a dual gate switch element shared between neighboring sub-pixels.

Description

Organic Light Emitting Display

The present invention relates to an organic light emitting diode display in which a switch element is shared between adjacent subpixels.

Liquid Crystal Display Device (LCD), Organic Light Emitting Diode Display (hereinafter referred to as "OLED display"), Plasma Display Panel (PDP), field emission display ( Various flat panel displays such as Field Emission Display, FED) are being used.

A liquid crystal display device displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. Active matrix type liquid crystal display devices have been applied to almost all display devices, from small mobile devices to large TVs, and are widely used due to lower cost and higher performance thanks to the development of process technology and driving technology.

Since the OLED display device is a self-luminous device, power consumption is lower than that of a liquid crystal display device that requires a backlight and can be manufactured to be thinner. In addition, the OLED display has a wide viewing angle and a fast response speed. OLED display devices are expanding the market while competing with liquid crystal display devices.

The pixels of the OLED display are a driving TFT (Thin Film Transistor) that controls the driving current flowing through the OLED according to the gate-source voltage, a capacitor that maintains the gate-source voltage of the driving TFT, and the driving TFT in response to the gate signal. And at least one switch TFT for programming the gate-source voltage of the. The driving current is determined by the gate-source voltage of the driving TFT according to the data voltage, and the brightness of the pixel is proportional to the magnitude of the driving current flowing through the OLED.

Due to process variations, gate-bias stress, and the like, variations in driving TFT characteristics may occur between pixels. In order to solve this problem, an internal compensation circuit is added in the pixel to program the gate-source voltage of the driving TFT, and according to the programming result, the influence of the change in the threshold voltage of the driving TFT on the driving current can be eliminated.

Display devices are continuously developing with high resolution in order to improve image quality. At the same screen size, the higher the resolution, the smaller the pixel size. When the pixel size decreases, the space for forming TFTs, wirings, contact holes, etc. in the pixel becomes insufficient, making pixel design difficult.

When the switch element of the pixels is designed as a dual gate, it is possible to reduce the power consumption of the display device by reducing the leakage current of the pixels. However, when the switch device is fabricated with a dual gate structure, it is difficult to reduce the pixel size because the number of TFTs of the pixel increases.

The present invention provides an organic light emitting display device capable of reducing a leakage current and reducing a pixel size.

The organic light-emitting display device of the present invention includes one or more switch elements, a driving element for supplying current to the organic light-emitting diode, and a pixel including a capacitor.

Among the switch elements, the driving element or the switch element connected to the organic light emitting diode is a dual gate switch element shared between neighboring sub-pixels.

The dual gate switch element is composed of a series connection of a TFT shared by neighboring sub-pixels and a TFT separated for each pixel.

The present invention enables a pixel design having an internal compensation function and a small leakage current in a high-resolution panel by allowing a dual gate switch device to be shared between neighboring sub-pixels in an organic light-emitting display device. Furthermore, according to the present invention, a smaller pixel in which a wiring and a contact hole are shared between neighboring subpixels in an organic light emitting diode display may be designed to be smaller.

1 is a block diagram showing an OLED display device according to an exemplary embodiment of the present invention.
2 is an equivalent circuit diagram showing a pixel structure of the display device illustrated in FIG. 1.
3 is a waveform diagram showing the operation of the pixel shown in FIG. 2.
4 is a diagram showing switch on/off timing of pixels.
5 is a diagram showing an initialization operation of a pixel.
6 is a diagram showing a sampling operation of a pixel.
7 is a diagram showing a programming operation of a pixel.
8 is a diagram showing an emission operation of a pixel.
9 is a circuit diagram showing an example in which a pair of TFTs having a dual gate structure is shared among neighboring sub-pixels.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numbers throughout the specification mean substantially the same constituent elements. In the following description, when it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

1 and 2, the organic light emitting diode display of the present invention includes a display panel 100, a data driver 102, a scan driver 104, and a timing controller 110.

The display panel 100 includes a pixel array in which pixels are arranged in a matrix form to display an input image. Each of the pixels of the display panel 100 may be implemented as shown in FIGS. 2 to 9, but is not limited thereto. Each of the pixels may be divided into red, green, and blue sub-pixels for color implementation. Each of the pixels may further include a white sub-pixel that generates white light. The pixels may further include color filters.

Each of the pixels includes one or more switch elements, a drive element for supplying current to the OLED, and a pixel with a capacitor. Among the switch elements, the driving element or the switch element in the OLED is a dual gate switch element shared between neighboring sub-pixels. The dual gate switch element is composed of a series connection of TFTs shared by neighboring sub-pixels and TFTs separated for each pixel.

TFTs shared between neighboring sub-pixels are T2a and T3a in the example of FIG. 9. TFTs connected in series with the shared TFT to constitute the dual gate switch element are T2b, T2c, T3b and T3c in the example of FIG. 9.

Each of the pixels has an internal compensation function for compensating for a characteristic change of the driving TFT. The structure and operation of these pixels will be described later with reference to FIGS. 2 to 9.

The data driver 102 generates a reference voltage Vref and a data voltage Vdata. The data driver 102 converts digital video data of an input image received from the timing controller 110 into a gamma compensation voltage, generates a data voltage Vdata, and supplies it to the data lines 11. The data driver 102 generates a preset reference voltage Vref irrespective of the input image and supplies it to the data lines 11.

The scan driver 104 sequentially supplies scan signals Scan1 and Scan2 to the scan lines 12a and 12b and sequentially supplies an emission signal EM to the EM lines 14.

The timing controller 110 transmits digital video data (RGB) received from an external host system (not shown) to the data driver 102. The timing controller 110 uses timing signals received from the host system, such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a dot clock (CLK). It generates timing control signals for controlling the operation timing of 102) and the scan driver 104.

The host system may be a navigation system, a set-top box, a DVD player, a Blu-ray player, a computer, a home theater system, a broadcast receiver, a phone system, and various information devices or home appliance systems.

2 is an equivalent circuit diagram showing a pixel structure of the display device illustrated in FIG. 1. 3 is a waveform diagram showing the operation of the pixel shown in FIG. 2. 4 is a diagram showing on/off switch timing of TFTs of a pixel.

2 to 4, each sub-pixel of the pixels includes an OLED, first to second TFTs T1 to T4, and first and second capacitors C1 and C2. This sub-pixel is a 4T2C circuit structure including 4 transistors and 2 capacitors.

One horizontal period (1H) of a pixel is divided into an initialization period (Ti), a sampling period (Ts), a programming period (Tp), and an emission period (Te). During one horizontal period (1H), the threshold voltage of the fourth TFT (T4), which is a driving element of the pixel, is sampled and the data voltage is compensated by the threshold voltage. Accordingly, during one horizontal period (1H), the data of the input image is compensated by the threshold voltage of the driving element and written to the pixel.

The first scan signal Scan1 is generated at an ON level for approximately one horizontal period 1H to turn on the first TFT T1, and is inverted to an OFF level in the emission period Te. The first TFT (T1) is turned off.

The second scan signal Scan2 is generated at an ON level in the initialization period Ti to turn on the third TFT T3, and maintains the OFF level for the remaining period to turn the third TFT T3 off. Control.

The emission signal EM is generated at the ON level in the sampling period Ts to turn on the second TFT T2, and is inverted to the OFF level in the initialization period Ti and the programming period Tp, and the second The TFT (T2) is turned off. In addition, the emission signal EM maintains the ON level during the emission period Te to maintain the second TFT T2 in the ON state.

The OLED emits light by the current supplied from the second TFT (T2). It includes a layer of organic compounds shaped between the anode and cathode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. EIL) may be included, but is not limited thereto. The anode of the OLED is connected to the second node n2, and the cathode is connected to a low-potential power supply voltage (VSS) or a ground voltage source (GND).

The first TFT T1 is a switch element that turns on/off a current path between the data line 11 and the first node n1 by being switched in response to the first scan signal Scan1. The gate of the first TFT (T1) is connected to the first scan line (12a), and the drain is connected to the data line (11). The source of the first TFT T1 is connected to the first node n1.

The second TFT T2 is a switch element that turns on/off a current path between the VDD line 15 and the drain of the fourth TFT T4 by being switched in response to the emission signal EM. The gate of the second TFT (T2) is connected to the EM line 14, and the drain is connected to the VDD line 15. The source of the second TFT (T2) is connected to the drain of the fourth TFT (T4).

The third TFT T3 is a switch element that turns on/off the current path between the Vini line 13 and the second node n2 by being switched in response to the second scan signal Scan2. The Vini line 13 is an initialization signal line. The gate of the third TFT T3 is connected to the second scan line 12b, and the drain is connected to the second node n2. The source of the third TFT (T3) is connected to the Vini line (13). An initialization signal (Vini) is supplied to Vini.

The fourth TFT T4 is a driving element that controls the current of the OLED according to its gate-source voltage Vgs. The gate of the fourth TFT (T4) is connected to the first node (n1), and the drain is connected to the source of the second TFT (T2). The source is connected to the anode of the OLED.

The first capacitor C1 is connected between the first node n1 and the second node n2 to store a difference voltage between both ends. The first capacitor C1 samples the threshold voltage Vth of the fourth TFT T4a, which is a driving element, in a source-follower method. The second capacitor C2 is connected between the VDD line 15 and the second node n2. When the potential of the first node n1 changes according to the data voltage Vdata in the programming period Tp, the first and second capacitors C1 and C2 divide the voltage to the second node n2. Reflect on.

5 is a diagram showing an initialization operation of a pixel. 6 is a diagram showing a sampling operation of a pixel. 7 is a diagram showing a programming operation of a pixel. 8 is a diagram showing an emission operation of a pixel.

Referring to FIG. 5, during the initialization period Ti, the first and third TFTs T1 and T3 are turned on in response to the first and second scan signals Scan1 and Scan2 of the ON level. The second TFT T2 is turned off in the initialization period Ti by the emission signal EM of the OFF level. During the initialization period Ti, a predetermined reference voltage Vref is supplied to the data line 11. During the initialization period Ti, the voltage of the first node n1 is initialized to a reference voltage Vref, and the voltage of the second node n1 is initialized to a predetermined initialization voltage Vini.

Referring to FIG. 6, during the sampling period Ts, the second TFT T2 is turned on in response to the emission signal EM of the ON level. During the sampling period Ts, the first TFT T1 is maintained in the ON state by the first scan signal Scan1 of the ON level. During the sampling period Ts, the reference voltage Vref is supplied to the data line 11. During the sampling period Ts, the potential of the first node n1 is maintained at the reference voltage Vref, while the potential of the second node n2 increases due to the drain-source current Ids. According to this source-follower method, the gate-source voltage Vgs of the fourth TFT T4 is sampled as the threshold voltage Vth of the fourth TFT T4, and the sampled threshold voltage Vth ) Is stored in the first capacitor C1. During the sampling period Ts, the voltage of the first node n1 is the reference voltage Vref, and the voltage of the second node n1 is Vref-Vth.

Referring to FIG. 7, during the programming period Tp, the first TFT T1 maintains the ON state according to the first scan signal Scan1 of the ON level, and the remaining TFTs T2 to T4 are turned off. During the programming period Tp, the data voltage Vdata of the input image is supplied to the data line 11. The data voltage Vdata is applied to the first node n1, and the voltage distribution result between the first and second capacitors C1 and C2 with respect to the potential change Vdata-Vref of the first node n1 is The voltage Vgs between the gate and source of the fourth TFT T4 is programmed by being reflected in the second node n2. During the programming period Tp, the voltage of the first node n1 is the data voltage Vdata, and the voltage of the second node n2 is the first and second voltages in “Vref-Vth” set through the sampling period Ts. The voltage distribution result (C'*(Vdata-Vref)) between the two capacitors C1 and C2 is added to become "Vref-Vth+C'*(Vdata-Vref)". Consequently, the gate-source voltage Vgs of the fourth TFT T4 is programmed to "Vdata-Vref+Vth-C'*(Vdata-Vref)" through the programming period Tp. Here, C'denotes CST1/(CST1+CST2), CST1 denotes the first capacitance of the first capacitor C1, and CST2 denotes the second capacitance of the second capacitor C2.

Referring to FIG. 8, the emission period Te continues from the programming period Tp to the initialization period Ti of the next frame. The emission signal EM is input at an ON level to turn on the second TFT T2. In the emission period Te, the driving current Ioled is applied to the OLED according to the gate-source voltage programmed through the programming period Tp to emit light. During the emission period Te, the first and second scan signals Scan1 and Scan2 are input at an OFF level to turn off the first and third TFTs T1 and T3.

The current (Ioled) flowing through the OLED during the emission period (Te) is shown in Equation 1. The OLED emits light by this current to express the brightness of the input image.

In Equation 2, k denotes a proportional constant determined by the electron mobility, parasitic capacitance, channel capacity, and the like of the fourth TFT (T4).

The driving current (Ioled) relationship is k/2 (Vgs-Vth) ² , and since Vgs programmed through the programming period (Tp) contains Vth, the Vth component in the driving current (Ioled) relationship as shown in Equation 1 is It is erased. Accordingly, the influence of the change in the threshold voltage Vth on the driving current Ioled is eliminated.

In the present invention, each TFT in a pixel is implemented as a TFT of a dual gate structure including a pair of TFTs in order to reduce the leakage current of each of the pixels. In addition, in order to reduce the number of wires and contact holes of the pixel array, the present invention reverses the structure of neighboring sub-pixels in a mirror reflection form, and provides a dual-gate TFT that can be shared with the neighboring sub-pixels. Share between pixels.

9 is a circuit diagram showing an example in which a pair of TFTs implementing a dual gate structure is shared among neighboring sub-pixels.

Referring to FIG. 9, the first sub-pixel P1 and the second sub-pixel have structures inverted to each other in the form of left and right mirrors except for some shared elements.

The first sub-pixel P1 includes a first TFT (T1a, T1b), a second TFT (T2a, T2b), a third TFT (T3a, T3b), a fourth TFT (T4a), a first capacitor (C1a), and 2 capacitors C2a, and OLED1.

As described above, the first sub-pixel P1 has a 4T2C structure as shown in FIGS. 2 to 8 and has an internal compensation function. Each of the first TFTs T1a and T1b, the second TFTs T2a and T2b, and the third TFTs T3a and T3b is composed of a pair of TFTs whose gates are connected to each other to reduce leakage current.

The first TFTs T1a and T1b are metal oxide semiconductor field-effect transistors (MOSFETs) having a dual gate structure including a 1a TFT (T1a) and a 1b TFT (T1b) having gates connected to each other. The gate of the 1a TFT (T1a) is connected to the first scan line 12a, and the drain is connected to the first data line 11. The source of the 1a TFT (T1a) is connected to the drain of the 1b TFT (T1b). The gate of the 1b TFT (T1b) is connected to the first scan line 12a, and the drain is connected to the source of the 1a TFT (T1a). The source of the 1b TFT (T1b) is connected to the first node n1. The first TFTs T1a and T1b are switching elements that turn on/off the current path between the first data line 11 and the first node n1 by being switched in response to the first scan signal Scan1. Since the first TFTs T1a and T1b are connected to the first data line 11, they are not shared between neighboring sub-pixels P1 and P2, but must be separated for each sub-pixel. If any one of the first TFTs T1a and T1b is shared between the neighboring subpixels P1 and P2, the data lines of the neighboring subpixels P1 and P2 are short circuited, resulting in subpixels. The same data is written to (P1, P2).

The second TFTs T2a and T2b are MOSFETs having a dual gate structure including a 2a TFT (T2a) and a 2b TFT (T2b) in which gates are connected to each other. The gate of the 2a TFT (T2a) is connected to the EM line 14, and its drain is connected to the VDD line 15. The source of the 2a TFT (T2a) is connected to the drain of the 2b TFT (T2b) and the drain of the 2c TFT (T2c). The gate of the 2b TFT (T2b) is connected to the EM line 14, and its drain is connected to the source of the 2a TFT (T2a). The source of the 2b TFT (T2b) is connected to the drain of the fourth TFT (T4a). The second TFTs T2a and T2b are switching elements that turn on/off the current path between the VDD line 15 and the drain of the fourth TFT T4a by being switched in response to the emission signal EM.

The 2a TFT (T2a) is implemented as a MOSFET of a dual gate structure together with the 2b TFT (T2b) of the first sub-pixel (P1) to operate as a switch element of the first sub-pixel (P1), and at the same time, the second sub-pixel (P1). It is implemented as a MOSFET of a dual gate structure together with the 2c TFT (T2c) of the pixel P2 and operates as a switch element of the second sub-pixel P2. Accordingly, the 2a TFT 2a is a switch element shared by the first and second sub-pixels P1 and P2. According to the present invention, the number of TFTs can be reduced by allowing the 2a TFT 2a to be shared between the adjacent sub-pixels P1 and P2.

The VDD line 15 is a power line shared between the first and second sub-pixels P1 and P2. The VDD line 15 is connected to the second capacitors C2a and C2b through a contact hole CH penetrating the insulating layer. Since the VDD line 15 is shared between the neighboring sub-pixels P1 and P2, the number of the VDD line 15 and the contact hole CH is reduced.

The third TFTs T3a and T3b are MOSFETs having a dual gate structure including a 3a TFT (T3a) and a 3b TFT (T3b) with gates connected to each other. The gate of the 3a TFT (T3a) is connected to the second scan line 12b, and the drain is connected to the source of the 3b TFT (T3b) and the source of the 3c TFT (T3c). The source of the 3a TFT (T3a) is connected to the Vini line 13. The gate of the 3b TFT (T3b) is connected to the second scan line 12b, and the drain is connected to the second node n2. The source of the 3b TFT (T3b) is connected to the drain of the 3a TFT (T3a). The third TFTs T3a and T3b are switching elements that turn on/off the current paths of the Vini line 13 and the second node n2 by switching in response to the second scan signal Scan2.

The 3a TFT (T3a) is implemented as a MOSFET of a dual gate structure together with the 3b TFT (T3b) of the first sub-pixel (P1) to operate as a switch element of the first sub-pixel (P1), and at the same time, the second sub-pixel (P1). It is implemented as a MOSFET of a dual gate structure together with the 3c TFT (T3c) of the pixel P2 and operates as a switch element of the second sub-pixel P2. Accordingly, the 3a TFT (T3a) is a switch element shared by the first and second sub-pixels P1 and P2. The present invention reduces the number of TFTs by allowing the 3a TFT 3a to be shared between the neighboring sub-pixels P1 and P2.

The fourth TFT (T4a) is connected between the first node (n1), the second node (n2), and the second TFTs (T2a, T2b) to control the current of OLED1 according to its gate-source voltage (Vgs). It is a driving element to control. The gate of the fourth TFT (T4a) is connected to the first node (n1), and the drain is connected to the source of the 2b TFT (T2b). The source of the fourth TFT (T4a) is connected to the anode of OLED1.

The first capacitor C1a is connected between the first node n1 and the second node n2 to store a difference voltage between both ends. The first capacitor C1a samples the threshold voltage of the fourth TFT T4a, which is a driving element, in a source follower method. The second capacitor C2a is connected between the VDD line 15 and the second node n2. When the potential of the first node n1 changes according to the data voltage Vdata in the programming period Tp, the first and second capacitors C1a and C2b divide the voltage to the second node n2. Reflect on.

The second sub-pixel P2 includes a first TFT (T1c, T1d), a second TFT (T2a, T2c), a third TFT (T3a, T3c), a fourth TFT (T4b), a first capacitor (C1b), and 2 capacitors (C2b), and OLED2.

The circuit configuration of the second sub-pixel P2 is a 4T2C structure as shown in FIGS. 2 to 8 and has an internal compensation function. Each of the first TFTs T1c and T1d, the second TFTs T2a and T2c, and the third TFTs T3a and T3c is composed of a pair of TFTs whose gates are connected to each other to reduce leakage current.

The first TFTs T1c and T1d are MOSFETs having a dual gate structure including a 1c TFT (T1c) and a 1d TFT (T1d) with gates connected to each other. The gate of the 1c TFT (T1c) is connected to the first scan line 12a, and the drain is connected to the second data line 11. The source of the 1c TFT (T1c) is connected to the drain of the 1d TFT (T1d). The gate of the 1d TFT (T1d) is connected to the first scan line 12a, and the drain is connected to the source of the 1c TFT (T1c). The source of the 1d TFT T1d is connected to the third node n3. The third node n3 is the same as the first node n1 of the first sub-pixel P1. The first TFTs T1c and T1d are switching elements that turn on/off the current path between the second data line 11 and the third node n3 by being switched in response to the first scan signal Scan1. Since the first TFTs T1c and T1d are connected to the second data line 11, they are not shared between neighboring sub-pixels P1 and P2, but must be separated for each sub-pixel.

The second TFTs T2a and T2c are MOSFETs having a dual gate structure including a 2a TFT (T2a) and a 2c TFT (T2c) with gates connected to each other. The gate of the 2a TFT (T2a) is connected to the EM line 14, and its drain is connected to the VDD line 15. The source of the 2a TFT (T2a) is connected to the drain of the 2b TFT (T2b) and the drain of the 2c TFT (T2c). The gate of the 2c TFT (T2c) is connected to the EM line 14, and its drain is connected to the source of the 2a TFT (T2a). The source of the 2c TFT (T2c) is connected to the drain of the fourth TFT (T4b). The second TFTs T2a and T2c are switching elements that turn on/off the current path between the VDD line 15 and the drain of the fourth TFT T4b by being switched in response to the emission signal EM.

The third TFTs T3a and T3c are MOSFETs having a dual gate structure including a 3a TFT (T3a) and a 3c TFT (T3c) with gates connected to each other. The gate of the 3a TFT (T3a) is connected to the second scan line 12b, and the drain is connected to the source of the 3b TFT (T3b) and the source of the 3c TFT (T3c). The source of the 3a TFT (T3a) is connected to the Vini line 13. The gate of the 3c TFT (T3c) is connected to the second scan line 12b, and the drain is connected to the fourth node n4. The fourth node n4 is the same as the second node n2 of the first sub-pixel P1. The source of the 3c TFT (T3c) is connected to the drain of the 3a TFT (T3a). The third TFTs T3a and T3b are switching elements that turn on/off the current paths of the Vini line 13 and the second node n2 by switching in response to the second scan signal Scan2.

The 3a TFT (T3a) is implemented as a MOSFET of a dual gate structure together with the 3b TFT (T3b) of the first sub-pixel (P1) to operate as a switch element of the first sub-pixel (P1), and at the same time, the second sub-pixel (P1). It is implemented as a MOSFET of a dual gate structure together with the 3c TFT (T3c) of the pixel P2 and operates as a switch element of the second sub-pixel P2. Accordingly, the 3a TFT 3a is a switch element shared by the first and second sub-pixels P1 and P2. The present invention reduces the number of TFTs by allowing the 3a TFT 3a to be shared between the neighboring sub-pixels P1 and P2.

The fourth TFT (T4b) is connected between the third node (n3), the fourth node (n4), and the second TFTs (T2a, T2c) to control the current of OLED2 according to its gate-source voltage (Vgs). It is a driving element to control. The gate of the fourth TFT (T4b) is connected to the first node (n1), and the drain is connected to the source of the 2c TFT (T2c). The source of the fourth TFT (T4b) is connected to the anode of OLED2.

The first capacitor C1b is connected between the third node n3 and the fourth node n4 to store a difference voltage between both ends. The first capacitor C1b samples the threshold voltage of the fourth TFT T4b, which is a driving element, in a source follower method. The second capacitor C2b is connected between the VDD line 15 and the fourth node n4. When the potential of the first node n1 changes according to the data voltage Vdata in the programming period Tp, the first and second capacitors C1b and C2b divide the change in voltage.

In the first and second sub-pixels P1 and P2, the 2a and 3a TFTs T2a and T3a are shared between the neighboring sub-pixels P1 and P2. Dotted circles in FIG. 9 are switch elements shared in a dual gate structure. In addition, the wiring 15 and the contact hole CH are shared between the neighboring sub-pixels P1 and P2. Accordingly, the present invention enables a pixel design having an internal compensation function and a small leakage current in a high-resolution panel by sharing a dual gate structure switch element, wiring, and contact hole between neighboring sub-pixels.

The above-described embodiment is an example in which the switch element and the driving element are implemented as an n-type MOSFET, but the present invention is not limited thereto. For example, the switch element and the driving element may be implemented as a p-type MOSFET. In this case, the ON/OFF levels of the signals controlling the switch elements are inverted.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Accordingly, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

100: display panel 102: data driver
104: scan driver 11: timing controller

Claims (6)

At least one switch element, including a driving element for supplying current to the organic light emitting diode, and a pixel having a capacitor,
Among the switch elements, a switch element connected to the driving element or the organic light emitting diode is a dual gate switch element shared between neighboring sub-pixels,
An organic light emitting diode display comprising a TFT (Thin Film Transistor) shared by the dual gate switch element and a TFT separated for each pixel in series. The method of claim 1,
The organic light-emitting display device of the adjacent sub-pixels includes first and second sub-pixels whose circuit structures are inverted to each other in a mirror reflection form. The method of claim 2,
The first sub-pixel,
A first driving element supplying current to the first organic light emitting diode;
A first dual gate switch element for turning on/off a current path between the first data line and the first node by being switched in response to the first scan signal;
A second dual gate switch element for turning on/off a current path between a power line and the first driving element by being switched in response to an emission signal;
A third dual gate switch element for turning on/off a current path between the initial signal line and the second node by being switched in response to the second scan signal;
A first capacitor connected between the first node and the second node; And
A second capacitor connected between the power line and the second node,
The first driving element is connected between the first node, the second node, and the second dual gate element to control a current of the first organic light emitting diode according to a gate-source voltage,
One of a pair of TFTs constituting the second dual gate switch element is shared between the first and second sub-pixels,
An organic light-emitting display device in which one of a pair of TFTs constituting the third dual gate switch element is shared between the first and second sub-pixels. The method of claim 3,
The second sub-pixel,
A second driving element supplying current to the second organic light emitting diode;
A fourth dual gate switch element for turning on/off a current path between a second data line and a third node by being switched in response to the first scan signal;
A fifth dual gate switch element for turning on/off a current path between the power line and the second driving element by being switched in response to the emission signal;
A sixth dual gate switch element for turning on/off a current path between the initial signal line and a fourth node by switching in response to the second scan signal;
A third capacitor connected between the third node and the fourth node; And
A fourth capacitor connected between the power line and the fourth node,
The second driving element is connected between the third node, the fourth node, and the fifth dual gate element to control a current of the second organic light emitting diode according to a gate-source voltage,
One of a pair of TFTs constituting the fifth dual gate switch element is one of a pair of TFTs constituting the second dual gate switch element,
One of a pair of TFTs constituting the sixth dual gate switch element is one of a pair of TFTs constituting the third dual gate switch element. The method of claim 4,
An organic light emitting diode display in which the power line is shared between the first and second sub-pixels. The method of claim 5,
An organic light-emitting display device in which a contact hole for connecting the power line and the second and fourth capacitors is shared between the first and second sub-pixels through an insulating layer.

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