KR20200067545A - Manufacturing method of cell - Google Patents

Abstract

The present invention relates to a method for producing a solar battery. According to an embodiment of the present invention, the method for producing a solar battery comprises: an n-type film depositing step of depositing a first conductive region, which is a silicon layer containing n-type conductive impurities, onto a first surface of a semiconductor substrate made of a silicon wafer material; and a p-type film depositing step of depositing a second conductive region, which is a silicon layer containing p-type conductive impurities, onto a second surface of the semiconductor substrate following the n-type film depositing step, wherein a first deposition temperature in the n-type film depositing step is higher than a second deposition temperature in the p-type film depositing step. In addition, a method for producing a solar battery according to another embodiment of the present invention may further comprise: an n-type film depositing step; a p-type film depositing step; a transparent electrode depositing step of depositing first and second transparent electrode layers onto first and second conductive regions after the p-type film depositing step is performed; and an electrode firing step of applying paste for first and second contact electrodes onto the first and second transparent electrode layers, respectively, and firing the same, wherein a heat treatment temperature of the electrode firing step is higher than a first deposition temperature in the n-type film depositing step and a second deposition temperature in the p-type film depositing step.

Description

Solar cell manufacturing method {Manufacturing method of cell}

The present invention relates to a method for manufacturing a solar cell, and more specifically, in depositing an amorphous silicon layer on a crystalline semiconductor substrate having a heterojunction structure, suppresses epitaxial growth of the amorphous silicon layer and improves the film quality of the amorphous silicon layer. It relates to a solar cell manufacturing method that can be maintained.

Conventionally, in manufacturing a heterojunction solar cell, in depositing an amorphous silicon thin film directly on a crystalline silicon wafer, it is made to be deposited at a higher temperature when forming an intrinsic amorphous silicon thin film, than the temperature of depositing an impurity-doped amorphous silicon thin film, Although the impurity-doped amorphous silicon thin film was subsequently deposited, the intrinsic amorphous silicon thin film was configured so as not to change.

However, such a conventional method of manufacturing a heterojunction solar cell is problematic because the intrinsic amorphous silicon thin film is easily crystallized in the deposition process by deposition at a relatively high temperature.

In addition, since the deposition temperature of the conventional intrinsic amorphous silicon thin film is higher than the deposition temperature of the impurity doped amorphous silicon thin film subsequently deposited, there is a problem that further improvement is difficult, so that crystallization of the intrinsic amorphous silicon thin film is not performed In order to do this, there is a problem in that the process conditions for forming the intrinsic amorphous silicon thin film must be very narrow.

In addition, in depositing an intrinsic amorphous silicon thin film or an impurity-doped amorphous silicon thin film in a conventional heterojunction solar cell, in order to realize optimum thin film characteristics in the final structure of the solar cell, at a temperature controlled when depositing each layer There was no specific description.

For example, in the prior art, there has been a technique of depositing an intrinsic amorphous silicon thin film or an impurity-doped amorphous silicon thin film at 350°C or less, but how to control the formation temperature of n impurity-doped amorphous silicon and p impurity-doped amorphous silicon. There was no way to recognize and solve problems.

An object of the present invention is to provide a method for manufacturing a solar cell, which can further improve efficiency.

More specifically, the present invention, in depositing an amorphous silicon layer on a crystalline semiconductor substrate having a heterojunction structure, suppresses the epitaxial growth of the amorphous silicon layer, and a method of manufacturing a solar cell capable of maintaining the film quality of the amorphous silicon layer satisfactorily The purpose is to provide.

A solar cell manufacturing method according to an example of the present invention includes an n-type film deposition step of depositing a first conductive type region, which is a silicon layer containing an n-type conductive type impurity, on a first surface of a silicon semiconductor substrate; And a p-type film deposition step of depositing a second conductive type region, which is a silicon layer containing a p-type conductivity type impurity, on the second surface of the semiconductor substrate after the n-type deposition step. 1 The deposition temperature is higher than the second deposition temperature in the p-type film deposition step.

For example, the first deposition temperature in the n-type film deposition step may be between 160°C and 250°C, and the second deposition temperature in the p-type film deposition step is 150 in a range lower than the first deposition temperature in the n-type film deposition step. It may be between ℃ and 200 ℃.

In addition, the solar cell manufacturing method includes a first passivation layer deposition step of depositing a first passivation layer made of an intrinsic silicon layer on a first surface of a semiconductor substrate before the n-type film deposition step; and a p-type film deposition step after the n-type film deposition step Previously, a second passivation layer deposition step of depositing a second passivation layer made of an intrinsic silicon layer material on the second surface of the semiconductor substrate may be further provided.

Here, the third deposition temperature of each of the first passivation layer deposition step and the second passivation layer deposition step may be the same, and may be lower than the first and second deposition temperatures. However, the present invention is not limited thereto, and the third deposition temperature of each of the first passivation layer deposition step and the second passivation layer deposition step may be different in a range lower than the first and second deposition temperatures.

For example, the third deposition temperature may be between 140°C and 180°C in a range lower than the first and second deposition temperatures.

In addition, the first passivation layer deposition step and the n-type film deposition step are performed in the same first chamber, and after the first passivation layer deposition step and the n-type film deposition step, the second passivation layer deposition step and the p-type film deposition step are the first. It may be performed in a second chamber different from the chamber.

As an example, after the semiconductor substrate is loaded into the first chamber for the first passivation layer deposition step, the internal temperature of the first chamber is increased at a first temperature change rate from room temperature to the third deposition temperature, and then the first passivation layer After the deposition step is performed and the first passivation layer deposition step is performed, the internal temperature of the first chamber is increased from the third deposition temperature to the first deposition temperature at a slower second temperature change rate than the first temperature change rate. Thereafter, an n-type film deposition step is performed, and may be unloaded from the first chamber.

Thereafter, after the n-type film deposition step, the semiconductor substrate is loaded into the second chamber, and then the internal temperature of the second chamber is increased at a first temperature change rate from room temperature to the third deposition temperature, and then the second passivation layer deposition step is performed. Is performed, and after the second passivation layer deposition step is performed, the internal temperature of the second chamber is increased from the third deposition temperature to the second deposition temperature at a slower second temperature change rate than the first temperature change rate, A p-type film deposition step may be performed and unloaded from the second chamber.

Here, the second deposition time deposited by the p-type film deposition step may be longer than the first deposition time deposited by the n-type film deposition step, and the third deposition time deposited by the first and second passivation layer deposition steps may be Same, and may be shorter than the first and second hours.

Here, the first and second conductivity-type regions formed by the n-type film deposition step and the p-type film deposition step are amorphous silicon material or microcrystalline silicon material, and are formed by the first passivation layer deposition step and the second passivation layer deposition step. The first and second passivation layers may be at least one of an amorphous silicon oxide material, an amorphous silicon material, or a microcrystalline silicon material.

In the solar cell manufacturing method, after the n-type film deposition step and the p-type film deposition step are performed, the first transparent electrode layer is formed on the first conductive type region and the second transparent electrode layer is deposited on the second conductive type region, respectively. step; And an electrode firing step of applying and firing first and second contact electrode pastes on each of the first and second transparent electrode layers, wherein the heat treatment temperature of the electrode firing step may be higher than the first and second deposition temperatures. .

Here, the deposition temperature of the transparent electrode deposition step is between 100°C and 200°C, and the heat treatment temperature of the electrode firing step may be between 170°C and 350°C in a range higher than the first and second deposition temperatures.

In addition, a solar cell manufacturing method according to another example of the present invention includes an n-type film deposition step of depositing a first conductivity-type region containing an n-type conductivity type impurity on a first surface of a semiconductor substrate having a silicon wafer material; After the n-type deposition step, a p-type film deposition step of depositing a second conductivity type region containing a p-type conductivity type impurity on the second surface of the semiconductor substrate; a transparent electrode deposition step of depositing a first transparent electrode layer on the first conductivity type region and depositing a second transparent electrode layer on the second conductivity type region after the p-type film deposition step is performed; And an electrode firing step of applying and firing first and second contact electrode pastes on each of the first and second transparent electrode layers, wherein the heat treatment temperature of the electrode firing step is the first deposition temperature in the n-type film deposition step and It may be higher than the second deposition temperature in the p-type film deposition step.

Here, the first deposition temperature in the n-type film deposition step may be higher than the second deposition temperature in the p-type film deposition step.

The present invention by first depositing a silicon layer containing an impurity of n-type conductivity type deposited at a relatively high temperature, and subsequently depositing a silicon layer containing an impurity of p-type conductivity type on top to be deposited at a relatively low temperature, It is possible to prevent deterioration of the film quality of the silicon layer containing p-type conductivity type impurities.

In addition, the present invention deposits the intrinsic silicon layer forming the first and second passivation layers at a relatively low temperature, and deposits an impurity-doped silicon layer at a relatively high temperature, thereby forming the intrinsic silicon layer by a subsequent heat treatment effect. The film properties can be further improved, and by depositing the intrinsic silicon layer at a relatively low temperature, it is possible to suppress epitaxial growth occurring during high temperature deposition.

1 is a partial cross-sectional view of a solar cell for explaining a solar cell manufactured according to an example of the present invention.
2 is a flowchart illustrating a method of manufacturing the solar cell shown in FIG. 1 according to an example of the present invention.
3 is a view for explaining a temperature profile applied to the first chamber performing the first passivation layer deposition step and the n-type film deposition step of FIG. 2.
4 is a view for explaining a temperature profile applied to the second chamber performing the second passivation layer deposition step and the p-type film deposition step of FIG. 2.
5 is a view for explaining a concentration change characteristic according to the enthalpy (H) each conductive type region receives in the deposition step for each conductive type region.
6 is a view for explaining the effect on the manufacturing method of the present invention, taking into account the characteristics of the doping concentration change according to the enthalpy of FIG. 5.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily practice. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. In addition, in order to clearly describe the present invention in the drawings, parts irrelevant to the description are omitted, and like reference numerals are assigned to similar parts throughout the specification.

In the drawings, the thickness is enlarged to clearly express the various layers and regions. When a portion of a layer, film, region, plate, or the like is said to be “above” another portion, this includes not only the case “directly above” other portions, but also other portions in between. Conversely, when one part is "just above" another part, it means that there is no other part in the middle. In addition, when a part is formed “overall” on another part, it means that not only is formed on the entire surface (or the entire surface) of the other part, but also not formed on a part of the edge.

In addition, hereinafter, the meaning that the thickness, width, or length of a component is the same is compared with the thickness, width, or length of a second component, in which the thickness, width, or length of a first component is considered in consideration of process errors. Therefore, it means that it is in the error range of 10%.

Hereinafter, the first surface of the semiconductor substrate refers to any one of the planes of the semiconductor substrate, and the second surface of the semiconductor substrate refers to a surface positioned opposite to the first surface of the semiconductor substrate.

Then, the present invention will be described with reference to the accompanying drawings.

1 is a partial cross-sectional view of a solar cell for explaining a solar cell manufactured according to an example of the present invention.

Referring to FIG. 1, the solar cell according to the present embodiment includes a semiconductor substrate 10 including a base region 110 and a first formed on a first surface (eg, a front surface) of the semiconductor substrate 10. The passivation layer 21, the second passivation layer 31 formed on the second surface (eg, the back surface) of the semiconductor substrate 10, and the first passivation layer 21 on the first surface side of the semiconductor substrate 10 ), a first conductivity type region 20 having a first conductivity type, and a second conductivity type formed on a second passivation layer 31 on the second surface side of the semiconductor substrate 10 and having a second conductivity type It may include a region 30, a first electrode 40 electrically connected to the first conductivity type region 20, and a second electrode 50 electrically connected to the second conductivity type region 30. have.

The semiconductor substrate 10 may include a base region 110 having a first or second conductivity type by including impurities of a first or second conductivity type at a relatively low doping concentration.

The base region 110 may be formed of a single crystalline semiconductor (eg, a single crystalline or polycrystalline semiconductor, for example, single crystalline or polycrystalline silicon, particularly single crystalline silicon) including impurities of the first or second conductivity type.

In particular, when the semiconductor substrate is formed of a single crystal silicon material, it may be formed of a single crystal silicon wafer. In the manufacturing method of FIG. 2 or less, a case where the semiconductor substrate is formed of a silicon wafer material will be described as an example.

As described above, the solar cell based on the base region 110 or the semiconductor substrate 10 having few defects due to high crystallinity may have excellent electrical characteristics.

At this time, in this embodiment, the semiconductor substrate 10 may be composed of only the base region 110 that does not have a doped region formed by additional doping or the like. Accordingly, it is possible to prevent degradation of the passivation characteristics of the semiconductor substrate 10 due to the doped region.

In addition, anti-reflection structures capable of minimizing reflection may be formed on front and rear surfaces of the semiconductor substrate 10. For example, as an anti-reflection structure, a texturing structure having irregularities in the form of a pyramid or the like may be provided.

The texturing structure formed on the semiconductor substrate 10 may have a constant shape (eg, a pyramid shape) having an outer surface formed along a specific crystal plane (eg, (111) plane) of the semiconductor. When surface roughness is increased due to irregularities formed on the front surface of the semiconductor substrate 10 by the texturing, the reflectance of light entering the semiconductor substrate 10 may be lowered to minimize light loss.

However, the present invention is not limited thereto, and a texturing structure may be formed only on the first surface of the semiconductor substrate 10 or a texturing structure may not be formed on the front and rear surfaces of the semiconductor substrate 10.

A first passivation layer 21 is formed (eg, in contact) on the front surface of the semiconductor substrate 10, and a second passivation layer 31 is formed (eg, in contact) on the back surface of the semiconductor substrate 10. Thereby, the passivation characteristics can be improved.

In this case, the first and second passivation layers 21 and 31 may be formed on the front and rear surfaces of the semiconductor substrate 10, respectively.

Accordingly, while having excellent passivation characteristics, it can be easily formed without additional patterning. Since the carrier passes through the first or second passivation layers 21 and 31 to the first or second conductivity type regions 20 and 30, the thicknesses of the first and second passivation layers 21 and 31 are respectively May be smaller than the thickness of each of the first conductivity type region 20 and the second conductivity type region 30.

For example, the thickness of each of the first and second passivation layers 21 and 31 may be formed between 1 nm and 10 nm smaller than the thickness of the semiconductor substrate, and the thickness of each of the first and second conductivity type regions 20 and 3 may be different. It may be formed between 2 nm and 30 nm in a range larger than the thickness of each of the 1 and 2 passivation layers 21 and 31.

Here, the thickness of the second conductivity type region may be formed thicker than the thickness of the first conductivity type region.

In addition, as an example, the first and second passivation layers 21 and 31 are intrinsic silicon semiconductors containing a large amount of hydrogen, for example, amorphous silicon oxide material, microcrystalline silicon layer (i-mc-Si), or intrinsic amorphous It may be made of at least one of a silicon (ia-Si) layer.

Then, since the first and second passivation layers 21 and 31 have similar characteristics including the same semiconductor material as the semiconductor substrate 10 and contain a large amount of hydrogen, the passivation characteristics can be improved more effectively. Thereby, the passivation characteristics can be greatly improved.

A first conductivity type region 20 including impurities of the first conductivity type at a higher doping concentration than the semiconductor substrate 10 may be positioned on the first passivation layer 21 (eg, in contact). Further, a second conductivity type region 30 including impurities of a second conductivity type having a second conductivity type opposite to the first conductivity type at a higher doping concentration than the semiconductor substrate 10 is formed on the second passivation layer 31. Location (eg, contact).

When the first and second passivation layers 21 and 31 contact the first and second conductive regions 20 and 30, respectively, the carrier transmission path can be shortened and the structure can be simplified.

The first conductivity type region 20 and the second conductivity type region 30 are not formed by thermal diffusion into the semiconductor substrate 10, but are respectively deposited on the first and second passivation layers 21 to form a semiconductor substrate 10. Since it is formed separately, it may have a different material and/or crystal structure from the semiconductor substrate 10 so that it can be easily formed on the semiconductor substrate 10.

For example, each of the first conductivity type region 20 and the second conductivity type region 30 is an amorphous silicon material (a-Si) or fine containing a large amount of hydrogen that can be easily produced by various methods such as deposition. It may be formed by doping a crystalline silicon material (mc-Si) with impurities of the first or second conductivity type. Then, the first conductivity type region 20 and the second conductivity type region 30 can be easily formed by a simple process.

For example, the semiconductor substrate 10 may have a first conductivity type. Then, the first conductivity type region 20 has the same conductivity type as the semiconductor substrate 10 and constitutes a front electric field region having a high doping concentration, and the second conductivity type region 30 is formed with the semiconductor substrate 10. With the opposite conductivity type, the emitter region can be constructed.

Then, the second conductivity type region 30, which is the emitter region, is located at the rear surface of the semiconductor substrate 10 and does not interfere with the absorption of light to the front surface, so that it can have a sufficient thickness. In addition, since the first conductivity type region 20, which is the front electric field region, is not directly involved in photoelectric conversion, and is located on the front surface of the semiconductor substrate 10 and is related to light absorption to the front surface, it is thinner than the second conductivity type region 30. Can be formed with. Accordingly, light loss due to the first conductivity type region 20 can be minimized.

Examples of the impurity of the p-type conductivity type used as the impurity of the first or second conductivity type include Group 3 elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In), and n Examples of the impurity of the type conductivity type include Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb). In addition to this, various dopants may be used as impurities of the first or second conductivity type. For reference, in the manufacturing method of FIG. 3 or less, a case where the impurity of the first conductivity type is n-type and the impurity of the second conductivity type is p-type will be described as an example.

For example, the semiconductor substrate 10 and the first conductivity-type region 20 may have an n-type, and the second conductivity-type region 30 may have a p-type. According to this, the semiconductor substrate 10 has an n-type, so that the life of the carrier can be excellent. For example, the semiconductor substrate 10 and the first conductivity type region 20 may include phosphorus (P) as an n-type conductivity type impurity, and the second conductivity type region 30 may be a p-type conductivity type impurity. Boron (B). However, the present invention is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type.

In this embodiment, the first conductivity type region 20 and the second conductivity type region 30 are amorphous silicon materials (a-Si) or fine, each containing a large amount of hydrogen and impurities of the first or second conductivity type It may include a crystalline silicon material (mc-Si).

Accordingly, the first and second conductivity-type regions 20 and 30 include the semiconductor substrate 10 and the same semiconductor materials (ie, silicon) as the first and second passivation layers 21 and 31 (ie, silicon). ).

Thereby, the movement of the carrier can be made more effectively and a stable structure can be realized. In addition, the first passivation layer 21 and the first conductivity type region 20 are changed by an in-situ process performed continuously while changing only the source gas in the same apparatus (eg, a deposition apparatus). The second passivation layer 31 and the second conductivity type region 30 can be formed by an in-situ process performed continuously while changing only the fuel gas in the same device. This can simplify the manufacturing process.

The first electrode 40 electrically connected to the first conductive region 20 is positioned (eg, in contact), and the second electrode 50 is electrically connected to the second conductive region 30. This position (eg, contact).

The first electrode 40 may include a first transparent electrode layer 41 positioned over the first conductivity type region 20 and a first contact electrode 43 positioned over the first transparent electrode layer 41. . A ribbon, a wiring material, an interconnector, and the like for connection to another solar cell or an external circuit may be bonded on at least a portion of the first contact electrode 43.

Here, the first transparent electrode layer 41 may be entirely formed (eg, in contact) on the first conductive type region 20. As described above, when the first transparent electrode layer 41 is entirely formed on the first conductive type region 20, a desired carrier can easily reach the first contact electrode 43 through the first transparent electrode layer 41, so that it is horizontal. Resistance in the direction can be reduced. As described above, since the first transparent electrode layer 41 is formed entirely on the first conductivity type region 20, it may be formed of a material (transmissive material) capable of transmitting light. For example, the first transparent electrode layer 41 is indium tin oxide (ITO), aluminum-zinc oxide (AZO), boron-zinc oxide (BZO), indium-tungsten It may include at least one of indium tungsten oxide (IWO) and indium cesium oxide (ICO). However, the present invention is not limited to this, and may include various materials other than the first transparent electrode layer 41.

In this case, the first transparent electrode layer 41 of this embodiment may contain hydrogen while using the above-described material as a main material. As described above, when the first transparent electrode layer 41 contains hydrogen, mobility of electrons or holes may be improved and transmittance may be improved.

The first contact electrode 43 positioned on the first transparent electrode layer 41 may include metal as a main material (a material included in the largest amount) to improve characteristics such as carrier collection efficiency and resistance reduction. As the metal, various materials that provide conductivity may be used, for example, silver (Ag), aluminum (Al), copper (Cu), or tin (Sn). At this time, the first contact electrode 43 may be formed by applying and firing a paste further containing a crosslinked resin, a solvent, etc., in addition to the metal. However, since the first contact electrode 43 does not require fire-through, the first contact electrode 43 may not include a glass frit.

As described above, since the first contact electrode 43 may interfere with the incidence of light including metal, the first contact electrode 43 may have a certain pattern to minimize shading loss. Accordingly, light is allowed to enter the portion where the first contact electrode 43 is not formed. For example, the first contact electrode 43 extends in the first direction and includes a plurality of finger lines positioned parallel to each other, and a second direction intersecting (eg, orthogonal) with the first direction (vertical direction of the drawing). It may be formed to include a bus bar that is electrically connected to the first finger line. For example, the wiring material or the like may be attached or connected to one-to-one correspondence on the bus bar.

Similarly, in this embodiment, the second electrode 50 may include a second transparent electrode layer 51 and a second contact electrode 53. The roles, materials, and roles of the second transparent electrode layer 51 and the second contact electrode 53 of the second electrode 50, except that the second electrode 50 is located on the second conductivity type region 30, Since the shape, thickness, etc. are the same as the roles, materials, shapes, and thicknesses of the first transparent electrode layer 41 and the first contact electrode 43 of the first electrode 40, the description thereof may be applied as it is.

In addition, the second contact electrode 53 may include a finger line and a bus bar. At this time, the bus bar of the first contact electrode 43 and the bus bar of the second contact electrode 53 may be formed in the same number. The finger line of the first contact electrode 43 and the finger line of the second contact electrode 43 may have the same width, pitch and/or number, or may have different widths, pitches and/or numbers.

However, the present invention is not limited thereto, and the first and second transparent electrode layers 420 and 440 or the first and second contact electrodes 43 and 53 may have various materials, shapes, and thicknesses. In addition, the first and second contact electrodes 43 and 53 may have different shapes.

As described above, in this embodiment, the first and second contact electrodes 43 and 53 of the solar cell have a constant pattern so that the solar cell can receive light through the front and rear surfaces of the semiconductor substrate 10 (bi -facial) structure. Accordingly, it is possible to increase the amount of light used in the solar cell and contribute to the improvement of the efficiency of the solar cell. However, the present invention is not limited to this. Therefore, it is also possible to have a structure in which the second contact electrode 53 is formed entirely on the rear side of the semiconductor substrate 10.

So far, the structure of a solar cell that can be manufactured in the solar cell manufacturing method according to an example of the present invention has been described.

On the other hand, in the conventional heterojunction solar cell manufacturing process similar to the above-described heterojunction solar cell, epitaxial growth is performed in the first and second passivation layers 21 and 31 during the process, or p-type impurities are contained due to dehydrogenation. There was a problem that the impurity concentration in the conductive type region was lowered.

However, in the solar cell manufacturing method according to an example of the present invention, the deposition temperature of the intrinsic silicon layers forming the first and second passivation layers 21 and 31 is relatively low, and the n-type conductivity type is deposited at a relatively high temperature. The silicon layer of the first conductivity-type region 20 containing impurities is first deposited, and then the silicon layer of the second conductivity-type region 30 containing impurities of the p-type conductivity type is deposited on top of the deposition at a relatively low temperature. By vapor deposition, it is possible to prevent the film quality of the silicon layer of the second conductivity type region 30 containing the p-type conductivity type impurities from being damaged.

Hereinafter, a method of manufacturing such a heterojunction solar cell will be described in detail.

2 is a flow chart for explaining a method of manufacturing the solar cell shown in FIG. 1 according to an example of the present invention, FIG. 3 is a first passivation layer deposition step (S1) and n-type film deposition step (S2) of FIG. 2 ) Is a view for explaining a temperature profile applied to the first chamber, and FIG. 4 is applied to the second chamber performing the second passivation layer deposition step (S3) and p-type film deposition step (S4) of FIG. 2. It is a diagram for explaining a temperature profile.

As another example of the solar cell manufacturing method of the present invention, as shown in Figure 2, the first passivation layer deposition step (S1), n-type film deposition step (S2), the second passivation layer deposition step (S3), p-type film deposition Step S4, a transparent electrode forming step S5, an electrode patterning step S6, and an electrode firing step S7 may be included, and each of these steps may be sequentially performed.

Here, the first passivation layer deposition step (S1) and the n-type film deposition step (S2) may be performed by plasma chemical vapor deposition (PECVD, Plasma-enhanced chemical vapor deposition) in the first chamber, the second passivation layer deposition Step S3 and p-type film deposition step S4 may be performed by plasma chemical vapor deposition (PECVD) in a second chamber different from the first chamber.

Hereinafter, as illustrated in FIG. 2, after each step of the solar cell manufacturing method is first described, the deposition temperature and the deposition time in each step will be described with reference to FIGS. 3 and 4.

In order to perform the first passivation layer deposition step (S1), the semiconductor substrate 10 may be loaded into the first chamber. At this time, the surfaces of the first and second surfaces of the semiconductor substrate 10 to be loaded may be provided with textured irregularities, as shown in FIG. 1, and the semiconductor substrate 10 uses a thin wafer of 150 μm or less. Can be.

In the first passivation layer deposition step (S1), after the semiconductor substrate 10 is loaded into the first chamber, the plasma formed by plasma chemical vapor deposition (PECVD) in the first chamber is used to epitaxial the intrinsic silicon layer material. In order to suppress growth, the first passivation layer 21 made of an intrinsic silicon layer may be deposited on the first surface of the semiconductor substrate 10 at a relatively low third deposition temperature T3. In this case, the first passivation layer 21 may be directly formed on the first surface of the semiconductor substrate 10.

After the first passivation layer deposition step S1 is performed in the first chamber, the n-type film deposition step S2 is continuously performed by a plasma chemical vapor deposition method (PECVD) at a relatively high first deposition temperature T1. In order to form the first conductivity type region 20 directly on the first passivation layer 21 formed on the first surface of (10), a silicon layer containing an n-type conductivity type impurity may be deposited.

The first deposition temperature T1 of the n-type film deposition step S2 is the second deposition temperature T2 of the p-type film deposition step S4 and the third deposition temperature T3 of the first passivation layer deposition step S1. ).

As described above, in order to deposit the first passivation layer 21 and the first conductivity type region 20 only on the first surface of the semiconductor substrate 10 in the first chamber, the semiconductor substrate 10 is loaded into the first chamber. When the two semiconductor substrates 10 are provided in a pair, each of the first surfaces of the pair of semiconductor substrates 10 may be loaded in contact with each other, after which the first passivation layer deposition step (S1) ) And an n-type film deposition step (S2) are performed, so that the first passivation layer 21 and the first conductivity type region 20 may be deposited only on the first surface, which is the outer surface of the pair of semiconductor substrates 10. . However, it is not necessarily limited to this.

Thereafter, the semiconductor substrate 10 may be unloaded from the first chamber and loaded into the second chamber. At this time, after the semiconductor substrate 10 is unloaded from the first chamber and before being loaded into the second chamber, the second passivation layer 31 and the second conductivity type region 30 only on the second surface of the semiconductor substrate 10 ) To be deposited, after unloading from the first chamber, the pair of semiconductor substrates 10 are separated from each other, and then each semiconductor substrate so that each second surface of the pair of semiconductor substrates 10 abuts each other With the 10 positioned, a pair of semiconductor substrates 10 can be loaded into the second chamber.

In the second passivation layer deposition step (S3), after the semiconductor substrate 10 is loaded into the second chamber, the plasma formed by plasma chemical vapor deposition (PECVD) in the second chamber is used to epitaxial the intrinsic silicon layer material. In order to suppress growth, a second passivation layer 31 made of an intrinsic silicon layer material may be deposited on the second surface of the semiconductor substrate 10 at a relatively low third deposition temperature T3. At this time, the second passivation layer 31 may be directly formed on the second surface of the semiconductor substrate 10.

After the second passivation layer deposition step S3 is performed in the second chamber, the p-type film deposition step S4 is continuously performed by plasma chemical vapor deposition (PECVD), and the first deposition temperature T1 and the third deposition temperature. At a second deposition temperature T2 having a value between (T3), a second containing a p-type conductivity type impurity directly on the second passivation layer 31 deposited on the second surface of the semiconductor substrate 10 The conductive region 30 may be deposited.

Thereafter, the semiconductor substrate 10 on which the second passivation layer 31 and the second conductivity type region 30 are deposited on the second surface may be unloaded from the second chamber.

Subsequently, in the transparent electrode forming step S5, after the n-type film deposition step S2 and the p-type film deposition step S4 are performed, the first transparent electrode layer 41 is deposited on the first conductivity type region 20 and removed. The second transparent electrode layer 51 may be deposited on the second conductivity type region 30. The deposition temperature of the transparent electrode forming step (S5) may be between 100°C and 200°C.

After the transparent electrode forming step (S5) is completed, the electrode patterning step (S6) and the electrode firing step (S7) may be performed.

In the electrode patterning step S6, the paste for the first contact electrode 43 is applied in a predetermined pattern on the first transparent electrode layer 41 formed on the first surface of the semiconductor substrate 10, and the semiconductor substrate 10 is On the second transparent electrode layer 51 formed on the second surface, the paste for the second contact electrode 53 may be applied in a predetermined pattern.

That is, in the electrode patterning step (S6), the finger line and the bus bar of the first contact electrode 43 are applied in a predetermined pattern to the first transparent electrode layer 41 as a paste for the first contact electrode 43, followed by drying. A finger line and a bus bar of the second contact electrode 53 may be coated on the second transparent electrode layer 51 as a paste for the second contact electrode 53 in a predetermined pattern and then dried.

Then, in the electrode firing step (S7), the paste for the first contact electrode 43 patterned on the first transparent electrode layer 41 and the paste for the second contact electrode 53 patterned on the second transparent electrode layer 51. After heat treatment and sintering, the first contact electrode 43 is formed on the first transparent electrode layer 41 positioned on the first surface of the semiconductor substrate 10, and on the second surface of the semiconductor substrate 10. The second contact electrode 53 may be formed on the second transparent electrode layer 51.

At this time, the heat treatment temperature of the electrode firing step (S7) may be higher than the first and second deposition temperatures (T1, T2), for example, in the range higher than the first and second deposition temperatures (T1, T2), 170 ℃ ~ 350°C.

In the solar cell manufacturing process, the first and second conductive regions 20 and 30 formed by the n-type film deposition step (S2) and the p-type film deposition step (S4) may be formed of an amorphous silicon material or a microcrystalline silicon material. However, hereinafter, an example in which the first and second conductive regions 20 and 30 formed by the n-type film deposition step S2 and the p-type film deposition step S4 are formed of an amorphous silicon material will be described as an example.

In addition, the first and second passivation layers 21 and 31 formed by the first passivation layer deposition step (S1) and the second passivation layer deposition step (S3) are amorphous silicon oxide material, amorphous silicon material, or microcrystalline silicon material The first and second passivation layers 21 and 31 formed by the first passivation layer deposition step (S1) and the second passivation layer deposition step (S3) may be formed of at least one of amorphous silicon materials. The case where it is formed is explained as an example.

The solar cell manufacturing method according to an example of the present invention performs the n-type film deposition step (S2) deposited at a relatively high temperature first, and the p-type film deposition step at a temperature relatively lower than the temperature of the n-type film deposition step (S2). By performing (S4) after the n-type film deposition step (S2), the film quality of the second conductivity-type region 30, which is a silicon layer containing impurities of the p-type conductivity type, is deposited on the p-type film deposition step (S4). Deterioration can be prevented.

In addition, the solar cell manufacturing method according to an example of the present invention deposits the first and second passivation layers 21 and 31 made of an intrinsic silicon layer material at a relatively low temperature, and contains impurities of an n-type or p-type conductivity type By depositing the silicon layer first and second conductivity type regions 20 and 30 at a relatively high temperature, the first and second passivation layers are formed by heat treatment effects of the n-type film deposition step (S2) and the p-type film deposition step (S4). It is possible to further improve the film properties of (21, 31), and by depositing the first and second passivation layers 21 and 31 made of an intrinsic silicon layer at a relatively low temperature, epitaxial generated during high temperature deposition. Growth can be suppressed.

Hereinafter, specific deposition temperatures and times of each deposition step will be described with reference to FIGS. 3 and 4.

3, after the semiconductor substrate 10 is loaded into the first chamber for the first passivation layer deposition step (S1), the internal temperature of the first chamber is from room temperature to the third deposition temperature (T3) It may be increased at a first temperature change rate (V1).

Here, the normal temperature may mean 25°C as an example. Here, the first temperature change rate (V1), for example, may be between 1 ℃ / sec ~ 50 ℃ / sec.

As such, after the temperature inside the first chamber is increased to the third deposition temperature T3, the first passivation layer deposition step S1 may be performed during the third deposition time P3 at the third deposition temperature T3. have.

The third deposition temperature T3 of the first passivation layer deposition step S1 may be lower than the first and second deposition temperatures T1 and T2, for example, and lower than the first and second deposition temperatures T1 and T2. In the range may be between 140 ℃ ~ 180 ℃. In addition, the third deposition time P3 may be a time shorter than the first and second deposition times P1 and P2, which will be described later, for example, 3 seconds in a range shorter than the first and second deposition times P1 and P2. It can be between 20 seconds.

Accordingly, the first passivation layer deposition step (S1) may be performed for a relatively short third deposition time P3 at a relatively low third deposition temperature T3, thereby causing the first of the semiconductor substrate 10 to be performed. The epitaxial growth of the first passivation layer 21, which is an intrinsic silicon layer deposited on the surface, can be more effectively suppressed.

The first passivation layer 21 may be deposited on the first surface of the semiconductor substrate 10 by the first passivation layer deposition step S1 as described above, for example, between 1 nm and 10 nm.

As such, after the first passivation layer deposition step S1 is performed, the internal temperature of the first chamber is slower than the first temperature change rate V1 from the third deposition temperature T3 to the first deposition temperature T1. It can be increased by one second temperature change rate (V2).

Here, the second temperature change rate (V2) in the first chamber may be gentler than the first temperature change rate (V1), for example, 0.5 °C / in a more gentle range than the first temperature change rate (V1) It may be between sec ~ 30 ℃ / sec.

As described above, after the first passivation layer deposition step (S1) is performed, hydrogen contained in the first passivation layer 21 is increased by relatively slowly raising the temperature inside the first chamber at the second temperature change rate V2. Can minimize dehydrogenation of.

As such, in a state where the internal temperature of the first chamber reaches the first deposition temperature T1, the n-type film deposition step S2 may be performed during the first deposition time P1 at the first deposition temperature T1. have.

Here, the first deposition temperature (T1) is higher than the third deposition temperature (T3), may be higher than the second deposition temperature (T2) to be described later, for example, the first deposition temperature (T1) is the third deposition temperature ( T3) and may be between 160°C and 250°C in a range higher than the second deposition temperature T2.

The first deposition time P1 deposited by the n-type film deposition step S2 is longer than the third deposition time P3 at which the first passivation layer deposition step S1 is performed, and the p-type film deposition step S4 is performed. It may be shorter than the second deposition time (P2). For example, the first deposition time P1 may be a time between 5 seconds and 1 minute in a range longer than the third deposition time P3 and shorter than the second deposition time P2.

Through the n-type film deposition step (S2), the impurity silicon layer of the n-type conductivity type deposited on the first passivation layer 21 to form the first conductivity type region 20 is the first passivation layer 21 It is deposited thicker, for example, may be deposited between 2nm to 20nm.

Here, the n-type conductivity type impurity contained in the first conductivity-type region 20 may be phosphorus (P), for example.

As described above, after the n-type film deposition step S2 is performed, the internal temperature of the first chamber is lowered to room temperature at a first temperature change rate V1, and the semiconductor substrate 10 can be unloaded from the first chamber. have.

Thereafter, the semiconductor substrate 10 is loaded into the second chamber, and a silicon layer may be deposited on the second surface of the semiconductor substrate 10.

After the semiconductor substrate 10 is loaded into the second chamber, the internal temperature of the second chamber is increased at a first temperature change rate V1 from room temperature to the third deposition temperature T3, and then a second passivation layer deposition step is performed. (S3) may be performed.

Here, the third deposition temperature T3 of the second chamber may be the same as the third deposition temperature T3 of the first chamber. That is, the third deposition temperature T3 of the first passivation layer deposition step S1 and the third deposition temperature T3 of the second passivation layer deposition step S3 may be the same. However, the present invention is not limited thereto, and the third deposition temperature T3 of the first passivation layer deposition step S1 and the third deposition temperature T3 of the second passivation layer deposition step S3 are first and second deposition. It is also possible that they are different in a range lower than the temperatures T1 and T2.

Accordingly, the third deposition temperature T3 of the second passivation layer deposition step S3 may be lower than the first and second deposition temperatures T1 and T2, for example, and the first and second deposition temperatures T1 and T2. It may be between 140°C and 180°C in a lower range.

In addition, the time at which the second passivation layer deposition step (S3) is performed is also the same as the third deposition time (P3) at which the first passivation layer deposition step (S1) is performed, and the first and second deposition times (P1, P2) are performed. ), and may be, for example, a time between 3 seconds and 20 seconds in a range shorter than the first and second deposition times P1 and P2.

Accordingly, the second passivation layer deposition step (S3) may be performed for a relatively short third deposition time (P3) at a relatively low third deposition temperature (T3 ), whereby the second passivation of the semiconductor substrate 10 is performed. The epitaxial growth of the second passivation layer 31, which is an intrinsic silicon layer deposited on the surface, can be more effectively suppressed.

The second passivation layer 31 may be directly deposited on the second surface of the semiconductor substrate 10 between 1 nm and 10 nm, for example, by the second passivation layer deposition step (S3 ).

In addition, the first temperature change rate V1 in the second chamber may be the same as the first temperature change rate V1 in the first chamber.

As such, after the second passivation layer deposition step S3 is performed, the internal temperature of the second chamber is slower than the first temperature change rate V1 from the third deposition temperature T3 to the second deposition temperature T2. After increasing to a second temperature change rate V2, a p-type film deposition step S4 may be performed.

Here, the second temperature change rate V2 in the second chamber may be the same as the second temperature change rate V2 in the first chamber, and accordingly, the second temperature change rate in the second chamber ( V2) may be slower than the first temperature change rate V1, and may be, for example, between 0.5°C/sec and 30°C/sec in a slower range than the first temperature change rate V1.

As described above, after the second passivation layer deposition step (S3) is performed, hydrogen contained in the second passivation layer 31 is increased by relatively slowly raising the temperature inside the second chamber at the second temperature change rate V2. Can minimize dehydrogenation of.

As such, in a state where the internal temperature of the second chamber reaches the second deposition temperature T2, the p-type film deposition step S4 may be performed during the second deposition time P2 at the second deposition temperature T2. have.

Here, the second deposition temperature (T2) in the p-type film deposition step (S4) is lower than the first deposition temperature (T1) in the n-type film deposition step (S2), than the temperature of the second passivation layer deposition step (S3) It can be set at a high range.

In one example, the second deposition temperature (T2) in the p-type film deposition step (S4) is lower than the first deposition temperature (T1) in the n-type film deposition step (S2), the temperature of the second passivation layer deposition step (S3) It can be determined between 150°C and 200°C in a higher range.

Therefore, the difference (D2) between the second deposition temperature (T2) and the third deposition temperature (T3) performed in each of the second passivation layer deposition step (S3) and the p-type film deposition step (S4) of the second chamber is the first. It may be smaller than the difference (D1) between the first deposition temperature (T1) and the third deposition temperature (T3) performed in each of the first passivation layer deposition step (S1) and the n-type film deposition step (S2) of the chamber.

Accordingly, after the second passivation layer deposition step (S3), in order to perform the p-type film deposition step (S4), when raising the temperature inside the second chamber, the second deposition temperature (T2) and the third deposition temperature ( The difference (D2) of T3) is relatively small, and the hydrogen contained in the second passivation layer 31, which is the intrinsic silicon layer deposited in the second passivation layer deposition step (S3), is dehydrogenated (out diffusion). It can be improved.

Here, the second deposition time (P2) deposited by the p-type film deposition step (S4) is the first deposition time (P1) and the second passivation layer deposition step (S3) deposited by the n-type film deposition step (S2) It may be longer than the third deposition time P3.

For example, the second deposition time P2 deposited by the p-type film deposition step S4 may be determined between 10 seconds and 2 minutes in a range longer than the first deposition time P1 and the third deposition time P3. .

Accordingly, the second conductivity type region 30 deposited by the p-type film deposition step S4 may be deposited thicker than the second passivation layer 31 and the first conductivity type region 20, for example, 3 nm. It can be deposited between ~ 30nm. Here, the p-type conductivity type impurity contained in the second conductivity type region 30 may be boron (B), for example.

Here, the second deposition time (P2) of the p-type film deposition step (S4) is longer than the first deposition time (P1) of the n-type film deposition step (S2), so that the thickness of the second conductivity type region (30) is the first The reason for making it thicker than the thickness of the conductive region 20 is as follows.

Phosphorus (P) contained as an impurity of the n-type conductivity type in the first conductivity type region 20 is relatively more diffused than boron (B) contained as an impurity of p-type conductivity type in the second conductivity type region 30. It has fast material properties.

Therefore, boron (B) during the p-type film deposition step (S4) may be contained in the amorphous silicon with a relatively low doping density.

That is, the second deposition time P2 of the p-type film deposition step S4 of depositing the second conductivity type region 30 containing boron B is the first deposition time P1 of the n-type film deposition step S2. ), the boron (B) doping density in the second conductivity type region 30 may be relatively lower than the phosphorus (P) doping density in the first conductivity type region 20, and accordingly, the first conductivity type When the film thickness of the region 20 and the second conductivity type region 30 are the same, the total doping concentration of the boron B contained in the second conductivity type region 30 is the first conductivity type region 20 ) May be relatively smaller than the total doping concentration of phosphorus (P), and accordingly, the impurity concentration between the first conductivity type region 20 and the second conductivity type region 30 may not be balanced with each other. have.

Accordingly, the second deposition time P2 of the p-type film deposition step S4 of depositing the second conductivity type region 30 containing boron B is the first deposition time of the n-type film deposition step S2 ( P1) to make the film thickness of the second conductivity type region 30 larger than the thickness of the first conductivity type region 20, thereby making the first conductivity type region 20 and The impurity concentrations between the second conductivity type regions 30 may be balanced with each other.

In addition, in the solar cell manufacturing method according to the present invention, as an example, the second deposition temperature (T2) of the p-type film deposition step (S4) for the second conductivity-type region 30 containing boron (B) is n-type film deposition Boring during the p-type film deposition step (S4) by being deposited after the n-type film deposition step (S2) having a relatively high first deposition temperature (T1) while being lower than the first deposition temperature (T1) of the step (S2) The dehydrogenation phenomenon in the second conductivity type region 30 containing (B) can be suppressed as much as possible, and the concentration of boron (B) in the second conductivity type region 30 is prevented from decreasing, and the sun The efficiency of the battery can be further improved. The effect of preventing the concentration of boron B in the second conductivity type region 30 from being lowered will be described later in more detail in FIGS. 5 and 6.

Then, thereafter, the transparent electrode forming step (S5) is performed at a deposition temperature between 100° C. and 200° C., depositing the first transparent electrode layer 41 on the first conductive type region 20, and the second conductive type region ( 30) A second transparent electrode layer 51 may be deposited thereon.

After the transparent electrode forming step (S5) is completed, the electrode patterning step (S6) and the electrode firing step (S7) may be performed as described in FIG. 2.

At this time, the heat treatment temperature of the electrode firing step (S7) may be higher than the first and second deposition temperatures (T1, T2), for example, in the range higher than the first and second deposition temperatures (T1, T2), 170 ℃ ~ 350°C.

Thus, even if the heat treatment temperature of the electrode firing step (S7) is performed in a range higher than the first and second deposition temperatures (T1 and T2), the n-type film deposition step (S2) containing the impurity of the n-type conductivity type deposited Dehydrogenation of the first conductivity type region 20, which is a silicon layer, or dehydrogenation of the second conductivity type region 30, which is a silicon layer containing impurities of the p-type conductivity type deposited in the p-type film deposition step S4, is not a problem. It may not.

That is, before the electrode firing step (S7), the first conductivity type region 20, which is a silicon layer already containing an impurity of n-type conductivity type, and the second conductivity type, which is a silicon layer containing an impurity of p-type conductivity type. First and second transparent electrode layers 41 and 51 are formed on each of the regions 30, even if the heat treatment temperature of the electrode firing step (S7) is increased, the first and second conductivity type regions 20 and 30 are respectively Above, each of the first and second transparent electrode layers 41 and 51 serves as a capping layer to prevent impurities contained in each of the first and second conductivity type regions 20 and 30 from being out diffusion. Can be.

Hereinafter, the effect of preventing the concentration of boron B in the second conductivity type region 30 from being lowered will be described in more detail.

5 is a view for explaining the concentration change characteristic according to the enthalpy (H) of each conductive type region in the deposition step for each conductive type region, and FIG. 6 considers the doping concentration change characteristic according to the enthalpy of FIG. 5 , It is a view for explaining the effect on the manufacturing method of the present invention.

More specifically, (a) of FIG. 5 is an n-type conductivity type impurity (eg, phosphorus (p)) concentration and enthalpy (H) contained in the first conductivity type region 20 during the n-type film deposition step (S2). ), and FIG. 5( b) is a p-type conductivity type impurity (eg, boron (B)) contained in the second conductivity type region 30 during the p-type film deposition step (S4 ). It is a graph showing the relationship between concentration and enthalpy (H).

As illustrated in FIG. 5A, the concentration of an n-type conductivity type impurity (eg, phosphorus (p)) contained in the first conductivity-type region 20 during the n-type film deposition step S2 is the first. Even if the enthalpy (H), which is the total amount of heat received by the conductive region 20, is increased, it can be satisfactorily maintained at a specific enthalpy.

That is, during the n-type film deposition step (S2), even if the first deposition temperature T1 is increased to increase the enthalpy (H), which is the amount of heat received by the first conductive type region 20 to be deposited, the first conductivity The outdiffusion of hydrogen contained in the mold region 20 proceeds relatively slowly, so that the concentration of phosphorus (p) doping in the first conductivity type region 20 can be maintained relatively good.

However, as shown in FIG. 5(b), the concentration of impurities of p-type conductivity (eg, boron (B)) contained in the second conductivity-type region 30 during the p-type film deposition step (S4) is When the enthalpy (H), which is the total amount of heat received by the second conductivity type region 30, is increased, there is a characteristic of rapidly decreasing.

That is, during the p-type film deposition step (S4), the second deposition temperature (T2) is relatively high, and the enthalpy (H), which is the amount of heat received by the deposited second conductive type region (30), also increases. , The doping concentration of the boron (B) contained in the second conductivity type region 30 is rapidly reduced.

There are two reasons for having the characteristics as shown in Fig. 5B.

First, when the boron (B) receives heat from the outside, compared to phosphorus (P), boron (B) has a relatively fast diffusion material property.

Therefore, during the p-type film deposition step (S4), when the boron (B) combined with silicon receives heat, the boron (B) may break the bond with the silicon and diffuse rapidly, and the boron (B) quickly falls out of the film. Will come out.

Second, it is because the mutual bonding force of boron (B) and hydrogen (H) that are bonded to each other during the p-type film deposition step (S4) is vulnerable to heat.

Therefore, when the enthalpy (H) is increased during the p-type film deposition step (S4), the boron (B) absorbs heat, so that the boron (B) and hydrogen (H) break each other, and the boron (B) and Boron (B), which is a p-type conductivity type in the film of the second conductivity type region 30, is subjected to out hydrogenation (out diffusion) that quickly escapes out of the thin film of the second conductivity type region 30 where each of the hydrogen H is deposited. ) Doping concentration is rapidly reduced.

Accordingly, when the second deposition temperature T2 of the p-type film deposition step S4 is increased to the level of the first deposition temperature T1 of the n-type film deposition step S2, as a result, the second conductivity type region 30 to be deposited ) In the thin film of boron (B) and hydrogen (H) is mutually disconnected from each other and quickly out of the thin film (out diffusion) proceeds, the film quality characteristics of the second conductivity type region 30 is rapidly deteriorated Can be.

Accordingly, in consideration of the characteristics of the boron, the present invention is based on the enthalpy H1, which is the amount of heat received by the first deposition temperature T1 in the n-type film deposition step (S2), as illustrated in FIG. 6. By reducing the second deposition temperature (T2) during the p-type film deposition step (S4) relatively lower than the first deposition temperature (T1), by reducing the enthalpy at the p-type film deposition step (S4) relative to H1 or lower H2 level, During the p-type film deposition step S4, out diffusion of the second conductivity type region 30 is suppressed, thereby preventing deterioration of the film quality characteristics of the second conductivity type region 30.

Accordingly, the present invention first deposits a silicon layer containing an n-type conductivity type impurity deposited at a relatively high temperature, and deposits a silicon layer containing a p-type conductivity type impurity on top of it deposited at a relatively low temperature. By doing so, it is possible to prevent the film quality of the silicon layer containing p-type conductivity type impurities from being damaged.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (16)

An n-type film deposition step of depositing a first conductivity type region, which is a silicon layer containing an n-type conductivity type impurity, on a first surface of the silicon semiconductor substrate; And
After the n-type deposition step, a p-type film deposition step of depositing a second conductive type region, a silicon layer containing a p-type conductivity type impurity on the second surface of the semiconductor substrate opposite to the first surface; includes and,
The first deposition temperature in the n-type film deposition step is a method of manufacturing a solar cell higher than the second deposition temperature in the p-type film deposition step. According to claim 1,
The first deposition temperature in the n-type film deposition step is a method of manufacturing a solar cell between 160 ℃ ~ 250 ℃. According to claim 1,
The second deposition temperature in the p-type film deposition step is a method of manufacturing a solar cell between 150 ℃ ~ 200 ℃ in a range lower than the first deposition temperature in the n-type film deposition step. According to claim 1,
The solar cell manufacturing method
Before the n-type film deposition step, a first passivation layer deposition step of depositing a first passivation layer of an intrinsic silicon layer material on the first surface of the semiconductor substrate; And
And a second passivation layer deposition step of depositing a second passivation layer made of an intrinsic silicon layer on the second surface of the semiconductor substrate after the n-type film deposition step and before the p-type film deposition step. . According to claim 4,
The third passivation temperature of the first passivation layer deposition step and the second passivation layer deposition step are the same as each other, and a method of manufacturing a solar cell lower than the first and second deposition temperatures. According to claim 4,
The third deposition temperature is a method of manufacturing a solar cell between 140 ℃ ~ 180 ℃ in a range lower than the first and second deposition temperature. According to claim 4,
The first passivation layer deposition step and the n-type film deposition step are performed in the same first chamber,
After the first passivation layer deposition step and the n-type film deposition step, the second passivation layer deposition step and the p-type film deposition step are performed in a second chamber different from the first chamber. The method of claim 5,
After the semiconductor substrate is loaded into the first chamber for the first passivation layer deposition step, after the internal temperature of the first chamber is increased from room temperature to the third deposition temperature at a first temperature change rate, the first 1 passivation layer deposition step is performed,
After the first passivation layer deposition step is performed, the internal temperature of the first chamber is increased from the third deposition temperature to the first deposition temperature at a slower second temperature change rate than the first temperature change rate. , The n-type film deposition step is performed, the method of manufacturing a solar cell unloaded from the first chamber. The method of claim 5,
After the n-type film deposition step, the semiconductor substrate is loaded into the second chamber, and then the internal temperature of the second chamber is increased from room temperature to the third deposition temperature at the rate of change of the first temperature, and then the first 2, the passivation layer deposition step is performed,
After the second passivation layer deposition step is performed, after the internal temperature of the second chamber is increased from the third deposition temperature to the second deposition temperature at a slower second temperature change rate than the first temperature change rate , The p-type film deposition step is performed, the method of manufacturing a solar cell unloaded from the second chamber. According to claim 4,
The second deposition time deposited by the p-type film deposition step is a method of manufacturing a solar cell longer than the first deposition time deposited by the n-type film deposition step. The method of claim 10,
The third deposition time deposited by the first and second passivation layer deposition steps is equal to each other, and the method for manufacturing a solar cell shorter than the first and second hours. According to claim 4,
The first and second conductivity type regions formed by the n-type film deposition step and the p-type film deposition step are amorphous silicon material or microcrystalline silicon material,
The first and second passivation layers formed by the first passivation layer deposition step and the second passivation layer deposition step are at least one of an amorphous silicon oxide material, an amorphous silicon material, or a microcrystalline silicon material. . According to claim 1,
The solar cell manufacturing method
After the n-type film deposition step and the p-type film deposition step is performed,
Forming a transparent electrode layer on each of the first transparent electrode layer and the second transparent electrode layer on the first conductive type region; And
Further comprising: an electrode firing step of applying and firing a paste for the first and second contact electrodes on each of the first and second transparent electrode layers;
The method of manufacturing a solar cell having a heat treatment temperature higher than the first and second deposition temperatures of the electrode firing step. The method of claim 13,
The deposition temperature of the transparent electrode deposition step is between 100 ℃ ~ 200 ℃,
The heat treatment temperature of the electrode firing step is higher than the first and second deposition temperature, a method of manufacturing a solar cell between 170 ℃ to 350 ℃. An n-type film deposition step of depositing a first conductivity-type region containing an n-type conductivity type impurity on a first surface of the silicon semiconductor substrate;
After the n-type deposition step, a p-type film deposition step of depositing a second conductivity type region containing a p-type conductivity type impurity on the second surface of the semiconductor substrate;
A transparent electrode deposition step of depositing a first transparent electrode layer on the first conductivity type region and depositing a second transparent electrode layer on the second conductivity type region after the p-type film deposition step is performed; And
Includes; the first and second transparent electrode layer on each of the first and second contact electrode paste and firing the electrode firing step; includes,
The heat treatment temperature of the electrode firing step is a method of manufacturing a solar cell higher than the first deposition temperature in the n-type film deposition step and the second deposition temperature in the p-type film deposition step. The method of claim 15,
A method of manufacturing a solar cell, wherein a first deposition temperature in the n-type film deposition step is higher than a second deposition temperature in the p-type film deposition step.

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