KR20170073480A - Solar cell and method for manufacturing the same - Google Patents

Abstract

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A first passivation film located on the front surface of the semiconductor substrate; A second passivation film located on a rear surface of the semiconductor substrate; A front field region located on the first passivation film on the front side of the semiconductor substrate and having the same conductivity type as the semiconductor substrate; An emitter region located on the second passivation film on the rear side of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate; A first electrode electrically connected to the front electric field area; And a second electrode electrically connected to the emitter region.

Description

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a manufacturing method thereof, and more particularly, to a solar cell having improved structure and a manufacturing method thereof.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. However, solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize solar cells, it is required to overcome low efficiency, and various layers and electrodes are required to be designed so as to maximize the efficiency of the solar cell.

The present invention provides a solar cell having high efficiency and a manufacturing method thereof.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A first passivation film located on the front surface of the semiconductor substrate; A second passivation film located on a rear surface of the semiconductor substrate; A front field region located on the first passivation film on the front side of the semiconductor substrate and having the same conductivity type as the semiconductor substrate; An emitter region located on the second passivation film on the rear side of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate; A first electrode electrically connected to the front electric field area; And a second electrode electrically connected to the emitter region.

A method of manufacturing a solar cell according to an embodiment of the present invention includes: forming a first passivation film and a second passivation film on the front and rear surfaces of a semiconductor substrate; A first passivation film located on the first passivation film on the front side of the semiconductor substrate and having a front electric field area having the same conductivity type as the semiconductor substrate and a conductive type opposite to the semiconductor substrate located on the second passivation film on the rear side of the semiconductor substrate, A conductive type region forming step of forming a plurality of emitter regions; Forming a first transparent electrode layer on the front electric field area and a second transparent electrode layer on the emitter area; And a metal electrode layer forming step of forming a first metal electrode layer located on the first transparent electrode layer and a second transparent electrode layer located on the emitter region.

According to this embodiment, the thickness of the front electric field area is relatively reduced, the light loss is minimized, and the thickness of the emitter area is relatively increased, so that the photoelectric conversion can be smoothly performed and the passivation property can be improved. And, the semiconductor substrate does not have a doped region but consists only of a base region and can have excellent passivation characteristics. The first passivation film and the first transparent electrode layer positioned on the front side of the semiconductor substrate and the second passivation film and the second transparent electrode layer located on the rear side of the semiconductor substrate have a thickness relationship, The material of the first and second passivation films and the first and second transparent electrode layers may be defined together to maximize the passivation characteristic and maximize the current density. Thus, the efficiency of the solar cell can be maximized.

1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention.
2 is a plan view of the first and second metal electrode layers of the solar cell shown in FIG.
3A to 3E are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
4 is a cross-sectional view of a solar cell according to another embodiment of the present invention.
5 is a cross-sectional view of a solar cell according to another embodiment of the present invention.
6 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a solar cell according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention.

1, a solar cell 100 according to the present embodiment includes a semiconductor substrate 110 including a base region 10, a first passivation film 52 formed on a front surface of the semiconductor substrate 110, A second passivation film 54 formed on the rear surface of the semiconductor substrate 110, a front electric field area 20 formed on the first passivation film 52 on the front side of the semiconductor substrate 110, The emitter region 30 formed on the second passivation film 54 at the rear side of the emitter region 110 and the first electrode 42 electrically connected to the front field region 20, And a second electrode 44 connected to the second electrode 44. This will be explained in more detail.

The semiconductor substrate 110 may be formed of a crystalline semiconductor. In one example, the semiconductor substrate 110 may be composed of a single crystal or polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon). In particular, the semiconductor substrate 110 may be composed of a single crystal semiconductor (for example, a single crystal semiconductor wafer, more specifically, a single crystal silicon wafer). Thus, when the semiconductor substrate 110 is made of a single crystal semiconductor (for example, a single crystal silicon), the solar cell 100 constitutes a single crystal semiconductor solar cell (for example, a single crystal silicon solar cell). As described above, the solar cell 100 based on the semiconductor substrate 110 made of a crystalline semiconductor having high crystallinity and having few defects can have excellent electrical characteristics.

In this embodiment, the semiconductor substrate 110 may be composed of only the base region 10 without forming a separate doping region in the semiconductor substrate 110. If a separate doping region is not formed in the semiconductor substrate 110 as described above, damage to the semiconductor substrate 110, increase in defects, and the like, which may occur when the doping region is formed, are prevented so that the semiconductor substrate 110 has excellent passivation characteristics Lt; / RTI > Thus, surface recombination occurring on the surface of the semiconductor substrate 110 can be minimized.

In this embodiment, the semiconductor substrate 110 or the base region 10 may have a first conductivity type doped with a low doping concentration of the first conductivity type dopant, which is a base dopant. At this time, the semiconductor substrate 110 or the base region 10 may have a lower doping concentration, higher resistance, or lower carrier concentration than the front electric field region 20 having the same conductivity type.

The front surface and / or the rear surface of the semiconductor substrate 110 may have irregularities 112 and 114 to prevent reflection. More specifically, in this embodiment, the concavities and convexities 112 and 114 are formed on the rear surface (rear surface side) of the semiconductor substrate 110 and the first concavities and convexities 112 formed on the front surface (or front surface side surface) And the second concave and convex portions 114 may be formed on the second concave and convex portions. Thus, reflection of light incident on the front surface and the rear surface of the semiconductor substrate 110 can be prevented, and the optical loss in the solar cell 100 having the bi-facial structure similar to that of the present embodiment can be effectively . However, the present invention is not limited to this, and it is also possible that only one of the first irregularities 112 and the second irregularities 114 is formed.

The first irregularities 112 located on the front surface of the semiconductor substrate 110 may include first irregularities 112a and second irregularities 112b to minimize optical loss. The second concavo-convex portion 112b is formed on the first concavo-convex portion 112a, more specifically, on the outer surface constituting the first concavo-convex portion 112a and may have a smaller size than the first concavo-convex portion 112a have. The average size of the second concave-convex portion 112b may be smaller than the average size of the first concave-convex portion 112a and the second concave-convex portion 112b may be smaller than the average size of the first concave- At least one, e.g., a plurality of, locations. The first irregular portion 112a and the second irregular portion 112b may be formed by different methods.

The first irregular portion 112a may be formed by a texturing process. Accordingly, the outer surface of the first concavo-convex portion 112a may be composed of specific crystal faces. For example, the first irregular portion 112a may have a rough pyramid shape formed by four outer surfaces that are (111) surfaces.

(For example, an average value of the height of the first irregular portion 112a) of the first irregular portion 112a may be a micrometer level (for example, 1um to 1mm), for example, Lt; / RTI > It may be difficult to manufacture the first concave portion 112a having an average size of less than 10 um and the average size of the first concave portion 112a may be formed to be less than 30 um to improve the antireflection effect. The deviation of the size of the first concavo-convex portion 112a may have a relatively large first variation. The first concavo-convex portion 112a may be formed by anisotropic etching by wet etching. When the first irregular portion 112a is formed by wet etching, the first irregular portion 112a can be formed within a short time by a simple process.

The second concavo-convex portion 112b may be formed on the outer surface (for example, the (111) surface) of the first concavo-convex portion 112a while having a minute size. The second concave-convex portion 112b may have a pointed end, but the present invention is not limited thereto and the second concave-convex portion 112b may have rounded ends.

The average size (for example, the average value of the height of the second concave-convex portion 112b) of the second concave-convex portion 112b may be on the order of nanometers (i.e., 1um or less, for example, 1nm to 1um) For example, it may have a size of about 100 nm to 500 nm. If the second concave-convex portion 112b having a smaller size than the first concave-convex portion 112a is formed in this way, the anti-reflection effect can be improved. The second concavo-convex portion 112b having an average size of less than 100 nm may be difficult to manufacture, and if the average size of the second concavo-convex portion 112b is set to 500 nm or less, the antireflection effect can be further improved. The size variation of the second concave and convex portion 112b may have a second variation smaller than the first variation. This is because the average size of the second concave-convex portion 112b is smaller, and the process of the second concave-convex portion 112b is based on isotropic etching. Thus, in this embodiment, the uniform and fine second concave-convex portion 112b is formed on the outer surface of the first concave-convex portion 112a.

The second concavo-convex portion 112b may be formed by isotropic etching by dry etching. As the dry etching, for example, reactive ion etching (RIE) may be used. The second irregular portion 112b can be formed finely and uniformly by reactive ion etching. The shape, average size, size deviation, etc. of the second concavo-convex portion 112b may be variously modified. The present invention is not limited to the shape, the average size, and the size variation of the second concavo-convex portion 112b.

In this embodiment, the second concave and convex portions 114 formed on the rear surface of the semiconductor substrate 110 may include the first concave and convex portions 114a. The description of the first concavity and convexity 112a of the first concavity and convexity 112 may be applied to the first concavity and convexity 114a of the second concavity and convexity 114, and thus a detailed description thereof will be omitted. When the second concave and convex portions 114 of the semiconductor substrate 110 have different shapes from the first concave and convex portions 112 having the first and second concave and convex portions 112a and 112b with only the first concave and convex portions 114a, Reflection of the light from the front surface of the semiconductor substrate 110 having a large amount of light can be effectively prevented by the first irregularities 112 and the second irregularities 114 can have a simple structure, The process can be simplified.

However, the present invention is not limited thereto. The first irregularities 112 formed on the front surface of the semiconductor substrate 110 may not have the first irregularities 112a and / or the second irregularities 114 may not be formed. Various other variations are possible.

A first passivation film 52 is formed on the front surface of the semiconductor substrate 110 and a second passivation film 54 is formed on the rear surface of the semiconductor substrate 110. Thus, the front surface and the rear surface of the semiconductor substrate 110 can be passivated.

Although the terms first passivation film 52 and second passivation film 54 are used in this specification, the first passivation film 52 and / or the second passivation film 54 can also serve as a tunneling film. have. That is, the first and second passivation films 52 and 54 function as a kind of barrier for electrons and holes to prevent the minority carriers from passing therethrough, and the first and second passivation films 52 and 54, Only the majority carriers having a certain energy or more are allowed to pass through the first and second passivation films 52 and 54, respectively. At this time, the majority carriers having a certain energy or more can easily pass through the first and second passivation films 52 and 54 by the tunneling effect. Here, the thickness of the passivation films 52 and 54 may be smaller than the front electric field area 20 and the emitter area 30 in order to sufficiently realize the tunneling effect.

In one example, the first and second passivation films 52 and 54 may comprise an intrinsic amorphous semiconductor. For example, the first and second passivation films 52 and 54 may be made of an intrinsic amorphous silicon (i-a-Si) layer. Since the first and second passivation films 52 and 54 have similar characteristics including the same semiconductor material as the semiconductor substrate 110, the surface characteristics of the semiconductor substrate 110 can be improved more effectively. As a result, the passivation characteristic can be greatly improved. However, the present invention is not limited thereto. Accordingly, the first and / or second passivation films 52 and 54 may be formed of the intrinsic amorphous silicon carbide (ia-SiCx) layer or the first and second passivation films 52 and 54, . According to this, although the effect due to the wide energy band gap can be improved, the passivation characteristic may be somewhat lower than in the case of including an intrinsic amorphous silicon (i-a-Si) layer.

At this time, the first and second passivation films 52 and 54 may be formed on the front surface and the rear surface of the semiconductor substrate 110, respectively. Accordingly, the front surface and the rear surface of the semiconductor substrate 110 can be entirely passivated, and can be easily formed without additional patterning.

On the first passivation film 52, a front electric field area 20 having a first conductivity type may be formed. On the second passivation film 54, an emitter region 30 having a second conductivity type opposite to the first conductivity type may be disposed.

The front electric field area 20 may be a region including the first conductive type dopant and having a first conductive type. The emitter region 30 may include a second conductivity type dopant and may have a second conductivity type. For example, the front field region 20 may contact the first passivation film 52 and the emitter region 30 may contact the second passivation film 54. Then, the structure of the solar cell 100 can be simplified and the tunneling effect of the first and second passivation films 52 and 54 can be maximized. However, the present invention is not limited thereto.

Since the front electric field area 20 and the emitter area 30 are formed separately from the semiconductor substrate 110 on the semiconductor substrate 110 so that the front electric field area 20 and the emitter area 30 can be easily formed on the semiconductor substrate 110, The gate electrode 30 may have a different material and / or crystal structure than the semiconductor substrate 110.

For example, each of the front electric field region 20 and the emitter region 30 may be formed by doping a first or second conductive type dopant into an amorphous semiconductor, which can be easily manufactured by various methods such as vapor deposition. Then, the front electric field area 20 and the emitter area 30 can be easily formed by a simple process. At this time, if the first and second passivation films 52 and 54 are made of an intrinsic amorphous semiconductor (for example, intrinsic amorphous silicon) as described above, excellent adhesion properties and excellent electrical conductivity can be obtained.

In this embodiment, the energy band gap of the front electric field area 20 may be larger than the energy band gap of the semiconductor substrate 110. Similarly, the energy band gap of the emitter region 30 may be greater than the energy band gap of the semiconductor substrate 110. According to this, energy band bending is sufficiently performed, so that selective collection of holes or electrons can be effectively performed.

Examples of the p-type dopant used as the first or second conductivity type dopant include a Group 3 element such as boron (B), aluminum (Al), gallium (Ga), and indium (In) Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb). However, the present invention is not limited thereto, and various dopants may be used as the first or second conductivity type dopant.

For example, the semiconductor substrate 110 having the first conductivity type and the front electric field region 20 may have an n-type, and the emitter region 30 may have a p-type. In this case, the semiconductor substrate 110 has an n-type structure, so that the lifetime of the carrier can be excellent. In this case, the semiconductor substrate 110 and the front electric field region 20 may include phosphorus (P) as an n-type dopant and the emitter region 30 may include boron (B) as a p-type dopant . However, the present invention is not limited thereto, and the semiconductor substrate 110 having the first conductivity type and the front electric field region 20 may have a p-type, and the emitter region 30 may have an n-type.

In this embodiment, the front electric field area 20 and the emitter area 30 are formed of an amorphous silicon (a-Si) layer, an amorphous silicon oxide (a-SiOx) layer, an amorphous silicon carbide (a- (IGZO) layer, a titanium oxide (TiOx) layer, and a molybdenum oxide (MoOx) layer. At this time, the amorphous silicon (a-Si) layer, the amorphous silicon oxide (a-SiOx) layer, and the amorphous silicon carbide (a-SiCx) layer, which are applied to the front electric field area 20 or the emitter area 30, And may be doped with a second conductivity type dopant. The indium-gallium-zinc oxide layer, the titanium oxide layer, and the molybdenum oxide layer, which are applied to the front electric field area 20 or the emitter area 30, are used as first and second conductive type dopants in addition to the materials contained in the oxide layer (For example, boron, phosphorus), and the like. The indium-gallium-zinc oxide layer, the titanium oxide layer, and the molybdenum oxide layer may collect electrons or holes by themselves to perform the same function as the n-type or p-type conductivity type regions. More specifically, the indium-gallium-zinc oxide layer may have an n-type conductivity, the titanium oxide layer may have an n-type, and the molybdenum oxide layer may have a p-type conductivity.

Although the amorphous silicon (a-Si) layer, the amorphous silicon oxide (a-SiOx) layer and the amorphous silicon carbide (a-SiCx) layer have a crystal structure different from that of the semiconductor substrate 110, (E. G., Silicon). ≪ / RTI > Accordingly, a difference in characteristics that may occur when a semiconductor material other than the semiconductor material of the semiconductor substrate 110 is included can be minimized. Among these, the amorphous silicon oxide layer and the amorphous silicon carbide layer have a high energy band gap, so that the energy band bending can sufficiently occur and the carrier can be selectively passed. In addition, the indium-gallium-zinc oxide (IGZO) layer, the titanium oxide (TiOx) layer and the molybdenum oxide (MoOx) layer have a wide energy bandgap and the light absorption rate is low, .

In one example, the front electric field region 20 may include at least one of an indium-gallium-zinc oxide layer, a titanium oxide layer, and a molybdenum oxide layer having a low light absorptivity. Accordingly, absorption of light in the front electric field area 20 located on the front surface of the semiconductor substrate 110 can be minimized. In this embodiment, the front electric field area 20 is formed on the first irregularities 112 including the first irregularities 112a and the second irregularities 112b. The indium-gallium-zinc oxide layer, the titanium oxide Layer, a molybdenum oxide layer, and the like may have excellent properties regardless of surface defects of the semiconductor substrate 110. [ On the other hand, if the front electric field area 20 includes an amorphous silicon layer, an amorphous silicon oxide layer, or an amorphous silicon carbide layer, if the formation conditions are not excellent due to surface defects of the semiconductor substrate 110, May be degraded.

And the emitter region 30 may comprise at least one of an amorphous silicon layer, an amorphous silicon oxide layer, and an amorphous silicon carbide layer. The emitter region 30 is a layer directly involved in photoelectric conversion by forming a pn junction with the semiconductor substrate 110 (or a pin junction between the second passivation film 54) It is possible to have similar characteristics including a semiconductor material (i.e., silicon) so that the carrier can be moved more effectively.

In this embodiment, the thickness of the emitter region 30 may be larger than the total electric field region 20. [ That is, since the emitter region 30 directly involved in the photoelectric conversion is located on the rear surface of the semiconductor substrate 110 and does not interfere with light absorption to the front surface, the emitter region 30 can be formed relatively thick. Since the front electric field area 20 is not directly involved in photoelectric conversion but is located on the front surface of the semiconductor substrate 110 and is related to light absorption to the front surface, the front electric field area 20 may be relatively thin. In addition, when the emitter region 30 has a p-type, the emitter region 30 can be doped with boron (B). Since the boron can be easily diffused due to its small size, the thickness of the emitter region 30 So that it is possible to prevent the dopant from being heavily doped into the semiconductor substrate 110. Here, if the dopant included in the emitter region 30 is heavily doped into the semiconductor substrate 110, deterioration of the solar cell 100 may occur. However, the present invention is not limited thereto, and even when the emitter region 30 has the n-type, the thickness of the emitter region 30 may be larger than the total electric field region 20. [

For example, the ratio of the thickness of the front electric field area 20 to the thickness of the emitter area 30 may be 1: 1.5 to 1: 5.5. If the ratio is less than 1: 1.5, the emitter region 30 does not have a sufficient thickness, so that the photoelectric conversion by the emitter region 30 may not be smooth. If the ratio is more than 1: 5.5, the thickness of the front electric field area 20 is too thin to sufficiently play a role, or the thickness of the emitter area 30 is increased to make the manufacturing time longer, Collection efficiency may be low.

The thickness of the second passivation film 54 may be equal to or greater than the thickness of the first passivation film 52. For example, the thickness of the second passivation film 54 may be greater than the thickness of the first passivation film 52. This can prevent the dopant of the emitter region 30 from being undesirably doped into the semiconductor substrate 110 in consideration of the fact that the emitter region 30 is formed thicker than the front electric field region 20. [ In particular, when the emitter region 30 has a p-type, the boron contained in the emitter region 30 can be prevented from being highly doped into the semiconductor substrate 110. For example, the thickness ratio of the first passivation film 52: second passivation film 54 may be 1: 1 to 1: 2.5. These ratios take into account the passivation characteristics of the semiconductor substrate 110, the characteristics of the dopant in the emitter region 30, and the like, but the present invention is not limited thereto.

The ratio of the thickness of the emitter region 30 to the thickness of the second passivation film 54 may be larger than the ratio of the thickness of the front field region 20 to the thickness of the first passivation film 52. [ This is because the thickness of the emitter region 30 is larger than the thickness of the front electric field region 20. The ratio of the thickness of the first passivation film 52 to the thickness of the front field region 20 is 1: 1 to 1: 2 and the thickness of the second passivation film 54 is the thickness of the emitter region 30 Thickness ratio may be from 1: 2 to 1: 5. The ratio of the thickness of the first passivation film 52 to the thickness of the front field region 20 is less than 1: 1 or the ratio of the thickness of the second passivation film 54 to the thickness of the emitter region 30 is 1: 2 , It may be difficult to sufficiently perform the role of the front electric field area 20 or the emitter area 30. The ratio of the thickness of the first passivation film 52 to the thickness of the front field region 20 exceeds 1: 2 or the ratio of the thickness of the second passivation film 54 to the thickness of the emitter region 30 becomes 1: If the thickness of the first or second passivation film 52 or 54 is insufficient, the passivation property may be lowered or the thickness of the front electric field area 20 or the emitter area 30 may be relatively large, The efficiency may be lowered. However, the present invention is not limited thereto.

Alternatively, for example, the thickness of the front electric field area 20 is 1 nm to 10 nm (for example, 3 nm to 5.7 nm) and the thickness of the emitter area 30 is 3 nm to 15 nm (for example, 8 nm to 17.6 nm) . The thickness of the first passivation film 52 may be 1 nm to 5 nm, and the thickness of the second passivation film 54 may be 1 nm to 7 nm. This range is limited so that the front electric field area 20, the emitter area 30, and the first and second passivation films 52 and 54 can sufficiently exhibit the above-described effects. However, the present invention is not limited thereto.

A first electrode 42 electrically connected to the front electric field area 20 is positioned (for example, in contact) on the front electric field area 20 and a second electrode 44 electrically connected to the emitter area 30 is positioned For example, contact).

The first electrode 42 may include a first transparent electrode layer 421 and a first metal electrode layer 422 that are sequentially stacked on the front electric field area 20. [

Here, the first transparent electrode layer 421 may be entirely formed (e.g., in contact with) the front electric field area 20. The formation as a whole may include not only covering the entire front electric field area 20 without voids or voids, but also inevitably a case where some parts are not formed. When the first transparent electrode layer 421 is formed entirely on the front electric field area 20, the carrier can easily reach the first metal electrode layer 422 through the first transparent electrode layer 421, The resistance can be reduced. The mobility of the carrier may be low because the crystallinity of the entire electric field area 20 composed of the amorphous semiconductor layer or the like is relatively low and the mobility of the carrier may be low. Therefore, when the carrier is provided with the first transparent electrode layer 421, Thereby lowering the resistance.

Since the first transparent electrode layer 421 is formed entirely over the front electric field area 20, it can be made of a material (transmissive material) capable of transmitting light. That is, the first transparent electrode layer 421 is made of a transparent conductive material so that the carrier can be easily moved while allowing transmission of light. Accordingly, even if the first transparent electrode layer 421 is entirely formed on the front electric field area 20, the transmission of light is not blocked.

For example, the first transparent electrode layer 421 may include indium tin oxide (ITO), aluminum zinc oxide (AZO), boron zinc oxide (BZO), indium tungsten And may include at least one of indium tungsten oxide (IWO) and indium cesium oxide (ICO). Furthermore, the first transparent electrode layer 421 may be indium oxide doped with titanium (Ti) and tantalum (Ta), that is, indium-titanium-tantalum oxide. However, the present invention is not limited thereto and may include the first transparent electrode layer 421 and various other materials.

At this time, the first transparent electrode layer 421 of the present embodiment may contain hydrogen while using the above-described material as a main material. That is, the first transparent electrode layer 421 may be formed of indium-tin oxide (ITO: H) containing hydrogen, aluminum-zinc oxide (AZO: H) containing hydrogen, boron- H), indium-tungsten oxide (IWO: H) containing hydrogen, and indium-cesium oxide (ICO: H) containing hydrogen.

The first transparent electrode layer 421 may be formed by vapor deposition. When hydrogen gas is injected at the time of deposition, hydrogen may be included in the first transparent electrode layer 421. When the first transparent electrode layer 421 includes hydrogen, the mobility of electrons or holes can be improved and the transmittance can be improved.

For example, in this embodiment, the first transparent electrode layer 421 can further improve its optical characteristics by using ICO: H. This will be explained in more detail. Table 1 below shows the resistivity, carrier density and mobility of ITO, IWO, ICO, ICO: H.

ITO IWO ICO ICO: H Resistivity [ohm * cm] 1.98E-04 3.85E-04 3.57E-04 2.23E-04 Carrier density [/ cm ³ ] 9.00E + 20 2.50E + 20 2.50E + 20 2.00E + 20 Mobility [cm ² / V * s] 35 65 70 130 ~ 145

Referring to Table 1, although the specific resistance of ITO is a somewhat lower value, the electrical characteristics constituting the ITO have a high carrier density and a very low mobility. IWO and ICO have lower carrier density and higher mobility than ITO and have higher resistivity than ITO. On the other hand, ICO: H has a similar resistivity level to that of ITO, but has a carrier density lower than that of ITO, IWO and ICO which do not contain hydrogen. ICO: H having such low carrier density and high mobility can improve the transmittance by lowering the light absorption by free carriers while having a low resistivity. Accordingly, ICO: H has excellent electrical characteristics due to low resistivity, and can improve the transmittance and have excellent optical characteristics. Such superior optical characteristics can exhibit excellent effects in a solar cell that performs photoelectric conversion by using light rather than other electric devices (e.g., display devices, semiconductors, etc.) that do not directly use light.

In this embodiment, a first metal electrode layer 422 having a pattern may be formed on the first transparent electrode layer 421. For example, the first metal electrode layer 422 may be formed in contact with the first transparent electrode layer 421 to simplify the structure of the first electrode 42. However, the present invention is not limited to this, and various modifications such as the existence of a separate layer between the first transparent electrode layer 421 and the first metal electrode layer 422 are possible.

The first metal electrode layer 422 located on the first transparent electrode layer 421 may be formed of a material having a higher electric conductivity than the first transparent electrode layer 421. Thus, characteristics such as carrier collection efficiency and resistance reduction by the first metal electrode layer 422 can be further improved. For example, the first metal electrode layer 422 may be composed of an opaque metal having a good electrical conductivity or a metal having a lower transparency than the first transparent electrode layer 421.

As described above, the first metal electrode layer 422 may be opaque or have a low transparency and may interfere with the incidence of light, so that it may have a certain pattern so as to minimize shading loss. Thus, light can be incident on a portion where the first metal electrode layer 422 is not formed. The planar shape of the first metal electrode layer 422 will be described later in more detail with reference to FIG.

The second electrode 44 may include a second transparent electrode layer 441 and a second metal electrode layer 442 that are sequentially stacked on the emitter region 30. [ Material, shape, etc. of the second transparent electrode layer 441 and the second metal electrode layer 442 of the second electrode 44, except that the second electrode 44 is located on the emitter region 30, Material, shape and the like of the first transparent electrode layer 421 and the first metal electrode layer 422 of the first electrode 42 are the same as those of the first transparent electrode layer 421 and the first metal electrode layer 422.

The thickness of the first transparent electrode layer 421 may be greater than the thickness of the second transparent electrode layer 441 in this embodiment. That is, the second transparent electrode layer 441, which has a relatively large thickness and does not require a large role as an antireflection film so that the first transparent electrode layer 421 can serve as an antireflection film capable of preventing reflection of light, And can have a small thickness.

For example, the ratio of the thickness of the second transparent electrode layer 441: the first transparent electrode layer 421 may be 1: 1.1 to 1: 4 (for example, 1: 1.2 to 1: 2.25). If the thickness ratio is less than 1: 1.1, the second transparent electrode layer 441 may not have a sufficient role as an antireflection film. If the thickness ratio is more than 1: 4, the thickness of the second transparent electrode layer 441 is not sufficient, so that the electrical characteristics are lowered or the thickness of the first transparent electrode layer 421 is increased, have. If the ratio is 1: 1.2 to 1: 1.25, the effects of the first and second transparent electrode layers 421 and 441 can be sufficiently exerted. However, the present invention is not limited thereto.

Alternatively, for example, the thickness of the first transparent electrode layer 421 may be 70 nm to 90 nm, and the thickness of the second transparent electrode layer 441 may be 50 nm to 80 nm. This range is limited so that the first and second transparent electrode layers 421 and 441 can sufficiently realize desired characteristics. However, the present invention is not limited thereto.

In this embodiment, the first metal electrode layers 422 and 442 of the first and second electrodes 42 and 44 are formed of a material that can be fired by low-temperature firing (for example, firing at a process temperature of 300 ° C or less) ≪ / RTI > For example, the first metal electrode layers 422 and 442 may include glass frit composed of a certain metal compound (for example, an oxide containing oxygen, a carbide containing carbon, a sulfide containing sulfur) But may include only conductive materials and resins (binders, curing agents, additives). So that the glass frit can be easily fired even at a low temperature. The conductive material may include silver (Ag), aluminum (Al), copper (Cu), etc. The resin may include a binder such as a cellulosic or phenolic resin, and a hardener such as an amine.

Since the first and second metal electrode layers 422 and 442 are formed in contact with the first and second transparent electrode layers 421 and 441 in this embodiment, Is not required. Since the first metal electrode layers 422 and 442 do not have the glass frit but are made of the conductive material and the resin, the conductive material is sintered and connected to each other by using the low temperature firing paste from which the glass frit is removed. They can be brought into contact with each other and aggregated to have conductivity.

Alternatively, the first and second metal electrode layers 422 and 442 may be formed by plating.

The planar shapes of the first and second metal electrode layers 422 and 442 of the first and second electrodes 42 and 44 will be described in more detail with reference to FIG.

FIG. 2 is a plan view of the first and second metal electrode layers 422 and 442 of the solar cell 100 shown in FIG. In FIG. 2, the semiconductor substrate 110 and the first and second metal electrode layers 422 and 442 of the first and second electrodes 42 and 44 are mainly shown.

Referring to FIG. 2, the first and second metal electrode layers 422 and 442 may include a plurality of finger electrodes 42a and 44a spaced from each other with a predetermined pitch. Although the finger electrodes 42a and 44a are parallel to each other and parallel to the edge of the semiconductor substrate 110, the present invention is not limited thereto. The first and second metal electrode layers 422 and 442 include bus bar electrodes 42b and 44b formed in a direction crossing the finger electrodes 42a and 44a and connecting the finger electrodes 42a and 44a can do. Only one bus electrode 42b or 44b may be provided or a plurality of bus electrodes 42b and 44b may be provided with a larger pitch than the pitch of the finger electrodes 42a and 44a as shown in FIG. At this time, the width of the bus bar electrodes 42b and 44b may be larger than the width of the finger electrodes 42a and 44a, but the present invention is not limited thereto. Therefore, the width of the bus bar electrodes 42b and 44b may be equal to or smaller than the width of the finger electrodes 42a and 44a.

In the drawing, the first and second metal electrode layers 422 and 442 have the same planar shape. The width and the pitch of the finger electrode 42a and the bus bar electrode 42b of the first metal electrode layer 422 are not limited to the width of the finger electrode 44a of the second metal electrode layer 442, The width, the pitch, and the like of the bar electrode 44b. Also, the first and second metal electrode layers 422 and 442 may have different planar shapes, and various other modifications are possible.

As described above, in this embodiment, the first and second metal electrode layers 422 and 442, which are opaque or contained in the first and second electrodes 42 and 44 of the solar cell 100, have a certain pattern, And has a bi-facial structure in which light can be incident on the front surface and the rear surface of the substrate 110. Accordingly, the amount of light used in the solar cell 100 can be increased to contribute to the efficiency improvement of the solar cell 100. However, the present invention is not limited thereto, and it is also possible that the second metal electrode layer 442 of the second electrode 44 is formed entirely on the rear side of the semiconductor substrate 110. This will be described in detail later with reference to FIG. 5 and FIG.

The front field region 20 is located on the front side of the semiconductor substrate 110 with the first passivation layer 52 therebetween and the emitter region 30 is located between the second passivation layer 54, And is located on the rear side of the semiconductor substrate 110. [ As a result, the thickness of the front electric field area 20 can be made relatively small to minimize the light loss, and the thickness of the emitter area 30 can be relatively increased, so that the photoelectric conversion can be smoothly performed and the passivation property can be improved . In addition, the semiconductor substrate 110 does not have a doped region but has only a base region 10 so that it can have excellent passivation characteristics. The first passivation film 52 and the first transparent electrode layer 421 located on the front side of the semiconductor substrate 110 and the second passivation film 54 and the second passivation film 54 located on the rear side of the semiconductor substrate 110 are formed, The ratio of the thickness of the transparent electrode layer 441 and the ratio of the thickness of the transparent electrode layer 441 and the thicknesses of the front electric field area 20, the emitter area 30, the first and second passivation films 52 and 54, and the first and second transparent electrode layers 421, 441), etc. can be defined together to maximize the passivation characteristic and maximize the current density. Thus, the efficiency of the solar cell 100 can be maximized.

The solar cell 100 described above can be formed by various processes. 3A to 3E, a method of manufacturing a solar cell 100 according to an embodiment of the present invention will be described in detail. 3A to 3E are cross-sectional views illustrating a method of manufacturing a solar cell 100 according to an embodiment of the present invention.

First, as shown in FIG. 3A, first and second irregularities 112 and 114 are formed on a semiconductor substrate 110. More specifically, the first irregularities 112a and 114a of the first and second irregularities 112 and 114 are formed by wet etching as described above, and then the first irregularities 112a and 114a are formed by reactive ion etching The second concavo-convex portion 112b can be formed. However, the present invention is not limited thereto, and the first and second irregularities 112 and 114 may be formed by various methods.

Subsequently, as shown in FIG. 3B, first and second passivation films 52 and 54 may be formed on the semiconductor substrate 110. The first and second passivation films 52 and 54 may be formed by thermal growth, vapor deposition (for example, chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like). However, the present invention is not limited thereto, and the first and second passivation films 52 and 54 may be formed by various methods. The first and second passivation films 52 and 54 may be formed at the same time or sequentially

Next, as shown in FIG. 3C, a front electric field area 20 and an emitter area 30 are formed on the first and second passivation films 52 and 54, respectively. More specifically, the front field region 20 is formed on the first passivation film 52 and the emitter region 30 is formed on the second passivation film 52.

The front electric field area 20 and the emitter area 30 can be formed by a deposition method (for example, chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or the like). The first or second conductivity type dopant may be included together in the step of growing the semiconductor layer forming the front electric field area 20 and the emitter area 30 or may be formed after the semiconductor layer is formed by ion implantation, , Laser doping, or the like. However, the present invention is not limited thereto, and the front electric field area 20 and the emitter area 30 may be formed by various methods. The front electric field region 20 and the emitter region 30 may be doped after being formed simultaneously and may be sequentially deposited and / or doped.

For example, the front electric field region 20 and the emitter source material of the main material constituting these regions 30 (for example, silane (SiH4) gas), the gas containing the dopant material with a hydrogen gas (H ₂₎ And a carrier gas (for example, argon gas (Ar) or nitrogen gas (N ₂ )).

In the case where the front electric field area 20 includes an n-type semiconductor layer, a gas containing a dopant material may use a phosphine gas (PH3), and when the emitter region 30 is a p- (B2H6) can be used. The semiconductor layer having a higher doping concentration can be formed as the ratio of the gas containing the dopant to the silane gas is higher.

For example, in the front field region 20, the ratio of the gas containing the dopant material to the silane gas may be greater than 0 and less than 0.5%, wherein the ratio of silane gas to hydrogen gas may be from 1 to 20% have. In the front electric field region 20, the ratio of the gas containing the dopant to the silane gas may be more than 0.5 to 1.0%, and the ratio of the hydrogen gas to the silane gas may be 20 to 70%.

The ratio of the hydrogen gas to the silane gas may be in the range of 20 to 70 percent, and the amount of the hydrogen gas may increase as the dopant gas increases, at the gas ratio of more than 0.5 to 1.0%. In this case, the doped semiconductor layer may have a hydrogen concentration higher than that of the intrinsic semiconductor layer.

Within the above range, the front field region 20 can have a sufficient doping concentration and can maintain stability with a hydrogen gas and a proper deposition rate. In addition, in the emitter region 30, The proportion of gas containing material may be greater than 0 and less than 0.3%, wherein the ratio of silane gas to hydrogen gas may be between 1 and 120%. In the emitter region 30, the ratio of the gas containing the dopant to the silane gas may be more than 0.3 to 1.0%, and the ratio of the silane gas to the hydrogen gas may be 20 to 200%. Within the aforementioned range, the emitter region 30 can have a sufficient doping concentration and can maintain stability by hydrogen gas and appropriate deposition rate. However, the present invention is not limited to these numerical ranges. In the formation of the front electric field area 20 and the emitter area 30, the range of the ratio of the dopant gas to the silane gas is different from each other as described above. That is, the range of the ratio of the dopant gas to the silane gas used for forming the front electric field area 20 may be wider than the range of the ratio of the dopant gas to the silane gas used for forming the emitter area 30 .

On the other hand, in forming the front electric field region 20 and the emitter region 30, the deposition temperature may be 100 to 250 degrees, and in this case, the ratio of the hydrogen gas to the silane gas may be 2 to 30%. In the narrower range, the deposition temperature may be 140 to 200 degrees in the formation of the front field region 20 and the emitter region 30. In this case, the ratio of the hydrogen gas to the silane gas is preferably 5 to 20% Lt; / RTI > That is, in this embodiment, the deposition temperature and the ratio of the hydrogen gas to the silane gas are proportional to each other, and accordingly, the ratio of the hydrogen gas to the silane gas may be high as the deposition temperature is high. Within this range, stability with hydrogen gas can be improved and an appropriate deposition rate can be maintained.

Meanwhile, in this embodiment, the energy band gap of the front electric field area 20 may be larger than the energy band gap of the semiconductor substrate 110. Similarly, the energy band gap of the emitter region 30 may be greater than the energy band gap of the semiconductor substrate 110. Accordingly, the front electric field area 20 and the emitter area 30 can selectively collect carriers (electrons and holes). Here, the band gap between the front field region 20 and the emitter region 30 may also depend on the ratio of the hydrogen gas to the silane gas.

In the formation of the front electric field area 20 and the emitter area 30, a silane gas is provided, and when a gas containing a dopant is not provided (i.e., an intrinsic semiconductor) The band gap may be formed to be larger than the band gap of the emitter region 30. [ That is, the ratio of the hydrogen gas to the silane gas is controlled so that the energy band gap of the intrinsic semiconductor of the front electric field area 20 is formed to be larger than the energy band gap of the intrinsic semiconductor of the emitter area 30. In this case, the band gap ratio of the front electric field area 20 to the emitter area 30 may be 1 to 1.15.

On the other hand, in the case where the front electric field area 20 and the emitter area 30 have a band gap of 1.7 to 1.8, the ratio of the gas containing the dopant to the silane gas may form the front electric field area 20 Emitter region 30 may be formed. That is, the ratio of the gas containing the dopant to the silane gas when forming the front electric field area 20 may be 3 to 10 times larger than the ratio of the gas containing the dopant to the silane gas.

On the other hand, when the front electric field area 20 and the emitter area 30 each have a band gap of 1.6 to 1.7, the ratio of the gas containing the dopant to the silane gas may be in the range of forming the front electric field area 20 Emitter region 30 may be formed. That is, the ratio of the gas containing the dopant to the silane gas when forming the front electric field area 20 may be 1 to 8 times larger than the ratio of the gas containing the dopant to the silane gas.

 In this embodiment, the energy band gap of each of the front electric field area 20 and the emitter area 30 can be controlled effectively by controlling the ratio of the dopant gas to the silane gas. In the present embodiment, , The front electric field area 20 has an n-type conductivity type and the emitter area 30 has a p-type electric conductivity type. However, this is an example for illustrating the technical idea of the present invention, The technical idea of the present invention is not limited thereto. Therefore, it is needless to say that, contrary to the above, the front electric field area 20 may have a p-type conductivity and the emitter area 30 may have an n-type conductivity. Further, although the front electric field area 20 is disposed on the front surface of the solar cell and the emitter area 30 is disposed on the rear surface of the solar cell, this is also an example, and the front electric field area 20, The arrangement of the regions 30 may be interchanged. In this case, the front electric field area 20 may be referred to as a rear electric field area.

Subsequently, as shown in FIG. 3D, first and second transparent electrode layers 421 and 441 are formed on the front electric field area 20 and the emitter area 30, respectively. More specifically, the first transparent electrode layer 421 may be formed on the front electric field area 20 and the second transparent electrode layer 441 may be formed on the emitter area 30.

The first and second transparent electrode layers 421 and 441 can be formed by a deposition method (for example, chemical vapor deposition (PECVD)), a coating method, or the like. However, the present invention is not limited thereto, and the first and second transparent electrode layers 421 and 441 can be formed by various methods.

For example, the first and second transparent electrode layers 421 and 441 may be formed of a hydrogen gas (H ₂ ) and a carrier gas (for example, argon gas (Ar) or nitrogen gas (N ₂ ) May be injected. Then, hydrogen is contained in the first and second transparent electrode layers 421 and 441, thereby realizing the effect. In one example, the ratio of the hydrogen gas to the carrier gas (for example, the ratio of H ₂ / N ₂ or the ratio of H ₂ / Ar) may be 0.5 to 5% (for example, by volume). If the ratio is less than 0.5%, the effect due to hydrogen may not be sufficient. However, the present invention is not limited to these numerical ratios. If the ratio exceeds 5%, the stability may be lowered by the hydrogen gas and the deposition rate may be lowered. More specifically, the ratio of hydrogen gas to carrier gas (i.e., the ratio of H ₂ / N ₂ ) may be between 0.5% and 2%. In this range, stability can be further improved and the deposition rate can be increased. However, the present invention is not limited to these numerical ranges.

In this embodiment, the hydrogen gas and the nitrogen gas may be combined with the oxygen gas. Oxygen is included as a raw material of the main material, but oxygen gas can be further injected to maintain the oxygen ratio in the first and second transparent electrode layers 421 and 441 at an appropriate ratio. As an example, the ratio of the oxygen gas to the carrier gas (for example, the ratio of O ₂ / N ₂ or the ratio of O ₂ / Ar) may be 15 to 40% (for example,% by volume). If the ratio is less than 15%, the effect of oxygen gas may be insufficient, and if it exceeds 40%, the electrical characteristics of the first and second transparent electrode layers 421 and 441 may be deteriorated. However, the present invention is not limited to these numerical ranges.

Next, as shown in FIG. 3E, first and second metal electrode layers 422 and 442 are formed on the first and second transparent electrode layers 421 and 441, respectively.

For example, a first low-temperature paste layer may be formed on one of the front electric field area 20 and the emitter area 30 (more specifically, on one of the first and second transparent electrode layers 421 and 441) And one of the first and second metal electrode layers 422 and 442 is formed by drying to form a second low-temperature paste layer on the other of the front electric field area 20 and the emitter area 30, And the second metal electrode layers 422 and 442 may be formed. It may be difficult to form the first or second low-temperature paste layer having fluidity together so as to have a desired pattern on both sides. In consideration of this, a first low-temperature paste layer having fluidity is formed and then dried to form a second low-temperature paste layer having fluidity on the other surface in a state where one of the first and second metal electrode layers 422 and 442 is formed . Thus, it is possible to prevent the problem that the first low-temperature paste layer flows down when the second low-temperature paste layer is formed. However, the present invention is not limited thereto, and it is also possible to form the first and second low-temperature paste layers simultaneously on both sides and dry them together.

The first or second low temperature paste layer may include a conductive material, a resin (binder, curing agent, additive, etc.) and a solvent. Conductive materials and constituent materials of the resin have already been described and are therefore omitted. As the solvent, various materials can be used. For example, an ether solvent can be used. At this time, the first or second low-temperature paste layer may include 85 to 90 parts by weight of the conductive material in 100 parts by weight, the resin may be included in 1 to 15 parts by weight, and the solvent may be included in 5 to 10 parts by weight. However, the present invention is not limited thereto.

The first or second low temperature paste layer may be formed by various methods. For example, the first or second low temperature paste layer may be formed by printing with a desired pattern. Then, the first or second low-temperature paste layer can be formed in a desired pattern by a simple process.

The drying of the first or second low temperature paste layer can be performed at a temperature of 300 DEG C or lower. This temperature is limited to a low temperature that can prevent the deterioration of the first and second passivation films 52 and 54 and the front electric field area 20 and the emitter area 30. [ However, the present invention is not limited thereto.

By this drying step, the solvent of the first or second low-temperature paste layer is blown away and the first or second metal electrode layer 422 or 442 does not contain a metal compound including oxygen, carbon, sulfur, And resin.

However, the present invention is not limited thereto, and at least one of the first and second metal electrode layers 422 and 442 may be formed by plating. For example, the first or second metal electrode layer 422, 442 may be an electroplating layer formed by electroplating copper to include copper.

A solar cell according to another embodiment of the present invention will be described in detail with reference to the accompanying drawings. Since the above description can be applied to the same or extremely similar parts as the above description, the detailed description will be omitted and only the different parts will be described in detail. It is also within the scope of the present invention to combine the above-described embodiments or variations thereof with the following embodiments or modifications thereof.

4 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

4, in this embodiment, a front electric field area 20 is formed by a first electric field portion (low-concentration portion) 20a formed adjacent to the semiconductor substrate 110 or the first passivation film 52, And a second electric field portion (high-concentration portion) 20b having a resistance lower than that of the first electric field portion 20a by including the conductive-type dopant at a higher doping concentration than the first electric field portion 20b. A first emitter portion (low concentration portion) 30a formed in the emitter region 30 adjacent to the semiconductor substrate 110 or the second passivation film 54 and a second emitter portion And a second emitter portion (high concentration portion) 30b having a resistance lower than the first emitter portion 30a including a higher doping concentration than the portion 30a.

The first electric field portion 20a or the first emitter portion 30a may form a constant electric field on the semiconductor substrate 110 to passivate the semiconductor substrate 110. [ The second electric field portion 20b or the second emitter portion 30b may improve the contact characteristics of the first or second transparent electrode layer 421 or 441 and improve the contact property of the first or second transparent electrode layer 421 or 441 It can serve to minimize the inconsistency of the work function.

At this time, the ratio of the thickness of the second electric field portion 20b to the thickness of the front electric field region 20 may be 35 to 55%, and the ratio of the thickness of the second emitter portion 30b to the thickness of the emitter region 30 may be, May be 30 to 50%. In one example, the thickness of the first electric field portion 20a may be 1 nm to 4 nm, and the thickness of the second electric field portion 20b may be 1 nm to 5 nm (for example, 2 nm to 5 nm). And the thickness of the first emitter portion 30a may be between 5 nm and 10 nm and the thickness of the second emitter portion 30b may be between 3 nm and 8 nm. Within this range, the above-described functions of the first electric field portion 20a and the second electric field portion 20b, and the first and second emitter portions 30a and 30b can be sufficiently performed.

At this time, for example, the thickness of the first electric field portion 20a may be greater than the thickness of the second electric field portion 20b. Similarly, the thickness of the first emitter portion 30a may be greater than the thickness of the second emitter portion 30b. If the thickness of the first electric field portion 20a or the first emitter portion 30a that performs the passivation is small, the passivation effect may be relatively lowered. On the other hand, the second electric field portion 20b or the second emitter portion 30b can sufficiently perform its role even if it has a relatively small thickness. The thickness of the first electric field portion 20a is made larger than the thickness of the second electric field portion 20b and the thickness of the first emitter portion 30a is made larger than the thickness of the second emitter portion 30b, And the contact characteristics between the first and second transparent electrode layers 421 and 441 can be improved. However, the present invention is not limited thereto. Therefore, the thickness of the first electric field portion 20a may be smaller than the thickness of the second electric field portion 20b, and various other modifications are possible.

And the ratio of the doping concentration of the second emitter portion 30b to the doping concentration of the first emitter portion 30a is greater than the doping concentration of the second electric field portion 20b with respect to the doping concentration of the first electric field portion 20a Or greater. Alternatively, the doping concentration of the second conductive dopant in the first emitter portion 30a may be equal to or less than the doping concentration of the first conductive dopant in the first electric field portion 20a. The ratio of the doping concentration of the second emitter portion 30b to the doping concentration of the first emitter portion 30a is less than the doping concentration of the second electric field portion 20b relative to the doping concentration of the first electric field portion 20a The doping concentration of the second conductive dopant in the first emitter portion 30a may be less than the doping concentration of the first conductive dopant in the first electric field portion 20a.

Boron may be used as the second conductive dopant when the first emitter portion 30a has a p-type. Boron diffuses to the interface between the semiconductor substrate 110 and the second passivation film 54, . As the amount of boron increases, the hydrogen of the semiconductor substrate 110 or the second passivation film 54 may be out-diffused at a high out-diffusion rate to lower the passivation characteristics. In consideration of this, the doping concentration of the first emitter portion 30a can be made smaller than the doping concentration of the first electric field portion 20a, whereby the above-described relationship can be satisfied.

For example, if the ratio of the doping concentration of the second field portion 20b to the doping concentration of the first field portion 20a is greater than 1 and less than or equal to 1.3 and the dopant concentration of the first emitter portion 30a 2 emitter portion 30b may be greater than 1 and less than 1.5. For example, the ratio of the doping concentration of the second field portion 20b to the doping concentration of the first field portion 20a may be 1.05 to 1.3, and the ratio of the doping concentration of the second field portion 20b to the doping concentration of the second field portion 20a may be 1.05 to 1.3, The ratio of the doping concentration of the emitter portion 30b may be 1.05 to 1.5. This range is limited to the range in which the effects of the first and second electric field portions 20a and 20b and the first and second emitter portions 30a and 30b can be maximized, but the present invention is not limited thereto.

5 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

Referring to FIG. 5, the second metal electrode layer 442 may be formed entirely on the second metal electrode layer 442 on the rear side of the semiconductor substrate 110 without a pattern. The second metal electrode layer 442 functions as a reflective film on the rear surface side of the semiconductor substrate 110 to reflect light reaching the first metal electrode layer 442 through the semiconductor substrate 110 and the emitter region 30 And can be reused. Thereby increasing the amount of light and improving the photoelectric conversion effect.

At this time, since the second metal electrode layer 442 is formed entirely on the rear side of the semiconductor substrate 110, the second metal electrode layer 442 may have a sufficient thickness and thus a thickness smaller than that of the first metal electrode layer 421 having a pattern.

6 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

Referring to FIG. 6, in the present embodiment, the rear surface of the semiconductor substrate 110 does not have the second irregularities (reference numeral 114 in FIG. 1), so that it can have a smaller surface roughness than the front surface of the semiconductor substrate 110. For example, the rear surface of the semiconductor substrate 110 may be mirror polished to have a surface roughness of 100 nm or less. And the second metal electrode layer 442 may be formed entirely on the second metal electrode layer 442 on the rear side of the semiconductor substrate 110 without a pattern. According to this, the reflection effect of the second metal electrode layer 442 on the rear surface side of the semiconductor substrate 110 can be further improved.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
110: semiconductor substrate
10: Base area
52: First passivation film
54: Second passivation film
20: front electric field area
30: Emitter area
42: first electrode
44: Second electrode

Claims (28)

A semiconductor substrate;
A first passivation film located on the front surface of the semiconductor substrate;
A second passivation film located on a rear surface of the semiconductor substrate;
A front field region located on the first passivation film on the front side of the semiconductor substrate and having the same conductivity type as the semiconductor substrate;
An emitter region located on the second passivation film on the rear side of the semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate;
A first electrode electrically connected to the front electric field area; And
And a second electrode electrically connected to the emitter region
≪ / RTI > The method according to claim 1,
And the thickness of the emitter region is larger than that of the front electric field region. 3. The method of claim 2,
Wherein the thickness of the front electric field region: the ratio of the thickness of the emitter region is 1: 1.5 to 1: 5.5. The method according to claim 1,
The energy band gap of the front electric field region is larger than the energy band gap of the semiconductor substrate,
Wherein the energy band gap of the emitter region is larger than the energy band gap of the semiconductor substrate. The method according to claim 1,
Wherein the front electric field region and the emitter region each include at least one of doped amorphous silicon, amorphous silicon oxide, amorphous silicon carbide, indium-gallium-zinc oxide, titanium oxide, and molybdenum oxide. 6. The method of claim 5,
Wherein the front electric field region includes at least one of indium-gallium-zinc oxide, titanium oxide, and molybdenum oxide,
Wherein the emitter region comprises at least one of amorphous silicon doped with amorphous silicon, amorphous silicon oxide and amorphous silicon carbide. The method according to claim 1,
Wherein at least one of the first and second passivation films comprises an intrinsic amorphous silicon layer. The method according to claim 1,
Wherein the thickness of the second passivation film is equal to or greater than the thickness of the first passivation film. 9. The method of claim 8,
Wherein the thickness ratio of the first passivation film: the second passivation film is 1: 1 to 1: 2.5. The method according to claim 1,
Wherein a ratio of a thickness of the first passivation film to a thickness of the emitter region is larger than a ratio of a thickness of the front passivation film to a thickness of the first passivation film. 11. The method of claim 10,
Wherein a ratio of a thickness of the first passivation film to a thickness of the front electric field area is 1: 1.1 to 1: 2,
Wherein a ratio of a thickness of the second passivation film to a thickness of the emitter region is 1: 2 to 1: 5. The method according to claim 1,
Wherein at least one of the emitter region and the front electric field region includes a first portion and a second portion having a higher doping concentration than the first portion,
Wherein a thickness of the first portion is greater than a thickness of the second portion. The method according to claim 1,
Wherein the front field region comprises a first field portion located above the first passivation film and a second field portion located above the first field portion and having a doping concentration higher than the first field portion,
Wherein said emitter region comprises a first emitter portion located above said second passivation film and a second emitter portion located above said first emitter portion and having a higher doping concentration than said first emitter portion, ,
Wherein a ratio of a doping concentration of the second emitter portion to a doping concentration of the first emitter portion is equal to or greater than a ratio of a doping concentration of the second electric field portion to a doping concentration of the first electric field portion, Wherein the doping concentration of the second conductivity type dopant in the first emitter portion is equal to or less than the doping concentration of the first conductivity type dopant in the first electric field portion. 14. The method of claim 13,
Wherein a ratio of a doping concentration of the second electric field portion to a doping concentration of the first electric field portion is greater than 1 and equal to or less than 1.3,
Wherein the ratio of the doping concentration of the second emitter portion to the doping concentration of the first emitter portion is greater than 1 and less than or equal to 1.5. The method according to claim 1,
Wherein at least one of the first electrode and the second electrode includes a transparent electrode layer and a metal electrode layer located on the transparent electrode layer,
The transparent electrode layer may be formed of indium tin oxide (ITO), aluminum zinc oxide (AZO), boron zinc oxide (BZO), indium tungsten oxide (IWO) ) And indium-cesium oxide (ICO), indium-titanium-tantalum oxide. 16. The method of claim 15,
Wherein the transparent electrode layer further comprises hydrogen. 17. The method of claim 16,
Wherein the transparent electrode layer comprises indium-cesium oxide (ICO: H) containing hydrogen. The method according to claim 1,
Wherein the first electrode includes a first transparent electrode layer formed on the front electric field area and a first metal electrode layer disposed on the first transparent electrode layer,
Wherein the second electrode includes a second transparent electrode layer formed on the front electric field area and a second metal electrode layer disposed on the second transparent electrode layer,
Wherein a thickness of the first transparent electrode layer is larger than a thickness of the second transparent electrode layer. 19. The method of claim 18,
Wherein a ratio of a thickness of the second transparent electrode layer to a thickness of the first transparent electrode layer is from 1: 1.1 to 1: 4. The method according to claim 1,
The semiconductor substrate and the front electric field area have n-type,
Wherein the emitter region has a p-type. The method according to claim 1,
And a first uneven portion and a second uneven portion on the front surface of the semiconductor substrate. A passivation film forming step of forming a first passivation film and a second passivation film which are respectively located on the front surface and the rear surface of the semiconductor substrate;
A first passivation film located on the first passivation film on the front side of the semiconductor substrate and having a front electric field area having the same conductivity type as the semiconductor substrate and a conductive type opposite to the semiconductor substrate located on the second passivation film on the rear side of the semiconductor substrate, A conductive type region forming step of forming a plurality of emitter regions;
Forming a first transparent electrode layer on the front electric field area and a second transparent electrode layer on the emitter area; And
Forming a first metal electrode layer on the first transparent electrode layer and a second transparent electrode layer on the emitter region,
Wherein the method comprises the steps of: 23. The method of claim 22,
At least one of the first metal electrode layer and the second metal electrode layer is formed with a pattern,
Wherein at least one of the first metal electrode layer and the second metal electrode layer is formed by forming a low temperature paste layer including a solvent, a conductive material and a binder, and drying or forming the metal layer by plating. 23. The method of claim 22,
Before the step of forming the passivation film,
Forming first irregularities on the front and rear surfaces of the semiconductor substrate by texturing using wet etching; And
Forming a second concavo-convex portion that is smaller than the first concavo-convex portion by reactive ion etching at least on the entire surface of the semiconductor substrate
Further comprising the steps of: 23. The method of claim 22,
Wherein the transparent electrode layer is formed by vapor deposition, and the raw material, the hydrogen gas, and the carrier gas constituting the transparent electrode layer are injected in the transparent electrode layer forming step. 26. The method of claim 25,
Wherein the carrier gas comprises a nitrogen gas or an argon gas,
And the hydrogen gas is contained in an amount of 0.5% to 5% with respect to the carrier gas. 26. The method of claim 25,
And the oxygen gas is injected together with the raw material, the hydrogen gas, and the carrier gas in the step of forming the transparent electrode layer. 28. The method of claim 27,
And the oxygen gas is contained in an amount of 15% to 40% with respect to the carrier gas.

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