KR102132738B1 - Mask assembly and method for manufacutring solar cell using the same - Google Patents

Abstract

Mask assembly according to an embodiment of the present invention, the mask; A semiconductor substrate and a base plate to which the mask is fixed; And a mask moving member moving the mask to change the position of the mask with respect to the semiconductor substrate.

Description

Mask assembly and manufacturing method of solar cell using the same{MASK ASSEMBLY AND METHOD FOR MANUFACUTRING SOLAR CELL USING THE SAME}

The present invention relates to a mask assembly and a method of manufacturing a solar cell using the same, and more particularly, to a mask assembly having an improved structure and a method of manufacturing a solar cell using the same.

With the recent depletion of existing energy resources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, the solar cell has been spotlighted as a next-generation cell that converts solar energy into electrical energy.

In such a solar cell, various layers and electrodes can be manufactured according to design. However, by forming various layers and electrodes, the manufacturing process is complicated and the manufacturing cost is increased, so that the productivity of the solar cell may be lowered.

The present invention is to provide a mask assembly that can be used to manufacture a solar cell to improve productivity and a method of manufacturing a solar cell using the same.

Mask assembly according to an embodiment of the present invention, the mask; A semiconductor substrate and a base plate to which the mask is fixed; And a mask moving member moving the mask to change the position of the mask with respect to the semiconductor substrate.

The mask includes a plurality of openings, and the mask moving member can move the mask in a direction crossing the longitudinal direction of the plurality of openings.

The mask includes a plurality of openings having a first pitch, and a movement distance of the mask by the mask moving member may correspond to 0.4 to 0.6 times the first pitch of the mask.

A mask accommodating portion accommodating the mask may be located on the base plate, and the length of the mask accommodating portion may be greater than that of the mask.

The length of the mask receiving portion may be equal to or greater than the sum of the length of the mask and the distance traveled by the mask moving member.

The mask moving member includes a first member and a second member fixed to the mask, and the first member and the second member may be positioned on both sides of the diagonal direction of the mask.

The base plate may include a plate portion including a substrate receiving portion on which the semiconductor substrate is placed, and a cover portion covering at least a portion of the mask positioned while covering the semiconductor substrate.

A guide portion providing a path for the mask moving member to move may be located in the cover portion.

The guide portion may have a hole or opening shape.

The mask may include a plurality of openings, and the guide portion may extend in a direction intersecting the longitudinal direction of the plurality of openings.

A fixing part to which the mask moving member is fixed may be positioned on the mask.

The mask moving member may be screwed to the fixing part.

The cover portion may include a first portion covering one edge portion of the mask and a second portion covering the other edge portion of the mask. The mask moving member may include a first member positioned on one side in the longitudinal direction of the first portion, and a second member positioned on the other side in the longitudinal direction of the second portion.

A mask accommodating portion in which the mask is located may be located on a side surface of the cover portion, or a mask accommodating portion in which the mask is located in the plate portion may be located.

The mask may include a mask portion in which a plurality of openings are formed, and a flexible portion formed in both edge portions of the mask body. The base plate may include a plate portion including a substrate receiving portion on which the semiconductor substrate is placed. The mask moving member may include a roller portion that winds the flexible portion and secures it to the plate portion.

The base plate may include graphite or silicon carbide.

A method of manufacturing a solar cell according to an embodiment of the present invention includes mounting a semiconductor substrate on a mask assembly including a mask having a plurality of openings, a base plate and a mask moving member; Forming a first conductivity type region by doping a first conductivity type dopant on the semiconductor substrate using the mask; Moving the mask using the mask moving member; And forming a second conductivity type region by doping a second conductivity type dopant at a position different from the first conductivity type region on the semiconductor substrate using the mask.

In the step of moving the position of the mask, the mask moving member may move the mask in a direction crossing a length direction of the plurality of openings of the mask.

In the step in which the plurality of openings of the mask have a first pitch and move the position of the mask, a movement distance of the mask by the mask moving member is 0.4 to 0.6 times the first pitch of the mask. It may be.

An undoped barrier region may be located between the first conductivity type region and the second conductivity type region because the first pitch is greater than the width of each of the plurality of openings.

When the mask assembly according to the present embodiment is used, the first conductive type region and the second conductive type region can be formed into one mask assembly or mask by moving the mask by the mask moving member, thereby simplifying the manufacturing process. Manufacturing costs can be reduced. In addition, the mask assembly and the mask moving member can precisely align the mask and the semiconductor substrate, thereby improving alignment characteristics of the first and second conductivity type regions.

1 is a cross-sectional view showing an example of a solar cell that can be manufactured by a mask assembly according to an embodiment of the present invention.
FIG. 2 is a rear plan view schematically showing the arrangement of the first and second conductivity type regions and the barrier region of the solar cell illustrated in FIG. 1.
3A is a perspective view showing a mask assembly according to an embodiment of the present invention.
3B is a perspective view showing the base plate of the mask assembly of FIG. 3A.
4 is a schematic cross-sectional view taken along line IV-IV of FIG. 3A.
5 is a cross-sectional view showing a mask assembly according to a modification of the present invention.
6 is a perspective view showing a mask assembly according to a modification of the present invention.
7A to 7I are cross-sectional views showing a method of manufacturing a solar cell according to an embodiment of the present invention.
8A and 8B are plan views showing a mask assembly in the processes shown in FIGS. 6D and 6F, respectively.
9 is a plan view showing another example of a solar cell that can be manufactured by a mask assembly according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it should be understood that the present invention is not limited to these embodiments and can be modified in various forms.

In the drawings, in order to clearly and briefly describe the present invention, illustration of parts irrelevant to the description is omitted, and the same reference numerals are used for the same or extremely similar parts throughout the specification. In addition, in the drawings, the thickness, the area, etc. are enlarged or reduced in order to make the description more clear. The thickness, area, etc. of the present invention are not limited to those shown in the drawings.

In addition, when a part is "included" in another part of the specification, the other part is not excluded and other parts may be further included unless specifically stated to the contrary. In addition, when a part such as a layer, film, region, plate, etc. is said to be "above" another part, this includes not only the case where the other part is "just above" but also another part in the middle. When a part such as a layer, a film, a region, or a plate is said to be "directly above" another part, it means that no other part is located in the middle.

Hereinafter, a mask assembly according to an embodiment of the present invention and a method of manufacturing a solar cell using the same will be described in detail with reference to the accompanying drawings. First, an example of a solar cell that can be manufactured using the mask assembly according to this embodiment will be described, and then a specific structure of the mask assembly and a method of manufacturing the solar cell using the same will be described.

1 is a cross-sectional view showing an example of a solar cell that can be manufactured by a mask assembly according to an embodiment of the present invention. For reference, FIG. 1 is a cross-sectional view taken along line I-I of FIG. 2.

Referring to FIG. 1, the solar cell 100 according to the present embodiment includes a semiconductor substrate 10 including a base region 110 and one surface (eg, a semiconductor substrate 10) of the semiconductor substrate 10. And conductive electrodes 32 and 34 located on the back side, and electrodes 42 and 44 connected to the conductive areas 32 and 34. In addition, the solar cell 100 may further include a tunneling layer 20, a passivation film 24, an anti-reflection film 26, an insulating layer 40, and the like. This will be explained in more detail.

The semiconductor substrate 10 may include a base region 110 including a second conductivity type dopant at a relatively low doping concentration. The base region 110 of this embodiment may include crystalline (single crystal or polycrystalline) silicon including a second conductivity type dopant. For example, the base region 110 may be formed of a single crystal silicon substrate (eg, a single crystal silicon semiconductor substrate) including a second conductivity type dopant. And the second conductivity type dopant may be n-type or p-type. As the n-type dopant, Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used, and as the p-type dopant, boron (B), aluminum (Al), and gallium Group 3 elements such as (Ga) and indium (In) can be used. For example, when the base region 110 has an n-type, the p-type forming a junction (for example, a pn junction with the tunneling layer 20) formed by the base region 110 and photoelectric conversion, The first conductivity type region 32 may be formed to increase the photoelectric conversion area. In addition, in this case, the first conductive type region 32 having a large area may effectively collect holes having a relatively slow moving speed, thereby further contributing to improving the photoelectric conversion efficiency. However, the present invention is not limited to this.

In addition, the semiconductor substrate 10 may include a front electric field region 130 positioned on the front side. The front electric field region 130 may have the same conductivity type as the base region 110 and have a higher doping concentration than the base region 110.

In this embodiment, it is illustrated that the front electric field region 130 is formed of a doping region formed by doping the semiconductor substrate 10 with a second conductivity type dopant at a relatively high doping concentration. Accordingly, the front surface region 130 includes the crystalline (single crystal or polycrystalline) semiconductor layer having the second conductivity type to form the semiconductor substrate 10. For example, the front electric field region 130 may be configured as a part of a single crystal semiconductor substrate (eg, a single crystal silicon semiconductor substrate substrate) having a second conductivity type. However, the present invention is not limited to this. Accordingly, the front electric field region 130 may be formed by doping a second conductive type dopant on the semiconductor substrate 10 and other semiconductor layers (eg, an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer). have. Alternatively, a role similar to that in which the front electric field region 130 is doped by a fixed charge of a layer (for example, the passivation film 24 and/or the antireflection film 26) formed adjacent to the semiconductor substrate 10 is provided. It may also consist of an electric field region. The front electric field region 130 having various structures may be formed by various other methods.

In this embodiment, the front surface of the semiconductor substrate 10 may be textured to have irregularities such as a pyramid. When surface roughness is increased by forming irregularities on the front surface of the semiconductor substrate 10 by the texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 may be reduced. Therefore, the amount of light reaching the pn junction formed by the base region 110 and the first conductivity type region 32 can be increased, thereby minimizing light loss.

In addition, the rear surface of the semiconductor substrate 10 may be formed of a relatively smooth and flat surface having a lower surface roughness than the front surface by mirror polishing. When the first and second conductivity-type regions 32 and 34 are formed on the back side of the semiconductor substrate 10 as in this embodiment, the characteristics of the solar cell 100 according to the characteristics of the back side of the semiconductor substrate 10 Because this can vary greatly. Accordingly, it is possible to improve passivation characteristics by not forming irregularities due to texturing on the rear surface of the semiconductor substrate 10, thereby improving the characteristics of the solar cell 100. However, the present invention is not limited to this, and in some cases, irregularities may be formed by texturing on the rear surface of the semiconductor substrate 10. Various other modifications are also possible.

A tunneling layer 20 is formed on the rear surface of the semiconductor substrate 10. The interfacial properties of the rear surface of the semiconductor substrate 10 can be improved by the tunneling layer 20, and the carrier generated by the photoelectric conversion is smoothly transferred by the tunneling effect. The tunneling layer 20 may include various materials through which the carrier can be tunneled. For example, the tunneling layer 20 may include oxide, nitride, semiconductor, conductive polymer, and the like. For example, the tunneling layer 20 may include silicon oxide, silicon nitride, silicon oxide nitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and the like. At this time, the tunneling layer 20 may be formed entirely on the back surface of the semiconductor substrate 10. Accordingly, the entire back surface of the semiconductor substrate 10 can be passivated and easily formed without additional patterning.

To sufficiently implement the tunneling effect, the thickness of the tunneling layer 20 may be smaller than the thickness of the insulating layer 40. For example, the thickness of the tunneling layer 20 may be 10 nm or less, and may be 0.5 nm to 10 nm (more specifically, 0.5 nm to 5 nm, for example, 1 nm to 4 nm). If the thickness of the tunneling layer 20 exceeds 10 nm, the tunneling does not occur smoothly and the solar cell 100 may not operate, and if the thickness of the tunneling layer 20 is less than 0.5 nm, the tunneling layer 20 of desired quality It may be difficult to form. In order to further improve the tunneling effect, the thickness of the tunneling layer 20 may be 0.5 nm to 5 nm (more specifically, 1 nm to 4 nm). However, the present invention is not limited thereto, and the thickness of the tunneling layer 20 may have various values.

Conductive regions 32 and 34 may be positioned on the tunneling layer 20. More specifically, the conductivity-type regions 32 and 34 have a first conductivity-type dopant having a first conductivity-type dopant, and a second conductivity-type dopant having a first conductivity-type region 32 and a second conductivity-type dopant. 2 may include a conductive region 34. In addition, a barrier region 36 may be positioned between the first conductivity type region 32 and the second conductivity type region 34.

The first conductivity type region 32 forms a pn junction (or a pn tunnel junction) with the base region 110 and the tunneling layer 20 therebetween to form an emitter region that generates carriers by photoelectric conversion.

In this case, the first conductivity type region 32 may include a semiconductor (eg, silicon) including a first conductivity type dopant opposite to the base region 110. In this embodiment, the first conductivity type region 32 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the tunneling layer 20 ), and the first conductivity type dopant is doped. It consists of a semiconductor layer. Accordingly, the first conductivity type region 32 may be formed of a semiconductor layer having a different crystal structure from the semiconductor substrate 10 so that it can be easily formed on the semiconductor substrate 10. For example, the first conductivity type region 32 is an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor that can be easily manufactured by various methods such as deposition (eg, amorphous silicon, microcrystalline silicon, or polycrystalline silicon) It may be formed by doping the first conductive type dopant on the back. The first conductivity type dopant may be included in the semiconductor layer in the process of forming the semiconductor layer, or may be included in the semiconductor layer by various doping methods such as a heat diffusion method and an ion implantation method after forming the semiconductor layer.

In this case, the first conductivity type dopant is sufficient as long as it is a dopant capable of exhibiting a conductivity type opposite to the base region 110. That is, when the first conductivity type dopant is p-type, a group 3 element such as boron (B), aluminum (Al), gallium (Ga), and indium (In) can be used. When the first conductivity type dopant is n-type, Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used.

The second conductivity type region 34 forms a back surface field to prevent carrier loss due to recombination on the surface of the semiconductor substrate 10 (more precisely, the back surface of the semiconductor substrate 10). It constitutes the rear electric field area.

In this case, the second conductivity type region 34 may include a semiconductor (eg, silicon) including the second conductivity type dopant that is the same as the base region 110. In this embodiment, the second conductivity type region 34 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the tunneling layer 20 ), and the second conductivity type dopant is doped. It consists of a semiconductor layer. Accordingly, the second conductivity type region 34 may be formed of a semiconductor layer having a different crystal structure from the semiconductor substrate 10 so that it can be easily formed on the semiconductor substrate 10. For example, the second conductivity type region 34 is an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor that can be easily manufactured by various methods such as vapor deposition (eg, amorphous silicon, microcrystalline silicon, or polycrystalline silicon) It may be formed by doping a second conductive type dopant on the back. The second conductivity-type dopant may be included in the semiconductor layer in the process of forming the semiconductor layer, or may be included in the semiconductor layer by various doping methods such as a heat diffusion method and an ion implantation method after forming the semiconductor layer.

In this case, the second conductivity type dopant is sufficient as long as it is a dopant capable of exhibiting the same conductivity type as the base region 110. That is, when the second conductivity type dopant is n-type, Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used. When the second conductivity-type dopant is p-type, Group 3 elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In) may be used.

In addition, a barrier region 36 is positioned between the first conductivity type region 32 and the second conductivity type region 34 to separate the first conductivity type region 32 and the second conductivity type region 34 from each other. When the first conductivity type region 32 and the second conductivity type region 34 are in contact with each other, a shunt may occur to degrade the performance of the solar cell 100. Accordingly, in the present embodiment, an unnecessary shunt can be prevented by positioning the barrier region 36 between the first conductivity type region 32 and the second conductivity type region 34.

The barrier region 36 may include various materials capable of substantially insulating them between the first conductivity type region 32 and the second conductivity type region 34. That is, an insulating material (eg, oxide, nitride) that is not doped (ie, undoped) with the barrier region 36 may be used. Alternatively, the barrier region 36 may include an intrinsic semiconductor. At this time, the first conductivity type region 32 and the second conductivity type region 34 and the barrier region 36 are formed on the same plane and have substantially the same thickness and are the same semiconductor (eg, amorphous silicon, microcrystalline silicon, Polycrystalline silicon), but may be substantially free of dopants. As an example, after forming a semiconductor layer including a semiconductor material, a first conductivity type dopant is doped in some regions of the semiconductor layer to form a first conductivity type region 32 and a second conductivity type dopant is formed in some of the other regions. When the second conductivity-type region 34 is formed by doping, regions where the first conductivity-type region 32 and the second conductivity-type region 34 are not formed may constitute the barrier region 36. Accordingly, the method of manufacturing the first conductivity type region 32, the second conductivity type region 34, and the barrier region 36 can be simplified.

However, the present invention is not limited to this. Therefore, when the barrier region 36 is formed separately from the first conductivity type region 32 and the second conductivity type region 34, the thickness of the barrier region 36 is the first conductivity type region 32 and the second. It may be different from the conductive region 34. For example, in order to more effectively prevent shorts in the first conductivity type region 32 and the second conductivity type region 34, the barrier region 36 has the first conductivity type region 32 and the second conductivity type region 34. It may have a thicker thickness. Alternatively, the thickness of the barrier region 36 may be smaller than the thickness of the first conductivity type region 32 and the second conductivity type region 34 in order to save raw materials for forming the barrier region 36. Of course, various other modifications are possible. Further, the basic constituent material of the barrier region 36 may include a material different from the first conductivity type region 32 and the second conductivity type region 34. Alternatively, the barrier region 36 may be configured as an empty space (eg, a trench) positioned between the first conductivity type region 32 and the second conductivity type region 34.

In addition, the barrier region 36 may be formed to separate only a part of the boundary between the first conductivity type region 32 and the second conductivity type region 34. Accordingly, other portions of the boundary between the first conductivity type region 32 and the second conductivity type region 34 may contact each other. In addition, the barrier region 36 is not necessarily provided, and the first conductivity type region 32 and the second conductivity type region 34 may be formed in full contact. Various other modifications are possible.

In this embodiment, it is illustrated that the conductive regions 32 and 34 are located on the rear surface of the semiconductor substrate 10 with the tunneling layer 20 interposed therebetween. However, the present invention is not limited to this, and it is also possible that the tunneling layer 20 is not provided and the conductive regions 32 and 34 are formed of a doped region formed by doping a dopant in the semiconductor substrate 10. That is, the conductive regions 32 and 34 may be formed as a doped region of a single crystal semiconductor structure constituting a part of the semiconductor substrate 10. The conductive regions 32 and 34 may be formed by various other methods.

The insulating layer 40 may be formed on the first conductivity type region 32 and the second conductivity type region 34 and the barrier region 36. The insulating layer 40 is an electrode to which the first conductivity type region 32 and the second conductivity type region 34 should not be connected (that is, the second electrode 44 in the case of the first conductivity type region 32), In the case of the second conductivity type region 34, it may be prevented from being connected to the first electrode 42, and may have an effect of passivating the first conductivity type region 32 and the second conductivity type region 34. . The insulating layer 40 includes a first opening 402 exposing the first conductivity type region 32 and a second opening 404 exposing the second conductivity type region 34.

The insulating layer 40 may be formed to have a thickness equal to or greater than that of the tunneling layer 20. Thereby, the insulating property and the passivation property can be improved. The insulating layer 40 may be made of various insulating materials (eg, oxide, nitride, etc.). For example, the insulating layer 40 is a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxide nitride film, Al ₂ O ₃ , MgF ₂ , ZnS, TiO ₂ and any one single film selected from CeO ₂ Or it may have a multi-layer film structure in which two or more films are combined. However, the present invention is not limited thereto, and the insulating layer 40 may include various materials.

Electrodes 42 and 44 positioned on the rear surface of the semiconductor substrate 10 are connected to the first electrode 42 electrically and physically connected to the first conductivity type region 32 and the second conductivity type region 34. And a second electrode 44 electrically and physically connected.

In this case, the first electrode 42 is connected to the first conductivity type region 32 through the first opening 402 of the insulating layer 40, and the second electrode 44 is the second electrode of the insulating layer 40. It is connected to the second conductivity type region 34 through the opening 404. The first and second electrodes 42 and 44 may include various metal materials. In addition, the first and second electrodes 42 and 44 are connected to the first conductivity type region 32 and the second conductivity type region 34, respectively, without being electrically connected to each other to collect and transfer the generated carriers to the outside. It can have a variety of planar shapes. That is, the present invention is not limited to the planar shape of the first and second electrodes 42 and 44.

Hereinafter, the planar shapes of the first conductivity type region 32, the second conductivity type region 34, and the barrier region 36 will be described in detail with reference to FIG. 2. FIG. 2 is a rear plan view schematically showing the arrangement of the first and second conductivity type regions 32 and 34 and the barrier region 36 of the solar cell shown in FIG. 1. For clarity and simplicity, the illustration of the insulating layer 40 and the first and second electrodes 42 and 44 is omitted in FIG. 2.

Referring to FIG. 2, in the present embodiment, the first conductivity type region 32 and the second conductivity type region 34 are formed to be long to form a stripe shape, and are alternately positioned in a direction intersecting the longitudinal direction. . A barrier region 36 spaced apart from the first conductivity type region 32 and the second conductivity type region 34 may be located. Although not illustrated in the drawing, a plurality of first conductivity type regions 32 spaced apart from each other may be connected to each other at one edge, and a plurality of second conductivity type regions 34 spaced apart from each other may be connected to each other at the other edge. However, the present invention is not limited to this.

In this embodiment, for example, the width of the first conductivity type region 32 and the width of the second conductivity type region 34 may be the same or similar to each other, and the pitch P1 of the first conductivity type region 32 may be the same. ) And the pitch P2 of the second conductivity type region 34 may be the same or similar to each other. Accordingly, the first conductivity-type region 32 (or the second conductivity-type region 34) is formed using the mask 210, and then the mask 210 is shifted to form the second conductivity-type region 34 (or the second conductivity-type region 34). One conductive type region 32 can be formed. That is, since the first conductivity type region 32 and the second conductivity type region 34 can be formed using one mask 210, the use amount of the mask 210 can be greatly reduced. This will be described in more detail later by explaining a method of manufacturing a mask assembly 200 including the mask 210 and a solar cell 100 using the mask assembly 200.

Referring to FIG. 1 again, the first electrode 42 is formed in a stripe shape corresponding to the first conductivity type region 32, and the second electrode 44 is striped in response to the second conductivity type region 34. It can be formed into a shape. In the drawing, it is illustrated that the first and second openings 402 and 404 are formed in the entire area of the first and second electrodes 42 and 44, respectively, corresponding to the first and second electrodes 42 and 44. Accordingly, it is possible to improve carrier collection efficiency by maximizing the contact area between the first and second electrodes 42 and 44 and the first conductivity type region 32 and the second conductivity type region 34. However, the present invention is not limited to this. The first and second openings 402 and 404 are also formed to connect only a portion of the first and second electrodes 42 and 44 to the first conductivity type region 32 and the second conductivity type region 34, respectively. Of course it is possible. For example, the first and second openings 402 and 404 may be formed of a plurality of contact holes. In addition, although not shown in the drawing, the first electrode 42 may be formed to be connected to each other at one edge, and the second electrode 44 may be formed to be connected to each other at the other edge. However, the present invention is not limited to this.

The passivation film 24 and/or the anti-reflection film 26 may be positioned on the front surface of the semiconductor substrate 10 (more precisely, on the front electric field region 130 formed on the front surface of the semiconductor substrate 10 ). Depending on the embodiment, only the passivation film 24 may be formed on the front electric field region 130, only the anti-reflection film 26 may be formed on the front electric field region 130, or passivation on the front electric field region 130. The film 24 and the anti-reflection film 26 may be sequentially positioned. In the drawing, the passivation film 24 and the anti-reflection film 26 are sequentially formed on the front electric field region 130 so that the front electric field region 130 formed on the front side of the semiconductor substrate 10 is in contact with the passivation film 24. Was illustrated. However, the present invention is not limited thereto, and the front electric field region 130 may be formed in contact with the anti-reflection film 26, and various other modifications may be made.

The passivation film 24 and the anti-reflection film 26 may be substantially formed on the entire surface of the semiconductor substrate 10. Here, the term “completely formed” includes not only those that are completely formed physically but also inevitably partially excluded.

The passivation film 24 is formed in contact with the front surface of the semiconductor substrate 10 to passivate defects existing in the front surface or bulk of the semiconductor substrate 10. Thereby, the recombination site of the minority carriers may be removed to increase the open voltage of the solar cell 100. The antireflection film 26 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. Accordingly, the amount of light reaching the pn junction formed at the interface between the base region 110 and the first conductivity type region 32 can be increased by reducing the reflectance of light incident through the front surface of the semiconductor substrate 10. Accordingly, the short circuit current (Isc) of the solar cell 100 can be increased. As described above, the passivation film 24 and the anti-reflection film 26 increase the open voltage and short-circuit current of the solar cell 100 to improve the efficiency of the solar cell 100.

The passivation film 24 and/or anti-reflection film 26 may be formed of various materials. For example, the passivation film 24 is a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxide nitride film, an aluminum oxide film, MgF ₂ , ZnS, TiO ₂ and any one single film selected from the group consisting of CeO ₂ or It may have a multilayer film structure in which two or more films are combined. For example, the passivation film 24 may include silicon oxide, and the anti-reflection film 26 may include silicon nitride.

When light enters the solar cell 100 according to the present embodiment, electrons and holes are generated by photoelectric conversion at a pn junction formed between the base region 110 and the first conductivity type region 32, and the generated holes And the electron tunnels the tunneling layer 20 to move to the first conductivity type region 32 and the second conductivity type region 34, respectively, and then to the first and second electrodes 42 and 44. Thereby, electrical energy is generated.

As in the present embodiment, the electrodes 42 and 44 are formed on the rear surface of the semiconductor substrate 10, and in the solar cell 100 of the rear electrode structure in which no electrodes are formed on the front surface of the semiconductor substrate 10, the semiconductor substrate 10 ), it is possible to minimize shading loss. Thereby, the efficiency of the solar cell 100 can be improved.

The mask assembly 200 according to the present embodiment, which can be used for manufacturing such a solar cell 100, and a method of manufacturing the solar cell 100 using the same will be described in detail below.

Figure 3a is a perspective view showing a mask assembly according to an embodiment of the present invention, Figure 3b is a perspective view showing the base plate of the mask assembly of Figure 3a. And Figure 4 is a schematic cross-sectional view taken along the line IV-IV of Figure 3a.

Referring to FIG. 3A, the mask assembly 200 according to the present embodiment includes a base plate 220 to which the mask 210 and the semiconductor substrate (reference numeral 10 in FIG. 1 are the same) and the mask 20 are fixed. And, it may include a mask moving member 230 that can adjust the position of the mask 210.

In this embodiment, the mask 210 is a mask 210 corresponding to the first conductivity type region (reference numeral 32 in FIG. 1, hereinafter the same) or the second conductivity type region (reference numeral 34 in FIG. 1, hereinafter the same). A plurality of openings 212 are formed to correspond to the region. The plurality of openings 212 may have a stripe shape extending in one direction to correspond to the shape of the first or second conductivity type regions 32 and 34.

The first pitch P of the plurality of openings 212 may be substantially the same as the pitch P1 of the first conductivity type region 32 or the pitch P2 of the second conductivity type region 34. In addition, the opening 212 may have the same or similar width and length to the first conductivity type region 32 or the second conductivity type region 34. However, when the dopant is doped using the mask 210, the dopant passing through the opening 212 may be doped into the semiconductor substrate 10 while having a larger width and length than the opening 212. In consideration of this, the width and length of the opening 212 may be somewhat different from the width and length of the second conductivity type region 34.

The mask 210 may have a larger planar area than the semiconductor substrate 10. This is to allow the mask 210 to entirely cover the semiconductor substrate 10 even if an alignment error occurs. In addition, in the present embodiment, even if the mask 210 is moved by the mask moving member 230, the mask 210 can cover the semiconductor substrate 10 as a whole.

The base plate 220 may include a plate portion 222 having a substrate receiving portion 226 in which the semiconductor substrate 10 is accommodated. The plate portion 222 may have a plate shape having a larger area than the semiconductor substrate 10 and the mask 210 while supporting the lower portions of the semiconductor substrate 10 and the mask 210. The substrate accommodating portion 226 formed on the plate portion 222 has a planar shape that is the same or extremely similar to the planar shape of the semiconductor substrate 10 and recesses or grooves recessed to a depth corresponding to the thickness of the semiconductor substrate 10 It can have a shape. Then, the semiconductor substrate 10 can be stably fixed by placing the semiconductor substrate 10 in the substrate accommodating portion 226. However, the present invention is not limited thereto, and various modifications are possible, such as fixing the semiconductor substrate 10 using a separate fixing member.

In addition, the base plate 220 may include a cover portion 224 that covers a part of the mask 210. As an example, the cover portion 224 may include a first portion 2221 covering one edge portion of the mask 210 and a second portion 2242 covering the other edge portion of the mask 210 opposite thereto. Can. Here, the first and second portions 2241 and 2242 may be located on both sides in a direction intersecting the opening 212 formed in the mask 210, and a direction parallel to the opening 212 formed in the mask 210 It can be formed as.

At this time, the cover portion 224 (or the first and second portions 2241 and 2242, respectively) includes a side portion 224a covering the side edge of the mask 210 and a bending portion extending from the side portion 224a to form a plate portion ( 222) and a horizontal portion 224b spaced apart from each other by a predetermined distance. A mask receiving portion 228 into which the mask 210 is inserted is formed between the plate portion 222 and the horizontal portion 224b by such a shape.

The mask accommodating portion 228 is a space formed between the first accommodating groove 228a formed in the first portion 2221 and the second accommodating groove 228b formed in the second portion 2242. One edge of the mask 210 is positioned in the first receiving groove 228a of the first portion 2221, and the other edge of the mask 210 is placed in the second receiving groove 228b of the second portion 2242. When positioned, the mask 210 is stably fixed between the base plate 220 and the cover portion 224 and can be stably positioned on the semiconductor substrate 10.

At this time, the length of the mask receiving portion 228 (that is, the distance L1 between the first receiving groove 228a and the second receiving groove 228b) (that is, the second from the inner side of the first receiving groove 228a) The distance between the inner side surfaces of the receiving groove 228b may be greater than the length L2 of the mask 210 measured in a direction parallel thereto (the direction intersecting the opening 212 of the mask 210). This is to provide a clearance in which the mask 210 can move in consideration of the movement of the mask 210 by the mask moving member 230. At this time, the length L1 of the mask receiving portion 228 is the mask ( The length L2 of 210 may be equal to or greater than the sum of the movement distances of the mask 210 by the mask movement member 230. Then, the mask 210 may be moved by the mask movement member 230. Here, at this time, the length L1 of the mask accommodating portion 228, the length L2 of the mask 210, and the movement distance of the mask 210 by the mask moving member 230 can be moved. If the sum is the same, one edge or the other edge of the mask 210 is in close contact with the first receiving groove 228a or the second receiving groove 228b, so that the fixing stability of the mask 210 can be improved. The invention is not limited to this.

In this embodiment, the mask receiving portion 228 is formed by the receiving groove 228 formed in the cover portion 224 of the base plate 220. Accordingly, the mask 210 is inserted into the receiving groove 228 formed in the cover portion 224 on the upper surface of the plate portion 222. However, the present invention is not limited to this, and the shape and structure of the mask receiving portion 228 can be variously modified. For example, as a modified example, as shown in FIG. 5, the mask receiving portion 228 formed of a groove or a recess recessed by the thickness of the mask 210 from the upper surface of the plate portion 222 may be formed. . In this case, the substrate accommodating portion 226 is formed in the mask accommodating portion 228, so that the substrate accommodating portion 226 is recessed or recessed by the depth of the semiconductor substrate 10 from the bottom surface of the mask accommodating portion 228. It may consist of wealth. And the cover portion 224 may be made of only a horizontal portion (224b) without having a side portion (224a). In addition, various modifications are possible.

The cover portion 224 may be fixed to the plate portion 222 by various structures, methods, and the like. For example, the cover portion 224 may be fixed on the plate portion 222 by a hinge structure. In this case, the cover portion 224 is rotated to be away from the plate portion 222, and the semiconductor substrate 10 is placed on the substrate receiving portion 226 and the mask 210 is placed on the plate portion 222 in an open state. The cover portion 224 may be rotated toward the mask 210 to cover the mask 210. Alternatively, the cover portion 224 may be fixed on the plate portion 222 using screws or the like. In this case, in a state in which the semiconductor substrate 10 is placed on the substrate accommodating portion 226 while the lid portion 224 is separated from the plate portion 222, the lid portion is placed in a state where the mask 210 is placed on the plate portion 222. The 224 may be fixed to the plate portion 222 with screws or the like.

The plate portion 222 and/or the cover portion 224 constituting the base plate 220 may include graphite or silicon carbide. This is because the heat resistance is strong and doping characteristics can be improved by hardly emitting impurities during the process. However, the present invention is not limited to this.

In this embodiment, the mask moving member 230 may have a sliding lever structure. The sliding lever constituting the mask moving member 230 may include graphite or silicon carbide. This is because the heat resistance is strong and doping characteristics can be improved by hardly emitting impurities during the process. However, the present invention is not limited to this.

More specifically, a guide portion 220a that is opened to provide a path through which the mask moving member 230 can move may be formed on the cover portion 224. In addition, the fixing part 210a may be formed on the mask 210 to correspond to a part of the area exposed by the guide part 220a.

The guide portion 220a formed in the cover portion 224 may have a hole or opening shape in which the guide portion 220a is larger than the area of the mask moving member 230. Accordingly, the mask moving member 230 can be moved by a length corresponding to the guide portion 220a. At this time, the guide portion 220a may extend in a direction intersecting the longitudinal direction of the opening 212 to provide a path for the mask 210 to move opposite to the longitudinal direction of the opening 212.

The fixing part 210a formed on the mask 210 may have various structures capable of fixing the mask moving member 230. For example, a thread may be formed at an end of the mask moving member 230, and a thread corresponding to the thread may be formed on the inner surface of the fixing part 210a. Then, while rotating the end of the mask moving member 230, screw the screw of the inner surface of the fixing member 210a and the screw of the mask moving member 230 to fix the mask moving member 230 on the mask 210 can do. Having such a structure can simplify the structure and fixing structure of the mask moving member 230, and the mask moving member 230 can be stably fixed on the mask 210 by an easy and simple method. In addition, the mask moving member 230 and the mask 210 can be easily fastened and separated. However, the present invention is not limited thereto, and the mask moving member 230 may be fixed on the mask 210 by various structures and methods.

Due to this structure, the mask moving member 230 passes through the guide portion 220a in a state fixed to the fixing portion 210a of the mask 210 and is positioned to be exposed to the outside. Then, the user may move the mask moving member 230 or the mask moving member 230 by another device driving the mask moving member 230. Then, the position of the mask 210 may be changed while the mask 210 to which the mask moving member 230 is fixed moves together according to the movement of the mask moving member 230.

The moving distance of the mask 210 may vary depending on the embodiment. As described above, when the first conductivity type region 32 and the second conductivity type region 34 are alternately positioned, the movement distance of the mask 210 is approximately the first pitch P of the mask 210. It may be about half (for example, 0.4 to 0.6 times). Alternatively, the pitch P3 of the first and second conductivity type regions 32 and 34 (that is, the pitch between the conductivity type regions 32 and 34 adjacent to each other in the first and second conductivity type regions 32 and 34). ) May be about 0.8 to 1.2 times. Then, the first conductivity type region 32 and the second conductivity type region 34 can be easily manufactured by one mask 210 or the mask assembly 200.

A plurality of mask moving members 230 may be positioned. When a plurality of mask moving members 230 are positioned, the mask 210 can be moved to a desired position more stably. For example, in this embodiment, two mask moving members 230 are provided, and two mask moving members 230 may be positioned one on each side of the diagonal direction of the mask 210 or the mask assembly 200. . For example, the first member positioned on one side (the right side of the drawing) in the longitudinal direction of the first portion 2241 and the other side (left side of the drawing) in the longitudinal direction of the second portion 2242, for example, the mask moving member 230 ) May include a second member. Then, it is possible to effectively prevent the mask 210 from being tilted when the mask 210 is moved. However, the present invention is not limited to this, and the number and arrangement of the mask moving members 230 may vary.

In this embodiment, it is illustrated that the mask 210 is fixed to the mask moving member 230 by a screw structure or the like. However, the present invention is not limited to this, and various modifications are possible. For example, as another modification, as shown in FIG. 6, the mask moving member 230 is fixed to the plate portion 222 and may include a roller portion 232 that winds up the mask 210. Then, the position of the mask 210 may be changed by rotating the roller unit 232.

In this case, the flexible portion 2012 may be positioned on the upper and lower edges of the mask 210 so that the edges of the mask 210 can freely rotate on the roller portion 232. That is, the central portion of the mask 210 is composed of a mask portion 2100 having a plurality of openings 212, and the flexible portions 2012 are positioned at upper and lower edges of the mask portion 2100, respectively. Can. According to this, the mask 210 can be easily moved by rotating the roller part 232.

The plate portion 222 and/or the cover portion 224 constituting the base plate 220 may include graphite or silicon carbide. This is because the heat resistance is strong and doping characteristics can be improved by hardly emitting impurities during the process. However, the present invention is not limited to this. The mask portion 2100 of the mask 210 may include graphite or silicon carbide, and the flexible portion 2012 may include various resins. However, the present invention is not limited to this.

A method of manufacturing the solar cell 100 using the mask assembly 200 having the above-described structure will be described in detail. Details that are the same or extremely similar to those already described will be omitted, and different parts will be described in detail. Hereinafter, an example using the mask assembly 200 illustrated in FIGS. 1 to 4 is illustrated, but the present invention is not limited thereto. Therefore, the mask assembly 200 shown in FIGS. 5 and 6 may be used.

7A to 7I are cross-sectional views showing a method of manufacturing a solar cell according to an embodiment of the present invention, and FIGS. 8A and 8B are plan views showing a mask assembly in the processes shown in FIGS. 6D and 6F, respectively.

First, as shown in FIG. 7A, a semiconductor substrate 10 composed of a base region 110 having a first conductivity type impurity is prepared.

At this time, at least one surface of the front and rear surfaces of the semiconductor substrate 10 may be textured to have irregularities. As the texturing of the surface of the semiconductor substrate 10, wet or dry texturing can be used. Wet texturing can be performed by immersing the semiconductor substrate 10 in a texturing solution, and has a short process time. Dry texturing is to cut the surface of the semiconductor substrate 10 by using a diamond grill or a laser, etc., it is possible to form irregularities uniformly, while the process time is long and damage to the semiconductor substrate 10 may occur. In addition, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like. As described above, in the present invention, the semiconductor substrate 10 can be textured in various ways.

Subsequently, as shown in FIG. 7B, a tunneling layer 20 is formed on the rear surface of the semiconductor substrate 10. The tunneling layer 20 may be formed by, for example, thermal growth, vapor deposition (eg, chemical vapor deposition (PECVD), atomic layer deposition (ALD)). However, the present invention is not limited thereto, and the tunneling layer 20 may be formed by various methods.

Subsequently, as shown in FIG. 7C, a semiconductor layer 30 is formed on the tunneling layer 20. The semiconductor layer 30 may be formed of a fine crystalline, amorphous, or polycrystalline semiconductor. The semiconductor layer 30 may be formed by, for example, a thermal growth method, a vapor deposition method (for example, chemical vapor deposition (PECVD)), or the like. However, the present invention is not limited thereto, and the semiconductor layer 30 may be formed by various methods.

Subsequently, as shown in FIGS. 7D to 7F, an emitter region 32, a rear electric field region 34, and a barrier region 36 are formed in the semiconductor layer 30. For simplicity and clarity, only the mask 210 is shown in the mask assembly 200 in FIGS. 7D to 7G, and the shape of the entire mask assembly 200 is shown in FIGS. 8A and 8B.

That is, as shown in FIGS. 7D and 8A, the first conductivity type dopant is diffused to form the first conductivity type region 32 while the mask 210 is positioned on the semiconductor layer 30 side. This will be explained in more detail.

The semiconductor substrate 10 on which the tunneling layer 20 and the semiconductor layer 30 are formed is mounted on the mask assembly 200. At this time, the semiconductor layer 30 is mounted so that the front side of the semiconductor substrate 10 is located on the bottom side of the mask accommodating portion 206 on the side of the mask 210. Then, the mask 210 is placed on the semiconductor substrate 10 (more specifically, the semiconductor layer 30 formed on the semiconductor substrate 10), the cover portion 224 is covered, and the mask is moved to penetrate the guide portion 220a. The member 230 is inserted and fixed to the fixing part 210a of the mask 210. In this state, when the first conductivity type dopant is doped into the semiconductor layer 30 by various methods, the first conductivity type dopant that has passed through the opening 212 of the mask 210 diffuses into the semiconductor layer 30 and the corresponding region In the first conductive region 32 is formed. As the doping method of the first conductivity type dopant, various methods such as a heat diffusion method and an ion implantation method can be used.

Subsequently, as shown in FIG. 7E, the mask 210 is moved using the mask moving member 230. That is, the position of the mask 210 is changed by moving the mask moving member 230 along the length direction of the guide portion 220a. At this time, since the guide portion 220a is formed in a direction crossing the longitudinal direction of the opening 212 of the mask 210, the mask 210 moves in a direction crossing the longitudinal direction of the opening 212.

For example, as described above, when the first conductivity type region 32 and the second conductivity type region 34 are alternately located, the mask 210 is the first pitch P of the opening 212 of the mask 210. ) Is moved by a distance corresponding to about half. At this time, since the movement distance of the mask 210 may have a slight error due to a process error or the like, more specifically, the movement distance of the mask 210 may be 0.4 to 0.6 times the first pitch P. In addition, the first pitch P of the opening 212 may be greater than the width of the opening 212. This is to form an undoped barrier region 36 between the first conductivity type region 32 and the second conductivity type region 34. However, the present invention is not limited to this, and various modifications are possible.

Subsequently, as shown in FIGS. 7F and 8B, when the second conductive dopant is doped into the semiconductor layer 30 by various methods while the mask 210 is moved, the opening 212 of the mask 210 is opened. The second conductive type dopant passing through is diffused into the semiconductor layer 30 to form a second conductive type region 34 in the corresponding region. As the doping method of the first conductivity type dopant, various methods such as a heat diffusion method and an ion implantation method can be used.

At this time, since the mask 210 is moved by approximately half (0.4 times to 0.6 times) of the first pitch P, the opening 212 of the mask 210 is formed of two adjacent first conductivity-type regions 32. Between them. Accordingly, when the second conductivity type dopant is doped, the second conductivity type region 34 may be formed between two adjacent first conductivity type regions 32. At this time, as described above, since the width of the opening 212 is smaller than the first pitch P, only a portion of the space between the two first conductivity-type regions 32 adjacent to the opening 212 is opened. Accordingly, the second conductivity type region 34 is formed only in a part of the space between two neighboring first conductivity type regions 32, whereby the first conductivity type region 32 and the second conductivity type region 34 are formed. ), there is a barrier region 36 which is a region that is not doped. However, the present invention is not limited to this, and various modifications are possible.

In the above description and drawings, the first conductivity type region 32 is first formed and then the second conductivity type region 34 is illustrated, but the present invention is not limited thereto. Therefore, it is also possible to first form the second conductivity type region 34 and then to form the first conductivity type region 32.

Subsequently, as illustrated in FIG. 7G, the front electric field region 130 may be formed by doping a second conductivity type dopant on the front surface of the semiconductor substrate 10. The front electric field region 130 may be formed by various methods such as ion implantation, heat diffusion, laser doping, and the like. Various other methods can be used.

Subsequently, as shown in FIG. 7H, the passivation film 24 and the anti-reflection film 26 are entirely formed on the front surface of the semiconductor substrate 10, and the first and second conductivity-type regions are formed on the rear surface of the semiconductor substrate 10. The insulating layer 40 is formed as a whole to cover the (32, 34). The passivation film 24, the anti-reflection film 26, and the insulating layer 40 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing or spray coating. The formation order of the passivation film 24, the anti-reflection film 26, and the insulating layer 40 can be variously modified.

Subsequently, as illustrated in FIG. 7I, first and second electrodes 42 and 44 connected to the first and second semiconductor layers 32 and 34, respectively, are formed. In this case, for example, the first and second openings 402 and 404 are formed in the insulating layer 40, and the first and second openings 402 and 404 are first formed in various methods such as a plating method and a deposition method. And second electrodes 42 and 44.

In another embodiment, the first and second electrode forming pastes are respectively applied to the insulating layer 40 by screen printing or the like, followed by fire through or laser firing contact. It is also possible to form the first and second electrodes 42 and 44 in the shape. In this case, since the first and second openings 402 and 404 are formed when the first and second electrodes 42 and 44 are formed, a process of separately forming the first and second openings 402 and 404 is performed. There is no need to add.

When the mask assembly 200 according to the present embodiment is used as described above, the first conductive type region 32 and the second conductive type region 34 are moved by moving the mask 210 by the mask moving member 230. It can be formed of a single mask assembly 200 or the mask 210 to simplify the manufacturing process and reduce manufacturing costs. Further, the mask 210 and the semiconductor substrate 10 can be precisely aligned by the mask assembly 200 and the mask moving member 230 so that the alignment of the first and second conductivity-type regions 32 and 34 is possible. Characteristics can be improved. In addition, in this embodiment, the relative position of the mask 210 with respect to the semiconductor substrate 10 can be easily and simply changed by using the mask assembly 200 with improved structure. On the other hand, in order to change the position of the mask assembly 200 itself or the semiconductor substrate 10 in order to change the relative position of the mask 210 with respect to the semiconductor substrate 10, it is necessary to modify the design of the equipment itself. It can grow.

In the above-described embodiment, the case where the first and second conductivity type regions 32 and 34 are formed by one mask 210 using the mask moving member 230 is illustrated. However, the present invention is not limited to this. Therefore, the mask 210 may also be applied when making one of the first and second conductivity-type regions 32 and 34. In this case, the mask moving member 230 may change the position of the mask 210 to change the relative position of the mask 210 and the semiconductor substrate 10. Accordingly, after the mask 210 is placed on the semiconductor substrate 10, the mask 210 may be moved so that the mask 210 is positioned at a more precise position. Accordingly, alignment accuracy between the semiconductor substrate 10 and the mask 210 can be improved.

And in the above-described embodiment, it was illustrated that the first conductivity type region 32 and the second conductivity type region 34 are alternately positioned. However, the present invention is not limited thereto, and the number of the first conductivity type regions 32 and the second conductivity type regions 34 having the same or similar width may be different from each other. That is, as shown in FIG. 9, the number of the first conductivity-type regions 32 may be greater than the number of the second conductivity-type regions 34.

In the drawing, for example, based on three conductive regions 32 and 34 of two first conductive regions 32 and one second conductive region 34, they may have a repeating structure. have. The first and second conductivity-type regions 32 and 34 having such a structure are used to replace the mask 210 of the mask assembly 200 with the pitch P3 of the conductivity regions 32 and 34 (ie, the first and second conductivity). It may be formed by doping the first conductivity type dopant twice and doping the second conductivity type dopant once while moving as much as corresponding to the pitch between two adjacent ones of the mold regions 32 and 34. However, the present invention is not limited to this, and the number of the first conductivity type region 32 and the second conductivity type region 34 may vary.

With this structure, the area of the first conductivity type region 32 having a conductivity type different from that of the base region 110 is wider than that of the second conductivity type region 34 having the same conductivity type as the base region 110. Can form. Accordingly, a pn junction formed through the tunneling layer 20 between the base region 110 and the first conductivity-type region 32 may be formed more widely. At this time, when the base region 110 and the second conductivity-type region 34 have an n-type conductivity type and the first conductivity-type region 32 has a p-type conductivity type, the first conductivity-type region formed broadly By (32), holes with a relatively slow moving speed can be effectively collected.

9 illustrates that the number of first and second conductivity type regions 34 are different while maintaining the widths of the first conductivity type region 32 and the second conductivity type region 34 similar. However, the present invention is not limited to this. The doping process of the first conductive type dopant (or the second conductive type dopant) is performed a plurality of times by adjusting the moving distance of the mask moving member 230, the width and pitch of the opening 212 of the mask 210, and the like. In addition, it is also possible to form different widths of the first conductivity type region 32 and the second conductivity type region 34. At this time, while performing the doping process of the first conductivity type dopant (the second conductivity type dopant) a plurality of times (for example, two times), a part of the openings 212 of the mask 210 may overlap in the plurality of doping processes. When the doping concentration is different, the first conductivity type region 32 (or the second conductivity type region 34) having an optional structure may be formed.

Features, structures, effects, and the like as described above are included in at least one embodiment of the present invention, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, and the like exemplified in each embodiment may be combined or modified for other embodiments by a person having ordinary knowledge in the field to which the embodiments belong. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the present invention.

100: solar cell
200: mask assembly
210: mask
220: base plate
230: mask movement member

Claims (20)

Mask;
A semiconductor substrate and a base plate to which the mask is fixed;
A mask moving member that moves the mask so that the position of the mask relative to the semiconductor substrate changes
Including,
The base plate includes a plate portion including a substrate receiving portion on which the semiconductor substrate is placed, and a mask assembly including a cover portion covering at least a portion of the mask positioned while covering the semiconductor substrate. According to claim 1,
The mask includes a plurality of openings,
A mask assembly in which the mask moving member moves the mask in a direction intersecting the longitudinal direction of the plurality of openings. According to claim 1,
The mask includes a plurality of openings having a first pitch,
A mask assembly in which a movement distance of the mask by the mask movement member corresponds to 0.4 to 0.6 times the first pitch of the mask. According to claim 1,
A mask accommodating portion accommodating the mask is located on the base plate,
The mask assembly having a length of the mask receiving portion greater than the length of the mask. According to claim 4,
The length of the mask receiving portion is equal to or greater than the sum of the length of the mask and the distance traveled by the mask moving member. According to claim 1,
The mask moving member includes a first member and a second member fixed to the mask,
A mask assembly in which the first member and the second member are located on both sides of the mask in a diagonal direction. delete According to claim 1,
A mask assembly in which a guide portion providing a path for the mask moving member to move is located in the cover portion. The method of claim 8,
A mask assembly having the guide portion having a hole or opening shape. The method of claim 8,
The mask includes a plurality of openings,
A mask assembly wherein the guide portion extends in a direction intersecting the longitudinal direction of the plurality of openings. The method of claim 8,
A mask assembly in which a fixing part to which the mask moving member is fixed is located on the mask. The method of claim 11,
A mask assembly in which the mask moving member is screwed to the fixing portion. The method of claim 8,
The cover portion includes a first portion covering one edge portion of the mask and a second portion covering the other edge portion of the mask,
The mask moving member includes a first member positioned on one side in the longitudinal direction of the first portion and a second member located on the other side in the longitudinal direction of the second portion. The method of claim 8,
A mask assembly in which a mask accommodation portion in which the mask is located is located on a side surface of the cover portion, or a mask accommodation portion in which the mask is located in the plate portion. delete According to claim 1,
A mask assembly wherein the base plate comprises graphite or silicon carbide. delete delete delete delete

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