KR101807789B1 - Solar cell and method for manufacturing the same - Google Patents

Abstract

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A conductive type region located on the semiconductor substrate; An electrode electrically connected to the conductive region; And an insulating film located between the conductive type region and the electrode. The insulating film includes a refractory metal oxide containing a refractory metal.

Description

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a manufacturing method thereof, and more particularly, to a solar cell having improved structure and a manufacturing method thereof.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

Such a solar cell can be manufactured by forming various layers and electrodes according to design. However, solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize solar cells, it is required to overcome low efficiency, and various layers and electrodes are required to be designed so as to maximize the efficiency of the solar cell. With reference to the patent document KR 2014-0096215, researches on bonding between the conductive type region of the solar cell, the insulating layer and the electrodes have been continued.

The present invention provides a solar cell having excellent efficiency and a manufacturing method thereof.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A conductive type region located on the semiconductor substrate; An electrode electrically connected to the conductive region; And an insulating film located between the conductive type region and the electrode. The insulating film includes a refractory metal oxide containing a refractory metal.

A method of manufacturing a solar cell according to an embodiment of the present invention includes: forming a conductive type region on a semiconductor substrate; Forming an insulating film on the conductive region; And forming an electrode electrically connected to the conductive region on the insulating film. Wherein the insulating film comprises a refractory metal oxide containing a refractory metal, and the insulating film is formed by atomic layer deposition.

According to the embodiment of the present invention, the insulating film located between the conductive type region and the electrode includes a refractory metal oxide, thereby increasing the degree of reflection of light with a long wavelength and lowering the interface contact resistance of the electrode. In addition, since the insulating film is located in the contact hole of the rear passivation film, the passivation property in the contact hole can be improved and the conductive type region can be protected. At this time, the insulating film can be formed by the atomic layer deposition method, and the film density can be greatly improved. Thus, the efficiency of the solar cell can be improved.

1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention.
2 is a partial rear plan view of the solar cell shown in Fig.
3 is a cross-sectional view illustrating a solar cell according to one modification of the present invention.
4 is a cross-sectional view of a solar cell according to another modification of the present invention,
5A to 5I are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
6 is a partial rear plan view of a solar cell according to another embodiment of the present invention.
7 is a graph showing the results of measurement of the reflectance of the back surface of the solar cell in the solar cells according to Production Examples 1 and 2 and Comparative Examples 1 and 2. [
8 is a graph showing the results of measurement of the contact resistance of electrodes of the solar cell according to Production Example 1 and Comparative Examples 1 and 2.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle. The terms first and second are used for distinguishing each other, and the present invention is not limited thereto.

Hereinafter, a solar cell and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing a solar cell according to an embodiment of the present invention, and FIG. 2 is a partial rear plan view of the solar cell shown in FIG.

1 and 2, a solar cell 100 according to this embodiment includes a semiconductor substrate 10 and conductive regions 32, 32 formed on one surface (hereinafter referred to as "rear surface") of the semiconductor substrate 10, Electrodes 42 and 44 electrically connected to the conductive regions 32 and 34 and electrodes 42 and 44 located between the conductive regions 32 and 34 and the electrodes 42 and 44, And an insulating film 41 that forms a metal-insulator-semiconductor (MIS) structure together with the conductive regions 32 and 34. At this time, the insulating film 41 includes a refractory metal oxide formed by combining refractory metal and oxygen, for example, a refractory metal oxide film made of refractory metal oxide. Here, the tunneling layer 20 may be positioned between the semiconductor substrate 10 and the conductive type regions 32 and 34. The conductive type regions 32 and 34 include a first conductive type region 32 having a first conductivity type and a second conductive type region 34 having a second conductive type which are located together on the tunneling layer 20 The electrodes 32 and 34 include a first electrode 42 electrically connected to the first conductive type region 32 and a second electrode 44 electrically connected to the second conductive type region 34 . The solar cell 100 may further include a front passivation film 24, an antireflection film 26, a rear passivation film 40, and the like, which are positioned on the front surface of the semiconductor substrate 10. This will be explained in more detail.

The semiconductor substrate 10 may include a base region 110 having a second conductivity type including a second conductivity type dopant at a relatively low doping concentration. The base region 110 may be formed of a crystalline semiconductor including a second conductive dopant. In one example, the base region 110 may be composed of a single crystal or a polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon) including a second conductive type dopant. In particular, the base region 110 may be comprised of a single crystal semiconductor (e.g., a single crystal semiconductor wafer, more specifically a semiconductor silicon wafer) comprising a second conductive dopant. The electrical characteristics are excellent based on the base region 110 or the semiconductor substrate 10 having high crystallinity and few defects.

The second conductivity type may be p-type or n-type. For example, if the base region 110 has an n-type, the p-type (n-type) semiconductor layer forming a junction with the base region 110 and forming a carrier by photoelectric conversion It is possible to increase the photoelectric conversion area by forming the first conductivity type region 32 of the first conductivity type. In this case, the first conductivity type region 32 having a large area can effectively collect holes having a relatively low moving speed, thereby contributing to the improvement of photoelectric conversion efficiency. However, the present invention is not limited thereto.

The semiconductor substrate 10 may include a front electric field area (or an electric field area) 130 positioned on the other surface (hereinafter referred to as "front surface") side of the semiconductor substrate 10. The front field region 130 may have a doping concentration higher than that of the base region 110 while having the same conductivity type as that of the base region 110. [

In this embodiment, the front electric field region 130 is formed on the semiconductor substrate 10 as a doped region formed by doping the same dopant as the base region 110 with a relatively high doping concentration. Accordingly, the front electric field area 130 includes a crystalline (single crystal or polycrystalline) semiconductor having a second conductivity type to constitute a part of the semiconductor substrate 10.

However, the present invention is not limited thereto. Therefore, it is also possible to form the front electric field area 130 by doping a second conductive type dopant to a semiconductor layer other than the semiconductor substrate 10 (for example, an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer) have. Alternatively, the front electric field region 130 has a role similar to that doped by the fixed electric charge of the layer (for example, the front passivation film 24 and / or the antireflection film 26) formed adjacent to the semiconductor substrate 10 As shown in FIG. For example, when the base region 110 is n-type, the front passivation film 24 may be formed of an oxide (for example, aluminum oxide) having a fixed negative charge to form an inversion layer ) Can be formed and used as an electric field region. In this case, the semiconductor substrate 10 does not have a separate doping region but consists only of the base region 110, thereby minimizing defects in the semiconductor substrate 10. [ The front electric field area 130 having various structures can be formed by various other methods.

In the present embodiment, the front surface of the semiconductor substrate 10 may be textured to have irregularities such as pyramids. The texturing structure formed on the semiconductor substrate 10 may have a certain shape (e.g., a pyramid shape) having an outer surface formed along a specific crystal plane of the semiconductor. If the surface roughness of the semiconductor substrate 10 is increased by forming concavities and convexities on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced. Accordingly, the amount of light reaching the pn junction formed by the base region 110 and the first conductivity type region 32 can be increased, and the light loss can be minimized.

The rear surface of the semiconductor substrate 10 may be made of a relatively smooth and flat surface having a surface roughness lower than that of the front surface by mirror polishing or the like. When the first and second conductivity type regions 32 and 34 are formed together on the rear side of the semiconductor substrate 10 as in the present embodiment, the characteristics of the solar cell 100 This can vary greatly. As a result, unevenness due to texturing is not formed on the rear surface of the semiconductor substrate 10, so that passivation characteristics can be improved and the characteristics of the solar cell 100 can be improved. However, the present invention is not limited thereto, and it is also possible to form concavities and convexities by texturing on the rear surface of the semiconductor substrate 10 according to circumstances. Various other variations are possible.

A tunneling layer 20 may be formed on the rear surface of the semiconductor substrate 10. For example, the tunneling layer 20 may be formed in contact with the rear surface of the semiconductor substrate 10 to simplify the structure and improve the tunneling effect. However, the present invention is not limited thereto.

The tunneling layer 20 acts as a kind of barrier to electrons and holes to prevent the minority carriers from passing therethrough and to prevent the majority carriers from being accumulated in the portion adjacent to the tunneling layer 20, so that only the majority carriers can pass through the tunneling layer 20. At this time, a plurality of carriers having energy above a certain level can easily pass through the tunneling layer 20 by the tunneling effect. The tunneling layer 20 may also serve as a diffusion barrier to prevent the dopants of the conductive regions 32 and 34 from diffusing into the semiconductor substrate 10. [ The tunneling layer 20 may include various materials through which a plurality of carriers can be tunneled. For example, the tunneling layer 20 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like. For example, the tunneling layer 20 may comprise silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and the like. In particular, the tunneling layer 20 may be comprised of a silicon oxide layer comprising silicon oxide. This is because the silicon oxide layer is a film which has excellent passivation characteristics and is susceptible to tunneling of the carrier.

At this time, the tunneling layer 20 may be formed entirely on the rear surface of the semiconductor substrate 10. Accordingly, it can be easily formed without additional patterning.

The tunneling layer 20 can have a thin thickness so that the tunneling effect can be sufficiently realized. In one example, the thickness of the tunneling layer 20 may be 5 nm or less (more specifically, 2 nm or less, for example, 0.5 nm to 2 nm). When the thickness T of the tunneling layer 20 exceeds 5 nm, the tunneling does not smoothly occur and the solar cell 100 may not operate. When the thickness of the tunneling layer 20 is less than 0.5 nm, It may be difficult to form the electrode 20. In order to further improve the tunneling effect, the thickness of the tunneling layer 20 may be 2 nm or less (more specifically, 0.5 nm to 2 nm). At this time, the thickness of the tunneling layer 20 may be 0.5 nm to 1.5 nm so as to further improve the tunneling effect. However, the present invention is not limited thereto, and the thickness of the tunneling layer 20 may have various values.

On the tunneling layer 20, a semiconductor layer 30 including conductive regions 32 and 34 may be located. For example, the semiconductor layer 30 may be formed in contact with the tunneling layer 20 to simplify the structure and maximize the tunneling effect. However, the present invention is not limited thereto.

In this embodiment, the semiconductor layer 30 includes a first conductivity type region 32 having a first conductivity type dopant and exhibiting a first conductivity type, a second conductivity type region 32 having a second conductivity type dopant and exhibiting a second conductivity type, Type region 34. [0040] The first conductive type region 32 and the second conductive type region 34 may be coplanar on the tunneling layer 20. That is, no other layer is located between the first and second conductivity type regions 32 and 34 and the tunneling layer 20, or the first and second conductivity type regions 32 and 34 and the tunneling layer 20 20, the other layers may have the same lamination structure. And a barrier region 36 may be positioned between the first conductivity type region 32 and the second conductivity type region 34 on the same plane.

The first conductive type region 32 forms a pn junction (or a pn tunnel junction) between the base region 110 and the tunneling layer 20 to form an emitter region for generating carriers by photoelectric conversion. The second conductivity type region 34 forms a back surface field to prevent carriers from being lost by recombination on the surface of the semiconductor substrate 10 (more precisely, the back surface of the semiconductor substrate 10) Thereby constituting a rear electric field area.

At this time, the first conductive type region 32 may include a semiconductor (for example, silicon) including a first conductive type dopant opposite to the base region 110. The second conductivity type region 34 may include a second conductivity type dopant that is the same as the base region 110 and the doping concentration thereof may be higher than the base region 110. In this embodiment, the first and second conductivity type regions 32 and 34 are formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the tunneling layer 20) Or a semiconductor layer doped with a second conductive dopant. The first and second conductivity type regions 32 and 34 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the first and second conductivity type regions 32 and 34 can be easily formed on the semiconductor substrate 10. For example, the first and second conductivity type regions 32 and 34 may be amorphous semiconductors, microcrystalline semiconductors, or polycrystalline semiconductors (e.g., amorphous silicon, microcrystalline silicon , Or polycrystalline silicon) or the like may be formed by doping with a first or second conductivity type dopant. In particular, if the first and second conductivity type regions 32 and 34 have a polycrystalline semiconductor, they can have a high carrier mobility. The first or second conductivity type dopant may be included in the semiconductor layer 30 in the step of forming the semiconductor layer 30 or may be doped with various doping methods such as a thermal diffusion method and an ion implantation method after forming the semiconductor layer 30 Or may be included in the semiconductor layer 30.

As the first or second conductivity type dopant, various materials which can be doped to the semiconductor layer 30 to exhibit n-type or p-type conductivity may be used. When the first or second conductivity type dopant is p-type, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. When the first or second conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used. In one example, one of the first and second conductivity type dopants may be boron (B) and the other may be phosphorus (P).

A barrier region 36 is positioned between the first conductive type region 32 and the second conductive type region 34 to separate the first conductive type region 32 and the second conductive type region 34 from each other. When the first conductive type region 32 and the second conductive type region 34 are in contact with each other, a shunt may be generated to deteriorate the performance of the solar cell 100. Accordingly, in this embodiment, unnecessary shunt can be prevented by positioning the barrier region 36 between the first conductive type region 32 and the second conductive type region 34.

An undoped (i.e., unshown) insulating material (e.g., oxide, nitride) or the like may be used as the barrier region 36. Alternatively, the barrier region 36 may comprise an intrinsic semiconductor. At this time, the first conductive type region 32, the second conductive type region 34, and the barrier region 36 are formed of the same semiconductor (for example, amorphous silicon, microcrystalline silicon, , The barrier region 36 may be an i-type (intrinsic) semiconductor material substantially free of dopants. For example, a semiconductor layer containing a semiconductor material may be formed, and then a first conductive type dopant may be doped in a part of the semiconductor layer to form a first conductive type region 32, and a second conductive type dopant A region where the first conductivity type region 32 and the second conductivity type region 34 are not formed may constitute the barrier region 36. In this case, This makes it possible to simplify the manufacturing method of the first conductivity type region 32, the second conductivity type region 34, and the barrier region 36.

However, the present invention is not limited thereto. Thus, the barrier region 36 may be formed by various methods to have various thicknesses and may have various shapes. The barrier region 36 may be a trench which is an empty space. Various other variations are possible. In the drawing, the barrier region 36 is shown as being entirely separated between the first conductivity type region 32 and the second conductivity type region 34. However, the barrier region 36 may be formed to separate only a part of the boundary portions of the first conductive type region 32 and the second conductive type region 34. Alternatively, since the barrier region 36 is not formed, the boundaries of the first conductive type region 32 and the second conductive type region 34 may be in contact with each other.

The rear passivation film 40 may be formed on the first and second conductivity type regions 32 and 34 and the barrier region 36 on the rear surface of the semiconductor substrate 10. [ For example, the rear passivation film 40 may be formed in contact with the first and second conductivity type regions 32 and 34 and the barrier region 36 to simplify the structure. However, the present invention is not limited thereto.

The rear passivation film 40 has contact holes 46 for electrical connection between the conductive regions 32 and 34 and the electrodes 42 and 42. The contact hole 46 includes a first contact hole 461 for connecting the first conductivity type region 32 and the first electrode 42 and a second contact hole 461 for connecting the second conductivity type region 34 and the second electrode 44, And a second contact hole 462 for connection of the second contact hole 462. As a result, the rear passivation film 40 is formed in the same manner as that of the first conductive type region 32 and the second conductive type region 34 in the case of the electrode to which the first conductive type region 32 and the second conductive type region 34 should not be connected 44 in the case of the second conductivity type region 34 and the first electrode 42 in the case of the second conductivity type region 34). In addition, the back passivation film 40 may have the effect of passivating the first and second conductivity type regions 32, 34 and / or the barrier region 36.

The front passivation film 24 and / or the antireflection film 26 can be positioned on the front surface of the semiconductor substrate 10 (more precisely, on the front electric field area 130 formed on the front surface of the semiconductor substrate 10) have. However, the present invention is not limited thereto, and another insulating layer having a stacked structure may be formed on the front electric field area 130.

The front passivation film 24 and the antireflection film 26 may be formed entirely on the entire surface of the semiconductor substrate 10. [ And the rear passivation film 40 may be formed entirely on the rear surface of the semiconductor layer 30 except for the contact hole 46. [ Here, the term " formed as a whole " includes not only completely formed physically but also includes cases where there are inevitably some exclusion parts.

The front passivation film 24 or the rear passivation film 40 may be formed in contact with the semiconductor substrate 10 or the semiconductor substrate 30 to prevent defects present in the front surface or bulk of the semiconductor substrate 10 or the semiconductor layer 30 Immobilized. Thus, the recombination site of the minority carriers can be removed to increase the open-circuit voltage of the solar cell 100. The antireflection film 26 may reduce the reflectivity of light incident on the front surface of the semiconductor substrate 10, thereby increasing the amount of light reaching the pn junction. Accordingly, the short circuit current Isc of the solar cell 100 can be increased.

The front passivation film 24, the antireflection film 26, and the rear passivation film 40 may be formed of various materials. In one example, the front passivation film 24, the anti-reflection film 26 or the passivation film 40 is a silicon nitride film, a silicon nitride film containing hydrogen, silicon oxide, silicon nitride oxide, aluminum oxide film, a silicon carbide film, MgF _2, ZnS, TiO _2, and CeO ₂ , or a multilayer structure in which two or more films are combined. For example, the front passivation film 24 may be formed on the semiconductor substrate 10 and may be a silicon oxide film, the antireflection film 26 may include a silicon nitride film, the rear passivation film 40 may be a silicon oxide film, A nitride film and / or a silicon carbide film. For example, in the present embodiment, the front passivation film 24 and / or the antireflection film 26 and the rear passivation film 40 may not include a dopant or the like so as to have excellent insulating properties, passivation properties, and the like.

The front passivation film 24, the antireflection film 26, and the rear passivation film 40 may have a thickness greater than that of the tunneling layer 20. [ As a result, the insulating characteristics and the passivation characteristics can be improved. Various other variations are possible.

The insulating film 41 is positioned between the conductive type regions 32 and 34 and the electrodes 42 and 44 in the contact hole 46 of the rear passivation film 40. The insulating film 41 is formed on the conductive type regions 32 and 34 in the contact holes 46 of the rear passivation film 40 so that the backside passivation film The passivation film 40 can be effectively prevented from being deteriorated due to the presence of the insulating film 41 on the portion where the passivation film 40 is not formed. In addition, the interface contact characteristics can be improved as compared with the direct contact between the conductive type regions 32 and 34 and the electrodes 42 and 44. Further, the insulating film 41 can prevent the conductive type regions 32 and 34 from being damaged in various processes performed after the contact holes 46 are formed.

At this time, the refractory metal oxide may be included in the insulating film 41 in this embodiment. Conventionally, in order to form an MIS structure in a semiconductor device or the like, an insulating film composed of silicon oxide has been used. The insulating film made of such a silicon oxide has low reflectivity. Since semiconductor devices do not consider using reflection of light, silicon oxide or the like having low reflectivity can be used as an insulating film. However, since the amount of light is directly related to the efficiency of the solar cell in the solar cell according to the present embodiment, the insulating film 41 made of refractory metal oxide having high reflectivity instead of silicon oxide having low reflectivity is used in this embodiment.

More specifically, the insulating film 41 composed of the refractory metal oxide can have a high refractive index, and the reflectance of a long wavelength can be further improved by such a high refractive index. The light of short wavelength is mostly absorbed from the front side of the semiconductor substrate 10 and the light of long wavelength mainly reaches to the rear side of the semiconductor substrate 10 because the insulating film 41 composed of the refractory metal oxide has high reflectivity with respect to light of a long wavelength , The light reaching the rear surface of the semiconductor substrate 10 can be effectively reflected.

The insulating film 41 made of refractory metal oxide is formed by atomic layer deposition, not chemical vapor deposition, and has a high film density and excellent crystallinity. By such high film density and excellent crystallinity, the absorption of light is minimized and the reflection of light can be improved more effectively.

As described above, the insulating film 41 including the refractory metal oxide can significantly improve the reflection characteristic of a long wavelength reaching the rear surface of the semiconductor substrate 10. Thus, the current density Jsc can be improved. Particularly, when the first and second electrodes 42 and 44 are all located on the rear surface as in the present embodiment, since the area ratio of the first and second electrodes 44 is large at the rear surface, The amount of light used for photoelectric conversion can be greatly increased.

Further, when the insulating film 41 contains a refractory metal oxide, the contact resistance of the electrodes 42 and 44 can be significantly reduced as compared with the case where the silicon oxide is used. This is because the insulating film 41 of this embodiment has a film density higher than that of silicon oxide and the pore is small, so that the tunneling characteristic can be improved. Further, the contact resistance of the electrodes 42 and 44 can be reduced as compared with the case where the insulating film 41 is not provided. This is thought to be due to the improved interfacial properties. Thereby increasing the fill factor (FF).

For example, the insulating film 41 may include titanium oxide (TiO x, for example, TiO ₂ ) or molybdenum oxide (MoO x, for example, MoO ₂ or MoO ₃ ). For example, the insulating layer 41 may be formed of a titanium oxide layer or a molybdenum oxide layer, and in particular, a titanium oxide layer. Titanium oxide or molybdenum oxide has a high reflectance to light of a long wavelength and can lower the contact resistance of the electrodes 42 and 44. In particular, titanium oxide is excellent in this effect. More specifically, if the insulating film 41 contains titanium oxide having an anatase phase, the titanium oxide may have better crystallinity and higher refractive index than the titanium oxide of the other phases, thereby greatly improving the reflectivity and the contact resistance lowering effect. However, the present invention is not limited thereto, and the insulating film 41 may include another phase (for example, a titanium oxide having a rutile phase).

At this time, since the conductive regions 32 and 34 and the electrodes 42 and 44 are electrically connected with the insulating film 41 interposed therebetween, the electrical connection between the conductive regions 32 and 34 and the electrodes 42 and 44 The insulating film 41 may be formed thin so as to improve the characteristics. That is, the insulating film 41 may have a thickness smaller than that of the rear passivation film 40, the front passivation film 24, and the antireflection film 26, and may have a thickness equal to or less than that of the tunneling layer 20. In particular, the insulating film 41 may have a thickness smaller than that of the tunneling layer 20. This is because the insulating film 41 may have a thin thickness enough not to deteriorate the electrical connection property.

For example, the thickness of the insulating film 41 may be 1 nm or less (for example, 0.005 nm to 1 nm). When the thickness of the insulating film 41 exceeds 1 nm, the conductivity type regions 32 and 34 and the electrodes 42 And 44 may be somewhat lowered. If the thickness of the insulating film 41 is less than 0.005 nm, it may be difficult to form the insulating film 41 as a whole with a uniform thickness, and the effect of the insulating film 41 However, the present invention is not limited thereto, and various modifications are possible.

The insulating film 41 having such a thickness can be formed by atomic layer deposition (ALD). In the atomic layer deposition method, after a precursor material is placed on the semiconductor layer 30, a reaction gas capable of reacting with the precursor material to form the refractory metal oxide is injected into the precursor material, and the precursor material is reacted by heat treatment. Gas and the like are removed by using a purge gas to form one atomic layer 41a.

As the precursor material, various materials including the above-described refractory metals can be used. For example, when the insulating film 41 includes titanium oxide, TiCl ₄ or Ti (OMe) ₄ Mo (CO) ₆ or the like can be used when the insulating film 41 contains molybdenum oxide. As the reaction gas, various materials including oxygen can be used. For example, H ₂ O or O ₃ may be used as the reaction gas. As the purge gas, an inert gas or nitrogen gas which does not react with other gases may be used. For example, Ar, N ₂ , or the like may be used as the purge gas. The process temperature of the atomic layer deposition process may be between 150 degrees and 200 degrees. However, the present invention is not limited thereto.

The insulating film 41 may be subjected to a plurality of cycles to have a desired thickness. When the insulating film 41 is formed by the atomic layer deposition method as described above, each of the atomic layers 41a formed by the respective cycles is formed on the conductive type regions 32, 34 or the rear passivation film 40 in plural The insulating film 41 can be formed. The insulating layer 41 may have a shape in which a plurality of atomic layers 41a are stacked. The plurality of atomic layers 41a may be formed by a microscope (for example, a transmission electron microscope You can easily check.

For example, in this embodiment, the insulating film 41 may have 10 or less (that is, 1 to 10 layers) of the atomic layer 41a by performing 10 cycles or less in the atomic layer deposition method. If the atomic layer 41a exceeds 10 layers, the cycle time may be increased to increase the process time and the thickness of the insulating film 41 may be increased so that the electrical connection between the conductive type regions 32 and 34 and the electrodes 42 and 44 The characteristics may be degraded.

The refractory metal oxide may be contained in an amount of 90 parts by weight or more with respect to the entire insulating film 41 formed by the atomic layer deposition method. In contrast, when an insulating film is formed by printing a paste or the like, followed by drying or firing, it contains a hardener, a resin, etc., and the weight of the metal oxide is less than 90 parts by weight and it is difficult for the insulating film 41 to have a uniform thickness. The effect of improvement and reduction of contact resistance can not be sufficiently realized. For example, when the insulating film is formed by using a paste or the like or by another deposition method, a plurality of atomic layers 41a as described above can not be found.

For example, when the insulating film 41 contains titanium oxide, the film density may be 3.8 g / cm ³ to 4.2 g / cm ³ , and may have a refractive index of 2.5 to 2.8. By such high film density and high refractive index, it is possible to greatly improve the reflection of light with a long wavelength and the contact resistance reducing effect of the electrodes 42 and 44. The insulating film 41 can effectively protect the rear passivation film 40 or the semiconductor layer 30 in the patterning process or the like in the process of forming the electrodes 42 and 44.

In this embodiment, the insulating film 41 includes a material different from that of the rear passivation film 40 and is formed by a method different from that of the rear passivation film 40. As described above, the rear passivation film 40 may be formed of a silicon oxide film, a silicon nitride film, a silicon carbide film, or the like. At this time, the rear passivation film 40 is formed by chemical vapor deposition (for example, plasma chemical vapor deposition). The rear passivation film 40 formed by chemical vapor deposition has a low film density and may have a porous structure. The film density of the insulating film 41 formed by the atomic layer deposition method is larger than that of the rear passivation film 40 formed by chemical vapor deposition and the refractive index of the insulating film 41 including the refractory metal oxide is higher than that of the silicon oxide, Silicon nitride, silicon nitride, or the like. More specifically, the refractive index of the silicon oxide film is 1.5, the refractive index of the silicon nitride film is 2.0, and the refractive index of the silicon carbide film is 1.5, which is much lower than the refractive index of the insulating film 41 containing titanium oxide.

The first electrode 42 is formed while filling at least a part of the first contact hole 461 of the rear passivation film 40 and is electrically connected to the first conductive type region 32 with the insulating film 41 therebetween And the second electrode 44 is formed while filling at least a part of the second contact hole 462 of the rear passivation film 40 and electrically connected to the second conductive type region 34 with the insulating film 41 therebetween do. For example, the insulating film 41 may be formed in contact with the conductive type regions 32 and 34, the rear passivation film 40, and the electrodes 42 and 44.

More specifically, the insulating film 41 is formed on at least the first and second contact holes 461 and 462 on the first or second conductive type regions 32 and 34 and the first and second contact holes 461 and 462. [ (That is, both sides of the rear passivation film 40 adjacent to the first and second contact holes 461 and 462) of the first and second contact holes 461 and 462. More specifically, the insulating film 41 is formed on the bottom surface of the contact hole 46 (that is, the surface of the conductive type regions 32 and 34 exposed by the contact hole 46) and on the side surface of the contact hole 46 The outer surface of the back passivation film 40, or between the large surface (bottom surface of the figure) and the electrodes 42, 44.

The insulating film 41 is formed on the passivation film 46 by the process of forming the contact holes 46 including the first and second contact holes 461 and 462 and the process of forming the electrodes 42 and 44 . The insulating film 41 can be formed entirely in the portion where the electrodes 42 and 44 are formed between the conductive type regions 32 and 34 and the rear passivation film 40 and the electrodes 42 and 44. [ The insulating film 41 is formed entirely and continuously on the back surface side of the semiconductor substrate 10 on the conductive type regions 32 and 34 and the rear side passivation film 40. [ At this time, since the insulating film 41 has a very thin thickness, the insulating film 41 can be formed with the steps, bend, etc. by the contact holes 46 as they are.

However, the present invention is not limited to this. As shown in FIG. 3, the insulating film 41 is patterned at the time of patterning the electrodes 42 and 44 and is formed only in the portion where the electrodes 42 and 44 are located, 42, and 44, respectively. In the drawings, the insulating film 41 is located only on the rear side of the semiconductor substrate 10 to prevent the reflection characteristic from changing on the front surface or the like. However, as shown in Fig. 4, the insulating film 41 may be located on the side and / or the front surface of the semiconductor substrate 10. [ Thus, it is possible to protect the side surface and / or the front surface of the semiconductor substrate 10 when the electrodes 42 and 44 are patterned. The insulating film 41 is located between the front electric field area 130 and the front passivation film 24, for example, on the front surface of the semiconductor substrate 10. However, the present invention is not limited to this, and the insulating film 41 may be disposed between the front passivation film 24 and the antireflection film 26 or on the antireflection film 26 according to the formation order of the insulating film 41.

Hereinafter, the lamination structure of the first and / or second electrodes 42 and 44 will be described in detail with reference to the enlargement circle in FIG. 1, and then the first and / or second electrodes 42 and 44 will be described with reference to FIG. Will be described in detail. Although the first electrode 42 is enlarged in the enlargement circle of FIG. 1, the second electrode 44 may have the same lamination structure. The first or second conductivity type regions 32 and 34 are referred to as conductive regions 32 and 34 and the first or second electrode 42 connected thereto is referred to as electrodes 42 and 44 Explain.

1, the electrodes 42 and 44 include a plurality of electrode layers located on the conductive regions 32 and 34 (more specifically, the insulating film 41 positioned thereon). For example, in the present embodiment, the electrodes 42 and 44 include a first electrode layer 422 located on the conductive regions 32 and 34 (for example, in contact with the insulating film 41) A second electrode layer 424, a third electrode layer 426, and a fourth electrode layer 428 located on the second electrode layer 422.

The first electrode layer 422 serves to prevent diffusion of the metal material of the second to fourth electrode layers 424, 426 and 428 (particularly, the second electrode layer 424) into the conductive regions 32 and 34 can do. At this time, since the insulating film 41 is further positioned between the conductive type regions 32 and 34 and the first electrode layer 422, the insulating film 41 also acts as a barrier to effectively prevent the problem of diffusion of the metal material .

More specifically, during the various manufacturing processes of the solar cell 100, various heat treatment processes are performed. For example, after the electrode material layer for forming the electrodes 42 and 44 is formed by physical vapor deposition (PVD) such as sputtering, the stress of the electrode material layer is reduced and the conductive type regions 32 and 34 The annealing process is performed to improve the contact characteristics with respect to the contact hole. Conventionally, during this heat treatment process, the semiconductor material of the conductive type regions 32 and 34 diffuses into the second electrode layer 424 and the electrode material of the second electrode layer 424 diffuses toward the conductive type regions 32 and 34, Lt; / RTI > For example, because the electrode material (especially aluminum) has a lower melting point than the semiconductor material, the electrode material located in the conductive regions 32, 34 by diffusion can easily be eluted, And 34 may have spikes in which small holes, holes, and the like are formed. If the sparking phenomenon occurs in the conductive type regions 32 and 34 as described above, defects are generated in the conductive type regions 32 and 34, so that the characteristics of the conductive type regions 32 and 34 may be greatly reduced. In this embodiment, the first electrode layer 422 and the insulating film 41 are positioned between the conductive type regions 32 and 34 and the second electrode 424 to prevent such a problem.

Particularly, in this embodiment, the first electrode layer 422 includes a refractory metal (for example, a refractory metal layer) to prevent undesired metallic material from diffusing into the conductive regions 32 and 34 in a high- have. For example, the first electrode layer 422 may comprise titanium, molybdenum, or tungsten.

The first electrode layer 422 may include a refractory metal (for example, titanium or molybdenum) the same as the refractory metal included in the metal oxide of the insulating film 41, and the first electrode layer 422 may include the insulating film 41 ) Of a metal oxide contained in the refractory metal layer. In particular, the metal of the first electrode layer 422 and the refractory metal contained in the insulating film 41 may be the same. Since the first refractory metal is provided in the first electrode layer 422 and the insulating layer 41, diffusion due to a chemical concentration gradient can be effectively prevented. For example, the insulating layer 41 may include titanium oxide and the first electrode layer 422 may include titanium. In this case, a low contact resistance and excellent thermal stability can be provided to form a stable MIS contact structure.

Also, the first electrode layer 424 may reduce the difference in characteristics between the conductive type region 32 and the second electrode layer 424 to improve contact characteristics. For example, the thermal expansion coefficient of the first electrode layer 422 may have a value between the thermal expansion coefficient of the conductive type regions 32 and 34 and the thermal expansion coefficient of the second electrode layer 424. As a result, it is possible to prevent the problem that the thermal expansion coefficient is large due to a large difference. For example, the second electrode layer 424 may include copper (Cu), aluminum (Al), silver (Ag), gold (Au), or the like. The first electrode layer 422 may include titanium, molybdenum, or tungsten The thermal expansion coefficient between the thermal expansion coefficient of silicon (Si) constituting the semiconductor substrate 10 and the thermal expansion coefficient of the metal of the second electrode layer 424 described above.

At this time, the first electrode layer 422 according to the present embodiment can have conductivity and transmittance that allows light to pass therethrough. The thickness of the first electrode layer 422 may be limited to a certain level or less so that the first electrode layer 422 may be made of metal So that it can have transparency. When the first electrode layer 422 has transparency as described above, the light having passed through the first electrode layer 422 is reflected by the second electrode layer 424 formed on the first electrode layer 422, . Accordingly, the efficiency and the efficiency of the solar cell 100 can be improved by increasing the amount of light existing in the semiconductor substrate 10 and the residence time.

Here, the term " permeability " includes not only a case of transmitting 100% of light but also a case of transmitting a part of light. That is, the first electrode layer 422 may be composed of a metal-permeable film or a metal-semitransmissive film. For example, the first electrode layer 422 may have a transmittance of 50% to 100%, and more specifically, a transmittance of 80% to 100%. If the transmittance of the first electrode layer 422 is less than 50%, the amount of light reflected by the second electrode layer 424 is insufficient, and it may be difficult to sufficiently improve the efficiency of the solar cell 100. If the transmittance of the first electrode layer 422 is 80% or more, the amount of light reflected by the second electrode layer 424 can be further increased, thereby contributing to the improvement of the efficiency of the solar cell 100.

The thickness of the first electrode layer 422 may be smaller than the thickness of the second electrode layer 424 and the fourth electrode layers 424 and 428. [ Specifically, the thickness of the first electrode layer 422 may be 50 nm or less. When the thickness of the first electrode layer 422 is more than 50 nm, the amount of light to be directed to the second electrode layer 424 may be insufficient because the transmittance of the first electrode layer 422 is reduced. The thickness of the first electrode layer 422 may be 15 nm or less and the transmittance of the first electrode layer 422 may be further improved. Here, the first electrode layer 422 may have a thickness of 2 nm to 50 nm (for example, 2 nm to 15 nm). When the thickness of the first electrode layer 422 is less than 2 nm, it may be difficult for the first electrode layer 422 to be uniformly formed on the conductive regions 32 and 34 and the effect of improving the adhesion property by the first electrode layer 422 is sufficient I can not. However, the present invention is not limited thereto, and the thickness of the first electrode layer 422 may vary depending on materials, process conditions, and the like.

In this embodiment, the first electrode layer 422 may be made of a pure titanium film, a tungsten film, or a molybdenum film (all but the unavoidable impurities are titanium, tungsten, or molybdenum) stacked by sputtering. Accordingly, the first electrode layer 422 may contain 99.9 wt% or more (more specifically, 99.99 wt% or more) of titanium, tungsten, or molybdenum. However, the present invention is not limited thereto, and the content of the metal material in the first electrode layer 422 may vary depending on the manufacturing method of the first electrode layer 422, process conditions, and the like.

The second electrode layer 424 positioned (e.g., in contact with) the first electrode layer 422 has a low resistance and may function to reflect light. As described above, the second electrode layer 424 may include copper, aluminum, silver, gold, and the like. In particular, the second electrode layer 424 includes aluminum to improve the reflection characteristic.

The third electrode layer 426 positioned (e.g., in contact with) the second electrode layer 424 may serve as a barrier to prevent the metal material of the second electrode layer 424 from diffusing into the fourth electrode layer 428 . The resistance of the metal material of the second electrode layer 424 may be increased by the alloy formed by reacting with the metal material of the fourth electrode layer 428. This can be prevented by the third electrode layer 426. [ The third electrode layer 426 may have the same material as the first electrode layer 424 (i.e., a refractory metal, e.g., titanium, molybdenum, or tungsten).

The fourth electrode layer 428 located on (or in contact with) the third electrode layer 426 is connected to another solar cell 100 or a ribbon for connection to the outside, . ≪ / RTI >

The fourth electrode layer 428 may comprise tin (Sn) or a nickel-vanadium alloy (NiV). The tin has the advantage of excellent bonding properties with ribbons or pastes for connection thereto. The nickel-vanadium alloy is excellent in bonding properties to a ribbon or a paste for connection thereto. More specifically, in the case of a paste containing tin and bismuth, the bonding properties of the tin of the paste and the nickel of the nickel-vanadium alloy are excellent. The nickel-vanadium alloy has a melting point higher than that of the first to third electrode layers 422, 424, and 426 because the melting point thereof is a very high level of about 1000 ° C or more. As a result, the capping layer can be sufficiently performed to protect the first to third electrode layers 422, 424, and 426 without being deformed during the bonding process with the ribbon or the manufacturing process of the solar cell 100. However, the present invention is not limited thereto, and the fourth electrode layer 428 may be formed of various conductive materials (e.g., various metals).

At this time, the second to fourth electrode layers 424, 426, and 428 may be formed of a metal film made of pure metal (unnecessary impurities in addition to the remaining metal) stacked by sputtering. Accordingly, the second to fourth electrode layers 424, 426, and 428 may contain the above-described metal in an amount of 99.9 wt% or more (more specifically, 99.99 wt% or more). However, the present invention is not limited thereto, and the content of the electrode material (or metal material) in the second to fourth electrode layers 424, 426, and 428 may be appropriately selected depending on the manufacturing method of the second to fourth electrode layers 424, 426, Process conditions and the like.

The second electrode layer 424 may have a greater thickness than the first electrode layer 422, the diffusion barrier layer 428 and / or the fourth electrode layer 428, and may have a thickness of, for example, 50 nm to 400 nm. For example, the thickness of the second electrode layer 424 may be 100 nm to 400 nm (more specifically, 100 nm to 300 nm). When the thickness of the second electrode layer 424 is less than 50 nm, it may be difficult to perform the role of the barrier layer and the reflective electrode layer. If the thickness of the second electrode layer 424 exceeds 400 nm, the fabrication cost may increase while the reflection characteristics and the like are not greatly improved. If the thickness of the second electrode layer 424 is 100 nm or more, the resistance can be further reduced. If the thickness of the second electrode layer 424 is 300 nm or less, the resistance can be kept low and the peeling phenomenon due to the increase in thermal stress can be effectively prevented. However, the present invention is not limited thereto, and the thickness of the second electrode layer 424 may be varied.

The third electrode layer 426 may have a thickness smaller than that of each of the second electrode layer 424 and the fourth electrode layer 428. For example, the thickness of the third electrode layer 426 may be 50 nm or less. If the thickness of the third electrode layer 426 exceeds 50 nm, the resistance may increase relatively. Here, the thickness of the third electrode layer 426 may be 5 nm to 50 nm. When the thickness of the third electrode layer 426 is less than 5 nm, the third electrode layer 426 is not uniformly formed between the second electrode layer 424 and the fourth electrode layer 428 and the effect of preventing the reaction between them is not sufficient . However, the present invention is not limited thereto, and the thickness of the third electrode layer 426 may vary depending on materials, process conditions, and the like.

Alternatively, the third electrode layer 426 may have the same or similar thickness as the first electrode layer 422, or may have a thickness greater than that of the first electrode layer 422. This is because the first electrode layer 424 must have translucency for reflection, but the third electrode layer 426 does not need to have translucency. However, the present invention is not limited to this, and the thickness of the third electrode layer 426 may be smaller than that of the first electrode layer 422.

The fourth electrode layer 428 may have a nano-level thickness, for example, a thickness of 50 nm to 300 nm. If the thickness of the fourth electrode layer 428 is less than 50 nm, the bonding property with the ribbon may be deteriorated, and if it exceeds 300 nm, the manufacturing cost may increase. However, the present invention is not limited thereto, and the thickness and the like of the fourth electrode layer 428 may be variously changed.

In this embodiment, the first electrode layer 422, the second electrode layer 424, the third electrode layer 426, and the fourth electrode layer 428 may be in contact with each other. Then, the lamination structure of the electrodes 42, 44 can be simplified while improving the characteristics of the electrodes 42, 44. For example, in the present embodiment, the electrodes 42 and 44 may have a four-layer laminated structure including the first to fourth electrode layers 422, 424, 426, and 428. According to this, the laminated structure of the electrodes 42 and 44 can be simplified as much as possible. However, the present invention is not limited thereto, and the electrodes 42 and 44 may have a separate layer between or on the first to fourth electrode layers 422, 424, 426 and 428. Also, it may not include at least one electrode layer among the first to fourth electrode layers 422, 424, 426, and 428.

In this embodiment, a plurality of electrode material layers including the first to fourth electrode layers 422, 424, 426 and 428 may be formed by sputtering or the like, and then the electrodes 42 and 44 may be formed by patterning the electrode material layers. More specifically, the electrode material layers corresponding to the first to fourth electrode layers 422, 424, 426 and 428 are formed in order so as to fill the contact holes 46 of the rear passivation film 40 on the insulating film 41 After that, the electrodes 42 and 44 can be formed by patterning them.

According to the above-described sputtering, since the material is stacked in the thickness direction of the solar cell 100, the first electrode layer 422 has a uniform thickness over the entire portion, and the second electrode layer 424 has a uniform thickness over the entire portion The third electrode layer 426 has a uniform thickness throughout and the fourth electrode layer 428 has a uniform thickness over the entire portion. Here, the uniform thickness may mean a thickness (for example, a thickness having a difference of 10% or less) that can be judged to be uniform in consideration of process errors and the like.

The electrodes 42 and 42 may be formed to have a width larger than the width of the contact hole 46. [ This is to sufficiently secure the widths of the first and second electrodes 42 and 44 (the widest width of the portions constituting the electrodes 42 and 44) to reduce the resistance of the electrodes 42 and 44 . Accordingly, the electrodes 42 and 44 (particularly, the first electrode layer 422) are formed on the insulating film 41 located inside (bottom and side) of the contact hole 46 and on the rear passivation film 42 adjacent to the contact hole 46. [ And over the insulating film 41 located above the insulating film 40.

Thus, in this embodiment, the electrodes 42 and 44 can be formed without using a plating process. If a part of the electrodes 42 and 44 is formed by plating, if there is a defect such as a pin hole or a scratch on the rear passivation film 40 or the insulating film 41, the plating is also performed in that part, . Since the plating solution used in the plating process is acidic or alkaline, it may damage the rear passivation film 40 or the insulating film 41 or deteriorate the characteristics of the rear passivation film 40 or the insulating film 41. In this embodiment, the characteristics of the rear passivation film 40 or the insulating film 41 can be improved by not using the plating process, and the electrodes 42 and 44 can be formed by a simple process. However, the present invention is not limited thereto, and the first to fourth electrode layers 422, 424, 426 and 428 may be formed by various methods and may be patterned by various methods.

1 and 2, the first conductive type region 32 and the second conductive type region 34, the barrier region 36, and the planar shape of the first and second electrodes 42 and 44 Will be described in detail.

1 and 2, in the present embodiment, the first conductive type region 32 and the second conductive type region 34 are formed to be long in a stripe shape, and alternate with each other in the direction crossing the longitudinal direction Respectively. Barrier regions 36 may be located between the first conductivity type region 32 and the second conductivity type region 34 to isolate them. Although not shown, a plurality of first conductive regions 32 spaced apart from each other may be connected to each other at one edge, and a plurality of second conductive regions 34 separated from each other may be connected to each other at the other edge. However, the present invention is not limited thereto.

At this time, the area of the first conductivity type region 32 may be larger than the area of the second conductivity type region 34. In one example, the areas of the first conductivity type region 32 and the second conductivity type region 34 can be adjusted by varying their widths. That is, the width W1 of the first conductivity type region 32 may be greater than the width W2 of the second conductivity type region 34. [

The first electrode 42 may be formed in a stripe shape corresponding to the first conductivity type region 32 and the second electrode 44 may be formed in a stripe shape corresponding to the second conductivity type region 34 . The contact hole 46 may be formed to connect only a part of the first and second electrodes 42 and 44 to the first conductive type region 32 and the second conductive type region 34, respectively. For example, the contact hole 46 may be formed of a plurality of contact holes. Alternatively, a contact hole (reference numeral 46 in FIG. 1, hereinafter the same) may be formed in the entire length of the first and second electrodes 42 and 44 corresponding to the first and second electrodes 42 and 44 . The contact area between the first and second electrodes 42 and 44 and the first conductivity type region 32 and the second conductivity type region 34 can be maximized to improve the carrier collection efficiency. Various other variations are possible. Although not shown in the figure, the first electrodes 42 may be connected to each other at one edge, and the second electrodes 44 may be connected to each other at the other edge. However, the present invention is not limited thereto.

When light is incident on the solar cell 100 according to the present embodiment, electrons and holes are generated by the photoelectric conversion at the pn junction formed between the base region 110 and the first conductivity type region 32, And electrons tunnel to the tunneling layer 20 to move to the first and second electrodes 42 and 44 after moving to the first conductivity type region 32 and the second conductivity type region 34, respectively. Thereby generating electrical energy.

In the solar cell 100 having the rear electrode structure in which the electrodes 42 and 44 are formed on the rear surface of the semiconductor substrate 10 and electrodes are not formed on the front surface of the semiconductor substrate 10 as in the present embodiment, The shading loss can be minimized at the front of the display device. Thus, the efficiency of the solar cell 100 can be improved. However, the present invention is not limited thereto.

Since the first and second conductive regions 32 and 34 are formed on the semiconductor substrate 10 with the tunneling layer 20 interposed therebetween, the first and second conductive type regions 32 and 34 are formed of different layers from the semiconductor substrate 10. As a result, the loss due to the recombination can be minimized as compared with the case where the doped region formed by doping the semiconductor substrate 10 with the dopant is used as the conductive type region.

The insulating film 41 located between the conductive type regions 32 and 34 and the electrodes 42 and 44 includes the refractory metal oxide to increase the degree of reflectance for the long wavelength light and to increase the interface contact resistance of the electrodes 42 and 44 Can be lowered. The insulating film 41 may be positioned in the contact hole 46 of the rear passivation film 40 to improve the passivation property inside the contact hole 46 and to protect the conductive type regions 32 and 34. Thus, the efficiency of the solar cell 100 can be improved.

A manufacturing method of the solar cell 100 having the above-described structure will be described in detail with reference to Figs. 5A to 5I. 5A to 5I are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

First, as shown in FIG. 5A, a semiconductor substrate 10 composed of a base region 110 having a second conductivity type dopant is prepared.

Next, as shown in FIG. 5B, a tunneling layer 20 is formed on the rear surface of the semiconductor substrate 10. Then, as shown in FIG. The tunneling layer 20 may be formed entirely on the rear surface of the semiconductor substrate 10. Here, the tunneling layer 20 can be formed, for example, by a thermal growth method, a deposition method (for example, chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like). However, the present invention is not limited thereto, and the tunneling layer 20 may be formed by various methods.

5C to 5E, a first conductive type region 32, a second conductive type region 34, and a front electric field region 130 are formed on the tunneling layer 20. A texturing structure may be formed on the entire surface of the semiconductor substrate 10. This will be described in more detail as follows.

As shown in FIG. 5C, the semiconductor layer 30 is formed on the tunneling layer 20. The semiconductor layer 30 may be composed of a microcrystalline, amorphous, or polycrystalline semiconductor. The semiconductor layer 30 can be formed, for example, by a thermal growth method, a vapor deposition method (e.g., low pressure chemical vapor deposition (LPCVD)), or the like. However, the present invention is not limited thereto, and the semiconductor layer 30 may be formed by various methods.

Then, as shown in FIG. 5D, the entire surface of the semiconductor substrate 10 may be textured to have irregularities. Wet or dry texturing may be used for texturing the surface of the semiconductor substrate 10. [ The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be formed uniformly, but the processing time is long and damage to the semiconductor substrate 10 may occur. Alternatively, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

In this embodiment, the front surface of the semiconductor substrate 10 is textured after the semiconductor layer 30 is formed. However, the present invention is not limited thereto. Therefore, the surface of the semiconductor substrate 10 can be textured before or after the semiconductor layer 30 is formed.

5E, a first conductive type region 32, a second conductive type region 34, and a barrier region 36 are formed in the semiconductor layer 30. Then, as shown in Fig. For example, the first conductive type dopant is doped into the region corresponding to the first conductive type region 32 by various methods such as ion implantation method, thermal diffusion method, laser doping method, and the like, The second conductivity type dopant can be doped to the corresponding region by various methods such as ion implantation, thermal diffusion, laser doping, and the like. Then, a region located between the first conductivity type region 32 and the second conductivity type region 34 constitutes the barrier region 36.

However, the present invention is not limited thereto, and various methods known as methods of forming the conductive regions 32 and 34 and the barrier region 36 can be used. And the barrier region 36 is not formed.

The entire surface area of the semiconductor substrate 10 may be doped with a second conductive dopant. The front electric field region 130 may be formed by various methods such as ion implantation, thermal diffusion, laser doping, or the like. Various other methods can be used. Alternatively, when the second conductive type dopant is doped to form the second conductive type region 34, the front conductive type region 130 may be formed by doping a second conductive type dopant together with the entire surface of the semiconductor substrate 10 have. Various other variations are possible.

5F, a front passivation film 24 and an antireflection film 26 are sequentially formed on the entire surface of the semiconductor substrate 10, and a rear passivation film 40 is formed on the rear surface of the semiconductor substrate 10 . The passivation film 24, the antireflection film 26 or the rear passivation film 40 may be formed by various methods such as a chemical vapor deposition method, a vacuum deposition method, a spin coating method, a screen printing method or a spray coating method. In particular, the front passivation film 24, the antireflection film 26 or the rear passivation film 40 may be formed by chemical vapor deposition.

Next, as shown in Fig. 5G, a contact hole 46 is formed in the rear passivation film 40. Then, as shown in Fig. The contact hole 46 may be formed by various methods such as laser etching, wet etching, and the like.

5H, the conductive passivation film 40 is exposed on the conductive regions 32 and 34 exposed by the contact holes 46, on the side surface of the rear passivation film 40, and on the outer surface or the rear surface of the rear passivation film 40. Next, as shown in FIG. The insulating film 41 is formed entirely on the surface (lower surface of the drawing). As described above, the insulating film 41 may be formed by atomic layer deposition. Since the atomic layer deposition method has already been described, a detailed description thereof will be omitted.

In the figure, the insulating film 41 is formed after the front passivation film 24 and the antireflection film 26 are formed. However, at least one of the front passivation film 24 and the antireflection film 26 may be formed after the insulating film 41 is formed. Various other variations are possible.

Next, as shown in FIG. 5I, first and second electrodes 42 and 44 are formed so as to fill the inside of the contact hole 46 on the insulating film 41. Next, as shown in FIG.

The first and second electrodes 42 and 44 may be formed by sequentially forming a plurality of electrode material layers on the insulating layer 41 in order by patterning the insulating layer 41 by sputtering or plating. As the patterning method, an etching solution, an etching paste, a dry etching, or the like can be used. Alternatively, the first and second electrodes 42 and 44 may be formed on the insulating film 41 while filling the contact hole 46 with a desired pattern. In the figure, the insulating film 41 is located entirely on the rear side of the semiconductor substrate 10. However, when the first and second electrodes 42 and 44 are patterned, the insulating film 41 may be patterned together to have a shape as shown in FIG.

In this embodiment, the insulating film 41 including the refractory metal oxide may be formed by atomic layer deposition to increase the film density of the insulating film 41. As a result, it is possible to maximize the effect of improving the reflectivity and the interface characteristics of the insulating film 41. Since the insulating film 41 is located on the contact holes 46 when the electrodes 42 and 44 or the electrode material layer are formed, the conductive regions 32 and 34 are not exposed to the outside. Therefore, it is possible to prevent the conductive type regions 32 and 34 from being damaged in the process of forming the first and second electrodes 42 and 44. Thus, the solar cell 100 having excellent characteristics and efficiency can be manufactured.

The rear electrode type solar cell in which the first and second electrodes 42 and 44 are all located on the rear surface of the semiconductor substrate 10 has been described. However, the present invention is not limited thereto. It is sufficient that at least one of the first and second electrodes 42 and 44 is located on the rear surface of the semiconductor substrate 10 and the electrodes 42 and 44 located on the rear surface of the semiconductor substrate 10 and the conductive regions 32, The insulating film 41 may be located between the insulating films 41 and 42 as described above.

Hereinafter, a solar cell according to another embodiment of the present invention and a method of manufacturing the same will be described in detail. Detailed descriptions will be omitted for the same or extremely similar parts as those described above, and only different parts will be described in detail. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

6 is a partial rear plan view of a solar cell according to another embodiment of the present invention. In FIG. 6, the rear passivation film (reference numeral 40 in FIG. 1) and the insulating film 41 are omitted, and the first and second conductivity type regions 32 and 34, the barrier region 36, The electrodes 42 and 44 are mainly shown. The rear passivation film 40 and the insulating film 41 are formed on the first and second conductivity type regions 32 and 34 and the barrier region 36 and the first and second electrodes 32 and 34. However, (42, 44). In the portion of the back passivation film 40 where the first conductivity type region 32 overlaps with the first electrode 42, a contact hole (reference numeral 46 in FIG. 1) for connecting to the first conductivity type region 32, And a contact hole 46 for connecting to the second conductive type region 34 may be formed at a portion where the second conductive type region 34 and the second electrode 44 overlap.

Referring to FIG. 6, in the solar cell 100 according to the present embodiment, the second conductivity type regions 34 are arranged in island form and are spaced apart from each other, 2 conductive type region 34 and the barrier region 36 surrounding the conductive type region 34

Then, the first conductive type region 32 functioning as the emitter region is formed with a maximally wide area, so that the photoelectric conversion efficiency can be improved. In addition, the second conductive type region 34 can be positioned entirely on the semiconductor substrate 10 while minimizing the area of the second conductive type region 34. The surface area of the second conductivity type region 34 can be maximized while effectively preventing the surface recombination by the second conductivity type region 34. However, the present invention is not limited thereto, and it goes without saying that the second conductivity type region 34 may have various shapes that minimize the area.

Although the second conductivity type region 34 has a circular shape in the drawing, the present invention is not limited thereto. Therefore, it is needless to say that the second conductivity type region 34 may have an elliptical shape or a polygonal planar shape such as a triangle, a square, or a hexagon.

Hereinafter, the present invention will be described in more detail with reference to the production examples of the present invention. However, the production example of the present invention to be described later is only provided for illustrative purposes, and the present invention is not limited thereto.

Manufacturing example  One

A tunneling layer composed of a silicon oxide film was formed on one surface of an n-type single crystal semiconductor substrate. A semiconductor layer containing polycrystalline silicon was formed on the tunneling layer by low pressure chemical vapor deposition. A semiconductor layer having a first conductivity type region and a second conductivity type region is formed by doping a p-type dopant in a portion of the semiconductor layer and doping an n-type dopant in another region. Then, a rear passivation film composed of a silicon nitride film and a silicon carbide film was formed, contact holes were formed, and an insulating film composed of a titanium oxide film having an anatase phase was formed in the contact holes and the rear passivation film. A first electrode and a second electrode electrically connected to the first conductive type region and the second conductive type region are formed on the insulating film through the contact hole. The first and second electrodes were formed by sequentially laminating a titanium film, an aluminum film, a titanium film, and a nickel-vanadium alloy film.

Manufacturing example  2

A solar cell was manufactured in the same manner as in the solar cell of Production Example 1 except that the insulating film was made of titanium oxide having a rutile phase.

Comparative Example  One

A solar cell was manufactured in the same manner as the solar cell except that the insulating film was not formed and the first and second electrodes were formed in contact with the first and second conductivity type regions.

Comparative Example  2

The solar cell was manufactured in the same manner as the solar cell except that the insulating film was made of a silicon oxide film.

The reflectance of the back surface of the solar cell in the solar cells according to Production Examples 1 and 2 and Comparative Examples 1 and 2 was measured and the results are shown in FIG. The results of measurement of the contact resistance of the electrodes of the solar cell according to Production Example 1 and Comparative Examples 1 and 2 are shown in FIG.

Referring to FIG. 7, it can be seen that the reflectance for long wavelength light is high in Comparative Examples 1 and 2 in Production Examples 1 and 2. In Production Example 1 having a titanium oxide film having an anatase phase as an insulating film, it was found that the reflectivity of the titanium oxide film having a rutile phase as an insulating film was higher than that of long wavelength light in Production Example 2 have. It can be seen that Comparative Example 1, which does not include an insulating film, and Comparative Example 2, which uses a silicon oxide film as an insulating film, have almost similar reflectivities. From this, it can be seen that the use of the silicon oxide film as the insulating film has no effect of improving the reflectivity.

Referring to FIG. 8, it can be seen that the contact resistance is significantly lowered in Production Example 1 than in Comparative Example 2 including a silicon oxide film as an insulating film. In addition, the contact resistance in Production Example 1 is lower than that in Comparative Example 1 which does not include an insulating film, and according to Production Example 1, it is possible to effectively reduce the interface contact resistance due to the insulating film containing refractory metal oxide.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
20: Tunneling layer
24: front passivation film
26: Antireflection film
30: semiconductor layer
32: first conductivity type region
34: second conductivity type region
36: Barrier area
40: rear passivation film
41: Insulating film
42: first electrode
44: Second electrode

Claims (20)

A semiconductor substrate;
A conductive type region located on the semiconductor substrate;
An electrode electrically connected to the conductive region;
A passivation film having a contact hole on the conductive type region; And
And an insulating film located between the conductive type region and the electrode
/ RTI >
Wherein the insulating film comprises titanium oxide or molybdenum oxide having an anatase phase,
The film density of the insulating film is larger than the film density of the passivation film,
The refractive index of the insulating film is larger than the refractive index of the passivation film
Solar cells. delete delete The method according to claim 1,
Wherein the thickness of the insulating film is equal to or less than the thickness of the tunneling layer. The method according to claim 1,
Wherein the insulating film has a thickness of 1 nm or less. The method according to claim 1,
Wherein the insulating film has a layered structure having a plurality of atomic layers. The method according to claim 6,
Wherein the plurality of atomic layers of the insulating film is 10 or less. The method according to claim 1,
Wherein the insulating film contains titanium oxide,
The film density of the insulating film is 3.8 g / cm 3 to 4.2 g / cm 3,
And the refractive index of the insulating film is 2.5 to 2.8. The method according to claim 1,
Wherein the insulating film includes a portion located between the electrode and the conductive type region in the contact hole,
Wherein the passivation film is made of a material different from the insulating film. 10. The method of claim 9,
Wherein the passivation film comprises at least one of a silicon oxide film, a silicon nitride film, and a silicon carbide film. delete 10. The method of claim 9,
Wherein the insulating film is entirely formed on the conductive type region and the passivation film, or is partially formed corresponding to the electrode. The method according to claim 1,
Further comprising a tunneling layer positioned between the conductive region and the semiconductor substrate,
Wherein the conductive region includes a first conductive type region having a first conductivity type and a second conductive type region having a second conductive type,
The first conductive type region and the second conductive type region are located together on the tunneling layer,
Wherein the electrode comprises a first electrode electrically connected to the first conductive type region and a second electrode electrically connected to the second conductive type region,
Wherein the insulating film is located between the first conductive type region and the first electrode and between the second conductive type region and the second electrode. The method according to claim 1,
Wherein the electrode has an electrode layer contacting the insulating film,
Wherein the electrode layer comprises a refractory metal. 15. The method of claim 14,
Wherein the electrode layer comprises the same refractory metal as the refractory metal contained in the insulating film. 16. The method of claim 15,
Wherein the insulating layer comprises titanium oxide and the electrode layer comprises titanium. Forming a conductive type region on a semiconductor substrate;
Forming an insulating film on the conductive region;
Forming a passivation film having a contact hole on the conductive type region; And
Forming an electrode electrically connected to the conductive region on the insulating film;
Lt; / RTI >
Wherein the insulating film comprises titanium oxide or molybdenum oxide having an anatase phase,
The film density of the insulating film is larger than the film density of the passivation film,
The refractive index of the insulating film is larger than the refractive index of the passivation film,
Wherein the insulating layer is formed by an atomic layer deposition method. delete 18. The method of claim 17,
Wherein the passivation film is made of a material different from that of the insulating film and is formed by a method different from that of the insulating film. 20. The method of claim 19,
Wherein the passivation film is formed by a chemical vapor deposition method.

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