Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.
In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.
Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.
Hereinafter, a solar cell according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention, and FIG. 2 is a partial rear plan view of the solar cell shown in FIG. 1. FIG.
1 and 2, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10, first and second conductive regions 32 and 34 located on one surface of the semiconductor substrate 10, And first and second electrodes 42 and 44 connected to the first and second conductivity type regions 32 and 34, respectively. At this time, at least one of the first and second electrodes 42 and 44 includes an electrode layer 424 having conductivity and located on the first or second conductivity type regions 32 and 34, Type regions 32 and 34 and the electrode layer 424. The diffusion barrier layer 428 is formed on the diffusion barrier layer 428, The diffusion barrier layer 428 includes a first material that is the same as the semiconductor material of the first or second conductivity type regions 32 and 34 and a second material that is conductive. The solar cell 100 may further include a tunneling layer 20 positioned between the semiconductor substrate 10 and the first and second conductivity type regions 32 and 34. In addition, the solar cell 100 may further include a passivation film 24, an antireflection film 26, an insulating layer 40, and the like. This will be explained in more detail.
The semiconductor substrate 10 may include a base region 110 having a second conductivity type including a second conductivity type dopant at a relatively low doping concentration. The base region 110 may be formed of a crystalline semiconductor including a second conductive dopant. In one example, the base region 110 may be composed of a single crystal or a polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon) including a second conductive type dopant. In particular, the base region 110 may be comprised of a single crystal semiconductor (e.g., a single crystal semiconductor wafer, more specifically a semiconductor silicon wafer) comprising a second conductive dopant. Thus, when the base region 110 is made of monocrystalline silicon, the solar cell 100 constitutes a single crystal silicon solar cell. Since the solar cell 100 having a single crystal semiconductor has high crystallinity and is based on the base region 110 or the semiconductor substrate 10 having few defects, the electrical characteristics are excellent.
The second conductivity type may be p-type or n-type. For example, if the base region 110 has an n-type, a p-type (e.g., p-type) layer which forms a junction with the base region 110 by photoelectric conversion The first conductivity type region 32 can be formed wide to increase the photoelectric conversion area. In this case, the first conductivity type region 32 having a large area can effectively collect holes having a relatively low moving speed, thereby contributing to the improvement of photoelectric conversion efficiency. However, the present invention is not limited thereto.
The semiconductor substrate 10 may include a front electric field area 130 located on the front side. The front field region 130 may have a doping concentration higher than that of the base region 110 while having the same conductivity type as that of the base region 110. [
In this embodiment, the front electric field region 130 is formed in the semiconductor substrate 10 as a doped region formed by doping the second conductive type dopant with a relatively high doping concentration. Accordingly, the front electric field area 130 includes a crystalline (single crystal or polycrystalline) semiconductor having a second conductivity type to constitute a part of the semiconductor substrate 10. For example, the front electric field area 130 can form a part of a single crystal semiconductor substrate having a second conductivity type (for example, a single crystal silicon wafer substrate). However, the present invention is not limited thereto. Therefore, it is also possible to form the front electric field area 130 by doping a second conductive type dopant to a semiconductor layer other than the semiconductor substrate 10 (for example, an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer) have. Or the front electric field area 130 is similar to that doped by the fixed electric charge of the layer (for example, the passivation film 24 and / or the antireflection film 26) formed adjacent to the semiconductor substrate 10 Or an electric field area. For example, when the base region 110 is n-type, the passivation film 24 may be formed of an oxide (for example, aluminum oxide) having a fixed negative charge to form an inversion layer on the surface of the base region 110. [ So that it can be used as an electric field area. In this case, the semiconductor substrate 10 does not have a separate doping region but consists only of the base region 110, thereby minimizing defects in the semiconductor substrate 10. [ The front electric field area 130 having various structures can be formed by various other methods.
In the present embodiment, the front surface of the semiconductor substrate 10 may be textured to have irregularities such as pyramids. If the surface roughness of the semiconductor substrate 10 is increased by forming concavities and convexities on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced. Accordingly, the amount of light reaching the pn junction formed by the base region 110 and the first conductivity type region 32 can be increased, and the light loss can be minimized.
The rear surface of the semiconductor substrate 10 may be made of a relatively smooth and flat surface having a surface roughness lower than that of the front surface by mirror polishing or the like. When the first and second conductivity type regions 32 and 34 are formed together on the rear side of the semiconductor substrate 10 as in the present embodiment, the characteristics of the solar cell 100 This can vary greatly. As a result, unevenness due to texturing is not formed on the rear surface of the semiconductor substrate 10, so that passivation characteristics can be improved and the characteristics of the solar cell 100 can be improved. However, the present invention is not limited thereto, and it is also possible to form concavities and convexities by texturing on the rear surface of the semiconductor substrate 10 according to circumstances. Various other variations are possible.
A tunneling layer 20 may be formed on the rear surface of the semiconductor substrate 10. The tunneling layer 20 acts as a kind of barrier to electrons and holes to prevent the minority carriers from passing therethrough and to prevent the majority carriers from being accumulated in the portion adjacent to the tunneling layer 20, so that only the majority carriers can pass through the tunneling layer 20. At this time, a plurality of carriers having energy above a certain level can easily pass through the tunneling layer 20 by the tunneling effect. The tunneling layer 20 may also serve as a barrier to prevent the dopants of the first and second conductivity type regions 32 and 34 from diffusing into the semiconductor substrate 10.
The tunneling layer 20 may include various materials through which the carrier can be tunneled. For example, the tunneling layer 20 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like. For example, the tunneling layer 20 may comprise silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and the like. At this time, the tunneling layer 20 may be formed entirely on the rear surface of the semiconductor substrate 10. Accordingly, the interface characteristics of the rear surface of the semiconductor substrate 10 can be improved as a whole, and can be easily formed without additional patterning.
On the tunneling layer 20, first and second conductive regions 32 and 34 positioned on the same plane may be located. More specifically, in this embodiment, the first and second conductivity type regions 32 and 24 include a first conductivity type region 32 having a first conductivity type dopant and exhibiting a first conductivity type, And a second conductivity type region 34 having a second conductivity type and exhibiting a second conductivity type. And the barrier region 36 may be located between the first conductivity type region 32 and the second conductivity type region 34.
The first conductive type region 32 forms a pn junction (or a pn tunnel junction) between the base region 110 and the tunneling layer 20 to form an emitter region for generating carriers by photoelectric conversion.
At this time, the first conductive type region 32 may include a semiconductor (for example, silicon) including a first conductive type dopant opposite to the base region 110. The first conductive type region 32 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the tunneling layer 20) and the first conductive type dopant is doped As shown in Fig. Accordingly, the first conductive type region 32 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the first conductive type region 32 can be easily formed on the semiconductor substrate 10. For example, the first conductivity type region 32 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the first conductive type dopant. The first conductive dopant may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a heat diffusion method and an ion implantation method after forming the semiconductor layer.
At this time, the first conductive type dopant may be a dopant that can exhibit a conductive type opposite to that of the base region 110. That is, when the first conductivity type dopant is a p-type, a Group 3 element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. When the first conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used.
The second conductivity type region 34 forms a back surface field to prevent carriers from being lost by recombination on the surface of the semiconductor substrate 10 (more precisely, the back surface of the semiconductor substrate 10) Thereby constituting a rear electric field area.
At this time, the second conductive type region 34 may include a semiconductor (e.g., silicon) including the same second conductive type dopant as the base region 110. In this embodiment, the second conductivity type region 34 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically on the tunneling layer 20) and the second conductivity type dopant is doped As shown in Fig. Accordingly, the second conductive type region 34 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the second conductive type region 34 can be easily formed on the semiconductor substrate 10. For example, the second conductivity type region 34 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the second conductive type dopant. The second conductive dopant may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a thermal diffusion method and an ion implantation method after forming the semiconductor layer.
At this time, the second conductive dopant may be a dopant capable of exhibiting the same conductivity type as that of the base region 110. That is, when the second conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used. When the second conductivity type dopant is p-type, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used.
A barrier region 36 is positioned between the first conductive type region 32 and the second conductive type region 34 to separate the first conductive type region 32 and the second conductive type region 34 from each other. When the first conductive type region 32 and the second conductive type region 34 are in contact with each other, a shunt may be generated to deteriorate the performance of the solar cell 100. Accordingly, in this embodiment, unnecessary shunt can be prevented by positioning the barrier region 36 between the first conductive type region 32 and the second conductive type region 34.
The barrier region 36 may comprise a variety of materials that can substantially insulate them between the first conductive type region 32 and the second conductive type region 34. That is, an undoped (i.e., unshown) insulating material (e.g., oxide, nitride) or the like may be used for the barrier region 36. Alternatively, the barrier region 36 may comprise an intrinsic semiconductor. At this time, the first conductive type region 32, the second conductive type region 34, and the barrier region 36 are formed of the same semiconductor (for example, amorphous silicon, microcrystalline silicon, ), While the barrier region 36 may be substantially free of dopants. For example, a semiconductor layer containing a semiconductor material may be formed, and then a first conductive type dopant may be doped in a part of the semiconductor layer to form a first conductive type region 32, and a second conductive type dopant A region where the first conductivity type region 32 and the second conductivity type region 34 are not formed may constitute the barrier region 36. In this case, This makes it possible to simplify the manufacturing method of the first conductivity type region 32, the second conductivity type region 34, and the barrier region 36.
However, the present invention is not limited thereto. Therefore, when the barrier region 36 is formed separately from the first conductivity type region 32 and the second conductivity type region 34, the thickness of the barrier region 36 is different from that of the first conductivity type region 32 and the second conductivity type region 34, Conductivity type region 34. [0060] For example, the barrier region 36 may include a first conductive type region 32 and a second conductive type region 34 to more effectively prevent shorting of the first conductive type region 32 and the second conductive type region 34, Or may have a thickness greater than that of the substrate. Alternatively, the thickness of the barrier region 36 may be made smaller than the thickness of the first conductivity type region 32 and the second conductivity type region 34 in order to reduce the raw material for forming the barrier region 36. Of course, various modifications are possible. In addition, the basic constituent material of the barrier region 36 may include a material different from the first conductive type region 32 and the second conductive type region 34. Alternatively, the barrier region 36 may be comprised of an empty space (e.g., a trench) located between the first conductive type region 32 and the second conductive type region 34.
In this embodiment, the barrier region 36 is entirely spaced apart from the first conductivity type region 32 and the second conductivity type region 34. However, the present invention is not limited thereto. Therefore, the barrier region 36 may be formed to separate only a part of the boundary portions of the first conductive type region 32 and the second conductive type region 34. According to this, other portions of the boundaries of the first conductivity type region 32 and the second conductivity type region 34 may be in contact with each other. In addition, the barrier region 36 is not necessarily provided, and the first conductive type region 32 and the second conductive type region 34 may be formed in contact with each other as a whole. Various other variations are possible.
Here, the area of the first conductivity type region 32 having a conductivity type different from that of the base region 110 can be wider than the area of the second conductivity type region 34 having the same conductivity type as that of the base region 110 have. Accordingly, the pn junction formed through the tunneling layer 20 between the base region 110 and the first conductive type region 32 can be made wider. At this time, when the base region 110 and the second conductivity type region 34 have the n-type conductivity and the first conductivity type region 32 has the p-type conductivity, the first conductivity type region It is possible to effectively collect holes having a relatively slow moving speed by the electron beam 32. [ An example of the planar structure of the first conductive type region 32, the second conductive type region 34, and the barrier region 36 will be described later in more detail with reference to FIG.
The insulating layer 40 may be formed on the first and second conductive type regions 32 and 34 and the barrier region 36. [ The insulating layer 40 includes a first opening 402 for connecting the first conductivity type region 32 and the first electrode 42 and a second opening 42 for connecting the second conductive type region 34 and the second electrode 44 And a second opening 404 for the second opening. The insulating layer 40 is formed on the first conductive type region 32 and the second conductive type region 34 in the case of the electrode to which the second conductive type region 34 should not be connected And the first electrode 42 in the case of the second conductivity type region 34). In addition, the insulating layer 40 may have the effect of passivating the first and second conductivity type regions 32 and 34 and / or the barrier region 36.
The insulating layer 40 may be located on the semiconductor layer 30 at a portion not located at the electrodes 42 and 44. [ The insulating layer 40 may have a greater thickness than the tunneling layer 20 (more precisely, the tunneling layer 20), thereby improving isolation and passivation characteristics. no.
The insulating layer 40 may be made of various insulating materials (e.g., oxides, nitrides, etc.). For example, the insulating layer 40 may be formed of any one single layer selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, Al 2 O 3 , MgF 2 , ZnS, TiO 2, and CeO 2 Or may have a multilayered film structure in which two or more films are combined. However, the present invention is not limited thereto, and it goes without saying that the insulating layer 40 may include various materials.
Electrodes 42 and 44 located on the rear surface of the semiconductor substrate 10 include a first electrode 42 electrically and physically connected to the first conductivity type region 32 and a second electrode 42 electrically connected to the second conductivity type region 34 And a second electrode 44 electrically and physically connected.
The first electrode 42 is connected to the first conductive type region 32 through the first opening portion 402 of the insulating layer 40 and the second electrode 44 is connected to the first conductive type region 32 of the insulating layer 40. In this case, 2 opening 404 and is connected to the second conductivity type region 34. The first and second electrodes 42 and 44 may include various conductive materials (e.g., a metal material). The first and second electrodes 42 and 44 are connected to the first conductive type region 32 and the second conductive type region 34 without being electrically connected to each other, And can have a variety of planar shapes. That is, the present invention is not limited to the planar shapes of the first and second electrodes 42 and 44.
Hereinafter, the lamination structure of the first and / or second electrodes 42 and 44 will be described in detail with reference to the enlargement circle in FIG. 1, and then the first and / or second electrodes 42 and 44 will be described with reference to FIG. Will be described in detail. Although the first electrode 42 is shown enlarged in the enlargement circle of FIG. 1, the second electrode 44 may have the same lamination structure. The first or second conductivity type regions 32 and 34 are referred to as conductive regions 32 and 34 and the first or second electrode 42 connected thereto is referred to as electrodes 42 and 44 Explain.
1, the electrodes 42 and 44 are disposed between the electrode layer 424 located on the conductive type regions 32 and 34 and between the conductive type regions 32 and 34 and the electrode layer 424 The diffusion barrier layer 428 is formed on the diffusion barrier layer 428. The electrodes 42 and 44 are positioned between the conductive regions 32 and 34 and the diffusion barrier layer 428 and include an adhesive layer 422 having permeability and conductivity and an adhesive layer 422 disposed over the electrode layer 424, (Not shown). Here, the electrode layer 424 has a low resistance due to a relatively large thickness, and plays a fundamental role in collecting carriers generated by photoelectric conversion and transferring the carriers to the outside. The diffusion barrier layer 428 is formed on the surface of the electrode layer 424 while performing a barrier function to prevent diffusion of substances constituting these between the adhesive layer 422 (or the conductive regions 32 and 34) ) To perform the basic role of the electrode. The adhesive layer 422 serves to improve the adhesion characteristics between the conductive regions 32 and 34 and the electrode layer 424 and the capping layer 426 functions as a ribbon for connection with another solar cell 100 or the outside. (Or connecting member, tap, etc., hereinafter referred to as a ribbon).
The adhesive layer 422 may be formed between the conductive type regions 32 and 34 and the electrode layer 424 in contact with them. The adhesive layer 422 may include a metal that is conductive and has excellent contact properties with the conductive regions 32 and 34. This makes it possible to improve the adhesion characteristics between the conductive regions 32 and 34 and the electrode layer 424 without deteriorating the conductivity of the electrodes 42 and 44. The thermal expansion coefficient of the adhesive layer 422 is set to be between the thermal expansion coefficient of the conductive type regions 32 and 34 and the thermal expansion coefficient of the electrode layer 424 so as to improve the contact property between the adhesive layer 422 and the conductive type regions 32 and 34. [ Value. ≪ / RTI >
More specifically, when the thermal expansion coefficient difference between the conductive type regions 32 and 34 and the electrodes 42 and 44 is large, the conductive type regions 32 and 34 ) And the electrodes 42, 44 may be deteriorated. As a result, the contact resistance between the conductive type regions 32 and 34 and the electrodes 42 and 44 can be increased. This is achieved by reducing the line width of the conductive type regions 32 and 34 or the electrodes 42 and 44 to reduce the contact area between the conductive type regions 32 and 34 and the electrodes 42 and 44 Can be a bigger problem. Accordingly, in this embodiment, the coefficient of thermal expansion of the adhesive layer 422 contacting the semiconductor layer in the electrodes 42 and 44 is limited so that the difference in thermal expansion coefficient between the conductive regions 32 and 34 and the electrodes 42 and 44 To improve the interface contact characteristics.
(Cu), aluminum (Al), silver (Ag), and gold (Au), which have a thermal expansion coefficient of about 4.2 ppm / K and can form the electrode layer 424 when the conductive regions 32 and 34 include silicon (Au) has a thermal expansion coefficient of about 14.2 ppm / K or more. More specifically, the thermal expansion coefficient of copper is about 16.5 ppm / K, the thermal expansion coefficient of aluminum is about 23.0 ppm / K, the thermal expansion coefficient of silver is about 19.2 ppm / K, and the thermal expansion coefficient of gold is about 14.2 ppm / K .
Considering this, the thermal expansion coefficient of the material (e.g., metal) constituting the adhesive layer 422 may be about 4.5 ppm / K to about 14 ppm / K. If the coefficient of thermal expansion is less than 4.5 ppm / K or exceeds 14 ppm / K, the difference in thermal expansion coefficient between the conductive type regions 32 and 34 may be reduced and the effect of improving the adhesive property may not be sufficient. In consideration of this, the adhesive layer 422 may include titanium (Ti) having a thermal expansion coefficient of about 8.4 ppm / K or tungsten (W) having a thermal expansion coefficient of about 4.6 ppm / K, and may be made of titanium or tungsten .
When the adhesive layer 422 includes titanium or tungsten, the contact characteristics can be improved by reducing the coefficient of thermal expansion between the conductive regions 32 and 34 and the electrodes 42 and 44. And titanium or tungsten can function as a barrier for the material (e.g., copper) that make up the electrode layer 424 and reduce diffusion thereof into the conductive regions 32, 34 or the semiconductor substrate 10 have. Accordingly, problems that may occur due to diffusion of the material constituting the electrode layer 424 into the conductive regions 32 and 34 or the semiconductor substrate 10 can be reduced. However, the present invention is not limited thereto, and the adhesive layer 422 may be composed of various conductive materials (for example, various metals).
At this time, the adhesive layer 422 according to the present embodiment can have conductivity and transmittance through which light can be transmitted. The thickness T1 of the adhesive layer 422 may be limited to a certain level or less so that even if the adhesive layer 422 has a metal So as to have transparency. When the adhesive layer 422 has a transmittance, the light having passed through the adhesive layer 422 is reflected by the electrode layer 424 formed on the adhesive layer 422 and can be directed to the inside of the semiconductor substrate 10 again. Accordingly, the efficiency and the efficiency of the solar cell 100 can be improved by increasing the amount of light existing in the semiconductor substrate 10 and the residence time.
Here, the term " permeability " includes not only a case of transmitting 100% of light but also a case of transmitting a part of light. That is, the adhesive layer 422 may be composed of a metal permeable membrane or a metal semipermeable membrane. For example, the adhesive layer 422 may have a transmittance of 50% to 100%, and more specifically, a transmittance of 80% to 100%. If the transmittance of the adhesive layer 422 is less than 50%, the amount of light reflected by the electrode layer 424 is not sufficient and it may be difficult to sufficiently improve the efficiency of the solar cell 100. If the transmittance of the adhesive layer 422 is 80% or more, the amount of light reflected by the electrode layer 424 can be further increased, thereby contributing to the improvement of the efficiency of the solar cell 100.
The thickness T1 of the adhesive layer 422 may be smaller than the thickness T2 of the diffusion barrier layer 428, the thickness T3 of the electrode layer 424 and the thickness T4 of the capping layer 426. [ Specifically, the thickness T1 of the adhesive layer 422 may be 50 nm or less. If the thickness T1 of the adhesive layer 422 exceeds 50 nm, the light transmittance of the adhesive layer 422 may decrease and the amount of light directed to the electrode layer 424 may be insufficient. The thickness T2 of the adhesive layer 422 may be 15 nm or less and the transmittance of the adhesive layer 422 may be further improved. Here, the thickness T1 of the adhesive layer 422 may be 2 nm to 50 nm (for example, 2 nm to 15 nm). When the thickness T1 of the adhesive layer 422 is less than 2 nm, it may be difficult to uniformly form on the conductive regions 32 and 34 of the adhesive layer 422 and the effect of improving the adhesive property by the adhesive layer 422 may be insufficient have. However, the present invention is not limited thereto, and the thickness T1 of the adhesive layer 422 may vary depending on materials, process conditions, and the like.
In this embodiment, the adhesive layer 422 may be made of pure titanium or tungsten (other than inevitable impurities, all of which are titanium or tungsten) stacked by sputtering. Accordingly, the adhesive layer 422 may contain 99.9 wt% or more (more specifically, 99.99 wt% or more) of titanium or tungsten. However, the present invention is not limited thereto, and the content of the metal material in the adhesive layer 422 may vary depending on the manufacturing method of the adhesive layer 422, process conditions, and the like.
The electrode layer 424 located on the adhesive layer 422 (more precisely on the diffusion barrier layer 428 located above the adhesive layer 422) has a low resistance and serves as a conducting layer that substantially transmits current do. And acts as a barrier to prevent the material of the capping layer 426 from being directed to the conductive regions 32, 34 or the semiconductor substrate 10, and to cause reflection by the reflective material. That is, the electrode layer 424 can perform both a role as a conductive layer, a role as a barrier layer, and a role as a reflective electrode layer. The electrode layer 424 may be made of a metal having excellent reflection characteristics and conductivity, and may include, for example, copper, aluminum, silver, gold, or an alloy thereof.
At this time, the electrode layer 424 may be formed of an electrode material composed of a pure metal (metal remaining after the inevitable impurities) stacked by sputtering. Accordingly, the electrode layer 424 may include 99.9 wt% or more (more specifically, 99.99 wt% or more) of electrode material (or metal material) such as copper, aluminum, silver, gold or an alloy thereof. However, the present invention is not limited thereto, and the content of the electrode material (or metal material) in the electrode layer 424 may vary depending on the manufacturing method of the electrode layer 424, process conditions, and the like.
The electrode layer 424 may have a greater thickness than the adhesive layer 422, the diffusion barrier layer 428 and / or the capping layer 426, and may, for example, have a thickness of 50 nm to 400 nm. For example, the thickness T3 of the electrode layer 424 may be 100 nm to 400 nm (more specifically, 100 nm to 300 nm). When the thickness T3 of the electrode layer 424 is less than 50 nm, it may be difficult to perform the role of the barrier layer and the reflective electrode layer. If the thickness T3 of the electrode layer 424 exceeds 400 nm, the fabrication cost may increase while the reflection characteristics and the like are not greatly improved. If the thickness T3 of the electrode layer 424 is 100 nm or more, the resistance can be further reduced. If the thickness T3 of the electrode layer 424 is 300 nm or less, the resistance can be kept low and the peeling phenomenon due to the increase in thermal stress can be effectively prevented. However, the present invention is not limited thereto, and the thickness T3 of the electrode layer 424 may be varied.
The diffusion barrier layer 428 located between the conductive type regions 32 and 34 and the electrode layer 424 (more precisely, between the adhesive layer 422 and the electrode layer 424 contacting the conductive type regions 32 and 34) Serves to prevent the semiconductor material constituting the conductive type regions 32 and 34 from diffusing into the electrode layer 424 or diffusing the electrode material of the electrode layer 424 into the conductive type regions 32 and 34.
More specifically, during the various manufacturing processes of the solar cell 100, various heat treatment processes are performed. For example, after the electrode material layer for forming the electrodes 42 and 44 is formed by physical vapor deposition (PVD) such as sputtering, the stress of the electrode material layer is reduced and the conductive type regions 32 and 34 The annealing process is performed to improve the contact characteristics with respect to the contact hole.
The semiconductor material of the conductive type regions 32 and 34 diffuses into the electrode layer 424 and the electrode material of the electrode layer 424 diffuses toward the conductive type regions 32 and 34 during the heat treatment process. For example, because the electrode material (especially aluminum) has a lower melting point than the semiconductor material, the electrode material located in the conductive regions 32, 34 by diffusion can easily be eluted, And 34 may have spikes in which small holes, holes, and the like are formed. For reference, FIG. 3 shows a photograph of a conductive type region where a spiking phenomenon occurs. If the sparking phenomenon occurs in the conductive type regions 32 and 34 as described above, defects are generated in the conductive type regions 32 and 34, so that the characteristics of the conductive type regions 32 and 34 may be greatly reduced.
Thus, in this embodiment, the diffusion barrier layer 428 is formed to prevent the problem caused by diffusion of the semiconductor material and the electrode material. At this time, since the diffusion barrier layer 428 is a layer constituting a part of the electrodes 42 and 44, the diffusion barrier layer 428 must be conductive so that the electrical characteristics of the electrodes 42 and 44 are not degraded.
The diffusion barrier layer 428 thus includes a first material that is the same as the semiconductor material of the conductive regions 32 and 34 so as to prevent diffusion of the semiconductor material of the conductive regions 32 and 34, Lt; / RTI >
If the diffusion barrier layer 428 includes the same first material as the semiconductor material, the concentration gradient of the semiconductor material can be reduced between the conductive regions 32 and 34 and the electrode layer 424, 34 to the electrode layer 424 can be prevented. Thus, it is possible to prevent the electrode material of the electrode layer 424 from diffusing into the conductive regions 32 and 34. That is, in order for the electrode material of the electrode layer 424 to diffuse into the conductive regions 32 and 34, the semiconductor material of the conductive regions 32 and 34 must diffuse into the electrode layer 424, The diffusion of the electrode material can be naturally prevented. As described above, the conductive regions 32 and 34 may comprise silicon as a semiconductor material, so that the diffusion barrier layer 428 may comprise silicon as the first material.
The second material for ensuring the conductivity of the diffusion barrier layer 428 may include various materials (especially metal materials). For example, the diffusion barrier layer 428 may comprise copper, aluminum, silver, gold, alloys, etc., as the second material. For example, if the diffusion barrier layer 428 includes aluminum as the second material, the light having reached the first and second electrodes 42 and 44 is reflected again, and the light is incident on the solar cell 100 Can be reused. Alternatively, if the diffusion barrier layer 428 comprises copper as the second material, the productivity can be improved due to the low cost. Alternatively, if the diffusion barrier layer 428 includes silver or gold as the second material, the electrical properties of the first and second electrodes 42, 44 can be improved by the excellent electrical conductivity.
In particular, the second material of the diffusion barrier layer 428 may be the same material as the electrode material contained in the electrode layer 424. That is, if the electrode layer 424 is made of aluminum, the second material of the diffusion barrier layer 428 may be aluminum and if the electrode layer 424 is made of copper, the second material of the diffusion barrier layer 428 may be copper have. If the electrode layer 424 is made of silver, the second material of the diffusion barrier layer 428 may be silver, and if the electrode layer 424 is made of gold, the second material of the diffusion barrier layer 428 may be gold. If the second material of the diffusion barrier layer 428 is the same as the electrode material included in the electrode layer 424, the problem caused by the difference in characteristics (for example, difference in thermal expansion coefficient) .
At this time, the content of the second material of the diffusion barrier layer 428 may be smaller than that of the electrode layer 424. This is because the electrode layer 424 is made of an electrode material and the diffusion barrier layer 428 includes the first material together with the same second material as the electrode material. The content of the first material and the second material in the diffusion barrier layer 428 will be described later in more detail.
The diffusion barrier layer 428 may be composed of a mixture of the first material and the second material chemically bonded to each other. For example, the diffusion barrier layer 428 may be composed of an alloy formed by bonding the first material and the second material to each other. This allows the diffusion barrier layer 428 to remain chemically stable. However, the present invention is not limited thereto, and it is also possible that the first material and the second material exist in a mixture state in the diffusion barrier layer 428 according to process conditions and the like.
If the diffusion barrier layer 428 is an aluminum-silicon alloy, a copper-silicon alloy, a silver-silicon alloy, or a gold-silver alloy as long as the first material is silicon and the second material is aluminum, copper, Silicon alloy.
In particular, in this embodiment, the electrode layer 424 may comprise aluminum and the diffusion barrier layer 428 may comprise an aluminum-silicon alloy. Then, reflection by the diffusion barrier layer 428 and the electrode layer 424 can be maximized. The solar cell 100 has a rear electrode structure in which the first and second electrodes 42 and 44 are located on the rear surface of the solar cell 100 and the first and second electrodes 42 and 44 are formed in a wide area 100). ≪ / RTI > However, the present invention is not limited thereto, and the material of the electrode layer 424, the diffusion barrier layer 428, and the like can be variously modified.
If the diffusion barrier layer 428 includes the second material together with the first material as described above, the other layers constituting the electrodes 42 and 44 (i.e., the electrode layer 424, the electrode layer 424, and / Or capping layer 426) may be formed by sputtering. That is, when the diffusion barrier layer 428 includes only the first material, it is difficult to form the diffusion barrier layer 428 by sputtering. Therefore, the diffusion barrier layer 428 must be formed by another method, .
In this embodiment, the diffusion barrier layer 428 may comprise more of the second material than the first material. This is because, since the diffusion barrier layer 428 is basically a layer constituting the electrodes 42 and 44, it can have excellent electrical characteristics to include a large amount of a second conductive material having good conductivity. And the diffusion of the semiconductor material and the electrode material can be effectively prevented even if the first material is contained only a little.
For example, when the diffusion barrier layer 428 is 100 wt%, the wt% of the first material in the diffusion barrier layer 428 may be 1 wt% or less. When the first substance is 1 the diffusion of the semiconductor material and the electrode material can be sufficiently prevented, and when the first material is contained in an amount of more than 1 wt%, the electrical conductivity of the electrodes 42 and 44 may be lowered, Because. In one example, the wt% of the first material may be 0.1 to 1 wt%. If the first material is contained at 0.1 wt% or more, diffusion of the semiconductor material and the electrode material can be effectively prevented. And the diffusion barrier layer 428 may comprise the remainder of the second material (i.e., 99 wt% or more, for example, 99 wt% to 99.9 wt% or less). However, the present invention is not limited thereto, and the content of the first material and the second material in the diffusion barrier layer 428 may be variously changed.
The thickness T2 of the diffusion barrier layer 428 may be greater than the thickness T1 of the adhesive layer 422 and less than the thickness T3 of the electrode layer 424. [ If the thickness T2 of the diffusion barrier layer 428 is less than the electrode layer 424 the effect of the diffusion barrier layer 428 may not be sufficient and the thickness T2 of the diffusion barrier layer 428 may be less than the thickness of the electrode layer 424 The electrical characteristics of the electrodes 42 and 44 may be degraded by the diffusion barrier layer 428 having a resistance lower than that of the electrode layer 424. [
For example, the thickness T1 of the adhesive layer 422: the ratio of the total thickness of the adhesive layer 424 to the diffusion barrier layer 428 (T2 + T3) may be 1:20 to 1:80. If the ratio (T1: T2 + T3) is less than 1:20, the total thickness (T2 + T3) of the diffusion barrier layer 428 and the electrode layer 424 may be small and the electrical characteristics may be degraded. If the ratio (T1: T2 + T3) exceeds 1:80, the thickness T1 of the adhesive layer 422 is large and the permeability of the adhesive layer 422 is reduced or the electrode layer 424 and / May be excessively thick, which may cause problems such as an increase in material cost. Considering the electrical characteristics, the ratio (T1: T2 + T3) may be 1:60 to 1:80.
As an example, the ratio of the thickness T2 of the diffusion barrier layer 428 to the thickness T3 of the electrode layer 424 may be 1: 2 to 1: 4. If the ratio T2: T3 is less than 1: 2, the thickness T2 of the diffusion barrier layer 428 is large or the thickness T3 of the electrode layer 424 is small, so that the electrical characteristics of the electrodes 42, . If the ratio T2: T3 exceeds 1: 4, the thickness T2 of the diffusion barrier layer 428 may be small, and the effect of the diffusion barrier layer 428 may not be sufficiently realized.
Alternatively, the thickness T2 of the diffusion barrier layer 428 may be between 25 nm and 200 nm. This is achieved by maximizing the electrical characteristics of the electrodes 42 and 44 while maximizing the effect of the diffusion barrier layer 428 in consideration of the thickness T1 of the adhesive layer 422 and the thickness T3 of the electrode layer 424 It is limited. More specifically, the thickness T2 of the diffusion barrier layer 428 may be between 25 nm and 100 nm so as to reduce the process time in forming the diffusion barrier layer 428.
However, the present invention is not limited thereto, and the thicknesses T1, T2, and T3 of the electrode layer 424, the diffusion barrier layer 428, and the electrode layer 424 may be variously changed.
A capping layer 426 may be formed on the electrode layer 424. As an example, a capping layer 426 may be formed over the electrode layer 424. The capping layer 426 may include a material that is connected to another solar cell 100 or a ribbon for connection to the outside, and has excellent connection properties with the ribbon.
The capping layer 426 may comprise tin (Sn) or a nickel-vanadium alloy (NiV). The tin has the advantage of excellent bonding properties with ribbons or pastes for connection thereto. The nickel-vanadium alloy is excellent in bonding properties to a ribbon or a paste for connection thereto. More specifically, in the case of a paste containing tin and bismuth, the bonding properties of the tin of the paste and the nickel of the nickel-vanadium alloy are excellent. The nickel-vanadium alloy has a melting point higher than about 1000 ° C. and has a melting point higher than that of other layers constituting the electrode layer 424. Accordingly, it is not deformed during the joining process with the ribbon or the manufacturing process of the solar cell 100, and the capping layer that protects other layers constituting the electrode layer 424 can be sufficiently performed. However, the present invention is not limited thereto, and the capping layer 426 may be composed of various conductive materials (for example, various metals).
The capping layer 426 may have a nano-level thickness, for example, a thickness of 50 nm to 300 nm. If the thickness T4 of the capping layer 426 is less than 50 nm, the bonding properties with the ribbon may be deteriorated. If the thickness T4 exceeds 300 nm, the manufacturing cost may increase. However, the present invention is not limited thereto, and the thickness T4 of the capping layer 426 may be variously changed.
At this time, the capping layer 426 may be made of pure metal (metal remaining in addition to unavoidable impurities) stacked by sputtering. Accordingly, the capping layer 426 may include tin or nickel-vanadium alloy in an amount of 99.9 wt% or more (more specifically, 99.99 wt% or more). However, the present invention is not limited thereto, and the content of the electrode material (or metal material) in the capping layer 426 may vary depending on the manufacturing method of the capping layer 426, process conditions, and the like.
In this embodiment, a single electrode layer 424 is positioned between the diffusion barrier layer 428 and the capping layer 426. However, the present invention is not limited thereto, and another electrode layer may be disposed between the diffusion barrier layer 428 and the capping layer 426 to improve various characteristics. Another electrode layer is positioned between the electrode layer 424 and the capping layer 426 located on the diffusion barrier layer 428 so that the diffusion barrier layer 428 and the electrode layer 424 are adjacent to each other to maintain a laminated structure can do.
In this embodiment, the electrode layer 424, the diffusion barrier layer 428, the electrode layer 424, and the capping layer 426 may be formed so as to be in contact with each other. Then, the lamination structure of the electrodes 42, 44 can be simplified while improving the characteristics of the electrodes 42, 44. As an example, in the present embodiment, the electrodes 42,44 may have a four-layer stacked structure comprising an electrode layer 424, a diffusion barrier layer 428, an electrode layer 424 and a capping layer 426. [ According to this, the laminated structure of the electrodes 42 and 44 can be simplified as much as possible. However, the present invention is not limited thereto, and the electrodes 42 and 44 may have a separate layer between or on the electrode layer 424, the diffusion barrier layer 428, the electrode layer 424, and the capping layer 426 have.
The electrode material layer is formed by sputtering or the like on the electrodes 42 and 44 including the adhesive layer 422, the diffusion barrier layer 428, the electrode layer 424 and the capping layer 426 It can be formed by patterning it. More specifically, in the case of the first opening 402 and the second electrode 44 of the insulating layer 40 formed on the rear surface of the semiconductor substrate 10, the adhesive layer 422, the diffusion The electrodes 42 and 44 can be formed by sequentially forming the layers constituting each of the barrier layer 428, the electrode layer 424 and the capping layer 426 in order, and then patterning them.
Thus, since the material is stacked in the thickness direction of the solar cell 100 by sputtering, the adhesive layer 422 has a uniform thickness throughout, the electrode layer 424 has a uniform thickness over the entire portion, (426) are stacked so as to have a uniform thickness in the entire portion. Here, the uniform thickness may mean a thickness (for example, a thickness having a difference of 10% or less) that can be judged to be uniform in consideration of process errors and the like.
The first electrode 42 may be formed to have a width larger than the width of the first opening 402. This is to sufficiently secure the width of the first electrode 42 (the widest width of the portion constituting the first electrode 42) to reduce the resistance of the first electrode 42. For example, the width of the first opening 402 may be between 10 um and 50 um, and the width of the first electrode 42 may be between 200 um and 250 um. If the width of the first opening 402 is less than 10 μm, the first electrode 42 and the first conductivity type region 32 may not be connected smoothly. If the width of the first opening 402 exceeds 50 袖 m, the possibility of damaging the first conductivity type region 32 may be increased when the first opening 402 is formed. If the width of the first electrode 42 is less than 200 μm, the first electrode 42 may not have sufficient resistance. If the width of the first electrode 42 exceeds 250 袖 m, a problem such as unnecessarily short-circuiting with the neighboring second electrode 44 may occur. Similarly, the second electrode 44 may be formed to have a greater width than the second opening 404. For example, the width of the second opening 404 may be between 10 um and 50 um, and the width of the second electrode 44 may be between 200 um and 250 um. However, the present invention is not limited thereto, and the width of the openings 402 and 404 and the width of the first electrodes 42 and 44 may have various values.
The electrodes 42 and 44 (particularly the adhesive layer 422) are electrically connected to the bottom of the first opening 402 (the second opening 404 in the case of the second electrode 44) (The contact surface with the first and second openings 402 and 403), the side surface of the insulating layer 40 adjacent to the first opening 402, and the insulating layer 40 adjacent to the first opening 402 . In particular, the adhesive layer 422 is formed on the bottom surface (i.e., the contact surface with the conductive regions 32 and 34) of the first opening 402, the side surface of the insulating layer 40 adjacent the first opening 402, And may be positioned in contact with them on the insulating layer 40 adjacent to the first opening 402. The electrodes 42 and 44 are formed on the side surface of the insulating layer 40 adjacent to the opening 402 and on the insulating layer 40 adjacent to the first opening 402 so that the first and second electrodes 42 And 44 are formed on the insulating layer 40 and then patterned to form the electrodes 42 and 44.
Thus, in this embodiment, the electrodes 42 and 44 can be formed without using a plating process. If a part of the electrodes 42 and 44 is formed by plating, if there is a defect such as a pin hole or a scratch in the insulating layer 40, plating is also performed in that part, and an undesired portion can be plated. Since the plating solution used in the plating process is an acid or an alkali, it may damage the insulating layer 40 or deteriorate the characteristics of the insulating layer 40. In this embodiment, the characteristics of the insulating layer 40 can be improved by not using the plating process, and the electrodes 42 and 44 can be formed by a simple process. However, the present invention is not limited thereto, and the adhesive layer 422, the diffusion barrier layer 428, the electrode layer 424, and the capping layer 426 may be formed by various methods and may be patterned by various methods.
1 and 2, the first conductive type region 32 and the second conductive type region 34, the barrier region 36, and the planar shape of the first and second electrodes 42 and 44 Will be described in detail.
1 and 2, in the present embodiment, the first conductive type region 32 and the second conductive type region 34 are formed to be long in a stripe shape, and alternate with each other in the direction crossing the longitudinal direction Respectively. Barrier regions 36 may be located between the first conductivity type region 32 and the second conductivity type region 34 to isolate them. Although not shown, a plurality of first conductive regions 32 spaced apart from each other may be connected to each other at one edge, and a plurality of second conductive regions 34 separated from each other may be connected to each other at the other edge. However, the present invention is not limited thereto.
At this time, the area of the first conductivity type region 32 may be larger than the area of the second conductivity type region 34. In one example, the areas of the first conductivity type region 32 and the second conductivity type region 34 can be adjusted by varying their widths. That is, the width W1 of the first conductivity type region 32 may be greater than the width W2 of the second conductivity type region 34. [
The first electrode 42 may be formed in a stripe shape corresponding to the first conductivity type region 32 and the second electrode 44 may be formed in a stripe shape corresponding to the second conductivity type region 34 . However, the present invention is not limited thereto, and the first and second electrodes 42 and 44 may have various planar shapes.
The first and second openings (402 and 404 in FIG. 1, respectively, the same reference numerals) are formed on the entire length of the first and second electrodes 42 and 44 corresponding to the first and second electrodes 42 and 44, . The contact area between the first and second electrodes 42 and 44 and the first conductivity type region 32 and the second conductivity type region 34 can be maximized to improve the carrier collection efficiency. However, the present invention is not limited thereto. The first and second openings 402 and 404 are formed so as to connect only a part of the first and second electrodes 42 and 44 to the first conductivity type region 32 and the second conductivity type region 34 Of course it is possible. For example, the first and second openings 402 and 404 may be formed of a plurality of contact holes. Although not shown in the figure, the first electrodes 42 may be connected to each other at one edge, and the second electrodes 44 may be connected to each other at the other edge. However, the present invention is not limited thereto.
Referring again to FIG. 1, a passivation film 24 and / or an antireflection film 26 (not shown) are formed on the front surface of the semiconductor substrate 10 (more precisely, on the front electric field area 130 formed on the front surface of the semiconductor substrate 10) ) Can be located. Only the passivation film 24 may be formed on the semiconductor substrate 10 or only the antireflection film 26 may be formed on the semiconductor substrate 10 or the passivation film 24 And the antireflection film 26 may be disposed one after the other. In the figure, a passivation film 24 and an antireflection film 26 are sequentially formed on a semiconductor substrate 10, and the semiconductor substrate 10 is contacted with the passivation film 24. However, the present invention is not limited thereto, and the semiconductor substrate 10 may be formed in contact with the anti-reflection film 26, and various other modifications are possible.
The passivation film 24 and the antireflection film 26 may be formed entirely on the front surface of the semiconductor substrate 10 substantially. Here, the term " formed as a whole " includes not only completely formed physically but also includes cases where there are inevitably some exclusion parts.
The passivation film 24 is formed in contact with the front surface of the semiconductor substrate 10 to passivate the defects existing in the front surface or the bulk of the semiconductor substrate 10. [ Thus, the recombination site of the minority carriers can be removed to increase the open-circuit voltage of the solar cell 100. The antireflection film 26 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. The amount of light reaching the pn junction formed at the interface between the base region 110 and the first conductive type region 32 can be increased. Accordingly, the short circuit current Isc of the solar cell 100 can be increased. In this way, the efficiency of the solar cell 100 can be improved by increasing the open-circuit voltage and the short-circuit current of the solar cell 100 by the passivation film 24 and the antireflection film 26.
The passivation film 24 and / or the antireflection film 26 may be formed of various materials. In one example, the passivation film 24 and / or the anti-reflection film 26 is a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, a silicon carbide film, aluminum oxide film, MgF 2, ZnS, TiO 2 and CeO 2 , Or a multilayer structure in which two or more films are combined. As an example, the passivation film 24 may comprise silicon oxide or silicon carbide, and the antireflective film 26 may comprise silicon nitride.
When light is incident on the solar cell 100 according to this embodiment, electrons and holes are generated by the photoelectric conversion in the pn junction (or the pn tunnel junction) formed between the base region 110 and the first conductivity type region 32 The generated holes and electrons tunnel through the tunneling layer 20 to move the first and second electrodes 42 and 44 after moving to the first conductive type region 32 and the second conductive type region 34, . Thereby generating electrical energy.
Since the first and second conductive regions 32 and 34 are formed on the semiconductor substrate 10 with the tunneling layer 20 interposed therebetween, the semiconductor substrate 10 and the semiconductor substrate 10 are separated from each other. As a result, the loss due to the recombination can be minimized as compared with the case where the doped region formed by doping the semiconductor substrate 10 with the dopant is used as the conductive type region.
In the solar cell 100 according to the present embodiment, the electrodes 42 and 44 are formed on the rear surface of the semiconductor substrate 10 and the rear surface electrode structure is not formed on the front surface of the semiconductor substrate 10. Thus, shading loss at the front surface of the semiconductor substrate 10 can be minimized. Thus, the efficiency of the solar cell 100 can be improved.
In the present embodiment, the electrodes 42 and 44 are provided with the diffusion barrier layer 428 between the electrode layer 424 and the conductive regions 32 and 34 so that the electrode material of the electrode layer 424 is in the conductive type region 32, and 34, respectively. As a result, it is possible to prevent the problem caused by the diffusion of the electrode material, thereby improving the open-circuit voltage (Voc) of the solar cell 100 and preventing the fill factor (FF) . Layer structure of the electrode layer 424 and the diffusion barrier layer 428 can be formed to substantially keep the resistance of the electrodes 42 and 44 low.
In the above description, the first and second electrodes 42 and 44 have the same lamination structure, but the present invention is not limited thereto. Accordingly, the first electrode 42 and the second electrode 44 may have different materials or stacked structures.
Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.
