KR101816189B1 - Solar cell and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a solar cell and a manufacturing method thereof. According to an embodiment of the present invention, the solar cell includes: a semiconductor substrate; a rear electric field part located on the rear surface of the semiconductor substrate; an emitter part located on one among the front and rear sides of the semiconductor substrate; a rear dielectric layer located on the rear side of the semiconductor substrate, and including an opening part exposing the rear electric field part; a first electrode part electrically and physically connected with the rear dielectric layer through the opening part; and a second electrode part electrically and physically connected with the emitter part. As to a part protruding from the rear dielectric layer, the line width of a first surface of the first electrode, facing the semiconductor substrate, is practically equal to the line width of a second surface which is opposite to the first surface, or is larger than the line width of the second surface.

Description

SOLAR CELL AND MANUFACTURING METHOD THEREOF

The present invention relates to a solar cell and a manufacturing method thereof.

Recently, as energy resources such as oil and coal are expected to be depleted, interest in alternative energy to replace them is increasing, and solar cells that produce electric energy from solar energy are attracting attention.

The solar cell has a substrate and an emitter layer each made of a semiconductor of a different conductive type such as a p-type and an n-type, and electrodes having different polarities respectively connected to the substrate and the emitter portion . At this time, a pn junction is formed at the interface between the substrate and the emitter.

As a method for forming the electrodes of different polarities, conventionally, an electrode layer made of a metal material is formed on a front surface and a rear surface of the substrate (when electrodes having different polarities are located on the front surface and the rear surface of the substrate) The electrode having the other polarity is located on the rear surface of the substrate), and a mask is formed by printing a photo resist paste on a partial area on the electrode layer, and wet etching using the mask is performed Electrodes having different polarities were formed in accordance with a process of removing an electrode layer in an area not covered with the mask and then cleaning the mask after removing the mask.

However, according to this method, the use of the photoresist paste for forming the mask, the use of the etching solution for performing the wet etching, the use of the solution for removing the mask, the use of the cleaning liquid necessary for cleaning, There is a problem that the manufacturing cost increases and the number of processes increases.

When the electrode layer in the region not covered with the mask is removed by using the etching solution, since the side surface of the formed electrode is formed as an undercut (the lower surface is formed narrower than the upper surface), the bonding area The charge collection efficiency is lowered and the electrode is lifted up.

Therefore, there is a need for a manufacturing method capable of effectively reducing the number of steps and manufacturing cost while suppressing the above-mentioned problems.

The present invention provides a solar cell and a manufacturing method thereof.

A solar cell according to an aspect of the present invention includes: a semiconductor substrate; A rear electric field portion located on a rear surface of the semiconductor substrate; An emitter section located on one surface selected from the front surface of the semiconductor substrate or the rear surface of the semiconductor substrate; A back dielectric layer located on the back surface of the semiconductor substrate and including an opening exposing a back surface electric field; A first electrode part electrically and physically connected to the rear electric part through an opening; And a second electrode portion electrically and physically connected to the emitter portion, wherein the first electrode portion has a line width of the first surface facing the semiconductor substrate protruding to the outside of the rear dielectric layer at a position opposite to the first surface The width of the second surface is larger than the width of the second surface.

The rear dielectric layer is formed of any one of a silicon oxide film, a silicon nitride film, and a silicon carbide film, or a structure in which at least two films selected from the films are laminated, preferably a laminated structure of a silicon nitride film and a silicon carbide film.

The first electrode unit includes a plurality of first finger electrodes extending in a first direction and spaced apart from each other, and the second electrode unit may include a plurality of second finger electrodes extending in a first direction and spaced apart from each other.

The emitter electrode and the second electrode portion may be located on the rear surface of the semiconductor substrate and the second electrode portion may be formed on the portion of the rear dielectric layer protruding outward so that the line width of the first surface facing the semiconductor substrate is located on the opposite side of the first surface The width of the second surface may be substantially equal to the line width of the second surface.

The first finger electrode and the second finger electrode are spaced apart from each other, and a side surface of the first finger electrode facing the first finger electrode and a side surface of the second finger electrode facing each other out of the protruding portions of the rear dielectric layer, The gap may be formed to be smaller than an interval between the second surfaces.

The emitter portion and the rear surface electric field portion may be respectively formed of a polycrystalline silicon layer.

The solar cell may further include an intrinsic semiconductor layer located between the emitter portion and the rear electric portion and formed of a polycrystalline silicon layer.

The solar cell may further include a rear tunnel layer positioned between the back surface of the semiconductor substrate and the polysilicon layer.

The silicon carbide film may be positioned between the silicon nitride film and the first electrode portion and between the silicon nitride film and the second electrode portion when the rear dielectric layer is formed of a laminated structure of the silicon nitride film and the silicon carbide film, And may not be located on the silicon nitride film located between the portions.

The emitter portion and the second electrode portion may be positioned on the front surface of the semiconductor substrate.

A method of manufacturing a solar cell according to an aspect of the present invention includes: forming an emitter portion and a rear surface electric portion on a rear surface of a semiconductor substrate; Forming a rear dielectric layer on the back surface of the semiconductor substrate, the rear dielectric layer including openings exposing the emitter portions and the rear surface electric field portions, respectively; And forming an electrode layer electrically and physically connected to the rear electric and emitter portions through the opening on the entire rear surface of the rear dielectric layer; And separating the electrode layer into a first electrode portion connected to the rear electric field portion and a second electrode portion electrically and physically connected to the emitter portion, respectively, and separating the electrode layer into the first electrode portion and the second electrode portion, And irradiating a laser beam to the electrode layer in the emitter region and the rear electric field region, particularly, the electrode layer in the region not overlapping the opening portion on the projection plane to remove the electrode layer in the region irradiated with the laser.

The first electrode portion and the second electrode portion are formed so that the line width of the first surface facing the semiconductor substrate is substantially equal to the line width of the second surface located on the opposite side of the first surface, Or larger than the line width of the second surface.

In the step of forming the rear dielectric layer, the rear dielectric layer may be formed of any one of a silicon oxide film, a silicon nitride film, and a silicon carbide film, or the rear dielectric layer may be formed by laminating at least two films selected from the films.

For example, the rear dielectric layer can be formed by laminating a silicon nitride film and a silicon carbide film.

Wherein the first electrode and the second electrode have a wavelength of 30 nm to 1,200 nm and have a bandgap below the bandgap of the material forming the rear dielectric layer, A pulse laser following the distribution can be used.

The electrode layer can be formed by a sputtering method.

Forming the emitter portion and the rear surface electric field portion includes: forming a polycrystalline silicon layer on the rear surface of the semiconductor substrate; And selectively implanting or diffusing the second conductive impurity and the first conductive impurity into a part of the polycrystalline silicon layer.

The emitter portion and the rear electric field portion may be formed apart from each other and an intrinsic semiconductor layer formed of a polycrystalline silicon layer may be formed between the emitter portion and the rear electric field portion.

The manufacturing method of the solar cell may further include forming a rear tunnel layer between the rear surface of the semiconductor substrate and the polycrystalline silicon layer.

The rear dielectric layer can be formed by laminating a silicon nitride film and a silicon carbide film. In this case, when removing the electrode layer in the laser irradiated region, the silicon carbide film is used as a sacrifice layer to remove the silicon carbide film in the laser- , The silicon carbide film located between the silicon nitride film and the first electrode portion and between the silicon nitride film and the second electrode portion can be left.

According to another aspect of the present invention, there is provided a method of manufacturing a solar cell, including: forming a rear electric field portion on a rear surface of a semiconductor substrate; Forming a rear dielectric layer on the rear surface of the semiconductor substrate, the rear dielectric layer including an opening exposing the rear surface electric field portion; And forming a first electrode portion electrically and physically connected to the rear electrical conductor through the opening, wherein forming the first electrode portion comprises: forming an electrode layer over the entire rear surface of the rear dielectric layer; And irradiating a laser beam onto an electrode layer in an area not overlapping the opening on the projection plane to remove an electrode layer in a laser irradiated area, wherein the first electrode part is a part protruding outward from the rear dielectric layer, The line width of the first surface facing the first surface is formed to be substantially equal to the line width of the second surface located on the opposite side of the first surface or is formed to be larger than the line width of the second surface.

At this time, in forming the rear dielectric layer, the rear dielectric layer may be formed of a silicon oxide film, a silicon nitride film, or a silicon carbide film, or at least two films selected from the films may be stacked to form the rear dielectric layer .

For example, a silicon nitride film and a silicon carbide film may be laminated to form a rear dielectric layer.

In the step of forming the first electrode part, a pulse laser having a wavelength of 30 nm to 1,200 nm and having a band gap below the bandgap of the material forming the rear dielectric layer and having a Gaussian distribution of energy intensity in the cross section of the laser beam pulse laser) can be used.

The electrode layer can be formed by a sputtering method.

When the rear dielectric layer is formed by laminating a silicon nitride film and a silicon carbide film, the silicon carbide film in the region irradiated with the laser is removed using the silicon carbide film as a sacrificial layer when removing the electrode layer in the laser irradiated region, And the silicon carbide film located between the first electrode portion and the first electrode portion may remain.

According to this embodiment, since the electrode portion is formed by removing a part of the electrode layer by a laser lift-off (LLO) process, an acid-based etching solution for patterning the electrode layer may not be used.

As a result, it is possible to prevent problems such as deterioration of the passivation property due to the etching solution of the acid series, deterioration and damage of the region containing the conductive impurities.

Since the line width of the lower surface of the electrode portion can be made substantially equal to the line width of the upper surface or can be formed larger than the line width of the upper surface, The junction area is increased to improve the charge collection efficiency, and it is possible to suppress the floating of the electrode.

In addition, since it is possible to remove the use of a photoresist paste for forming a mask, use of an etching solution for performing a wet etching, use of a solution for removing a mask, and use of a cleaning liquid necessary for cleaning, Cost and process number can be reduced.

1 and 2 are views for explaining a solar cell according to a first embodiment of the present invention.
3 is a process diagram for explaining a method of manufacturing a solar cell according to the first embodiment of the present invention.
4 is a view for explaining a solar cell according to a second embodiment of the present invention.
5 is a process diagram for explaining a method of manufacturing a solar cell according to a second embodiment of the present invention.
6 is a view for explaining a solar cell according to a third embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. When a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case directly above another portion but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle. Also, when a part is formed as "whole" on the other part, it means not only that it is formed on the entire surface (or the front surface) of the other part but also not on the edge part.

The term "front surface" refers to a surface of a semiconductor substrate to which direct light is incident. The term "back surface" refers to a surface of the semiconductor substrate on which the direct light is not incident, .

In addition, the fact that any two values are equal means that the error range is equal to or less than 10%.

Hereinafter, a solar cell and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, an example of a solar cell that can be manufactured according to this embodiment will be described, and then a manufacturing method thereof will be described in detail.

FIG. 1 is a cross-sectional view illustrating a solar cell according to a first embodiment of the present invention, and FIG. 2 is a partial rear plan view of the solar cell shown in FIG. 1. FIG.

1 and 2, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10 including a base region 110, a semiconductor substrate 10 on one side of the semiconductor substrate 10, for example, The first and second electrode portions 44 and 44 connected to the first and second doped regions 32 and 34, respectively, and the polycrystalline silicon layer 30 including the first and second doped regions 32 and 34, 42).

The solar cell 100 may further include a rear tunnel layer 20 located between the semiconductor substrate 10 and the polycrystalline silicon layer 30.

The solar cell 100 further includes a passivation film 24 and an antireflection film 26 located on the front surface of the semiconductor substrate 10 and a rear dielectric layer 40 located on the rear surface of the semiconductor substrate 10. [ As shown in FIG.

The semiconductor substrate 10 may include a base region 110 having a first conductivity including a first conductive impurity at a relatively low doping concentration.

The base region 110 may be formed of a crystalline semiconductor containing a first conductive impurity. In one example, the base region 110 may be composed of a single crystal or a polycrystalline semiconductor (for example, single crystal or polycrystalline silicon) including a first conductive impurity.

In particular, the base region 110 may be comprised of a single crystal semiconductor (e.g., a single crystal semiconductor wafer, more specifically a semiconductor silicon wafer) containing a first conductive impurity.

If the base region 110 is made of monocrystal silicon, the solar cell 100 is excellent in electrical characteristics because it is based on the base region 110 or the semiconductor substrate 10 having high crystallinity and few defects.

The first conductivity may be p-type or n-type. For example, if the base region 110 has an n-type, a p-type (for example, a p-type junction with a back tunnel layer 20 interposed therebetween) forming a charge by photoelectric conversion with the base region 110 The first doped region 32 may be formed to be wide to increase the photoelectric conversion area.

Also, in this case, the first doped region 32 having a large area can effectively collect holes having a relatively low moving speed, thereby contributing more to the improvement of photoelectric conversion efficiency. However, the present invention is not limited thereto.

The semiconductor substrate 10 may include a front electrical part 130 located on the front side. The front electric field 130 may have a higher doping concentration than the base region 110 with the same conductivity as the base region 110.

In this embodiment, the front electric field portion 130 is formed of a doped region formed by doping the semiconductor substrate 10 with the first conductive impurity at a relatively high doping concentration. Accordingly, the front electric field 130 includes a crystalline (single crystal or polycrystalline) semiconductor having the first conductivity to constitute a part of the semiconductor substrate 10.

For example, the front electric field 130 may form part of a single-crystal semiconductor substrate having a first conductivity (e.g., a single-crystal silicon wafer substrate). However, the present invention is not limited thereto.

Therefore, when depositing a separate semiconductor layer (for example, an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer) other than the semiconductor substrate 10 on the semiconductor substrate 10, The electric field 130 may be formed.

Or the front electric field 130 has a role similar to that doped by the fixed charge of the layer (e.g., the passivation film 24 and / or the antireflection film 26) formed adjacent to the semiconductor substrate 10 Or an electric field area.

For example, when the base region 110 is n-type, the passivation film 24 may be composed of an oxide (for example, aluminum oxide) having a negative fixed charge, An inversion layer may be formed and used as an electric field region.

In this case, the semiconductor substrate 10 does not have a separate doping region but consists only of the base region 110, thereby minimizing defects in the semiconductor substrate 10. [

The front electric part 130 having various structures can be formed by various other methods.

In the present embodiment, the front surface of the semiconductor substrate 10 may be textured to have irregularities such as pyramids.

If the surface roughness of the front surface of the semiconductor substrate 10 is increased by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced. Accordingly, the amount of light reaching the pn junction formed by the base region 110 and the first doped region 32 can be increased, and the optical loss can be minimized.

The rear surface of the semiconductor substrate 10 may be made of a relatively smooth and flat surface having a surface roughness lower than that of the front surface by mirror polishing or the like.

When the first and second doped regions 32 and 34 are formed together on the rear side of the semiconductor substrate 10 as in the present embodiment, the characteristics of the solar cell 100 depend on the characteristics of the rear surface of the semiconductor substrate 10 Can vary greatly.

Accordingly, the passivation characteristic can be improved by not forming the irregularities due to texturing on the rear surface of the semiconductor substrate 10, and the characteristics of the solar cell 100 can be improved thereby.

However, the present invention is not limited to this. In some cases, irregularities due to texturing may be formed on the rear surface of the semiconductor substrate 10, and various other modifications are possible.

On the rear surface of the semiconductor substrate 10, a rear tunnel layer 20 may be formed. The rear tunnel layer 20 acts as a kind of barrier for electrons and holes to prevent the minority carriers from passing through and to prevent the electrons and holes from being transmitted through the rear tunnel layer 20 after having accumulated at a portion adjacent to the rear tunnel layer 20 So that only majority carriers can pass through the rear tunnel layer 20.

At this time, a plurality of charges having energy equal to or higher than a certain level can easily pass through the rear tunnel layer 20 by the tunneling effect. The rear tunnel layer 20 may serve as a diffusion barrier for preventing impurities of the first and second doped regions 32 and 34 from diffusing into the semiconductor substrate 10.

The rear tunnel layer 20 may include various materials through which the charge can be tunneled. For example, the rear tunnel layer 20 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like.

For example, the back tunnel layer 20 may comprise silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and the like.

At this time, the rear tunnel layer 20 may be formed entirely on the rear surface of the semiconductor substrate 10. Accordingly, the interface characteristics of the rear surface of the semiconductor substrate 10 can be improved as a whole, and can be easily formed without additional patterning.

On the rear tunnel layer 20, first and second doped regions 32 and 34 located at the same level can be located.

More specifically, in this embodiment, the first and second doped regions 32 and 24 include a first doped region 32 including a second conductive impurity and exhibiting a second conductivity, Lt; RTI ID = 0.0 > 1 < / RTI > conductivity.

The intrinsic semiconductor layer 36 as the intrinsic semiconductor layer may be located between the first doped region 32 and the second doped region 34.

The first doped region 32 forms a pn junction (or a pn tunnel junction) with the base region 110 and the rear tunnel layer 20 therebetween, thereby forming an emitter portion for generating charges by photoelectric conversion.

At this time, the first doped region 32 may be a semiconductor (e.g., silicon) including a second conductive impurity opposite to the base region 110.

In this embodiment, the first doped region 32 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the rear tunnel layer 20) and the second doped region 32 is doped And a semiconductor layer.

Accordingly, the first doped region 32 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the first doped region 32 can be easily formed on the semiconductor substrate 10.

For example, the first doped region 32 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (for example, amorphous silicon, microcrystalline silicon, or polycrystalline silicon) which can be easily manufactured by various methods such as vapor deposition And may be formed by doping a second conductive impurity.

The second conductive impurity may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as heat diffusion method and ion implantation method after forming the semiconductor layer.

At this time, the second conductive impurity may be an impurity that can exhibit conductivity opposite to the base region 110.

That is, when the second conductive impurity is p-type, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. In the case where the second conductive impurity is n-type, (P), arsenic (As), bismuth (Bi), and antimony (Sb).

The second doped region 34 forms a back surface field to prevent charges from being lost by recombination on the surface of the semiconductor substrate 10 (more precisely on the back surface of the semiconductor substrate 10) And constitutes an electric field portion.

At this time, the second doped region 34 may be a semiconductor (e.g., silicon) including the same first conductive impurity as the base region 110.

In this embodiment, the second doped region 34 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the rear tunnel layer 20) and the first conductive dopant is doped And a semiconductor layer.

Accordingly, the second doped region 34 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the second doped region 34 can be easily formed on the semiconductor substrate 10.

For example, the second doped region 34 may be an amorphous semiconductor (e.g., amorphous silicon), a microcrystalline semiconductor (e. G., Microcrystalline silicon), or a polycrystalline semiconductor For example, polycrystalline silicon) or the like by doping with a first conductive impurity.

The first conductive impurity may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a heat diffusion method and an ion implantation method after forming the semiconductor layer.

At this time, the first conductive impurity may be an impurity capable of exhibiting the same conductivity as the base region 110.

That is, when the first conductive impurity is n-type, Group 5 elements such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used, and when the first conductive impurity is p- (B), aluminum (Al), gallium (Ga), and indium (In).

The intrinsic semiconductor layer 36 as the intrinsic semiconductor layer is positioned between the first doped region 32 and the second doped region 34 to separate the first doped region 32 and the second doped region 34 from each other .

When the first doped region 32 and the second doped region 34 are in contact with each other, a shunt may occur, thereby deteriorating the performance of the solar cell 100.

Accordingly, in this embodiment, the intrinsic semiconductor layer 36 can be positioned between the first doped region 32 and the second doped region 34 to prevent unnecessary shunting.

The intrinsic semiconductor layer 36 may include various materials capable of substantially insulating them between the first doped region 32 and the second doped region 34.

That is, the intrinsic semiconductor layer 36 may be made of an insulating material (e.g., oxide or nitride) that is not doped with an impurity (that is, an undoped material).

The first doped region 32 and the second doped region 34 and the intrinsic semiconductor layer 36 are composed of the same semiconductor (for example, amorphous silicon, microcrystalline silicon, polycrystalline silicon) continuously formed while being in side contact with each other However, the intrinsic semiconductor layer 36 may be substantially free of impurities.

For example, after the polycrystalline silicon layer 30 is formed, a first doped region 32 is formed by doping a second conductive impurity in a part of the polycrystalline silicon layer 30, and a first conductive impurity The polycrystalline silicon layer 30 in the region where the first doped region 32 and the second doped region 34 are not formed forms the intrinsic semiconductor layer 36 .

Thus, the manufacturing method of the first doped region 32, the second doped region 34, and the intrinsic semiconductor layer 36 can be simplified. However, the present invention is not limited thereto.

Therefore, when the intrinsic semiconductor layer 36 is formed separately from the first doped region 32 and the second doped region 34, the thickness of the intrinsic semiconductor layer 36 is less than the thickness of the first doped region 32 and the second doped region 34. [ Region 34. [0035]

For example, in order to more effectively block shunts between the first doped region 32 and the second doped region 34, the intrinsic semiconductor layer 36 is thicker than the first doped region 32 and the second doped region 34 It may have a thickness.

Alternatively, the thickness of the intrinsic semiconductor layer 36 may be made smaller than the thickness of the first doped region 32 and the second doped region 34 in order to reduce the amount of raw material for forming the intrinsic semiconductor layer 36. Of course, various modifications are possible.

The intrinsic semiconductor layer 36 may include a material other than the first doped region 32 and the second doped region 34 and the first doped region 32 32) and the second doped region 34. In this case,

In this embodiment, the intrinsic semiconductor layer 36 is entirely separated from the first doped region 32 and the second doped region 34. However, the present invention is not limited thereto.

The intrinsic semiconductor layer 36 may be formed so as to separate only a part of the boundary portions of the first doped region 32 and the second doped region 34. [

According to this, other portions of the boundaries of the first doped region 32 and the second doped region 34 may be in contact with each other. In addition, the intrinsic semiconductor layer 36 is not necessarily provided, and the first doped region 32 and the second doped region 34 may be formed in contact with each other as a whole, and various other modifications are possible.

The area of the first doped region 32 having a conductivity different from that of the base region 110 can be wider than the area of the second doped region 34 having the same conductivity as the base region 110.

Accordingly, the pn junction formed through the rear tunnel layer 20 between the base region 110 and the first doped region 32 can be made wider.

At this time, when the base region 110 and the second doped region 34 have n-type conductivity and the first doped region 32 has the p-type conductivity, the first doped region 32 It is possible to effectively collect holes having a relatively low moving speed.

An example of the planar structure of the first doped region 32, the second doped region 34, and the intrinsic semiconductor layer 36 will be described later in more detail with reference to FIG.

A rear dielectric layer 40 may be formed on the first and second doped regions 32 and 34 and the intrinsic semiconductor layer 36.

The rear dielectric layer 40 includes a first opening portion 402 for electrical and physical connection between the first doped region 32 and the second electrode portion 42 and a second opening portion 40 for electrically connecting the second doped region 34 and the first electrode portion 44 And a second opening 404 for electrical and physical connection of the first and second electrodes.

In this case, the rear dielectric layer 40 is formed on the first electrode portion 44 (in the case of the first doped region 32, the first electrode portion 44 And in the case of the second doped region 34, the second electrode portion 42).

In addition, the rear dielectric layer 40 may have the effect of passivating the first and second doped regions 32, 34 and / or the intrinsic semiconductor layer 36.

The rear dielectric layer 40 may be located on the entire rear surface of the substrate except the regions where the electrode portions 44 and 42 are not located, specifically, the regions where the openings 404 and 402 are located above the polycrystalline silicon layer 30 .

The backside dielectric layer 40 may have a greater thickness than the backside tunnel layer 20. As a result, the insulating characteristics and the passivation characteristics can be improved. However, the present invention is not limited thereto.

The backside dielectric layer 40 may be comprised of various insulating materials (e.g., oxides, nitrides, etc.).

For example, the rear dielectric layer 40 may have a multilayer structure in which a single film selected from a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, and a silicon carbide film, or a combination of two or more films, , It may be formed of a material having a band gap of 3 or less.

However, the present invention is not limited thereto, and it goes without saying that the rear dielectric layer 40 may include various materials.

Electrode portions 44 and 42 located on the rear surface of the semiconductor substrate 10 include a second electrode portion 42 electrically and physically connected to the first doped region 32 and a second electrode portion 42 electrically connected to the second doped region 34. [ And a first electrode portion 44 electrically and physically connected.

The second electrode portion 42 is electrically and physically connected to the first doped region 32 through the first opening portion 402 of the rear dielectric layer 40 and the first electrode portion 44 is electrically connected to the first dielectric layer 40, And is electrically and physically connected to the second doped region 34 through the second opening 404 of the second doped region 40.

The first and second electrode portions 44 and 42 may include various metal materials. The first and second electrode units 44 and 42 are connected to the first doped region 32 and the second doped region 34 without being electrically connected to each other, And can have various planar shapes that can be transmitted. That is, the present invention is not limited to the planar shape of the first and second electrode portions 44 and 42.

Hereinafter, the lamination structure and the cross-sectional structure of the first and / or second electrode portions 44 and 42 will be described in detail with reference to the enlargement circle of FIG. 1, and then, referring to FIG. 2, The planar structures of the first and second contact members 44 and 42 will be described in detail.

1, the second electrode unit 42 is enlarged. However, the first electrode unit 44 may have the same lamination structure and cross-sectional structure.

1, the first and second electrode portions 44 and 42 are formed of an adhesive layer 422 formed in contact with the second and first doped regions 34 and 32 and having permeability and conductivity, A conductive layer 424 formed on the adhesive layer 422 and a capping layer 426 formed on the conductive layer 424. [

Here, the conductive layer 424 plays a fundamental role of collecting charges generated by photoelectric conversion and transferring the charges to the outside, and the adhesive layer 422 is formed between the first and second doped regions 32 and 34 and the conductive layer 422. [ And the capping layer 426 is used as a layer connected to another solar cell 100 or a ribbon (or a connecting member, a tap, etc.) for connection with the outside .

The adhesive layer 422 may be formed between the first and second doped regions 32 and 34 and the conductive layer 424 by contacting them. The adhesive layer 422 may include a metal having conductivity and excellent contact properties with the polycrystalline silicon layer 30. [ Thus, the adhesion characteristics between the polysilicon layer 30 and the conductive layer 424 can be improved without lowering the conductivity of the first electrode part 44. [

The thermal expansion coefficient of the adhesive layer 422 is higher than the thermal expansion coefficient of the polycrystalline silicon layer 30 and the thermal expansion coefficient of the adhesive layer 422 in the conductive layer 424 in order to improve the contact property of the adhesive layer 422 with the polycrystalline silicon layer 30. [ ) Between the thermal expansion coefficient of the portion adjacent to the center portion and the center portion.

If the thermal expansion coefficient difference between the polycrystalline silicon layer 30 and the first and second electrode portions 44 and 42 is large, in the various heat treatment processes for forming the solar cell 100, The interface contact characteristics between the first electrode portion 30 and the first and second electrode portions 44 and 42 may be degraded.

The contact resistance between the polycrystalline silicon layer 30 and the first and second electrode portions 44 and 42 can be increased. This is because when the contact area between the polycrystalline silicon layer 30 and the first and second electrode portions 44 and 42 is reduced by reducing the line width of the polycrystalline silicon layer 30 or the first and second electrode portions 44 and 42 For example, a backside electrode structure).

Accordingly, in this embodiment, the thermal expansion coefficient of the adhesive layer 422 in contact with the semiconductor layer of the first and second electrode portions 44 and 42 is limited, and the thermal expansion coefficient of the polycrystalline silicon layer 30, It is possible to reduce the coefficient of thermal expansion between the contact surfaces 44 and 42 and improve the interface contact property.

The thermal expansion coefficient of the polycrystalline silicon layer 30 is about 4.2 ppm / K and the portion of the conductive layer 424 adjacent to the adhesive layer 422 (for example, the conductive layer 424 in this embodiment) The thermal expansion coefficient of copper (Cu), aluminum (Al), silver (Ag), gold (Au) and the like is approximately 14.2 ppm / K or more.

More specifically, the thermal expansion coefficient of copper is about 16.5 ppm / K, the thermal expansion coefficient of aluminum is about 23.0 ppm / K, the thermal expansion coefficient of silver is about 19.2 ppm / K, and the thermal expansion coefficient of gold is about 14.2 ppm / K .

Taking this into consideration, the coefficient of thermal expansion of the material (e.g., metal) constituting the adhesive layer 422 may be about 4.5 ppm / K to about 14 ppm / K. If the coefficient of thermal expansion is less than 4.5 ppm / K or more than 14 ppm / K, the difference in thermal expansion coefficient between the polycrystalline silicon layer 30 and the polycrystalline silicon layer 30 may be reduced, and the effect of improving the adhesion property may not be sufficient.

In consideration of this, the adhesive layer 422 may include titanium (Ti) having a thermal expansion coefficient of about 8.4 ppm / K or tungsten (W) having a thermal expansion coefficient of about 4.6 ppm / K, and may be made of titanium or tungsten .

When the adhesive layer 422 includes titanium or tungsten, the contact characteristics can be improved by reducing the thermal expansion coefficient between the polycrystalline silicon layer 30 and the first and second electrode portions 44 and 42.

And titanium or tungsten may function as a barrier for a material (e.g., copper) that constitutes a portion (e.g., the conductive layer 424 in this embodiment) adjacent to the adhesive layer 422 in the conductive layer 424 So that they can be prevented from diffusing into the polycrystalline silicon layer 30 or the semiconductor substrate 10.

As a result, it is possible to prevent a problem that may occur due to diffusion of the material constituting the conductive layer 424 into the polycrystalline silicon layer 30 or the semiconductor substrate 10.

At this time, the adhesive layer 422 according to the present embodiment may have transparency allowing light to pass therethrough. In the present embodiment, the thickness of the adhesive layer 422 is limited to a certain level or less so that the adhesive layer 422 can have permeability.

When the adhesive layer 422 has transparency as described above, light having passed through the adhesive layer 422 is reflected by a layer constituting a part of the conductive layer 424 or the conductive layer 424 formed on the adhesive layer 422, (10). ≪ / RTI >

Thus, the efficiency of the solar cell 100 can be improved by increasing the amount of light incident on the semiconductor substrate 10 and the residence time by reflecting the light through the first and second electrode portions 44 and 42.

Here, the term " permeability " includes not only a case of transmitting 100% of light but also a case of transmitting a part of light.

That is, the adhesive layer 422 may be composed of a metal light-transmitting film or an optical semipermeable film.

For example, the adhesive layer 422 may have a light transmittance of 50% to 100%, and more specifically, a light transmittance of 80% to 100%.

If the light transmittance of the adhesive layer 422 is less than 50%, the amount of light reflected by the conductive layer 424 is not sufficient, and it may be difficult to sufficiently improve the efficiency of the solar cell 100.

If the light transmittance of the adhesive layer 422 is 80% or more, the amount of light reflected by the conductive layer 424 can be further increased, thereby contributing to the improvement of the efficiency of the solar cell 100.

For this, the thickness of the adhesive layer 422 may be less than the thickness of the conductive layer 424. In this embodiment, the conductive layer 424 is formed of one layer, but the present invention is not limited thereto.

Therefore, the thickness of the adhesive layer 422 may be smaller than the thickness of each of the plurality of layers constituting the conductive layer 424. In this case, Whereby the adhesive layer 422 can be formed to have permeability.

Specifically, the thickness of the adhesive layer 422 may be 50 nm or less. If the thickness of the adhesive layer 422 exceeds 50 nm, the transmittance of the adhesive layer 422 may decrease and the amount of light directed to the conductive layer 424 may not be sufficient.

The thickness of the adhesive layer 422 may be 15 nm or less and the light transmittance of the adhesive layer 422 may be further improved.

Here, the thickness of the adhesive layer 422 may be 5 nm to 50 nm (for example, 5 nm to 15 nm).

When the thickness of the adhesive layer 422 is less than 5 nm, it may be difficult for the adhesive layer 422 to be uniformly formed on the polycrystalline silicon layer 30, and the effect of improving the adhesive property by the adhesive layer 422 may not be sufficient. However, the present invention is not limited to this, and the thickness of the adhesive layer 422 may be changed in consideration of material, process conditions, and the like.

The conductive layer 424 formed on the adhesive layer 422 may be composed of a single layer or may include a plurality of layers to improve various characteristics.

In this embodiment, the conductive layer 424 may be composed of a single layer formed between and in contact with the adhesive layer 422 and the capping layer 426.

The conductive layer 424 plays a role of lowering the resistance of the first and second electrode portions 44 and 42 and enhancing the electric conductivity, thereby transferring substantially the electric current.

And acts as a barrier to prevent the material constituting the capping layer 426 from being directed to the polycrystalline silicon layer 30 or the semiconductor substrate 10, and to perform reflection by the reflective material.

That is, the conductive layer 424 can perform both a role as a barrier layer and a role as a reflective layer.

The conductive layer 424 may be made of a metal having excellent reflection characteristics and conductivity, and may include, for example, copper, aluminum, silver, gold, or an alloy thereof.

The conductive layer 424 may have a thickness greater than the adhesive layer 422 and a thickness of 50 nm to 400 nm.

In one example, the thickness of the conductive layer 424 may be 100 nm to 400 nm (more specifically, 100 nm to 30 nm).

When the thickness of the conductive layer 424 is less than 50 nm, it may be difficult to perform the role of the barrier layer and the reflective layer. If the thickness of the conductive layer 424 exceeds 400 nm, the manufacturing cost may increase, .

If the thickness of the conductive layer 424 is 100 nm or more, the resistance can be lowered further. When the thickness of the conductive layer 424 is 30 nm or less, the effect of lowering the resistance is not greatly increased, and the peeling phenomenon due to the increase of the thermal stress can be effectively prevented. However, the present invention is not limited thereto, and the thickness of the conductive layer 424 may be varied.

A capping layer 426 may be formed over the conductive layer 424. As an example, a capping layer 426 may be formed over the conductive layer 424. The capping layer 426 may be a portion connected to the ribbon, and may include a material having excellent connection properties with the ribbon.

The capping layer 426 may have a nano-level thickness, for example, a thickness of 50 nm to 30 nm.

If the thickness of the capping layer 426 is less than 50 nm, the bonding properties with the ribbon may be deteriorated, and if it exceeds 30 nm, the manufacturing cost may increase. However, the present invention is not limited thereto, and the thickness of the capping layer 426 and the like can be variously changed.

The first electrode portion 44 and the second electrode portion 42 including the adhesive layer 422, the conductive layer 424 and the capping layer 426 as described above are formed by sputtering or the like Followed by patterning using a laser.

The conductive layer 424 and the capping layer 426 to fill the first opening 402 and the second opening 404 of the rear dielectric layer 40 formed on the rear surface of the semiconductor substrate 10, The adhesive layer 422, the conductive layer 424, and the capping layer 426 of the first and second electrode portions 44 and 42 are formed by patterning the electrode layer, Can be formed.

Accordingly, the first electrode portion 44 and the second electrode portion 42 do not include a binder, unlike the electrode portion formed by mixing the conductive particles with a binder such as resin.

As a method of patterning the electrode layer, a lift-off process using a laser can be applied. By using this process, an undercut (not shown) may be formed on the side of the adhesive layer 422, the conductive layer 424 and the capping layer 426. [ And the side surfaces of the first and second electrode portions 44 and 42 are formed at right angles to the surface of the rear dielectric layer or in an arc shape with the center of curvature being outside the side surface of the electrode portion.

The first electrode portion 44 and the second electrode portion 42 are formed such that the line width W1 of the first surface facing the semiconductor substrate 10 is larger than the line width W1 of the first surface facing the semiconductor substrate 10, Is substantially equal to the line width (W2) of the second surface located on the opposite side, or is larger than the line width (W2) of the second surface.

FIG. 1 shows a case where the line width W1 of the first surface of the first electrode portion 44 and the second electrode portion 42 is larger than the line width W2 of the second surface.

As described above, according to the sputtering process, since the material is deposited in the thickness direction of the solar cell 100, the adhesive layer 422 has a uniform thickness throughout the entire portion, the conductive layer 424 has a uniform thickness throughout, The capping layer 426 can be stacked to have a uniform thickness throughout. Here, the uniform thickness may mean a thickness (for example, a thickness having a difference of 10% or less) that can be judged to be uniform in consideration of process errors and the like.

The second electrode portion 42 may be formed to have a width larger than the width of the first opening portion 402. This sufficiently secures the line width of the second electrode portion 42 (the width of the first surface having the widest width of the portion constituting the first electrode 42) to reduce the resistance of the second electrode portion 42 It is for this reason.

For example, the width of the first opening 402 may be 10 um to 50 um, and the width of the second electrode portion 42 may be 200 um to 250 um.

If the width of the first opening portion 402 is less than 10 μm, the second electrode portion 42 and the first doped region 32 may not be connected smoothly. If the width of the first opening portion 402 exceeds 50 μm , There is a high possibility that the first doped region 32 may be damaged when the first opening 402 is formed.

If the line width of the second electrode unit 42 is less than 200 μm, the second electrode unit 42 may not have sufficient resistance. If the line width of the second electrode unit 42 exceeds 250 μm, A problem such as unnecessary short-circuiting with the power supply 44 may occur.

Similarly, the first electrode portion 44 may be formed to have a line width larger than that of the second opening portion 404.

For example, the width of the second opening 404 may be 10 [mu] m to 50 [mu] m, and the width of the first electrode portion 44 may be 200 [mu] m to 250 [mu] m. However, the present invention is not limited thereto, and the width of the openings 402 and 404 and the line width of the electrode portions 44 and 42 may have various values.

The second electrode portion 42 and in particular the adhesive layer 422 is formed on the bottom surface of the first opening portion 402 (the second opening portion 404 in the case of the first electrode portion 44) (The contact surface with the second doped region 32), the side of the rear dielectric layer 40 adjacent the first opening 402, and over the rear dielectric layer 40 adjacent the first opening 402 . That is, the second electrode portion 42 has a portion protruding outward from the rear dielectric layer 40.

The first and second electrode portions 44 and 42 are formed on the side surfaces and the rear surface of the rear dielectric layer 40 adjacent to the second and first openings 404 and 402, 44 and 42 are formed on the rear dielectric layer 40 as a whole and then patterned by a laser to form the first and second electrode portions 44 and 42. [

Thus, in this embodiment, the first and second electrode portions 44 and 42 are formed without using the plating process.

If a portion of the first and second electrode portions 44 and 42 is formed by plating, if there is a defect such as a pin hole or a scratch on the rear dielectric layer 40, the plating is also performed at that portion, .

Since the plating solution used in the plating process is acidic or alkaline, it may damage the rear dielectric layer 40 or deteriorate the characteristics of the rear dielectric layer 40.

In this embodiment, the characteristics of the rear dielectric layer 40 can be improved by using a sputtering process without using a plating process, and the first and second electrode portions 44 and 42 can be formed by a simple process have.

However, the present invention is not limited thereto, and the adhesive layer 422, the conductive layer 424, and the capping layer 426 may be formed by various methods.

1 and 2, the planar shape of the first doped region 32 and the second doped region 34, the intrinsic semiconductor layer 36, and the first and second electrode portions 44 and 42 Will be described in detail.

1 and 2, in the present embodiment, the first doped region 32 and the second doped region 34 are formed to have a long stripe shape, and the first doped region 32 and the second doped region 34, They are alternately located in two directions.

The intrinsic semiconductor layer 36 may be positioned between the first doped region 32 and the second doped region 34.

The area of the first doped region 32 may be greater than the area of the second doped region 34. In one example, the areas of the first doped region 32 and the second doped region 34 can be adjusted by varying their widths.

That is, the width W3 of the first doped region 32 may be greater than the width W4 of the second doped region 34. [

The second electrode portion 42 may be formed in a stripe shape corresponding to the first doped region 32 and the first electrode portion 44 may be formed in a stripe shape corresponding to the second doped region 34 .

Accordingly, the first electrode unit 44 includes a plurality of first finger electrodes extending in a first direction, and the second electrode unit 42 includes a plurality of second finger electrodes extending in a first direction.

Therefore, in the side surfaces of the first finger electrode and the second finger electrode facing each other, the gap D1 between the first dielectric layer and the first dielectric layer opposes the gap between the second dielectric layer and the second dielectric layer, (D2)

However, the present invention is not limited thereto, and the first and second electrode portions 44 and 42 may have various plan shapes.

Each of the first and second openings 402 and 404 may be formed in the entire length of the second and first electrode portions 42 and 44 corresponding to the second and first electrode portions 42 and 44.

The contact area between the first electrode portion 44 and the second doped region 32 and between the second electrode portion 42 and the first doped region 32 can be maximized to improve charge collection efficiency.

However, the present invention is not limited thereto. The first and second openings 402 and 404 may be formed to connect only a portion of the second and first electrode portions 42 and 44 to the first doped region 32 and the second doped region 34, respectively. Of course.

For example, the first and second openings 402 and 404 may be formed of a plurality of contact holes.

Although not shown in the drawing, the second electrode unit 42 further includes a second bus bar electrically and physically connecting the plurality of second finger electrodes at one edge thereof, and the first electrode unit 44 includes a plurality of And a first bus bar electrically and physically connecting the first finger electrodes to each other at the other edge. However, the present invention is not limited thereto.

1, a passivation film 24 and / or an antireflection film 26 (not shown) is formed on the front surface of the semiconductor substrate 10 (more precisely, on the front electrical part 130 formed on the front surface of the semiconductor substrate 10) ) Can be located.

Specifically, only the passivation film 24 may be formed on the semiconductor substrate 10, only the antireflection film 26 may be formed on the semiconductor substrate 10, and the passivation film 24 and the reflection film 24 may be formed on the semiconductor substrate 10. [ Barrier film 26 may be disposed one after the other.

In the figure, a passivation film 24 and an antireflection film 26 are sequentially formed on a semiconductor substrate 10, and the semiconductor substrate 10 is contacted with the passivation film 24. However, the present invention is not limited thereto, and the semiconductor substrate 10 may be formed in contact with the anti-reflection film 26, and various other modifications are possible.

The passivation film 24 and the antireflection film 26 may be formed entirely on the front surface of the semiconductor substrate 10 substantially. Here, the term " formed as a whole " includes not only completely formed physically but also includes cases where there are inevitably some exclusion parts.

The passivation film 24 contacts the front surface of the semiconductor substrate 10 and immobilizes defects existing in the front surface or bulk of the semiconductor substrate 10. Thus, the open-circuit voltage of the solar cell 100 can be increased by removing the recombination site of the small number of charges.

The antireflection film 26 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. The amount of light reaching the pn junction formed at the interface between the base region 110 and the first doped region 32 can be increased and the short circuit current Isc of the solar cell 100 can be increased.

In this way, the efficiency of the solar cell 100 can be improved by increasing the open-circuit voltage and the short-circuit current of the solar cell 100 by the passivation film 24 and the antireflection film 26.

The passivation film 24 and / or the antireflection film 26 may be formed of various materials.

For example, the passivation film 24 and / or the antireflection film 26 may include a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, a silicon carbide film, an aluminum oxide film, a group consisting of MgF2, ZnS, TiO2, and CeO2 Or a multilayer film structure in which two or more films are combined.

As an example, the passivation film 24 may comprise silicon oxide or silicon carbide, and the antireflective film 26 may comprise silicon nitride.

When light is incident on the solar cell 100 according to the present embodiment, the holes and electrons generated in the base region 110 tunnel through the rear tunnel layer 20 to form the first doped region 32 and the second doped region 34 to move to the second and first electrode portions 42, 44, thereby generating electrical energy.

Since the first and second doped regions 32 and 34 are formed on the semiconductor substrate 10 with the rear tunnel layer 20 interposed therebetween, the semiconductor substrate 10 and the semiconductor substrate 10 are separated from each other. Thus, the loss due to the recombination can be minimized as compared with the case where the doped region formed by doping the semiconductor substrate 10 with the impurity is used as the doped region.

In the solar cell 100 according to the present embodiment, the first and second electrode portions 44 and 42 are formed on the rear surface of the semiconductor substrate 10 and the rear surface electrode Structure.

As a result, shading loss can be minimized at the front surface of the semiconductor substrate 10, and the efficiency of the solar cell 100 can be improved.

In the solar cell 100 having the rear electrode structure, since the first and second electrode portions 44 and 42 are located together on the rear side of the semiconductor substrate 10, an electrode layer is formed entirely on the rear side of the semiconductor substrate 10 And the first and second electrode portions 44 and 42 are formed by patterning the same.

Conventionally, etching solutions such as acid series are used for patterning. In this case, however, problems such as degradation of the passivation property due to the etching solution and damage to the first and second doped regions 32 and 34 .

This problem can be largely observed in the solar cell 100 having the rear electrode structure in which the first and second electrode portions 44 and 42 are located together on the rear side to pattern the electrode layer more precisely.

In consideration of this, in the manufacturing method of the solar cell 100 according to the present embodiment, the first and second electrode portions 44 and 42 are patterned without using a series-type etching solution.

An example of a manufacturing method of a solar cell according to this embodiment will be described in more detail with reference to FIGS. 3A to 3N.

3A to 3N are cross-sectional views illustrating a method of manufacturing a solar cell 100 according to an embodiment of the present invention.

First, as shown in FIG. 3A, a semiconductor substrate 10 composed of a base region 110 having a first conductive impurity is prepared.

In this embodiment, the semiconductor substrate 10 may be made of a silicon substrate (for example, a silicon wafer) having an n-type impurity. As the n-type impurity, phosphorus (P), arsenic (As), bismuth , Antimony (Sb), and the like can be used.

However, the present invention is not limited thereto, and the base region 110 may include a p-type impurity.

Both sides of the semiconductor substrate 10 can be mirror-polished and untextured.

Subsequently, as shown in FIG. 3B, a rear tunnel layer 20 is formed on the rear surface of the semiconductor substrate 10. The rear tunnel layer 20 may be formed entirely on the rear surface of the semiconductor substrate 10.

Here, the rear tunnel layer 20 can be formed by, for example, thermal growth, vapor deposition (for example, chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like). However, the present invention is not limited thereto, and the rear tunnel layer 20 may be formed by various methods.

3C to 3J, a polycrystalline silicon layer 30 (not shown) including a first doped region 32, a second doped region 34 and an intrinsic semiconductor layer 36 is formed on the rear tunnel layer 20, ). This will be described in more detail as follows.

First, as shown in FIG. 3C, a semiconductor layer 30 having intrinsic property is formed on the rear tunnel layer 20.

The semiconductor layer 30 may be composed of microcrystalline silicon, amorphous silicon, or polycrystalline silicon. In this embodiment, polycrystalline silicon is used as an example.

The intrinsic semiconductor layer, for example, the polycrystalline silicon layer 30 can be formed by a thermal growth method, a deposition method (for example, chemical vapor deposition (PECVD)), or the like. However, the present invention is not limited thereto, and the polycrystalline silicon layer 30 may be formed by various methods.

Then, the polycrystalline silicon layer 30 is doped to form the first doped region 32, the second doped region 34, and the intrinsic semiconductor layer 36, as shown in FIGS. 3D to 3J.

For example, a region corresponding to the first doped region 32 is doped with a second conductive dopant by various methods such as ion implantation, thermal diffusion, laser doping, etc., and a region corresponding to the second doped region 34 The first conductive impurity may be doped by various methods such as ion implantation, thermal diffusion, and laser doping.

Thus, the region located between the first doped region 32 and the second doped region 34 constitutes the intrinsic semiconductor layer 36.

For example, a first mask layer 302 is formed on the polycrystalline silicon layer 30, as shown in FIG. 3D.

The first mask layer 302 is removed by patterning so that impurities can be doped into a first opening portion 302a (FIG. 3E, the same applies hereinafter), and the portion covered by the first mask layer 302 It can prevent impurities from being doped.

The first mask layer 302 may be made of a material that can effectively prevent doping of impurities and that can be easily patterned.

In one example, the first mask layer 302 may be composed of a silicon carbide film (silicon carbide film) containing silicon carbide (silicon carbide). The first mask layer 302 made of a silicon carbide film can be easily patterned by a laser, and doping of the impurity can be effectively prevented.

However, the present invention is not limited thereto, and the first mask layer 302 may be composed of a silicon nitride film (silicon nitride film) or the like containing silicon nitride (silicon nitride).

The first mask layer 302 formed of a silicon nitride film can be easily formed by a deposition process or the like, and can be easily patterned using an etching solution, an etching paste, a laser, or the like. In addition, the first mask layer 302 may comprise a variety of materials.

The first mask layer 302 may be formed by various methods. For example, when the first mask layer 302 is formed of a silicon carbide film, the first mask layer 302 may be formed by chemical vapor deposition using silane (SiH4) gas and methane (CH4) gas. However, the present invention is not limited thereto.

Next, as shown in FIG. 3E, a portion where the first doped region 32 is to be formed in the first mask layer 302 is removed to form the first opening portion 302a.

The first opening portion 302a may be formed by a variety of patterning methods. For example, the first opening portion 302a may be formed by the laser 310. That is, the first opening portion 302a can be formed by laser ablation that selectively heats the first mask layer 302 using the laser 310 to remove the corresponding portion.

By forming the first opening portion 302a using the laser 310 as described above, the first opening portion 302a having a desired shape and width can be easily formed. However, the present invention is not limited thereto, and various known patterning methods such as photolithography and etching paste can be applied.

In the present embodiment, the first mask layer 302 is formed on the polycrystalline silicon layer 30 as a whole, and then the first opening portion 302a is formed by patterning.

However, the present invention is not limited to this, and the first mask layer 302 may be formed with a first opening portion 302a by various methods such as using a separate mask when depositing the first mask layer 302, Can be formed.

Then, as shown in FIG. 3F, a first doped region 32 is formed.

More specifically, the polycrystalline silicon layer 30 exposed by the first opening portion 302a on the rear surface side of the semiconductor substrate 10 is doped with the second conductive impurity, and the portion corresponding to the first opening portion 302a is doped Thereby forming a first doped region 32.

At this time, the first doped region 32 may be formed by an ion implantation method, a thermal diffusion method, or the like, in particular, by ion implantation. If the first doped region 32 is formed by the ion implantation method, the first doped region 32 can be stably improved only on the rear surface of the semiconductor substrate 10.

Then, as shown in Fig. 3G, the first mask layer 302 is removed. The first mask layer 302 may be removed by a variety of known methods.

For example, when the first mask layer 302 is composed of a silicon carbide film, heat treatment is performed at an elevated temperature (for example, 500 ° C to 600 ° C) to convert the silicon carbide film to a silicon oxide film, (diluted HF).

However, the present invention is not limited thereto, and various methods can be used depending on the material of the first mask layer 302.

Then, as shown in FIG. 3H, a second mask layer 304 is formed on the polycrystalline silicon layer 30. Next, as shown in FIG.

The second mask layer 304 allows the impurity to be doped into the second opening portion (reference numeral 304a in FIG. 3K) removed by patterning, and the portion covered by the second mask layer 304 is doped with impurities It can be a role to prevent.

This second mask layer 304 can be made of a material that can effectively prevent doping of impurities and that can be easily patterned.

As an example, the second mask layer 304 may be composed of a silicon carbide film containing silicon carbide. However, the present invention is not limited thereto, and the second mask layer 304 may be composed of various materials such as a silicon nitride film.

The material, manufacturing method, etc. of the second mask layer 304 may be applied to the material of the first mask layer 302, and the detailed description thereof will be omitted.

3I, a portion of the second mask layer 304 where the second doped region 34 is to be formed is removed to texture the front surface of the semiconductor substrate 10 to form a second opening portion 304a, .

Wet etching or dry etching may be used for texturing the front surface of the semiconductor substrate 10.

The wet etching can be performed by immersing the semiconductor substrate 10 in an etching solution, and has a short process time.

If wet etching is applied, texturing may be performed prior to forming the second opening portion 304a. Then, the second mask layer 304a acts as a mask, thereby preventing the occurrence of the texturing on the back surface of the semiconductor substrate 10.

When dry etching is applied, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like.

Such a dry etching can be performed before forming the second opening portion 304a, or even after forming the second opening portion 304a.

As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

In this embodiment, the texturing of the entire surface of the semiconductor substrate 10 is performed after the second mask layer 304 is formed, so that damage, deterioration in characteristics, undesired It may also serve to remove the front surface portion of the semiconductor substrate 10 in which oxide film formation or undesired doping of impurities occurs.

However, the present invention is not limited thereto, and the texturing process may be performed before forming the rear tunnel layer 20, and various other modifications are possible.

The second opening portion 304a may be formed by a variety of patterning methods, such as by laser 310, for example.

That is, the second opening portion 304a can be formed by laser ablation that selectively heats the second mask layer 304 using the laser 310 to remove the corresponding portion.

By forming the second opening portion 304a using the laser 310 as described above, the second opening portion 304a having a desired shape and width can be easily formed. However, the present invention is not limited thereto, and various known patterning methods such as photolithography and etching paste can be applied.

In this embodiment, the second mask layer 304 is entirely formed on the intrinsic semiconductor layer 30 and then the second opening portion 304a is formed by patterning.

However, the present invention is not limited thereto, and the second mask layer 304 may be formed in a state of having the second opening portion 304a by various methods such as using a separate mask when depositing the second mask layer 304, Can be formed.

Next, as shown in FIG. 3J, a second doped region 34 is formed and the second mask layer 304 is removed.

More specifically, the polycrystalline silicon layer 30 exposed by the second opening portion 304a is doped with a first conductive impurity to form a second doped region 34 at a portion corresponding to the second opening portion 304a .

Thus, the region located between the first doped region 32 and the second doped region 34 constitutes the intrinsic semiconductor layer 36. At this time, the front electric part 130 formed on the front surface of the semiconductor substrate 10 and having the first conductive impurities may be formed together.

At this time, the second doped region 34 may be formed by an ion implantation method, a thermal diffusion method, or the like, in particular, by a heat diffusion method.

If the second doped region 34 is formed by the thermal diffusion method, the front electrical portion 130 can be formed on the entire surface of the semiconductor substrate 10 without adding a separate process.

In addition, the activation heat treatment of the second conductive impurity in the first doped region 32 implanted by the ion implantation method or the like can be performed simultaneously during the process of the heat diffusion method.

In this embodiment, the first doped region 32 to be formed first is formed by ion implantation, the second doped region 34 to be formed thereafter is formed by thermal diffusion, and an activation heat treatment to be performed at the time of ion implantation is performed Can be performed together at the second doped region 34. Thus, the process can be simplified.

Here, boron may be used as an impurity forming the first doped region 32, and phosphorus may be used as an impurity forming the second doped region 34.

In this case, boron is first doped to form the first doped region 32, and then heat treatment is performed to form the second doped region 34, thereby preventing deterioration of the characteristics of the solar cell 100.

Conversely, if the first doped region 32 is formed by ion implantation after the second doped region 34 is formed first, a separate activation heat treatment process for the first doped region 32 must be performed, Phosphorus, which is an impurity in the second doped region 34, can be deeply doped in a separate activation heat treatment process for the first doped region 32. In particular, the phosphorus located in the front electrical portion 130 may be deeply doped into the semiconductor substrate 10, thereby lowering the open-circuit voltage.

The method of removing the second mask layer 304 is the same as or very similar to the method of removing the first mask layer 302 and therefore the description of the method of removing the first mask layer 302 can be applied as it is.

The above description is merely an example of a manufacturing process of the polycrystalline silicon layer 30 including the first and second doped regions 32 and 34, but the present invention is not limited thereto.

Accordingly, various methods known as methods for forming the first and second doped regions 32 and 34 and the intrinsic semiconductor layer 36 can be used. And that the intrinsic semiconductor layer 36 is not formed.

3C, a passivation film 24 and an antireflection film 26 are formed on the entire surface of the semiconductor substrate 10, and a rear dielectric layer 40 is formed on the rear surface of the semiconductor substrate 10. Next, as shown in FIG.

The passivation film 24 and the antireflection film 26 may be entirely formed on the entire surface of the semiconductor substrate 10 and the rear dielectric layer 40 may be formed entirely on the polycrystalline silicon layer 30. [

The passivation film 24, the antireflection film 26 and the rear dielectric layer 40 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing or spray coating.

At this time, the rear dielectric layer 40 may be formed of any one of a silicon oxide film, a silicon nitride film, and a silicon carbide film, and may include first and second openings 402 and 404. The first and second openings 402 and 404 may be formed by laser ablation. However, the present invention is not limited thereto.

The rear dielectric layer 40 may be formed of at least one of the materials having a bandgap higher than the bandgap of the laser in the patterning process of the electrode layer described later.

Then, first and second electrodes 44 and 42 connected to the first and second doped regions 32 and 34 are formed, respectively, as shown in Figs. 3L through 3M.

An electrode layer 400 constituting the first and second electrode portions 44 and 42 is formed on the rear dielectric layer 40 formed on the rear surface of the semiconductor substrate 10 by sputtering .

The electrode layer 400 is entirely formed on the rear side of the semiconductor substrate 10 (more precisely on the polycrystalline silicon layer 30 and the rear dielectric layer 40) while filling the inside of the first and second openings 402 and 404 .

The electrode layer 400 includes a polycrystalline silicon layer 30 exposed by the first and second openings 402 and 404 and a side surface of the first and second openings 402 and 404, Or the like.

In this embodiment, the thickness T2 of the electrode layer 400 can be varied in various ways. For example, the thickness T2 of the electrode layer 400 may be 100 nm to 750 nm. This is in consideration of the thicknesses of the adhesive layer 422, the conductive layer 424, and the capping layer 426 described above.

However, the present invention is not limited thereto, and the thickness T2 of the electrode layer 400 may be variously changed according to the lamination structure, materials, and the like of the electrode layer 400.

3L and 3M, the laser 320 is irradiated to the electrode layer 400 in the emitter region and the rear electric field region, particularly, the electrode layer 400 in the region not overlapping the opening portion on the projection plane, The first and second electrode portions 44 and 42 are formed.

The laser 320 for patterning the electrode layer 400 may have a bandgap smaller than the bandgap of the material forming the rear dielectric layer so that the wavelength of the laser light is not absorbed by the rear dielectric layer, In particular, a pulse laser having a wavelength of 532 nm and having a Gaussian distribution of energy intensity in the cross section of the laser beam can be used.

When the laser has a wavelength of 1,200 nm, the band gap is approximately 3 or less.

Accordingly, when the rear dielectric layer is formed of a material having a bandgap of 3 or less, the laser is transmitted through the rear dielectric layer, and only the metal layer 400 can be removed by adjusting the power of the laser.

In a lift-off process using a laser, a metal layer is melted and vaporized by a laser to remove a portion irradiated with the laser, or a part of the rear dielectric layer acts as a sacrifice layer due to energy of a laser transmitted to the rear dielectric layer So that the metal layer 400 can be removed while the sacrificial layer is explosion. In the latter case, a lower power than the former case can be used.

Thus, by appropriately adjusting the laser power, only the electrode layer 400 deposited on the rear dielectric layer 40 can be selectively removed.

The laser 320 may have a pulse width of pico seconds or nanoseconds and a frequency of several hertz (Hz) to several hundred kilohertz (kHz).

The laser 320 for patterning the electrode layer 400 and the lasers 310 used to form the opening portions 302a and 304a in the mask layers 302 and 304 may be the same or different from each other .

As described above, since the laser 320 follows the Gaussian distribution, the remaining electrode layer that is not removed by the laser 320, i.e., the first and second electrode portions 44 and 42, The line width W1 of the first surface facing the semiconductor substrate can be made larger than the line width W2 of the second surface.

On the contrary, if the laser beam whose energy density is uniformly adjusted is used, the line width W1 of the first surface of the portion of the first and second electrode portions 44 and 42 protruding outward from the rear dielectric layer, The line width W2 of the two surfaces may be formed to be substantially the same.

Therefore, when the first and second electrode portions 44 and 42 are formed by patterning the electrode layer 400 by a laser lift-off process, undercuts do not occur unlike wet etching.

Hereinafter, a solar cell according to a second embodiment of the present invention and a method of manufacturing the same will be described with reference to FIGS.

The solar cell according to the second embodiment has the same or similar structure as the solar cell of the first embodiment except that the rear dielectric layer 40 is composed of the silicon nitride film 40a and the silicon carbide film 40b. Therefore, only the constitution related to the rear dielectric layer 40 will be described below.

The rear dielectric layer 40 is formed of a laminated structure of a silicon nitride film 40a and a silicon carbide film 40b. The silicon carbide film 40b has a characteristic of being more explosive due to thermal explosion compared with the silicon nitride film 40a Lt; / RTI >

Accordingly, the silicon carbide film 40b acts as a sacrificial layer when patterning the electrode layer 400 by the lift-off process using the laser 320, thereby more effectively removing the electrode layer 400. [

At this time, when the silicon carbide film 40b is used as a sacrificial layer, it is possible to use a laser with lower power than the first embodiment, so that damage to the lower portion of the rear dielectric layer can be suppressed.

Generally, as the frequency of the laser increases, the pulse width increases and as the power of the laser increases, the pulse width decreases.

Accordingly, the silicon carbide film 40b of the rear dielectric layer 40 can be selectively removed by appropriately adjusting the power, frequency, pulse width, and the like of the laser.

When the electrode layer 400 and the silicon carbide film 40b in the region irradiated with the laser 320 are removed by using the silicon carbide film 40b as a sacrifice layer, the silicon carbide film 40b is formed on the silicon nitride film 40a, (400), and may include first and second opening portions (402, 404) formed in the silicon nitride film (40a).

That is, in the solar cell of this embodiment, after forming the first doped region 32, the second doped region 34, and the intrinsic semiconductor layer 36 therebetween in accordance with the steps shown in FIGS. 3A to 3J, 5A, a rear dielectric layer 40 (a laminated structure of a silicon nitride film and a silicon carbide film) is formed on the entire rear surface of the polycrystalline silicon layer 30, and first and second opening portions The electrode layer 400 is formed as shown in FIG. 5B and a lift-off process using a laser is performed to form the silicon carbide film 40b and the electrode layer 400 in the region irradiated with the laser, The first and second electrode portions 44 and 42 may be formed by removing the first and second electrode portions 44 and 42. [

Hereinafter, a solar cell according to a third embodiment of the present invention will be described with reference to FIG.

Although the solar cells of the first and second embodiments described above are formed with the rear electrode structure in which both the first and second electrode portions 44 and 42 are located on the rear surface of the substrate, The electrode portions 144 and 142 are formed in a double-sided electrode structure in which they are respectively located on different surfaces of the substrate.

The solar cell includes a semiconductor substrate 110, a first doped region 132 located on the front surface of the substrate 110 and serving as an emitter region, a second doped region 132 located above the first doped region 132, And a second electrode portion 142 electrically and physically connected to the first doped region 132 through an opening formed in the front dielectric layer 124. The second electrode portion 142 is electrically and physically connected to the first doped region 132 through the front dielectric layer 124, A second doped region 34 located on the back surface of the substrate 110 and functioning as a rear electric field portion, and a second doped region 34 located on the rear surface of the substrate 110 and having an antireflection function or a passivation function and an anti- And a first electrode portion 144 electrically and physically connected to the second doped region 134 through an opening formed in the rear dielectric layer 140 and the rear dielectric layer 140. Referring to FIG.

The first electrode part 144 is formed in the same lamination structure and sectional structure as the first electrode part 44 of the first and second embodiments and the second electrode part 142 is formed of the first electrode part 144 144, or other laminated structure and a cross-sectional structure.

Hereinafter, the second electrode unit 142 is formed to have a laminated structure and a cross-sectional structure different from those of the first electrode unit 144. However, as described above, Layer structure and the cross-sectional structure.

The second electrode portion 142 is disposed on the first doped region 132, that is, the emitter portion, of the front surface of the substrate, and includes a plurality of second finger electrodes 142A And a plurality of second bus bar electrodes 142B extending in a second direction Y perpendicular to the first direction.

Unlike the first electrode part 144, the second electrode part 142 having such a structure may be formed by a screen printing method for printing and firing a conductive paste containing a conductive material, or may be formed by a plating process using a seed layer As shown in FIG.

The first electrode unit 144 includes a plurality of first finger electrodes 144A extending in the first direction and a plurality of first finger electrodes 144A electrically and physically connecting the plurality of first finger electrodes 144A in the second direction. And a bus bar electrode 144B.

The first bus bar electrode 144B may be located at a position facing the second bus bar electrode 142B and the first finger electrode 144A may be positioned at the same position as or different from the width of the second finger electrode 142A. Width.

The first finger electrode 144A and the first bus bar electrode 144B have the same lamination structure and cross-sectional structure as the first electrode portion 44 of the first and second embodiments described above.

Therefore, in the side surfaces of the pair of first finger electrodes 144A facing each other, the interval D3 between the first surfaces can be made smaller than the interval D4 between the second surfaces.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment.

Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

10: semiconductor substrate 20: rear tunnel layer
30: polycrystalline silicon layer 32: first doped region
34: second doped region 36: intrinsic semiconductor layer
40: rear dielectric layer 42: second electrode portion
44: first electrode portion

Claims (20)

A semiconductor substrate;
A rear electric field portion located on a rear surface of the semiconductor substrate;
An emitter section located on one surface selected from the front surface of the semiconductor substrate or the rear surface of the semiconductor substrate;
A rear dielectric layer located on a rear surface of the semiconductor substrate and including an opening exposing the rear electric field portion or an opening exposing the emitter portion and the rear electric field portion, respectively;
A first electrode part electrically and physically connected to the rear electric part through the opening; And
A second electrode part electrically and physically connected to the emitter part,
Lt; / RTI >
The rear dielectric layer is formed of a silicon carbide layer serving as a sacrificial layer, and a silicon nitride layer positioned between the silicon carbide layer and the rear surface of the semiconductor substrate, wherein the electrode layer is located on the rear surface of the semiconductor substrate Wherein only the silicon nitride film is formed in a region of the rear surface of the semiconductor substrate where no electrode is formed,
Wherein the first electrode portion is formed such that a line width of a first surface facing the semiconductor substrate is larger than a line width of a second surface located on the opposite side of the first surface. delete The method of claim 1,
Wherein the first electrode portion includes a plurality of first finger electrodes extending in a first direction and spaced apart from each other and the second electrode portion includes a plurality of second finger electrodes extending in the first direction and spaced apart from each other, . 4. The method of claim 3,
Wherein the emitter electrode and the second electrode are located on the rear surface of the semiconductor substrate and protrude to the outside of the rear dielectric layer, wherein the second electrode unit has a line width of the first surface facing the semiconductor substrate, Is larger than the line width of the second surface located on the second surface. 5. The method of claim 4,
Wherein the first finger electrode and the second finger electrode are spaced apart from each other, and a side surface of the first finger electrode facing the first finger electrode and a side surface of the second finger electrode have a gap between the first surface and the second surface, Of the solar cell. The method of claim 5,
Wherein the emitter portion and the rear surface electric portion are each formed of a polycrystalline silicon layer. The method of claim 6,
And an intrinsic semiconductor layer disposed between the emitter section and the rear electric field section and formed of a polycrystalline silicon layer. 8. The method of claim 7,
And a rear tunnel layer located between the rear surface of the semiconductor substrate and the polycrystalline silicon layer. delete 9. The method of claim 8,
Wherein the silicon carbide film is not located on the silicon nitride film located between the first electrode portion and the second electrode portion. 4. The method of claim 3,
Wherein the emitter portion and the second electrode portion are located on a front surface of the semiconductor substrate and are spaced apart from each other by a distance between the first and second surfaces of the pair of first finger electrodes facing each other, Small size solar cells. Forming an emitter portion and a rear surface electric portion on a rear surface of the semiconductor substrate;
Forming a rear dielectric layer on the rear surface of the semiconductor substrate, the rear dielectric layer including an opening exposing the emitter portion and the rear surface portion, respectively; And
Forming an electrode layer electrically and physically connected to the rear electrical part and the emitter part through the opening part on the entire rear surface of the rear dielectric layer; And
Separating the electrode layer into a first electrode portion connected to the rear electric field portion and a second electrode portion electrically and physically connected to the emitter portion, respectively
Lt; / RTI >
Wherein the rear dielectric layer is formed of a silicon carbide film serving as a sacrificial layer and a silicon nitride film formed between the silicon carbide film and the rear surface of the semiconductor substrate,
And separating the electrode layer into the first electrode portion and the second electrode portion,
Wherein the electrode layer of the emitter region and the rear electric field region has a wavelength of 30 nm to 1,200 nm and has a bandgap below the bandgap of the material forming the rear dielectric layer and the energy intensity of the laser beam has a Gaussian distribution A step of irradiating a pulse laser to remove an electrode layer of the region irradiated with the laser
Lt; / RTI >
The silicon carbide film in the region irradiated with the laser is removed together with the electrode layer in the region irradiated with the laser when the electrode layer in the region irradiated with the laser is removed so that the laminated structure of the rear dielectric layer is formed on the rear surface of the semiconductor substrate Wherein the laser is formed only in the region not irradiated with the laser. The method of claim 12,
Wherein the first electrode portion and the second electrode portion are formed such that a line width of a first surface facing the semiconductor substrate is larger than a line width of a second surface located on the opposite side of the first surface, And the second electrode is larger than the first electrode. delete delete 14. The method according to claim 12 or 13,
Wherein the electrode layer is formed by a sputtering method. 14. The method according to claim 12 or 13,
Wherein forming the emitter portion and the backside electric field portion comprises:
Forming a polycrystalline silicon layer on a rear surface of the semiconductor substrate; And
Selectively implanting or diffusing a second conductive impurity and a first conductive impurity into a part of the polycrystalline silicon layer
Wherein the method comprises the steps of: The method of claim 17,
Wherein the emitter portion and the rear surface electric portion are spaced apart from each other to form an intrinsic semiconductor layer formed of the polycrystalline silicon layer between the emitter portion and the rear electric field portion. The method of claim 17,
And forming a rear tunnel layer between the rear surface of the semiconductor substrate and the polycrystalline silicon layer. 20. The method of claim 19,
Wherein the rear dielectric layer is formed by laminating a silicon nitride film and a silicon carbide film,
Wherein the silicon carbide film is used as a sacrificial layer to remove the silicon carbide film in the region irradiated with the laser when the electrode layer of the laser irradiated region is removed so that the silicon nitride film and the silicon nitride film And the silicon carbide film located between the first electrode portion and the second electrode portion.

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