KR20200125067A - Manufacturing method of heterojunction solar cell - Google Patents

Abstract

The present invention relates to a method of manufacturing a heterojunction solar cell. According to an embodiment of the present invention, a method of manufacturing a heterojunction solar cell comprises: an n-type film forming step of forming a first conductivity-type region that is an n-type silicon layer made of an amorphous material and contains impurities of an n-type conductivity type on a first surface of a semiconductor substrate made of crystalline silicon; and a p-type film forming step of forming a second conductivity-type region on a second surface of the semiconductor substrate opposite the first surface, which is a p-type silicon layer made of an amorphous material and contains impurities of a p-type conductivity type. The method of manufacturing a heterojunction solar cell further comprises a plasma processing step of plasma treating ammonia gas (NH3) on at least one among the silicon semiconductor substrate, the first conductivity-type region, and the second conductivity-type region.

Description

Heterojunction solar cell manufacturing method {Manufacturing method of heterojunction solar cell}

The present invention relates to a method of manufacturing a heterojunction solar cell, and more particularly, to a method of manufacturing a heterojunction solar cell to which a plasma treatment using ammonia gas (NH3) is applied in order to further improve passivation quality.

A heterojunction solar cell is a solar cell in which an amorphous silicon layer is formed on a surface of a crystalline semiconductor substrate. Since the crystalline semiconductor substrate and the amorphous silicon layer have a heterojunction structure with each other, there is an advantage of obtaining a high open-circuit voltage.

However, since the heterojunction solar cell has a structure in which an amorphous silicon layer is formed directly on the crystalline silicon semiconductor substrate, there are many surface defects between the crystalline silicon semiconductor substrate and the amorphous silicon layer, so there is a problem that carriers recombine. There is a problem in that the efficiency of the battery is lowered.

To improve this, in manufacturing a heterojunction solar cell, in order to remove defects on the surface of the crystalline silicon semiconductor substrate and the surface of the amorphous silicon layer, and to secure a passivation function, the surface of the semiconductor substrate is plasma treated or , After forming the first and second conductivity type regions, which are amorphous silicon layers, the surfaces of the first and second conductivity type regions have been subjected to plasma treatment using hydrogen gas.

However, such hydrogen plasma treatment has a relatively large dissociation energy of hydrogen bonds (for example, 104 kcal/mol), and requires high power to maintain the hydrogen gas in a plasma state. If hydrogen in the plasma state formed by is treated on the surface of a crystalline semiconductor substrate or the surface of amorphous first and second conductivity type regions, it has the effect of passivating the surface, but due to the high output of the plasma equipment, the surface of the semiconductor substrate or amorphous silicon There is a problem that damage occurs on the surface of the layer.

KR2017-0165374A

An object of the present invention is to provide a method of manufacturing a heterojunction solar cell in which efficiency can be further improved.

More specifically, in manufacturing a heterojunction solar cell, the present invention uses ammonia gas having a relatively low dissociation energy to plasma the surface of the semiconductor substrate or the surface of the amorphous silicon layer, thereby further improving the passivation quality of the film. An object of the present invention is to provide a method for manufacturing a heterojunction solar cell.

The method of manufacturing a heterojunction solar cell according to an example of the present invention includes an n-type conductivity type impurity on a first surface of a semiconductor substrate made of crystalline silicon, and forms a first conductivity-type region that is an n-type silicon layer of an amorphous material. Forming a mold; And forming a second conductivity-type region, which is a p-type film silicon layer made of an amorphous material and containing an impurity of a p-type conductivity type, on a second surface of the semiconductor substrate opposite the first surface. And a plasma processing step of plasma-processing ammonia gas (NH3) on at least one of the semiconductor substrate, the first conductivity type region, and the second conductivity type region.

The plasma treatment step is performed on the n-type silicon layer and the p-type silicon layer after each n-type film formation step and p-type film formation step, but the flow rate of ammonia gas during plasma treatment on the p-type silicon layer is n-type silicon It may be higher than the flow rate of ammonia gas during plasma treatment for the layer.

The plasma treatment step is further performed on the first side and the second side of the silicon semiconductor substrate before the n-type film formation step and the p-type film formation step, but the flow rate of ammonia gas during plasma treatment on the first side of the silicon semiconductor substrate The flow rates of the ammonia gas during the plasma treatment on the second surface of the silicon semiconductor substrate may be the same.

In addition, prior to the n-type film forming step, a first passivation layer forming step of forming a first passivation layer made of an intrinsic silicon layer on the first surface of the semiconductor substrate; And before the p-type film forming step, on the second surface of the semiconductor substrate A second passivation layer forming step of forming a second passivation layer made of an intrinsic silicon layer may be further provided.

In this case, the plasma treatment step is further performed on the first passivation layer and the second passivation layer after each of the first passivation layer formation step and the second passivation layer formation step, but during the plasma treatment of the first passivation layer The flow rate of the ammonia gas in the second passivation layer and the flow rate of the ammonia gas during the plasma treatment may be the same.

In addition, the first and second conductivity-type regions formed by the n-type film formation step and the p-type film formation step are at least one of an amorphous silicon material or a microcrystalline silicon material, and the first passivation layer formation step and the second passivation layer formation step The first and second passivation layers formed by this may be at least one of an amorphous silicon oxide material, an amorphous silicon material, or a microcrystalline silicon material.

In addition, in the solar cell manufacturing method, after the n-type film formation step and the p-type film formation step are performed, a transparent electrode is formed by depositing a first transparent electrode layer on each of the first conductive type region and the second transparent electrode layer on the second conductive type region. step; And an electrode forming step of forming first and second electrodes on each of the first and second transparent electrode layers.

The n-type film formation step includes forming a first n-type film on the silicon semiconductor substrate by depositing a first n-type film silicon layer containing impurities of a first concentration of n-type conductivity type; and a first concentration higher than the first concentration on the first n-type film silicon layer. A second n-type film forming step of depositing a second n-type film silicon layer containing impurities of an n-type conductivity type having a high second concentration; and the plasma treatment step includes each of the first n-type film forming steps and the second n After the formation of the first and second n-type silicon layers, the flow rate of ammonia gas in the plasma treatment for the first n-type silicon layer is ammonia in the plasma treatment for the second n-type silicon layer. May be more than the gas flow rate.

In addition, the p-type film forming step includes a first p-type film forming step of depositing a first p-type film silicon layer containing a first p-type conductivity type impurity on a silicon semiconductor substrate; and a first p-type film on the silicon layer. A second p-type film forming step of depositing a second p-type film silicon layer containing an impurity of a p-type conductivity type having a second concentration higher than the concentration, and the plasma treatment step includes, respectively, the first p-type film forming step and the first 2 After the p-type film formation step, it is performed on each of the first and second p-type silicon layers, but the flow rate of ammonia gas in the plasma treatment for the first p-type silicon layer is when plasma treatment for the second p-type silicon layer. May be higher than the flow rate of ammonia gas.

In the present invention, in manufacturing a heterojunction solar cell, the surface of at least one of a silicon semiconductor substrate, a first conductivity type region, and a second conductivity type region is plasma-treated using ammonia gas, thereby further improving passivation quality, and The short-circuit current of the junction solar cell can be further improved, and efficiency can be further improved.

1 is a diagram for explaining an example of a heterojunction solar cell manufactured according to the present invention.
2 is a flow chart illustrating a method of manufacturing the heterojunction solar cell shown in FIG. 1 according to an example of the present invention.
3 is a view for explaining a comparison of the flow rate of ammonia gas during ammonia plasma treatment applied to a method of manufacturing a heterojunction solar cell.
4 is a diagram illustrating another example of a heterojunction solar cell manufactured according to the present invention.
5 is a flowchart illustrating a method of manufacturing the heterojunction solar cell shown in FIG. 4.
6 is a view for explaining a comparison of the flow rate of ammonia gas during ammonia plasma treatment applied to the method of manufacturing the heterojunction solar cell shown in FIG. 5.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art can easily implement the embodiments of the present invention. However, the present invention may be implemented in various different forms and is not limited to the embodiments described herein. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and similar reference numerals are assigned to similar parts throughout the specification.

In the drawings, the thicknesses are enlarged to clearly express various layers and regions. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the case where the other part is "directly above", but also the case where the other part is in the middle. Conversely, when one part is "right above" another part, it means that there is no other part in the middle. In addition, when a part is "overall" formed on another part, it means that it is formed not only on the entire surface (or front) of the other part, but also not formed on a part of the edge.

In addition, in the following, the meaning that the thickness, width, or length of a certain component is the same means that the thickness, width, or length of a first component is compared with the thickness, width, or length of another second component in consideration of process errors. Thus, it means a case in the 10% error range.

Hereinafter, the first surface of the semiconductor substrate refers to any one of the planes of the semiconductor substrate, and the second surface of the semiconductor substrate refers to a surface located opposite the first surface of the semiconductor substrate.

Then, the present invention will be described with reference to the accompanying drawings.

1 is a diagram for explaining an example of a solar cell manufactured according to the present invention.

Referring to FIG. 1, the solar cell according to the present embodiment includes a semiconductor substrate 10 including a base region 110 and a first surface (for example, a front surface) of the semiconductor substrate 10. A passivation layer 21, a second passivation layer 31 formed on a second surface (for example, a rear surface) of the semiconductor substrate 10, and a first passivation layer 21 from the first surface side of the semiconductor substrate 10 ) Formed on the first conductivity type region 20 having a first conductivity type, and a second conductivity type formed on the second passivation layer 31 from the second surface side of the semiconductor substrate 10 and having a second conductivity type A region 30, a first electrode 40 electrically connected to the first conductivity type region 20, and a second electrode 50 electrically connected to the second conductivity type region 30. have.

The semiconductor substrate 10 may include a base region 110 having a first or second conductivity type by including impurities at a relatively low doping concentration.

The base region 110 may be composed of a single crystalline semiconductor containing impurities (eg, single crystal or polycrystalline semiconductor, for example, single crystal or polycrystalline silicon, particularly single crystal silicon).

Such a base region may contain, for example, an impurity of an n-type conductivity type or an impurity of a p-type conductivity at a low concentration as the first or second conductivity type impurity.

In particular, when the semiconductor substrate 10 is formed of a single crystal silicon material, it may be formed of a wafer made of a single crystal silicon material. In the following manufacturing method of FIG. 2, a case where the semiconductor substrate 10 is formed of a silicon wafer material will be described as an example.

As such, a solar cell based on the base region 110 or the semiconductor substrate 10 having fewer defects due to high crystallinity may have excellent electrical characteristics.

In this case, in the present embodiment, the semiconductor substrate 10 may be composed of only the base region 110 that does not have a doped region formed by additional doping or the like. Accordingly, it is possible to prevent a decrease in passivation characteristics of the semiconductor substrate 10 due to the doped region.

In addition, antireflection structures capable of minimizing reflection may be formed on the front and rear surfaces of the semiconductor substrate 10. As an example, a texturing structure having irregularities in the form of a pyramid or the like may be provided as an antireflection structure.

The texturing structure formed on the semiconductor substrate 10 may have a certain shape (for example, a pyramid shape) having an outer surface formed along a specific crystal plane (eg, (111) plane) of the semiconductor. When unevenness is formed on the front surface of the semiconductor substrate 10 by such texturing and the surface roughness is increased, the reflectance of light incident into the semiconductor substrate 10 may be lowered to minimize light loss.

However, the present invention is not limited thereto, and a texturing structure may be formed only on the first surface of the semiconductor substrate 10, or a texturing structure may not be formed on the front and rear surfaces of the semiconductor substrate 10.

A first passivation layer 21 is formed (for example, contact) on the front surface of the semiconductor substrate 10, and a second passivation layer 31 is formed (for example, contact) on the rear surface of the semiconductor substrate 10. Thereby, the passivation characteristic can be improved.

In this case, the first and second passivation layers 21 and 31 may be entirely formed on the front and rear surfaces of the semiconductor substrate 10, respectively.

Accordingly, it can be easily formed without additional patterning while having excellent passivation characteristics. Since the carrier passes through the first or second passivation layer 31 (21, 31) and is transferred to the first or second conductivity type regions 20, 30, the first and second passivation layers 21, 31 Each thickness may be smaller than the thickness of each of the first and second conductivity-type regions 20 and 30.

As an example, the thickness of each of the first and second passivation layers 21 and 31 may be formed between 1 nm and 10 nm smaller than the thickness of the semiconductor substrate 10, and the first and second conductivity-type regions 20, 30, 20 , 3) Each thickness may be formed between 2 nm and 30 nm in a range greater than the thickness of each of the first and second passivation layers 21 and 31.

Here, the thickness of the second conductivity type region 30 may be thicker than that of the first conductivity type region 20.

In addition, as an example, the first and second passivation layers 21 and 31 are intrinsic silicon semiconductors containing a large amount of hydrogen, for example, amorphous silicon oxide material, microcrystalline silicon layer (i-mc-Si) or intrinsic amorphous It may be formed of at least one of the silicon (ia-Si) layers.

Then, since the first and second passivation layers 21 and 31 contain the same semiconductor material as the semiconductor substrate 10 and have similar characteristics and contain a large amount of hydrogen, the passivation characteristics can be more effectively improved. As a result, the passivation quality can be greatly improved.

On the first passivation layer 21, a first conductivity type region 20 including an impurity of a first conductivity type at a doping concentration higher than that of the semiconductor substrate 10 may be positioned (for example, contact). In addition, on the second passivation layer 31, a second conductivity type region 30 including impurities of a second conductivity type having a second conductivity type opposite to the first conductivity type at a higher doping concentration than the semiconductor substrate 10 is formed. It can be located (for example, contact).

When the first and second passivation layers 21 and 31 contact the first and second conductivity-type regions 30, 20, and 30, respectively, a carrier transfer path can be shortened and a structure can be simplified.

The first conductivity type region 20 and the second conductivity type region 30 are not formed by thermal diffusion into the semiconductor substrate 10, but are deposited on the first and second passivation layers 21, respectively, and Since it is formed separately, it may have a material and/or crystal structure different from that of the semiconductor substrate 10 so that it can be easily formed on the semiconductor substrate 10.

Here, the first conductivity type region 20 may be formed as an n-type silicon layer 20 containing impurities of an n-type conductivity type on the first surface of the semiconductor substrate 10 made of silicon, for example, The 2-conductivity region 30 may be formed of, for example, a p-type silicon layer 30 containing a p-type conductivity type impurity on the second surface of the semiconductor substrate 10.

For example, each of the first conductivity-type region 20 and the second conductivity-type region 30 is made of an amorphous silicon material (a-Si) containing a large amount of hydrogen, which can be easily manufactured by various methods such as evaporation, or It may be formed by doping an impurity of the first or second conductivity type into the crystalline silicon material (mc-Si). Then, the first conductivity type region 20 and the second conductivity type region 30 can be easily formed through a simple process.

As an example, the semiconductor substrate 10 may have a first conductivity type. Then, the first conductivity type region 20 constitutes a front electric field region having the same conductivity type as the semiconductor substrate 10 and having a high doping concentration, and the second conductivity type region 30 is separated from the semiconductor substrate 10. The emitter region can be configured with the opposite conductivity type.

Then, since the second conductivity type region 30, which is an emitter region, is located on the rear surface of the semiconductor substrate 10 and does not interfere with light absorption to the front surface, it may have a sufficient thickness. In addition, the first conductivity-type region 20, which is a front electric field region, is not directly involved in photoelectric conversion, and is located on the front surface of the semiconductor substrate 10 and is related to light absorption to the front surface. It can be formed by Accordingly, light loss due to the first conductivity type region 20 can be minimized.

Examples of the p-type conductivity type impurities include group III elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In), and the n-type conductivity type impurities include phosphorus (P), Group 5 elements, such as arsenic (As), bismuth (Bi), and antimony (Sb), are mentioned. In addition to this, various dopants may be used as impurities of the first or second conductivity type.

For example, the semiconductor substrate 10 and the first conductivity-type region 20 may have an n-type, and the second conductivity-type region 30 may have a p-type. Accordingly, since the semiconductor substrate 10 has an n-type, the life time of the carrier can be excellent. For example, the semiconductor substrate 10 and the first conductivity type region 20 may contain phosphorus (P) as an n-type conductivity type impurity, and the second conductivity type region 30 is a p-type conductivity type impurity. It may contain boron (B). However, the present invention is not limited thereto, and the first conductivity type may be p-type and the second conductivity type may be n-type.

In this embodiment, the first conductivity-type region 20 and the second conductivity-type region 30 each contain a large amount of hydrogen and are made of an amorphous silicon material (a-Si) or microstructure containing impurities of the first or second conductivity type. It may include a crystalline silicon material (mc-Si).

Accordingly, the first and second conductivity-type regions 30 (20, 30) include the same semiconductor material (ie, silicon) as the semiconductor substrate 10 and the first and second passivation layers 21 and 31 It may have similar characteristics to the substrate 10.

Accordingly, the carrier can be moved more effectively and a stable structure can be implemented. In addition, the first passivation layer 21 and the first conductivity-type region 20 are changed in the same device (for example, a deposition device) by an in-situ process that is continuously performed while changing only the raw material gas. The second passivation layer 31 and the second conductivity type region 30 may be formed by an in-situ process that is continuously performed while changing only the fuel gas in the same device. This can simplify the manufacturing process.

A first electrode 40 electrically connected thereto is positioned on the first conductivity type region 20 (for example, contact), and a second electrode 50 electrically connected thereto is located on the second conductivity type region 30 This location (for example, contact).

The first electrode 40 may include a first transparent electrode layer 41 disposed on the first conductivity type region 20 and a first contact electrode 43 disposed on the first transparent electrode layer 41. . On at least a portion of the first contact electrode 43, a ribbon for connection with another solar cell or an external circuit, a wiring material, an interconnector, etc. may be bonded.

Here, the first transparent electrode layer 41 may be entirely formed (for example, in contact) on the first conductivity type region 20. In this way, when the first transparent electrode layer 41 is formed entirely on the first conductivity type region 20, a desired carrier can easily reach the first contact electrode 43 through the first transparent electrode layer 41, The resistance in the direction can be reduced. In this way, since the first transparent electrode layer 41 is entirely formed on the first conductivity type region 20, it may be made of a material (transmissive material) that can transmit light. For example, the first transparent electrode layer 41 is indium tin oxide (ITO), aluminum zinc oxide (AZO), boron zinc oxide (BZO), indium-tungsten It may include at least one of an oxide (indium tungsten oxide, IWO) and an indium-cesium oxide (ICO). However, the present invention is not limited thereto, and various materials other than the first transparent electrode layer 41 may be included.

In this case, the first transparent electrode layer 41 of the present embodiment may contain hydrogen while using the above-described material as a main material. As described above, when the first transparent electrode layer 41 contains hydrogen, mobility of electrons or holes may be improved, and transmittance may be improved.

The first contact electrode 43 positioned on the first transparent electrode layer 41 may include a metal as a main material (a material included in the largest amount) to improve characteristics such as carrier collection efficiency and resistance reduction. As the metal, various materials that provide conductivity, for example, silver (Ag), aluminum (Al), copper (Cu), or tin (Sn) may be used. At this time, the first contact electrode 43 may be formed by applying and firing a paste further including a crosslinking resin, a solvent, etc. in addition to metal. However, since fire-through is not required for the first contact electrode 43, the first contact electrode 43 may not include a glass frit.

As described above, since the first contact electrode 43 may contain a metal and interfere with the incidence of light, it may have a certain pattern so as to minimize shading loss. As a result, light can be incident to a portion where the first contact electrode 43 is not formed. For example, the first contact electrode 43 extends in a first direction and includes a plurality of finger lines positioned parallel to each other, and a second direction (a vertical direction in the drawing) that intersects (for example, orthogonal) with the first direction. It may include a bus bar formed of and electrically connected to the first finger line. For example, a wiring material or the like may be attached or connected to the bus bar to correspond one-to-one.

Similarly, in this embodiment, the second electrode 50 may include a second transparent electrode layer 51 and a second contact electrode 53. Roles, materials, and materials of the second transparent electrode layer 51 and the second contact electrode 53 of the second electrode 50 except that the second electrode 50 is positioned on the second conductivity type region 30 The shape, thickness, and the like are the same as the roles, materials, shapes, and thicknesses of the first transparent electrode layer 41 and the first contact electrode 43 of the first electrode 40, and thus descriptions thereof may be applied as they are.

In addition, the second contact electrode 53 may include a finger line and a bus bar. In this case, the bus bars of the first contact electrode 43 and the bus bars of the second contact electrode 53 may be formed in the same number. The finger lines of the first contact electrode 43 and the finger lines of the second contact electrodes 53 and 43 may have the same width, pitch, and/or number, or may have different widths, pitches, and/or numbers. have.

However, the present invention is not limited thereto, and the first and second transparent electrode layers 42, 420, 440 or the first and second contact electrodes 53, 43, 53 may have various materials, shapes, and thicknesses. I can. In addition, the first and second contact electrodes 53, 43 and 53 may have different shapes.

As described above, in this embodiment, since the first and second contact electrodes 53, 43, and 53 of the solar cell have a constant pattern, the solar cell receives double-sided light through which light can be incident on the front and rear surfaces of the semiconductor substrate 10. It can have a bi-facial structure. Accordingly, the amount of light used in the solar cell may be increased, thereby contributing to the improvement of the efficiency of the solar cell. However, the present invention is not limited thereto. Therefore, it is possible to have a structure in which the second contact electrode 53 is entirely formed on the rear side of the semiconductor substrate 10.

Meanwhile, in the solar cell according to the present invention, since the first and second conductivity type regions 20 and 30, which are amorphous silicon layers, are formed on the crystalline semiconductor substrate 10, the amorphous silicon layer and the crystalline semiconductor substrate 10 The passivation function to prevent recombination on the surface of the solar cell can greatly affect the efficiency of the solar cell.

In order to further improve the passivation function of the amorphous silicon layer and the crystalline semiconductor substrate 10, plasma treatment of the surface of the semiconductor substrate 10 prior to the formation of the amorphous silicon layer, or the first and second conduction of the amorphous silicon layer. After forming the type regions 20 and 30, the surfaces of the first and second conductivity type regions 20 and 30 may be plasma-treated.

However, conventionally, for such plasma treatment, hydrogen plasma treatment using hydrogen (H2) gas was performed, but such hydrogen plasma treatment has a relatively large dissociation energy of hydrogen bonds (for example, 104 kcal/ mol), high power was required to maintain the hydrogen gas in the plasma state, and the hydrogen plasma was applied to the surface of the crystalline semiconductor substrate 10 or the surface of the amorphous first and second conductivity type regions 20 and 30 with such high power. In the case of treatment, the surface is passivated, but the surface of the semiconductor substrate 10 or the surface of the amorphous silicon layer is damaged due to the high output of the plasma equipment, which is rather a problem.

In order to further improve the passivation function, the present invention uses ammonia gas (NH3) having a low dissociation energy (for example, 1 to 4 kcal/mol) instead of plasma treatment using hydrogen gas having a relatively high dissociation energy, Plasma treatment may be performed on the surface of the semiconductor substrate 10 or the surface of the amorphous silicon layer of the first conductivity type region 20 or the second conductivity type region 30.

Such ammonia gas (NH3) has a dissociation energy that is about 50 times lower than that of hydrogen gas (H2), thus minimizing surface damage to the interface of the plasma-treated film, and allowing a greater amount of hydrogen ?t to be included in the film. have.

Accordingly, in the present invention, by performing plasma treatment using ammonia gas (NH3), the surface of the semiconductor substrate 10 or the amorphous silicon layer of the first conductivity type region 20 or the second conductivity type region 30 By minimizing damage to the surface and providing abundant hydrogen, defects on the surface of the semiconductor substrate 10 or the surface of the amorphous silicon layer can be removed, and the level of the passivation effect can be increased.

Hereinafter, a method of manufacturing a heterojunction solar cell including plasma treatment using ammonia gas (NH3) will be described in more detail with reference to FIG. 2.

2 is a flowchart illustrating a method of manufacturing the solar cell shown in FIG. 1 according to an example of the present invention.

As shown in FIG. 2, the solar cell manufacturing method according to the exemplary embodiment of the present invention includes forming a first passivation layer (S1), forming an N-type film (S2), forming a second passivation layer (S3), and forming a P-type film. It may include a step (S4), a transparent electrode forming step (S5), a contact electrode forming step (S6), and a plasma processing step (NPT).

Here, the step of forming the first passivation layer (S1) and the step of forming the second passivation layer (S3) may be omitted in some cases.

In addition, in the flow chart shown in FIG. 2, after the first passivation layer forming step (S1) and the N-type film forming step (S2) are performed, the second passivation layer forming step (S3) and the P-type film forming step (S4) are performed. Although the case where it is performed is shown as an example, the present invention is not necessarily limited thereto, and on the contrary, after the second passivation layer forming step (S3) and the P-type film forming step (S4) are performed, the first passivation layer forming step It is also possible to perform (S1) and the N-type film forming step (S2).

Hereinafter, the first passivation layer forming step (S1), the N-type film forming step (S2), the second passivation layer forming step (S3), and the P-type film forming step (S4) are performed by plasma chemical vapor deposition (PECVD, Plasma-enhanced chemical). A case in which vapor deposition) is used is described as an example, but the present invention is not limited thereto, and may be formed by a chemical vapor deposition method using various CVD devices such as remote plasma CVD and hot-wired CVD.

In order to perform the first passivation layer forming step (S1), as shown in FIG. 1, textured unevenness may be provided on the surfaces of the first and second surfaces of the semiconductor substrate 10 to be prepared, As the semiconductor substrate 10, a wafer thinner of 150 μm or less may be used.

In the first passivation layer forming step S1, a first passivation layer 21 made of an intrinsic silicon layer may be deposited on the first surface of the semiconductor substrate 10 by using a plasma chemical vapor deposition method (PECVD). In this case, the first passivation layer 21 may be formed directly on the first surface of the semiconductor substrate 10.

After the first passivation layer forming step (S1) is performed, the N-type film forming step (S2) is performed at a higher temperature than the first passivation layer forming step (S1), and plasma chemical vapor deposition (PECVD) is used continuously. I can.

In such an N-type film forming step (S2), in order to form the first conductivity-type region 20, impurities of the n-type conductivity type are directly deposited on the first passivation layer 21 formed on the first surface of the semiconductor substrate 10. The containing n-type silicon layer 20 can be deposited.

In the second passivation layer forming step S3, a second passivation layer 31 made of an intrinsic silicon layer may be deposited on the second surface of the semiconductor substrate 10 by using a plasma chemical vapor deposition method (PECVD). In this case, the second passivation layer 31 may be formed directly on the second surface of the semiconductor substrate 10.

After the second passivation layer forming step (S3) is performed, the P-type film forming step (S4) is performed at a higher temperature than the second passivation layer forming step (S3), and plasma chemical vapor deposition (PECVD) is used continuously. I can.

In the P-type film forming step (S4), in order to form the second conductivity-type region 30, impurities of the p-type conductivity type are directly deposited on the second passivation layer 31 on the second surface of the semiconductor substrate 10. A p-type silicon layer 30 containing? May be deposited.

In the transparent electrode formation step (S5), after the N-type film formation step (S2) and the P-type film formation step (S4) are performed, the first transparent electrode layer 41 is deposited on the first conductivity type region 20 and the second conductivity is performed. A second transparent electrode layer 51 may be deposited on the mold region 30.

In the contact electrode forming step (S6), a paste for the first contact electrode 43 is applied in a predetermined pattern on the first transparent electrode layer 41 formed on the first surface of the semiconductor substrate 10, and the semiconductor substrate 10 The first and second contact electrodes may be formed by applying a paste for the second contact electrode 53 in a predetermined pattern on the second transparent electrode layer 51 formed on the second surface of and then drying and firing.

In the solar cell manufacturing process, the amorphous silicon material of the first and second conductivity type regions 20 and 30 formed by the N-type film forming step (S2) and the P-type film forming step (S4) is an amorphous silicon material or microcrystalline silicon. It may be at least one of the materials.

In addition, the amorphous silicon material of the first and second passivation layers 21 and 31 formed by the first passivation layer forming step (S1) and the second passivation layer forming step (S3) is an amorphous silicon oxide material, an amorphous silicon material, or It may be at least one of microcrystalline silicon materials.

The plasma treatment step NPT may be performed by plasma treatment of ammonia gas NH3 on at least one of the silicon semiconductor substrate 10, the first conductivity type region 20, and the second conductivity type region 30.

That is, the plasma processing step (NPT) may be performed between each step when each step described in the flow chart of FIG. 2 is performed.

More specifically, when the first and second passivation layer formation steps (S1, S3) are omitted, the plasma treatment step (NPT) is (1) before the first passivation layer formation step (S1), as a pretreatment step, Plasma treatment (NPT1) of ammonia gas (NH3) for each of the first and second surfaces of the substrate 10, or (2) formed into the first conductivity type region 20 after the N-type film formation step (S2). Ammonia gas (NH3) with respect to the surface of the amorphous material n-type silicon layer 20 and the p-type layer forming step (S4) of the amorphous material p-type silicon layer 30 formed as the second conductivity type region 30 Plasma treatment (NPT31, NPT32) or (3) including all of the preceding (1) and (2), ammonia gas (NH3) may be plasma treated.

As described above, when ammonia gas (NH3) is plasma-treated on at least one of the silicon semiconductor substrate 10, the first conductivity type region 20, and the second conductivity type region 30, the dissociation energy of the ammonia gas is low, and thus plasma The output of the processing equipment can be further lowered, thereby minimizing damage to the surface of the semiconductor substrate 10, the surface of the n-type silicon layer 20 or the surface of the p-th silicon layer 30, while minimizing hydrogen By providing abundantly, it is possible to reduce dangling bonds on the surface of the semiconductor substrate 10, the surface of the n-type silicon layer 20 or the surface of the p-th silicon layer 30, Passivation function can be provided.

In addition, as shown in the flow chart of FIG. 2, when the first and second passivation layer forming steps (S1 and S3) are provided, after the first and second passivation layer forming steps (S1 and S3), the first passivation layer 21 It is also possible to perform plasma treatment (NPT21, NPT22) of ammonia gas (NH3) on the surface and the surface of the second passivation layer 31.

Accordingly, the quality of the passivation effect on the surface of the first passivation layer 21 and the second passivation layer 31 may be further improved.

In addition, after the transparent electrode forming step S5 is completed, it is possible to perform plasma treatment (NPT4) of ammonia gas (NH3) on the surface of the first transparent electrode layer 41 and the surface of the second transparent electrode layer 42.

Accordingly, the first and second transparent electrode layers 41 and 51 may contain an abundant amount of hydrogen, thereby improving the mobility of electrons or holes, and improving the transmittance.

Here, in the plasma processing step (NPT), the flow rate of the ammonia gas may be determined between 10 sccm and 5000 sccm. For example, when performing the plasma processing step (NPT) on one semiconductor substrate 10, the flow rate of ammonia gas may be determined between 10 sccm and 50 sccm, but in the case of mass production, the flow rate of ammonia gas is 10 sccm It can increase much more than between ~50 sccm.

In the plasma treatment step (NPT), the RF power or power of the apparatus for performing the plasma treatment may be determined in more than 0W and less than 25KW. For example, when performing the plasma processing step (NPT) on one semiconductor substrate 10, the RF power or power of the apparatus for performing plasma processing may be determined from 10W to 50W, but in the case of mass production, plasma processing The RF power or power of the device performing the operation can be much increased than 10W to 50W.

In the plasma processing step (NPT), the internal pressure of the apparatus for performing the plasma processing may be between 1 Torr and 4 Torr.

In the plasma processing step (NPT) according to the present invention, the flow rate, RF power, and internal pressure are presented as examples, as described above, but are not necessarily limited thereto, and the plasma processing step (NPT) can be performed at one time during mass production. It may vary depending on the capacity of the plasma processing equipment.

In the plasma processing step (NPT), the flow rate of ammonia gas may vary according to each step of the method of manufacturing a heterojunction solar cell shown in the flow chart of FIG. 2.

Hereinafter, in the plasma treatment step (NPT), the flow rate of the ammonia gas will be described in more detail.

3 is a view for explaining a comparison of the flow rate of ammonia gas during ammonia plasma treatment applied to a method of manufacturing a heterojunction solar cell.

For pretreatment before the first passivation layer forming step S1, when the plasma treatment step NPT1 is performed on the first and second surfaces of the silicon semiconductor substrate 10, as shown in FIG. 3, The flow rate of the ammonia gas during plasma treatment on the first surface of the silicon semiconductor substrate 10 and the flow rate of ammonia gas during plasma treatment on the second surface of the silicon semiconductor substrate 10 may be the same.

This is because the first and second surfaces of the semiconductor substrate 10 have similar properties for the denglin bond.

In addition, after each of the first passivation layer forming step (S1) and the second passivation layer forming step (31), the plasma processing steps (NPT21, NPT22) are applied to the first passivation layer 21 and the second passivation layer 31. Further, the flow rate of ammonia gas during plasma treatment of the first passivation layer 21 and the flow rate of ammonia gas during plasma treatment of the second passivation layer 31 may be the same.

This is because the first and second passivation layers 21 and 31 are both intrinsic and thus have similar characteristics to the denglin bond.

However, when the plasma treatment step (NPT) is performed on the n-type silicon layer 20 and the p-type silicon layer 30 after each of the N-type film formation step (S2) and P-type film formation step (S4), p The flow rate of the ammonia gas in the plasma treatment NPT32 to the n-type silicon layer 30 may be greater than the flow rate of the ammonia gas in the plasma treatment NPT31 on the n-type silicon layer 20.

The p-type silicon layer 30 contains a group 3 element as an impurity, and the n-type silicon layer 20 contains a group 5 element as an impurity, and the p-type silicon layer 30 contains a group 3 element as an impurity. Since the number of denglin bonds of is relatively higher than that of the n-type silicon layer 20 containing a group 5 element as an impurity, the flow rate of ammonia gas during plasma treatment of the p-type silicon layer 30 is considered. The amount can be made larger than the flow rate of the ammonia gas during plasma treatment of the n-type silicon layer 20.

Accordingly, the method of manufacturing a heterojunction solar cell according to the present invention includes a plasma treatment step (NPT) using ammonia gas (NH3), so that the surface of the semiconductor substrate 10 or the first conductivity type region 20 It is possible to increase the level of the passivation effect while minimizing damage to the surface of the amorphous silicon layer of the 2-conductivity type region 30.

In addition, in FIGS. 2 and 3, a case where the first conductivity type region 20 or the second conductivity type region 30 is formed of a single amorphous silicon layer is described as an example. However, the first and second conductivity type regions 20, 30) can also be applied when formed of a plurality of amorphous silicon layers.

However, when the first and second conductivity-type regions 20 and 30 are formed of a plurality of amorphous silicon layers, the flow rate of the ammonia gas may be varied during the ammonia plasma treatment for each layer.

This will be described in more detail with reference to FIGS. 4 to 6.

4 is a view for explaining another example of the heterojunction solar cell manufactured according to the present invention, FIG. 5 is a flow chart for explaining a method of manufacturing the heterojunction solar cell shown in FIG. 4, and FIG. 6 is A diagram for comparing and explaining the flow rate of ammonia gas during ammonia plasma treatment applied to the method of manufacturing the heterojunction solar cell shown in FIG. 5.

In FIGS. 4 to 6, parts different from those described in FIGS. 1 to 3 will be mainly described, and descriptions of the same parts will be omitted.

As shown in FIG. 4, in another example of a solar cell manufactured according to the present invention, each of the first and second conductivity type regions 20 and 30 may be formed of a plurality of layers.

For example, the n-type silicon layer 20 formed as the first conductivity type region 20 may include a first n-type silicon layer 20a and a second n-type silicon layer 20b.

Here, the first n-type silicon layer 20a may be directly positioned on the first passivation layer 21, and the second n-type silicon layer 20b may be directly positioned on the first n-type silicon layer 20a.

Here, the concentration of the conductive impurities of the second n-type silicon layer 20b may be greater than the concentration of the conductive impurities of the first n-type silicon layer 20a.

In addition, the p-type silicon layer 30 formed as the second conductivity type region 30 may include a first p-type silicon layer 30a and a second p-type silicon layer 30b.

Here, the first p-type silicon layer 30a may be directly disposed on the second passivation layer 31, and the second p-type silicon layer 30b may be disposed directly on the first p-type silicon layer 30a.

Here, the concentration of the conductive impurities in the second p-type silicon layer 30b may be greater than the concentration of the conductive impurities in the first p-type silicon layer 30a.

Accordingly, as shown in FIG. 5, the solar cell manufacturing method may also include the step of forming the n-type film (S2) and the step of forming the first n-type film (S21) and the step of forming the second n-type film (S22). The forming step S4 may include forming a first p-type layer S41 and forming a second p-type layer S42.

In the first n-type film formation step (S21), a first n-type film silicon layer 20a containing impurities of a first concentration of n-type conductivity type is deposited on the silicon semiconductor substrate 10, and a second n-type film formation step ( In S22), a second n-type silicon layer 20b containing an n-type conductivity type impurity having a second concentration higher than the first concentration may be deposited on the first n-type silicon layer 20a.

In the first p-type film formation step (S41), a first p-type film silicon layer 30a containing impurities of a first concentration of p-type conductivity type is deposited on the silicon semiconductor substrate 10, and a second p-type film formation step ( S42) may deposit a second p-type silicon layer 30b containing impurities of a p-type conductivity type having a second concentration higher than the first concentration on the first p-type silicon layer 30a.

In such a case, in order to increase the passivation quality of the film, after the first n-type film forming step (S21) and after the second n-type film forming step (S22), the first and second n-type silicon layers 20a and 20b are each However, the ammonia plasma treatment steps (NPT31a, NPT31b) may be performed, and after the first p-type film formation step (S41) and the second p-type film formation step (S42), the first and second p-type film silicon layers It is performed for each of (30a, 30b), but ammonia plasma treatment steps (NPT32a, NPT32b) may be performed.

Here, in the n-type silicon layer 20, since the impurity concentration of the second n-type silicon layer 20b is higher, the dangling bond of the second n-type silicon layer 20b is higher than that of the first n-type silicon layer 20a. In the p-type silicon layer 30, the impurity concentration of the second p-type silicon layer 30b is higher, and thus the second p-type silicon layer ( The number of dangling bonds in 30b) may be higher.

However, as shown in FIG. 6, the flow rate of ammonia gas during the plasma treatment (NPT31a) for the first n-type silicon layer 20a is plasma treatment for the second n-type silicon layer 20b (NPT31b). May be higher than the flow rate of ammonia gas in the city.

In addition, the flow rate of ammonia gas in the plasma treatment (NPT32a) of the first p-type silicon layer 30a is greater than the flow rate of ammonia gas in the plasma treatment (NPT32b) of the second p-type silicon layer 30b. There can be many.

This makes the flow rate of the ammonia gas during plasma treatment on the first n-type silicon layer 20a higher than the flow rate of ammonia gas during plasma treatment on the second n-type silicon layer 20b. More hydrogen can be supplied to the inside 20, and the hydrogen supplied in the n-type silicon layer 20 is not only inside the first n-type silicon layer 20a, but also inside the second n-type silicon layer 20b formed subsequently By diffusing to increase the hydrogen content throughout the inside of the n-type silicon layer 20, as a whole, the number of dangling bonds in the second n-type silicon layer 20b as well as the inside of the first n-type silicon layer 20a. Because it can be reduced.

For the same reason, the flow rate of the ammonia gas during the plasma treatment (NPT32a) to the first p-type silicon layer 30a is the flow rate of the ammonia gas (NPT32b) during the plasma treatment to the second p-type silicon layer 30b. You can do more than the amount.

In addition, when the ammonia plasma treatment is performed on each of the n-type silicon layer 20 and the p-type silicon layer 30 provided as a plurality of layers, as shown in FIG. 6, during ammonia plasma treatment (NPT). , In consideration of the number of dangling bonds, the flow rate of ammonia gas can be made larger for the first p-type silicon layer 30a than for the first n-type silicon layer 20a, and the second n-type silicon layer ( It is possible to increase the flow rate of ammonia gas with respect to the second p-type silicon layer 30b than that of 20b).

As described above, the method of manufacturing a heterojunction solar cell according to the present invention includes a plasma treatment step (NPT) using ammonia gas (NH3), so that the surface of the semiconductor substrate 10 or the first conductivity type region 20 It is possible to increase the level of the passivation effect while minimizing damage to the surface of the amorphous silicon layer of the 2-conductivity type region 30.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (9)

An n-type film forming step of forming a first conductivity-type region that is an n-type silicon layer made of an amorphous material and contains an n-type conductivity type impurity on a first surface of a semiconductor substrate made of crystalline silicon; And
A p-type film forming step of forming a second conductivity-type region that is a p-type film silicon layer made of an amorphous material and contains p-type conductivity type impurities on a second surface of the semiconductor substrate opposite the first surface; and
A method of manufacturing a heterojunction solar cell further comprising a plasma processing step of plasma treating ammonia gas (NH3) on at least one of the silicon semiconductor substrate, the first conductivity type region, and the second conductivity type region. The method of claim 1,
The plasma processing step is performed on the n-type silicon layer and the p-type silicon layer after each of the n-type film forming step and the p-type film forming step,
A method of manufacturing a heterojunction solar cell in which the flow rate of the ammonia gas during the plasma treatment of the p-type silicon layer is greater than the flow rate of the ammonia gas during the plasma treatment of the n-type silicon layer. The method of claim 1,
The plasma treatment step is further performed on the first surface and the second surface of the silicon semiconductor substrate before the n-type film forming step and the p-type film forming step,
A heterojunction solar cell in which the flow rate of the ammonia gas during the plasma treatment with respect to the first surface of the silicon semiconductor substrate and the flow rate of the ammonia gas during the plasma treatment with respect to the second surface of the silicon semiconductor substrate are the same Manufacturing method. The method of claim 1,
Before the step of forming the n-type film, a first passivation layer forming step of forming a first passivation layer made of an intrinsic silicon layer on the first surface of the semiconductor substrate; and
Before the step of forming the p-type film, a second passivation layer forming step of forming a second passivation layer made of an intrinsic silicon layer on the second surface of the semiconductor substrate; a heterojunction solar cell manufacturing method further comprising. The method of claim 4,
The plasma processing step is further performed on the first passivation layer and the second passivation layer after each of the first passivation layer forming step and the second passivation layer forming step,
A method of manufacturing a heterojunction solar cell in which the flow rate of the ammonia gas during the plasma treatment on the first passivation layer and the flow rate of the ammonia gas during the plasma treatment on the second passivation layer are the same. The method of claim 1,
The first and second conductivity-type regions formed by the n-type film forming step and the p-type film forming step are at least one of an amorphous silicon material or a microcrystalline silicon material,
The first and second passivation layers formed by forming the first passivation layer and forming the second passivation layer are at least one of an amorphous silicon oxide material, an amorphous silicon material, or a microcrystalline silicon material. . The method of claim 1,
The solar cell manufacturing method
After the step of forming the n-type film and the step of forming the p-type film are performed,
A transparent electrode forming step of depositing a first transparent electrode layer on the first conductivity type region and a second transparent electrode layer on each of the second conductivity type region; And
An electrode forming step of forming first and second electrodes on each of the first and second transparent electrode layers, further comprising a heterojunction solar cell manufacturing method. The method of claim 1,
The step of forming the n-type film
A first n-type film forming step of depositing a first n-type film silicon layer containing an n-type conductivity type impurity of a first concentration on the silicon semiconductor substrate; and
A second n-type film forming step of depositing a second n-type silicon layer containing an n-type conductivity type impurity having a second concentration higher than the first concentration on the first n-type silicon layer,
The plasma treatment step is performed on each of the first and 2 n-type silicon layers, after each of the first n-type film forming step and the second n-type film forming step,
A method of manufacturing a heterojunction solar cell in which the flow rate of the ammonia gas during the plasma treatment on the first n-type silicon layer is greater than the flow rate of the ammonia gas during the plasma treatment on the second n-type silicon layer. The method of claim 1,
The step of forming the p-type film
A first p-type film forming step of depositing a first p-type film silicon layer containing impurities of a p-type conductivity type at a first concentration on the silicon semiconductor substrate; and
A second p-type film forming step of depositing a second p-type film silicon layer containing impurities of a p-type conductivity type having a second concentration higher than the first concentration on the first p-type film silicon layer, and
The plasma processing step is performed on each of the first and 2 p-type silicon layers, after each of the first p-type film forming step and the second p-type film forming step,
A method of manufacturing a heterojunction solar cell in which the flow rate of the ammonia gas during the plasma treatment on the first p-type silicon layer is greater than the flow rate of the ammonia gas during the plasma treatment on the second p-type silicon layer.

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