KR20190096731A - 반도체 장치용 소결 접합 방법 - Google Patents

반도체 장치용 소결 접합 방법 Download PDF

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Publication number
KR20190096731A
KR20190096731A KR1020180016522A KR20180016522A KR20190096731A KR 20190096731 A KR20190096731 A KR 20190096731A KR 1020180016522 A KR1020180016522 A KR 1020180016522A KR 20180016522 A KR20180016522 A KR 20180016522A KR 20190096731 A KR20190096731 A KR 20190096731A
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South Korea
Prior art keywords
copper
particle size
copper paste
particles
sintering
Prior art date
Application number
KR1020180016522A
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English (en)
Inventor
미치아키 히요시
Original Assignee
현대자동차주식회사
기아자동차주식회사
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Application filed by 현대자동차주식회사, 기아자동차주식회사 filed Critical 현대자동차주식회사
Priority to KR1020180016522A priority Critical patent/KR20190096731A/ko
Priority to US16/035,649 priority patent/US20190252348A1/en
Priority to JP2018196371A priority patent/JP7255994B2/ja
Publication of KR20190096731A publication Critical patent/KR20190096731A/ko

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F7/00—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression
    • B22F7/06—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression of composite workpieces or articles from parts, e.g. to form tipped tools
    • B22F7/062—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression of composite workpieces or articles from parts, e.g. to form tipped tools involving the connection or repairing of preformed parts
    • B22F7/064—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression of composite workpieces or articles from parts, e.g. to form tipped tools involving the connection or repairing of preformed parts using an intermediate powder layer
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    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • B22F1/07—Metallic powder characterised by particles having a nanoscale microstructure
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    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • B22F1/10—Metallic powder containing lubricating or binding agents; Metallic powder containing organic material
    • B—PERFORMING OPERATIONS; TRANSPORTING
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Abstract

본 발명은 반도체 장치용 소결 접합 방법에 관한 것으로서, 고온에서 연속 사용되는 반도체 칩을 금속 기판 위에 접합시킬 때 순동 입자와 산화 제1동 나노입자를 혼합하여 동 밀도를 높인 저가의 동 페이스트를 접합재로 사용함으로써, 재료비를 절감하는 동시에 환원성 분위기에서 상기 동 페이스트를 가열하여 소결시킬 때 공공이나 크랙 발생을 억제하고 최적의 고내열 접합을 구현할 수 있도록 하는 반도체 장치용 소결 접합 방법을 제공하는데 목적이 있다.

Description

반도체 장치용 소결 접합 방법 {Sintering bonding method for semiconductor devices}
본 발명은 반도체 장치용 소결 접합 방법에 관한 것으로서, 상세하게는 반도체 칩을 금속 기판 위에 접합하기 위한 반도체 장치용 소결 접합 방법에 관한 것이다.
최근 SiC 파워모듈(power Module) 등의 고온 연속사용 반도체 니즈가 늘어나면서 반도체의 칩(Chip) 접합부의 고내열, 고신뢰의 접합기술이 요구되고 있다. 그에 따라 고내열성의 접합기술로서 동 나노 입자를 바인더 안에 분산시킨 동 페이스트를 접합에 사용하는 기술이 확대되고 있다.
통상 금속 입자는 입자 크기가 작아질수록 표면 원자수 비율이 급증하여 불안정해지며 입자끼리 접합이 용이해진다. 따라서 소결 반응의 저온화를 위해서는 금속 입자의 사이즈를 소형화시키는 것이 대단히 유효하다.
그런데 순동 입자의 경우, 소경화에 의해 산화 및 응집 반응도 쉬워져서 취급이 용이하지 않다. 그래서 나노 입자로서는 순동이 아닌 것이 바람직하다.
아산화동 나노입자의 경우 사이즈가 극미세하지만 산화물이기 때문에 대단히 안정적이고 재료의 취급이 용이하다.
다만, 아산화동 나노입자는 재료면에서 고가인데다가 소결성을 높이기 위해 환원성 분위기 속에서 소결을 할 필요가 있으며, 입경이 극미세하기 때문에 용제에 분산시킨 페이스트의 동 밀도가 대단히 낮고 소결반응에서 부피수축율이 대단히 높다는 단점이 있다. 또한 소결반응과 수축반응이 동시에 진행되기 때문에 소결접합층 내부에 공공, 크랙 등이 발생하기 쉬운 문제점이 존재한다.
또한 상기한 아산화동 나노입자의 경우 치밀한 소결접합층을 얻기 위해서는 접합부에 개별적으로 고하중의 인가가 필요하며, 특히 대면적을 접합하는 반도체 칩의 접합재로 적합하지 않다.
한국공개특허 제2009-0037332호
본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 고온에서 연속 사용되는 반도체 칩을 금속 기판 위에 접합시킬 때 순동 입자와 산화 제1동 나노입자를 혼합하여 동 밀도를 높인 저가의 동 페이스트를 접합재로 사용함으로써, 재료비를 절감하는 동시에 환원성 분위기에서 상기 동 페이스트를 가열하여 소결시킬 때 공공이나 크랙 발생을 억제하고 최적의 고내열 접합을 구현할 수 있도록 하는 반도체 장치용 소결 접합 방법을 제공하는데 목적이 있다.
이에 본 발명에서는, 금속 기판 위에 반도체 칩을 접합하는 소결 접합 방법으로서, 산화 제1동(Cu2O) 나노입자와 상기 산화 제1동 나노입자보다 큰 입경을 갖는 순동(Cu) 입자를 혼합한 동 페이스트를 금속 기판 위에 도포하는 도포단계; 상기 동 페이스트 위에 반도체 칩을 탑재하는 탑재단계; 상기 반도체 칩이 탑재된 금속 기판의 동 페이스트를 환원분위기에서 가압 및 가열하는 소결단계;를 포함하는 것을 특징으로 하는 반도체 장치용 소결 접합 방법을 제공한다.
구체적으로, 상기 동 페이스트는 10nm ~ 100nm의 입경을 갖는 산화 제1동 나노입자와 0.10 ㎛ ~ 0.15 ㎛ 의 입경을 갖는 순동 입자를 함유하도록 조성될 수 있으며, 좀더 구체적으로 상기 동 페이스트는 10nm ~ 100nm의 입경을 갖는 산화 제1동 나노입자와 0.10 ㎛ ~ 0.15 ㎛의 입경을 갖는 순동 입자 및 1.0 ㎛ ~ 10.0 ㎛ 의 입경을 갖는 순동 입자를 함유하도록 조성될 수 있다.
바람직하게, 상기 동 페이스트는 30nm ~ 60nm의 입경을 갖는 산화 제1동 나노입자와 0.10 ㎛ ~ 0.15 ㎛ 의 입경을 갖는 순동 입자를 함유하도록 조성될 수 있으며, 좀더 바람직하게 상기 동 페이스트는 30nm ~ 60nm의 입경을 갖는 산화 제1동 나노입자와 0.10 ㎛ ~ 0.15 ㎛의 입경을 갖는 순동 입자 및 1.0 ㎛ ~ 10.0 ㎛ 의 입경을 갖는 순동 입자를 함유하도록 조성될 수 있다.
이때, 상기 동 페이스트는 전체 함량 100 중량% 중에 산화 제1동 나노입자의 함량이 0.1 중량% ~ 5.0 중량% 이며, 구체적으로는 순동 입자 87.6 ~ 91.6 중량% 와 산화 제1동 나노입자 0.1 ~ 5.0 중량% 및 용제 6.0 ~ 10.0 중량%를 혼합하여 조성될 수 있다.
본 발명에 의하면, 입경이 다른 순동 입자와 산화 제1동 나노입자를 혼합하여 동 밀도를 높인 저가의 동 페이스트를 접합재로 사용하게 되며, 이에 동 페이스트의 재료비를 절감하는 동시에 환원성 분위기에서 상기 동 페이스트를 가열하여 소결시킬 때 공공이나 크랙 발생을 억제할 수 있다.
도 1은 본 발명에 따른 반도체 장치의 소결 접합 방법을 나타낸 개념도이다.
도 2는 본 발명에 따른 반도체 장치의 소결 접합 방법을 나타낸 순서도이다.
도 3은 본 발명에 따른 동일 조건의 동 페이스트를 수소 100% 분위기 및 대기압에서 온도 조건만 달리하여 소결시킨 실험 결과를 나타낸 그래프이다.
이하, 본 발명을 해당 기술분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 설명하기로 한다.
본 발명은 SiC 파워모듈(power Module) 등과 같이 고온에서 연속 사용되는 반도체 칩을 금속 기판 위에 접합시키는 소결 접합 방법에 관한 것으로서, 고온에서 연속 사용되는 반도체 칩을 금속 기판 위에 접합시킬 때 순동 입자와 산화 제1동 나노입자를 혼합하여 동 밀도를 높인 동 페이스트를 접합재로 사용함으로써 동 페이스트의 재료비를 절감하는 동시에 환원성 분위기에서 상기 동 페이스트를 가열하여 소결시킬 때 공공이나 크랙 발생을 억제하고 최적의 고내열 접합을 구현할 수 있게 된다.
첨부한 도 1은 본 발명에 따른 반도체 장치의 소결 접합 방법을 나타낸 개념도이고, 도 2는 본 발명에 따른 반도체 장치의 소결 접합 방법을 나타낸 순서도이다.
도 1 및 도 2에 나타낸 바와 같이, 먼저 산화 제1동(Cu2O) 나노입자와 순동(Cu) 입자를 혼합한 동 페이스트를 금속 기판 위에 도포한다(S10).
상기 동 페이스트는 산화 제1동 나노입자와 순동 입자 및 용제를 혼합하여 조성한 것으로서, 상기 순동 입자는 산화 제1동 나노입자보다 큰 입경을 갖는 1종 또는 2종의 순동 입자를 사용할 수 있으며, 상기 산화 제1동 나노입자는 순동 입자보다 작은 입경을 갖는 산화 제1동 나노입자를 사용한다.
부연하면, 상기 순동 입자는 입자의 크기를 기준으로 1종 또는 2종의 순동 마이크로입자를 사용할 수 있다.
구체적으로, 1종의 순동 입자를 사용하는 경우 0.10 ㎛ ~ 0.15 ㎛ 의 입경을 갖는 순동 마이크로입자를 사용할 수 있으며, 2종의 순동 입자를 사용하는 경우 0.10 ㎛ ~ 0.15 ㎛ 의 상대적으로 작은 입경을 갖는 순동 마이크로입자와 1.0 ㎛ ~ 10.0 ㎛ 의 상대적으로 큰 입경을 갖는 순동 마이크로입자를 혼합 사용할 수 있다.
그리고, 상기 산화 제1동 나노입자는 동 페이스트의 동 밀도를 높이기 위해 100nm 이하, 구체적으로 10nm ~ 100nm의 입경을 갖는 것이 사용될 수 있으며, 바람직하게는 30nm ~ 60nm의 입경을 갖는 산화 제1동 나노입자를 사용할 수 있다.
이와 같이 순동 입자보다 매우 작은 크기를 갖는 산화 제1동 나노입자를 순동 입자와 혼합하여 동 페이스트를 조성함으로써 상기 동 페이스트의 동 밀도를 증대시킬 수 있다. 또한 입자의 크기를 기준으로 2종의 순동 입자를 혼합하여 산화 제1동 나노입자와 함께 사용하는 경우, 동 페이스트의 동 밀도를 보다 효과적으로 증대시킬 수 있다.
상기한 동 페이스트는 동 페이스트의 전체 함량(100 중량%) 중에 0.1 ~ 5.0 중량% 가 산화 제1동 나노입자로 채워지며, 나머지가 순동 입자와 용제로 채워진다.
구체적으로, 상기 동 페이스트는 순동(Cu) 입자 87.6 ~ 91.6 중량% 와 산화 제1동(Cu2O) 나노입자 0.1 ~ 5.0 중량% 및 용제 6.0 ~ 10.0 중량% 를 혼합하여 조성할 수 있다.
좀더 구체적으로, 상기 동 페이스트는 0.1 ㎛ ~ 10.0 ㎛ 의 입경을 갖는 순동 입자 87.6 ~ 91.5 중량% 와 30 nm ~ 60 nm의 입경을 갖는 산화 제1동(Cu2O) 나노입자 0.1 ~ 5.0 중량% 및 용제 6.0 ~ 10.0 중량% 를 혼합하여 조성할 수 있다.
또한, 상기 동 페이스트는 1.0 ㎛ ~ 10.0 ㎛ 의 큰 입경을 갖는 순동 입자 43.8 ~ 45.8 중량% 와 0.10 ㎛ ~ 0.15 ㎛의 작은 입경을 갖는 순동 입자 43.8 ~ 45.8 중량%, 30 nm ~ 60 nm의 입경을 갖는 산화 제1동 나노입자 0.1 ~ 5.0 중량%, 및 용제 6.0 ~ 10.0 중량% 를 혼합하여 조성할 수 있다.
이때 상기 용제로는 알파-테르피네올(α-Terpineol) 등을 사용할 수 있다.
이와 같이 조성되는 동 페이스트는, 고가의 산화 제1동 나노입자만을 사용하는 경우보다 저가로 조성 가능하고, 입자가 큰 순동 입자만을 사용하는 경우보다 동(Cu) 함량이 높은 고밀도로 조성 가능하여 소결 시 공공이나 크랙 발생을 억제하고 고밀도의 치밀한 접합재로 소결시킬 수 있게 되므로, 결국 반도체 칩을 금속 기판에 접합함에 있어 최적의 고내열 접합을 실현하는데 유리하다.
부연하면, 서로 다른 입경을 갖는 산화 제1동 나노입자와 순동 입자를 최적의 배합으로 혼합함으로써 상기 동 페이스트의 동 밀도를 효과적으로 증대시켜 용제의 함유량을 줄이고 동 밀도를 높인 저가의 동 페이스트를 조성할 수 있다.
이렇게 동 밀도가 높은 고밀도의 동 페이스트를 사용하는 경우, 소결 접합 후의 동 밀도가 높게 지속되어 금속 기판과 반도체 칩 사이의 소결접합층(동 페이스트)이 공공이나 크랙의 발생 없이 치밀하게 형성되고, 상기 소결합층의 접합강도가 증대되는 이점이 있다.
아울러, 상기 산화 제1동 나노입자는 열 플라즈마법으로 제조한 것을 사용하는 것이 바람직하며, 상기 금속 기판은 구리 기판 등을 사용할 수 있다.
산화 제1동 나노입자의 일반적인 제조법(액상법)은 가수분해법, 수열합성법, 액중환원법, 정석법 등이 있으나, 이러한 제조법은 입자 제조시에 입자의 입자가 오염되기 쉽고 입자끼리 달라붙기 쉬우며 또한 입경 및 형상의 편차가 크고 산화되기 쉬운 단점이 있다.
상기 열 플라즈마법으로 산화 제1동 나노입자를 제조하는 경우, 입자의 오염이 적고 입경 및 형상이 균일하며 가격이 저렴한 이점이 있으며, 또한 용제내에서 분산성이 좋고 동 페이스트의 조성시 2종 입자의 혼합 분산성을 향상시킬 수 있는 이점이 있다.
또한, 반도체 칩은 통상 금속 기판에 접합되는 측의 표면이 Ni층과 Au 박막층 또는 Ag 박막층으로 이루어지며, 산화 제1동 나노입자는 환원반응에 의해 반도체 칩의 Ni층과 접합이 잘 되고 계면이 강화된다.
다음, 상기한 동 페이스트를 도포한 금속 기판 위에 반도체 칩을 탑재하고(S11), 상기 반도체 칩을 실장한 금속 기판을 환원분위기를 형성한 챔버내에 투입하여 환원분위기내에서 가압한다(S12).
이때 상기 동 페이스트의 동 밀도가 높기 때문에, 상기 챔버내의 압력은 별도의 압력을 가하지 않는 무하중 상태(즉, 대기압)로 유지되어도 동 페이스트를 공공이나 크랙 발생없이 치밀하게 소결시킬 수 있기는 하나, 보다 효과적인 환원반응을 유도하기 위해 0.3MPa ~ 1.0 MPa 의 압력을 상기 챔버내에 형성하는 것이 바람직하다.
그 다음, 상기 챔버내의 환원분위기 상에서 상기 동 페이스트를 250 ~ 300℃의 온도에서 가열하여 산화 제1동 나노입자를 환원시킴으로써(S13) 산화 제1동 나노입자의 구리 나노입자와 순동 입자를 소결시킨다(S14).
이때 환원된 산화 제1동 나노입자의 구리 나노입자끼리 소결하거나 또는 환원된 구리 나노입자와 순동 입자를 소결하여 금속 기판과 반도체 칩의 접합이 이루어진다.
그리고, 도 3에 나타낸 바와 같이, 상기 동 페이스트는 280 ~ 300℃의 온도에서 가열되는 것이 전단강도가 최대가 되어 바람직하다. 도 3은 상기한 조성 조건을 만족하는 동일 조건의 동 페이스트를 수소 100% 분위기 및 대기압에서 온도 조건만 달리하여 소결시킨 실험 결과를 나타낸 그래프이다.
상기와 같이 대기압 이상의 환원분위기상에서 동 페이스트에 개별적인 부가하중을 가하지 않고 바로 소결 접합하는 경우, 다음과 같은 이점이 있다.
1. 환원분위기를 제공하는 고압 챔버내에서 랙 위에 반도체 칩을 복수 배열하고 일괄적으로 소결 처리하여 금속 기판에 접합하는 것이 가능하고, 그에 따라 높은 생산성을 확보할 수 있다.
2. 페이스트 건조 등의 예비공정이 불필요하고, 30분 이내에 소결 접합 처리가 가능하다.
3. 동 페이스트에 부가하중을 가하기 위한 프레스 기구를 사용할 필요가 없으며, 상기 프레스 기구에 동 페이스트의 가열을 위해 부착한 히터를 이용하여 동 페이스트를 소결시킬 필요가 없다. 상기 히터를 이용한 소결 시 반도체 장치의 생산성이 매우 낮아지고 비용도 상승하게 된다.
4. 기존의 프레스 기구를 이용하는 경우 동 페이스트에 부가하중을 가하는 과정에서 반도체 칩의 표면에 파인 크랙 등의 데미지를 입힐 가능성이 높아 고품질 유지가 곤란하고 반도체 칩내의 압력분포에 편차가 발생하나, 본 발명에서는 프레스 기구를 이용하는 경우와 동등 수준의 접합강도를 확보하면서 프레스 기구를 사용함에 따른 품질 저하 및 성능 저하를 방지할 수 있다.
5. 대기압보다 다소 높은 고압의 환원 분위기상에서 반도체 칩 중앙부의 용제를 외부로 배출시킬 수 있어 대면적 반도체 칩의 소결 접합에 적합하다.
아울러, 본 발명에서는 상기한 동 페이스트 대신 은 페이스트를 금속 기판 위에 도포하고 상기 은 페이스트 위에 반도체 칩을 탑재하여 소결 접합하는 것도 가능하다.
부연하면, 상기 은 페이스트는 산화 제1은(Ag2O) 나노입자와 상기 산화 제1은 나노입자보다 큰 입경을 갖는 순은(Ag) 입자를 혼합 조성한 것이 사용될 수 있다. 그리고, 상기 산화 제1은(Ag2O) 나노입자와 순은(Ag) 입자의 함량 및 입경 등의 특징은 상기 산화 제1동 나노입자와 순동 입자의 함량 및 입경 등의 특징이 동일하게 적용될 수 있다.
한편, 아래 표 1은 서로 다른 입경을 갖는 2종의 순동 입자와 산화 제1동 나노입자를 혼합하여 동 페이스트를 제조한 경우(A)와, 서로 다른 입경을 갖는 2종의 순동 입자를 혼합하여 동 페이스트를 제조한 경우(B), 소결 처리에 따른 소결접합층(소결된 동 페이스트)의 전단강도를 비교하여 나타낸 것이다.
Figure pat00001
표 1에 나타낸 바와 같이, 2종의 순동 입자를 혼합하여 제조한 동 페이스트(B) 대비. 2종의 순동 입자와 산화 제1동 나노입자를 혼합하여 제조한 동 페이스트(A)의 전단강도가 훨씬 높은 것을 확인할 수 있었다.
아울러, 아래 표 2는 서로 다른 입경을 갖는 2종의 순동 입자와 산화 제1동 나노입자를 혼합하여 동 페이스트를 제조하되, 산화 제1동 나노입자의 배합비(함량)를 다르게 하여 제조한 동 페이스트(A',C)의 소결 처리에 따른 소결접합층(소결된 동 페이스트)의 전단강도를 비교하여 나타낸 것이다. 이때 300℃에서 60분 동안 가열하여 소결 처리를 하였다.
Figure pat00002
표 2에 나타낸 바와 같이, 상대적으로 산화 제1동 나노입자의 배합비가 작은 동 페이스트(C) 대비, 산화 제1동 나노입자의 배합비가 큰 동 페이스트(A')의 전단강도가 훨씬 높은 것을 확인할 수 있었다.
부연하면, 동 페이스트의 제조 시 산화 제1동 나노입자의 함량 최적화에 의해 동 페이스트의 소결에 따른 소결접합층(금속 기판과 반도체 칩 사이의 소결접합층)의 전단강도를 극대화할 수 있음을 확인할 수 있었다.
이때 상기 동 페이스트(A')는 0.13㎛ 의 입경을 갖는 순동 입자 43.8 중량%, 1㎛ 의 입경을 갖는 순동 입자 43.8 중량%, 30nm의 입경을 갖는 산화 제1동 나노입자 4.4 중량%, 용제 8.0 중량%를 혼합하여 조성된 동 페이스트를 사용하였다.
참고로, 표 2의 동 페이스트(A')는 표 1의 동 페이스트(A)와 입자 배합비는 동일하나 소결 처리 시의 온도 및 시간 조건 등이 상이함에 따라 전단강도의 차이가 존재하는 것이다.

Claims (8)

  1. 금속 기판 위에 반도체 칩을 접합하는 소결 접합 방법으로서,
    산화 제1동(Cu2O) 나노입자와 상기 산화 제1동 나노입자보다 큰 입경을 갖는 순동(Cu) 입자를 혼합한 동 페이스트를 금속 기판 위에 도포하는 도포단계;
    상기 동 페이스트 위에 반도체 칩을 탑재하는 탑재단계;
    상기 반도체 칩이 탑재된 금속 기판의 동 페이스트를 환원분위기에서 가압 및 가열하는 소결단계;
    를 포함하는 것을 특징으로 하는 반도체 장치용 소결 접합 방법.
  2. 청구항 1에 있어서,
    상기 동 페이스트는 10nm ~ 100nm의 입경을 갖는 산화 제1동 나노입자와 0.10 ㎛ ~ 0.15 ㎛ 의 입경을 갖는 순동 입자를 함유하는 것을 특징으로 하는 반도체 장치용 소결 접합 방법.
  3. 청구항 1에 있어서,
    상기 동 페이스트는 10nm ~ 100nm의 입경을 갖는 산화 제1동 나노입자와 0.10 ㎛ ~ 0.15 ㎛의 입경을 갖는 순동 입자 및 1.0 ㎛ ~ 10.0 ㎛ 의 입경을 갖는 순동 입자를 함유하는 것을 특징으로 하는 반도체 장치용 소결 접합 방법.
  4. 청구항 1에 있어서,
    상기 동 페이스트는 전체 함량 100 중량% 중에 산화 제1동 나노입자의 함량이 0.1 중량% ~ 5.0 중량% 인 것을 특징으로 하는 반도체 장치용 소결 접합 방법.
  5. 청구항 1에 있어서,
    상기 동 페이스트는 순동 입자 87.6 ~ 91.6 중량% 와 산화 제1동 나노입자 0.1 ~ 5.0 중량% 및 용제 6.0 ~ 10.0 중량%를 혼합하여 조성한 것임을 특징으로 하는 반도체 장치용 소결 접합 방법.
  6. 청구항 1에 있어서,
    상기 소결단계에서는 250 ~ 300℃의 온도에서 동 페이스트를 가열하여 소결시키는 것을 특징으로 하는 반도체 장치용 소결 접합 방법.
  7. 청구항 1에 있어서,
    상기 동 페이스트는 30nm ~ 60nm의 입경을 갖는 산화 제1동 나노입자와 0.10 ㎛ ~ 0.15 ㎛ 의 입경을 갖는 순동 입자를 함유하는 것을 특징으로 하는 반도체 장치용 소결 접합 방법.
  8. 청구항 1에 있어서,
    상기 동 페이스트는 30nm ~ 60nm의 입경을 갖는 산화 제1동 나노입자와 0.10 ㎛ ~ 0.15 ㎛의 입경을 갖는 순동 입자 및 1.0 ㎛ ~ 10.0 ㎛ 의 입경을 갖는 순동 입자를 함유하는 것을 특징으로 하는 반도체 장치용 소결 접합 방법.


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