KR20180098486A - Light emitting diode array on wafer level - Google Patents

Abstract

Disclosed is a light emitting diode array. The light emitting diode array comprises: a growth substrate; a plurality of light emitting diodes arranged on the substrate and respectively including a first semiconductor layer, an active layer, and a second semiconductor layer; and a plurality of upper electrodes arranged on the light emitting diodes, formed of the same material as each other, and electrically connected to the first semiconductor layers of the corresponding light emitting diodes. In addition, at least one of the upper electrodes is electrically connected to the second semiconductor layer of an adjacent light emitting diode, and the other one of the upper electrodes is insulated from the second semiconductor layer of the adjacent light emitting diode. Accordingly, the light emitting diode array capable of operating under a high voltage and simplifying a manufacturing process is provided.

Description

[0001] LIGHT EMITTING DIODE ARRAY ON WAFER LEVEL [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array, and more particularly, to a light emitting diode array in which a plurality of light emitting diodes are connected to each other through a wiring and formed in a flip chip type.

The light emitting diode is an element that performs a light emitting operation when a voltage higher than a turn-on voltage is applied through the anode terminal and the cathode terminal. Generally, the turn-on voltage that induces the light emitting operation of the light emitting diode has a very low value compared to the commercial power supply used. Therefore, the light emitting diode is disadvantageous in that it is difficult to directly use it under a commercial AC power source of 110V or 220V. In order to operate a light emitting diode using a commercial AC power source, a voltage converter is required to drop the supplied AC voltage. Accordingly, the driving circuit of the light emitting diode must be provided, and the manufacturing cost of the lighting device including the light emitting diode is increased. In addition, since a separate driving circuit must be provided, the volume of the lighting apparatus is increased, unnecessary heat is generated, and the power factor against the applied electric power remains.

In order to use commercial AC power without excluding a separate voltage converting means, a method of constructing an array by connecting a plurality of light emitting diode chips in series is proposed. In order to implement light emitting diodes as an array, the light emitting diode chips must be formed in individual packages. Accordingly, a substrate separation process, a packaging process for the separated light emitting diode chip, and the like are required. A mounting process for disposing the individual packages on the array substrate and a wiring process for the electrodes between the packages are separately required. Therefore, there is a problem that the process time for constructing the array increases and the manufacturing cost increases.

Further, wire bonding is used in the wiring step constituting the array, and a separate molding layer for protecting the bonding wire is formed on the entire surface of the array. Therefore, there is a problem that a molding forming process for forming a molding layer is further required, thereby increasing the complexity of the process. Particularly, when a chip type of a lateral structure is applied, deterioration of the light emitting performance and deterioration of the quality of the light emitting diode due to heat generation remain.

In order to solve the above-described problems, there is proposed a light emitting diode chip array in which an array of a plurality of light emitting diode chips is formed into a single package.

Korean Patent Publication No. 2007-0035745 discloses that a plurality of horizontal type light emitting diode chips are electrically connected to each other through a metal wiring formed by an air bridge process on a single substrate. According to the above-described patent, there is no need for a separate packaging process in individual chip units, and there is an advantage of forming an array at a wafer level. However, since it has an air bridge connection structure, its durability is poor, and the light emitting performance or heat generation performance is deteriorated due to the horizontal chip type.

In addition, U.S. Patent No. 6,573,537 discloses a plurality of flip chip type light emitting diodes on a single substrate. However, the n-electrode and the p-electrode of each light emitting diode are exposed while being separated from each other. Therefore, in order to use a single power source, a wiring process for connecting a plurality of electrodes to each other must be added. To this end, the submount substrate is used in the above patent. That is, flip chip type light emitting diodes should be mounted on a separate submount substrate for wiring between the electrodes. At least two electrodes for electrical connection with the substrate must be formed on the back surface of the submount substrate. Since the flip chip type is used, the light emitting performance and the heat generating performance are improved. On the other hand, the use of the submount substrate increases the manufacturing cost and increases the thickness of the final product. In addition, there is a disadvantage that an additional wiring process for the submount substrate and an additional process for mounting the submount substrate to the new substrate are required.

Korean Patent Publication No. 2008-0002161 discloses a configuration in which flip chip type light emitting diodes are connected in series to each other. According to the above-described patent, a chip-based packaging process is not required, and the use of the flip-chip type improves the light emitting characteristic and the heat generating performance. However, a separate reflective layer is used in addition to the wiring between the n-type semiconductor layer and the p-type semiconductor layer, and interconnection wiring is used on the n-type electrode. Therefore, a plurality of metalized metal layers must be formed, and various types of masks must be used for this purpose. Also, due to the difference in thermal expansion coefficient between the n electrode and the interconnection electrode, peeling or cracking is generated and electrical contact is opened.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a flip chip type light emitting diode array having an improved structure and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting diode array which can be used without a submount and a method of manufacturing the same.

Another object of the present invention is to provide a flip chip type light emitting diode array capable of preventing light loss in addition to a wiring for connecting a plurality of light emitting diodes without a separate reflective metal layer and a method of manufacturing the same.

Other features and advantages of the present invention will become apparent from the following description and from the description that follows.

According to one aspect of the present invention, there is provided a light emitting diode array including: a growth substrate; A plurality of light emitting diodes arranged on the substrate, the plurality of light emitting diodes including a first semiconductor layer, an active layer and a second semiconductor layer, respectively; And a plurality of upper electrodes arranged on the plurality of light emitting diodes and formed of the same material as each other and electrically connected to the first semiconductor layers of the corresponding light emitting diodes. Also, at least one of the upper electrodes is electrically connected to the second semiconductor layer of the adjacent light emitting diode, and the other of the upper electrodes is insulated from the second semiconductor layer of the adjacent light emitting diode.

Accordingly, it is possible to provide a flip chip type light emitting diode array which can be driven at a high voltage without using a submount and can simplify the manufacturing process.

The upper electrodes may include an ohmic contact layer that makes an ohmic contact with the first semiconductor layer. Since the upper electrodes include an ohmic contact layer, it is not necessary to form the ohmic contact layer and the upper electrode using a separate mask, and thus the manufacturing process can be further simplified.

The ohmic contact layer may comprise a metal material of Cr, Ni, Ti, Rh or Al, or ITO. The upper electrodes may further include a reflective layer positioned on the ohmic contact layer. The reflective layer may comprise Al, Ag, Rh or Pt. Furthermore, the upper electrodes may further include a barrier layer for protecting the reflective layer. The barrier layer may be formed as a single layer or a multilayer, and may have a thickness of 300 nm to 5000 nm.

The light emitting diode array may further include a first interlayer insulating film disposed between the light emitting diodes and the upper electrodes. The upper electrodes are insulated from the side surfaces of the light emitting diodes by the first interlayer insulating film. The first interlayer insulating layer may cover a side surface of the light emitting diodes as well as a region between the light emitting diodes. In addition, the upper electrodes are located on the first interlayer insulating film and may cover most of the region between the light emitting diodes. Conventionally, when a linear wiring is used, the wiring hardly covers the region between the light emitting diodes. In contrast, the upper electrodes may cover more than 30% of the area between the LEDs, and may cover more than 50% or even 90% of the area between the LEDs. However, since the upper electrodes are spaced apart from each other, the upper electrodes cover less than 100% of the area between the light emitting diodes.

By forming the upper electrode to have a relatively large area, the resistance due to the upper electrode can be reduced, so that the current dispersion can be facilitated and the forward voltage of the LED array can be lowered.

The light emitting diode array may further include lower electrodes aligned on a second semiconductor layer of each light emitting diode. The first interlayer insulating film exposes a part of the lower electrode on each light emitting diode. In addition, the upper electrode (s) electrically connected to the second semiconductor layer of the adjacent light emitting diode is connected to the exposed lower electrode through the first interlayer insulating film. Furthermore, the lower electrodes may each include a reflective layer.

The light emitting diode array may further include a second interlayer insulating film covering the upper electrodes. The second interlayer insulating layer exposes one of the lower electrodes and the upper electrode insulated from the second semiconductor layer of the adjacent light emitting diode.

Further, the light emitting diodes may be connected in series by the upper electrodes. At this time, the second interlayer insulating layer exposes the lower electrode and the upper electrode corresponding to the light emitting diodes at both ends of the series-connected light emitting diodes.

The light emitting diode array may further include a first pad and a second pad located on the second interlayer insulating layer. The first pad is connected to the lower electrode exposed through the second interlayer insulating film, and the second pad is connected to the upper electrode exposed through the second interlayer insulating film. Accordingly, a flip-type LED array capable of being mounted on a printed circuit board or the like using the first pad and the second pad is provided.

In some embodiments, the light emitting diodes may each have a via hole exposing the first semiconductor layer through a second semiconductor layer and an active layer. Each of the upper electrodes may be connected to the first semiconductor layer of the corresponding light emitting diode through the via hole.

On the other hand, the upper electrode may occupy an area of 30% or more and less than 100% of the total area of the LED array.

In addition, the upper electrode may have a plate or sheet shape with a ratio of width to width being in the range of 1: 3 to 3: 1. Unlike the conventional linear wiring, the upper electrode may be formed in a plate or sheet shape to facilitate current dispersion and reduce the forward voltage of the light emitting diode array.

At least one of the upper electrodes has a greater width or width than the width or width of the corresponding light emitting diode. Therefore, the upper electrode covers the region between the light emitting diodes and can reflect the light generated in the active layer to the substrate side.

According to another aspect of the present invention, a method of fabricating a light emitting diode array includes forming a plurality of light emitting diodes including a first semiconductor layer, an active layer, and a second semiconductor layer on a growth substrate, respectively. Each of the light emitting diodes has a first semiconductor layer exposed by removing the second semiconductor layer and the active layer. Thereafter, a first interlayer insulating film covering the light emitting diodes is formed. The first interlayer insulating layer exposes the exposed first semiconductor layers and has openings located above the second semiconductor layer of each light emitting diode. On the other hand, a plurality of upper electrodes are formed of the same material on the first interlayer insulating film. Each of the upper electrodes is connected to a first semiconductor layer of a corresponding light emitting diode. Further, at least one of the upper electrodes is electrically connected to the second semiconductor layer of the adjacent light emitting diode through the opening of the first interlayer insulating film, and the other of the upper electrodes is connected to the second semiconductor layer of the adjacent light emitting diode Is insulated.

According to this, a flip-chip type light emitting diode array capable of electrically connecting the light emitting diodes using the upper electrodes can be manufactured, so that it is not necessary to use the submount. In addition, the upper electrode may include an ohmic contact layer, and thus it is not necessary to separately form an ohmic contact on the first semiconductor layer of each light emitting diode.

The method may further include forming lower electrodes on the second semiconductor layer of each light emitting diode before forming the first interlayer insulating film. The lower electrodes may be formed after patterning the first semiconductor layer, the active layer, and the second semiconductor layer to form light emitting diodes spaced from each other, but they may be formed before forming the light emitting diodes.

The method may further include forming a second interlayer insulating film on the upper electrode. The second interlayer insulating film exposes another one of the lower electrodes and another upper electrode insulated from the second semiconductor layer of the adjacent light emitting diode.

The method may further include forming a first pad and a second pad on the second interlayer insulating film. The first pad is connected to the lower electrode, and the second pad is connected to the upper electrode.

The method may further include cutting the growth substrate into individual units, and the upper electrode may occupy an area of 30% or more but less than 100% of the area of the individual light emitting diode arrays cut.

According to embodiments of the present invention, a wafer level light emitting diode array capable of high voltage driving can be provided. The light emitting diode array does not require a submount, and the upper electrode may include an ohmic contact layer, so that it is not necessary to separately form the ohmic contact layer.

Furthermore, since the first pad and the second pad occupy a relatively large area, the light emitting diode array can be easily and firmly mounted on a printed circuit board or the like.

Also, since the upper electrode can cover most of the area between the side surfaces of the light emitting diodes and the light emitting diodes, light can be reflected by using the upper electrode, thereby reducing light loss occurring in the area between the light emitting diodes have. Therefore, it is not necessary to additionally form a separate reflective metal layer for reflecting light in addition to the upper electrode.

1 and 2 are a plan view and a cross-sectional view, respectively, illustrating formation of via holes in a plurality of stacked structures, according to an embodiment of the present invention.
FIGS. 3 and 4 are a plan view and a cross-sectional view illustrating that lower electrodes are formed on the second semiconductor layer of FIG.
5 is a plan view showing a state in which cell regions are separated from the structure of FIG.
6 is a cross-sectional view taken along the line A 1 -A 2 in the plan view of FIG. 5;
7 is a perspective view of the plan view of Fig.
8 is a plan view showing a first interlayer insulating film formed on the entire surface of the structures of FIGS. 5 to 7 and partially exposing the first semiconductor layer and the lower electrode in each cell region.
9 to 12 are cross-sectional views taken along a specific line in the plan view of FIG.
13 is a plan view showing top electrodes formed on the structure shown in Figs. 8 to 12. Fig.
Figs. 14 to 17 are cross-sectional views taken along a specific line in the plan view of Fig.
Fig. 18 is a perspective view showing the plan view of Fig. 13. Fig.
19 is an equivalent circuit diagram modeling the structures of FIGS. 13 to 18 according to an embodiment of the present invention.
FIG. 20 is a plan view of the structure of FIG. 13 in which a second interlayer insulating film is applied to the entire surface of the structure, a part of the first lower electrode of the first cell region is exposed, to be.
FIGS. 21 to 24 are cross-sectional views of the plan view of FIG. 20 taken along a specific line.
FIG. 25 is a plan view showing a first pad and a second pad formed on the structure of FIG. 20. FIG.
26 to 29 are cross-sectional views taken along a specific line in the plan view of Fig.
Fig. 30 is a perspective view of the plan view of Fig. 25 taken along line C2-C3.
31 is a circuit diagram modeling 10 LEDs connected in series according to an embodiment of the present invention.
32 is a circuit diagram modeling that light emitting diodes constitute an array in a linear / parallel form according to an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms.

In the present embodiments, "first "," second ", or "third" is not intended to impose any limitation on the components, but merely as terms for distinguishing components.

[Example]

1 and 2 are a plan view and a cross-sectional view, respectively, illustrating formation of via holes in a plurality of stacked structures, according to an embodiment of the present invention.

Particularly, Fig. 2 is a sectional view taken along line A1-A2 of the plan view of Fig.

1 and 2, a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 are formed on a substrate 100, and a surface of the first semiconductor layer 110 is exposed The via holes 140 are formed.

The substrate 100 may have a material of sapphire, silicon carbide, or GaN, and any material capable of inducing growth of a thin film to be formed may be used. The first semiconductor layer 110 may have an n-type conductivity. The active layer 120 may have a multiple quantum well structure, and the second semiconductor layer 130 may be formed on the active layer 120. When the first semiconductor layer 110 has an n-type conductivity, the second semiconductor layer 130 has a p-type conductivity. In addition, a buffer layer (not shown) may be further formed between the substrate 100 and the first semiconductor layer 110 to facilitate the single crystal growth of the first semiconductor layer 110.

Then, selective etching is performed on the structure formed up to the second semiconductor layer 130, and a plurality of via holes 140 are formed. A part of the lower first semiconductor layer 110 is exposed through the via hole 140. The via hole 140 may be formed according to a conventional etching process. For example, after a photoresist is applied, a photoresist pattern is formed by removing the photoresist in a region to be formed through a normal patterning process. Thereafter, the etching process is performed using the photoresist pattern as an etching mask. The etching process proceeds until a portion of the first semiconductor layer 110 is exposed. The remaining photoresist pattern is then removed.

The shape and the number of the via holes 140 may be variously changed.

FIGS. 3 and 4 are a plan view and a cross-sectional view, respectively, illustrating the formation of lower electrodes on the second semiconductor layer of FIG. 1. Particularly, FIG. 4 is a cross-sectional view taken along the line A1-A2 of FIG.

3 and 4, the lower electrodes 151, 152, 153, and 154 are formed in a region except for the via hole 140, and through the formation of the lower electrodes 151, 152, 153, and 154 A plurality of cell areas 161, 162, 163, and 164 may be defined. Further, the lower electrodes 151, 152, 153, and 154 may be formed using a lift-off process used in forming the metal electrode. For example, a photoresist is formed in an isolation region except the imaginary cell regions 161, 162, 163, and 164 and an area where the via hole 140 is formed, and a metal layer is formed through normal thermal evaporation or the like. Thereafter, the photoresist is removed to form lower electrodes 151, 152, 153, and 154 on the second semiconductor layer 130. The lower electrodes 151, 152, 153, and 154 may be formed of any metal that performs ohmic contact with the second semiconductor layer 130. The lower electrodes 151, 152, 153, and 154 may include Ni, Cr, or Ti, and may be formed of a composite metal layer of Ti / Al / Ni / Au, for example.

In FIGS. 3 and 4, an area where four lower electrodes 151, 152, 153, and 154 are formed defines four cell areas 161, 162, 163, and 164. The second semiconductor layer 130 is exposed in the spacing space between the cell regions 161, 162, 163, The number of the cell regions 161, 162, 163, and 164 may correspond to the number of the light emitting diodes included in the array to be formed. Therefore, the number of cell regions 161, 162, 163, and 164 can be variously changed.

4, the lower electrodes 151, 152, 153 and 154 are depicted as being separated in the same cell region 161, 162, 163 and 164, It is a phenomenon that occurs according to the cutting. 3, the lower electrodes 151, 152, 153, and 154 formed on the same cell regions 161, 162, 163, and 164 are physically connected. Therefore, the lower electrodes 151, 152, 153 and 154 formed on the same cell regions 161, 162, 163 and 164 are electrically short-circuited despite the formation of the via hole 140.

FIG. 5 is a plan view showing a state in which cell regions are separated from the structure of FIG. 3, FIG. 6 is a cross-sectional view taken along line A 1 -A 2 of FIG. 5, and FIG. 7 is a perspective view of a plan view of FIG. .

Referring to FIGS. 5, 6 and 7, a mesa etch region is formed through a mesa etch for a spacing space between four cell regions 161, 162, 163, and 164. The substrate 100 is exposed to the mesa etching region through the mesa etching. Therefore, the four cell regions 161, 162, 163, and 164 are completely electrically separated from each other. If the buffer layer is interposed between the substrate 100 and the first semiconductor layer 110 in FIGS. 1 to 4, the buffer layer may remain in the separation process of the cell regions 161, 162, 163, and 164 . However, the buffer layer between the cell regions 161, 162, 163, and 164 may be removed through the mesa etching in order to completely separate the cell regions 161, 162, 163, and 164.

The first semiconductor layers 111, 112, 113, 114 and the active layer (not shown) are formed for each of the cell regions 161, 162, 163, 164 through the separation process between the respective cell regions 161, 162, 163, The second semiconductor layers 131, 132, 133 and 134 and the lower electrodes 151, 152, 153 and 154 are formed. Accordingly, the first lower electrode 151 is exposed on the first cell region 161, and the first semiconductor layer 111 is exposed through the via hole 140. The second lower electrode 152 is exposed on the second cell region 162 and the first semiconductor layer 112 is exposed through the via hole 140. The third lower electrode 153 and the first semiconductor layer 113 are exposed on the third cell region 163 and the fourth lower electrode 154 and the first semiconductor layer 114 ) Is exposed.

In the present invention, the light emitting diode includes a structure in which the first semiconductor layers 111, 112, 113 and 114, the active layers 121, 122, 123 and 124 and the second semiconductor layers 131, 132, 133 and 134 are stacked Quot; Therefore, one light emitting diode is formed in one cell region. When the first semiconductor layers 111, 112, 113 and 114 have an n-type conductivity and the second semiconductor layers 131, 132, 133 and 134 have a p-type conductivity, The lower electrodes 151, 152, 153 and 154 formed on the second semiconductor layers 131, 132, 133 and 134 may be referred to as an anode electrode of the light emitting diode.

8 is a plan view showing a first interlayer insulating film formed on the entire surface of the structures of FIGS. 5 to 7 and partially exposing the first semiconductor layer and the lower electrode in each cell region.

9 to 12 are cross-sectional views of the plan view of FIG. 8 taken along a specific line. 8 is a cross-sectional view taken along line C1-C2 in FIG. 8, and FIG. 11 is a cross-sectional view taken along line D1-D2 in FIG. 12 is a cross-sectional view taken along line E1-E2 of the plan view of FIG. 8. FIG.

First, a first interlayer insulating film 170 is formed on the structures of FIGS. In addition, a part of the first semiconductor layers 111, 112, 113, 114 and the lower electrodes 151, 152, 153, 154 under the via hole is exposed through patterning.

For example, in the first cell region 161, two preformed via holes are opened to expose the first semiconductor layer 111, and a portion of the first lower electrode 151 formed on the formed second semiconductor layer 131 Is exposed. The first semiconductor layer 112 exposed through the previously formed via hole is exposed in the second cell region 162 and the second semiconductor layer 112 is etched through a portion of the first interlayer insulating film 170, Some are exposed. In addition, the first semiconductor layer 113 is exposed through the via hole in the third cell region 163, and a part of the third lower electrode 153 is exposed through etching of a part of the first interlayer insulating film 170 . In the fourth cell region 164, the first semiconductor layer 114 is exposed through the via hole, and a part of the fourth lower electrode 154 is exposed through etching of a part of the first interlayer insulating film 170.

8 to 12, a first interlayer insulating film 170 is formed on the entire surface of the substrate, and a first semiconductor layer 111 (not shown) in the via hole is formed for each of the cell regions 161, 162, 163, Portions of the lower electrodes 151, 152, 153 and 154 on the second semiconductor layers 131, 132, 133 and 134 are exposed. That is, the first semiconductor layers 111, 112, 113 and 114 exposed through the via holes formed in the previous step in the respective cell regions 161, 162, 163 and 164 are exposed, and the lower electrodes 151 and 152 , 153 and 154 are also exposed. And the remaining region is shielded by the first interlayer insulating film 170. The first interlayer insulating film 170 is made of an insulating material having predetermined light transmittance. For example, the first interlayer insulating film 170 may include SiO _2.

13 is a plan view showing top electrodes formed on the structure shown in Figs. 8 to 12. Fig. 14 to 17 are cross-sectional views of the plan view of FIG. 13 taken along a specific line. 13 is a cross-sectional view taken along the line C1-C2 in FIG. 13, and FIG. 16 is a cross-sectional view taken along line D1-D2 in FIG. 17 is a cross-sectional view of the plan view of FIG. 13 taken along line E1-E2.

Referring to FIG. 13, upper electrodes 181, 182, 183 and 184 are formed. The upper electrodes 181, 182, 183 and 184 are divided into four regions. For example, the first upper electrode 181 is formed over a portion of the first cell region 161 and the second cell region 162. Also, the second upper electrode 182 is formed over a portion of the second cell region 162 and a portion of the third cell region 163. The third upper electrode 183 is formed over a portion of the third cell region 163 and a portion of the fourth cell region 164 while the fourth upper electrode 184 is formed over a portion of the fourth cell region 164 . Thus, each of the upper electrodes 181, 182, 183, and 184 is formed to shield the spacing space between adjacent cell regions. The upper electrodes 181, 182, 183, and 184 may cover 30% or more, more than 50%, or 90% or more of the spacing space between cell areas. However, since the upper electrodes 181, 182, 183 and 184 are spaced apart from each other, the upper electrodes 181, 182, 183 and 184 cover less than 100% of the area between the light emitting diodes.

The entire upper electrodes 181, 182, 183, and 184 may occupy 30% or more of the total area of the LED array, and more than 50% or 90% or more of the total area of the LED array. Since the upper electrodes 181, 182, 183, and 184 are spaced apart from each other, they occupy less than 100% of the total area of the LED array. In addition, the upper electrodes 181, 182, 183 and 184 have a plate or sheet shape with a width-to-width ratio in the range of 1: 3 to 3: 1. Further, at least one of the upper electrodes 181, 182, 183, and 184 has a greater width or width than the width or width of the corresponding light emitting diode (cell region).

14, a first upper electrode 181 is formed on the first semiconductor layer 111 formed on the first interlayer insulating film 170 of the first cell region 161 and opened through a via hole . The first upper electrode 181 may open a part of the first lower electrode 151 of the first cell region 161 and may be formed on the exposed second lower electrode 152 of the second cell region 162 .

The second upper electrode 182 is formed on the first semiconductor layer 112 exposed through the via hole of the second cell region 162 while being physically separated from the first upper electrode 181, The first interlayer insulating film 170 is formed.

14, the first upper electrode 181 electrically connects the first semiconductor layer 111 of the first cell region 161 and the second semiconductor layer 132 of the second cell region 162. The second lower electrode 152 on the second cell region 162 is entirely electrically short-circuited in one cell region despite the presence of the via hole. The first semiconductor layer 111 of the first cell region 161 is electrically connected to the second semiconductor layer 132 of the second cell region 162 through the second lower electrode 152.

15, the second upper electrode 182 is formed on the first semiconductor layer 112 exposed through the via hole of the second cell region 162, and the third lower electrode 182 of the third cell region 163, (153). The third upper electrode 183 physically separated from the second upper electrode 182 is formed on the first semiconductor layer 113 exposed through the via hole of the third cell region 163.

The second upper electrode 182 is electrically connected to the first semiconductor layer 112 exposed through the via hole of the second cell region 162 and the third lower electrode of the third cell region 163 153, respectively. Therefore, the first semiconductor layer 112 of the second cell region 162 can maintain the same potential as the second semiconductor layer 133 of the third cell region 163.

16, the third upper electrode 183 is formed on the first semiconductor layer 113 exposed through the via hole of the third cell region 163, and the fourth lower electrode 183 of the fourth cell region 164 Electrode 154 as shown in Fig. Therefore, the first semiconductor layer 113 of the third cell region 163 and the second semiconductor layer 134 of the fourth cell region 164 are electrically connected. The fourth upper electrode 184 physically separated from the third upper electrode 183 is electrically connected to the first semiconductor layer 114 exposed through the via hole of the fourth cell region 164.

Referring to FIG. 17, a fourth upper electrode 184 is formed on the first semiconductor layer 114 exposed through the via hole of the fourth cell region 164. The first upper electrode 181 physically separated from the fourth upper electrode 184 is formed on the first semiconductor layer 111 exposed through the via hole on the first cell region 161, A portion of the first lower electrode 151 of the region 161 is exposed.

13 to 17, the first semiconductor layer 111 of the first cell region 161 and the second semiconductor layer 132 of the second cell region 162 are connected to the first upper electrode 181 ) To form an equipotential. The first semiconductor layer 112 of the second cell region 162 and the second semiconductor layer 133 of the third cell region 163 form an equal potential through the second upper electrode 182. The first semiconductor layer 113 of the third cell region 163 forms an equal potential with the second semiconductor layer 134 of the fourth cell region 164 through the third upper electrode 183. The first lower electrode 151 electrically connected to the second semiconductor layer 131 in the first cell region 161 is exposed.

Of course, the formation of the equipotential may be accomplished by changing the contact resistances of the upper electrodes 181, 182, 183 and 184 and the upper electrodes 181, 182, 183 and 184 and the lower electrodes 151, 152, 153 and 154 It is assumed that an ideal electrical connection is made in the ignored state. Therefore, in the actual operation of the device, a voltage drop due to resistance components of the upper electrodes 181, 182, 183, and 184 and the lower electrodes 151, 152, 153, and 154,

The upper electrodes 181, 182, 183, and 184 may be any material that can form an ohmic contact with the first semiconductor layers 111, 112, 113, and 114. The upper electrodes 181, 182, 183, and 184 may be used as the material that can form ohmic contact with the lower electrodes 151, 152, 153, and 154 made of metal. For example, the upper electrodes 181, 182, 183, and 184 may include a metal layer including Ni, Cr, Ti, Rh, or Al, or a conductive oxide layer such as ITO as an ohmic contact layer. In order to reflect light generated from the active layers 121, 122, 123 and 124 of the respective cell regions 161, 162, 163 and 164 toward the substrate 100, the upper electrodes 181, 182 and 183 , 184 may comprise a reflective layer such as Al, Ag, Rh or Pt. Particularly, light generated in the active layers 121, 122, 123, and 124 of the respective cell regions 161, 162, 163, and 164 is reflected from the lower electrodes 151, 152, 153, and 154 toward the substrate 100 do. The light transmitted through the spacing space between the cell regions 161,162, 163 and 164 also includes the upper electrodes 181,182, < RTI ID = 0.0 > 182, < / RTI & 183 and 184, respectively.

When the first semiconductor layers 111, 112, 113 and 114 have an n-type conductivity and the second semiconductor layers 131, 132, 133 and 134 have a p-type conductivity, May be modeled as a cathode electrode of a light emitting diode and the cathode electrode may be simultaneously modeled as a wiring connected to a lower electrode which is an anode electrode of a light emitting diode formed in an adjacent cell region. That is, in the light emitting diode formed on the cell region, the upper electrode may be modeled as a wiring which is electrically connected to the anode electrode of the light emitting diode of the adjacent cell region while forming the cathode electrode.

Fig. 18 is a perspective view showing the plan view of Fig. 13. Fig.

Referring to FIG. 18, the first to third upper electrodes 181 to 183 are formed over at least two cell regions. Thus, the spacing space between adjacent cell regions is shielded. In the case of the upper electrodes, light that may leak between adjacent cell regions is reflected through the substrate, and is electrically connected to the first semiconductor layer of each cell region. And is electrically connected to the second semiconductor layer of the adjacent cell region.

19 is an equivalent circuit diagram modeling the structures of FIGS. 13 to 18 according to an embodiment of the present invention.

Referring to Fig. 19, four light emitting diodes D1, D2, D3, and D4 and a wiring relationship therebetween are disclosed.

The first light emitting diode D1 is formed in the first cell region 161, the second light emitting diode D2 is formed in the second cell region 162, the third light emitting diode D3 is formed in the third cell region 163, And the diode D4 is formed in the fourth cell region 164. The first semiconductor layers 111, 112, 113 and 114 of the respective cell regions 161, 162, 163 and 164 are modeled as n-type semiconductors and the second semiconductor layers 131, 132, Is modeled as a p-type semiconductor.

The first upper electrode 181 is electrically connected to the first semiconductor layer of the first cell region 161 and extends to the second cell region 162 and is electrically connected to the second semiconductor layer of the second cell region 162 And is electrically connected. Accordingly, the first upper electrode 181 is modeled as wiring connecting the cathode terminal of the first light emitting diode D1 and the anode terminal of the second light emitting diode D2.

The second upper electrode 182 is modeled as wiring connecting between the cathode terminal of the second light emitting diode D2 and the anode terminal of the third light emitting diode D3 and the third upper electrode 183 is modeled as a wire connecting the anode terminal of the third light emitting diode D3 The cathode terminal and the anode terminal of the fourth light emitting diode D4. In addition, the fourth upper electrode 184 is modeled as wiring forming the cathode terminal of the fourth light emitting diode D4.

Accordingly, the anode terminal of the first light emitting diode D1 and the cathode terminal of the fourth light emitting diode D4 are electrically opened to the external power source, and the remaining light emitting diodes D2 and D3 form a series connection structure.

FIG. 20 is a plan view of the structure of FIG. 13 in which a second interlayer insulating film is applied to the entire surface of the structure, a part of the first lower electrode of the first cell region is exposed, to be.

20 is a cross-sectional view taken along the line B 1 -B 2 in FIG. 20, FIG. 22 is a cross-sectional view taken along line C 1 -C 2 of FIG. 20, FIG. 24 is a cross-sectional view of the plan view of FIG. 20 taken along line E1-E2.

Referring to FIG. 21, the first lower electrode 151 electrically connected to the second semiconductor layer 131 in the first cell region 161 is opened. And the remaining region is covered with the second interlayer insulating film 190 over the second cell region 162.

Referring to FIG. 22, the second cell region 162 and the third cell region 163 are completely covered with the second interlayer insulating film 190.

23 and 24, the fourth upper electrode 184 of the fourth cell region 164 is exposed, and the first lower electrode 151 of the first cell region 161 is exposed.

The second interlayer insulating film 190 is selected from an insulating material capable of protecting the underlying film from the external environment. Particularly, SiN, which has an insulating property and can block changes in temperature and humidity, can be used.

20 to 24, the second interlayer insulating film 190 is applied to the entire structure on the substrate. A part of the first lower electrode 151 of the first cell region 161 is exposed and the fourth upper electrode 184 of the fourth cell region 164 is exposed.

FIG. 25 is a plan view showing a first pad and a second pad formed on the structure of FIG. 20. FIG.

Referring to FIG. 25, the first pad 210 is formed over the first cell region 161 and the second cell region 162. The first pad 210 achieves electrical contact with the first lower electrode 151 of the first cell region 161 exposed in FIG.

The second pad 220 may be spaced apart from the first pad 210 by a predetermined distance and may extend over the third cell region 163 and the fourth cell region 164. The second pad 220 is electrically connected to the fourth upper electrode 184 of the fourth cell region 164 exposed in FIG.

25 is a cross-sectional view taken along the line C1-C2 in FIG. 25, and FIG. 28 is a cross-sectional view taken along the line D1-D2 in the plan view of FIG. And Fig. 29 is a cross-sectional view of the plan view of Fig. 25 taken along line E1-E2.

Referring to FIG. 26, a first pad 210 is formed over a first cell region 161 and a second cell region 162. The first pad 210 is formed on the first lower electrode 151 exposed in the first cell region 161. And is formed on the second interlayer insulating film 190 in the remaining region. Accordingly, the first pad 210 is electrically connected to the second semiconductor layer 131 of the first cell region 161 through the first lower electrode 151.

Referring to FIG. 27, a first pad 210 is formed on the second cell region 162 and a second pad 220 is formed on the third cell region 163 apart from the first pad 210 . The first pad 210 or the second pad 220 in the second cell region 162 and the third cell region 163 are electrically disconnected from the lower electrode or the upper electrode.

Referring to FIG. 28, a second pad 220 is formed over the third cell region 163 and the fourth cell region 164. In particular, the fourth upper electrode 184 opened in the fourth cell region 164 and the second pad 220 are electrically connected. Accordingly, the second pad 220 is electrically connected to the first semiconductor layer 114 of the fourth cell region 164.

29, a second pad 220 is formed on the fourth cell region 164 and a first pad 210 is formed on the first cell region 161 to be spaced apart from the second pad 220 . The first pad 210 is formed on the first lower electrode 151 of the first cell region 161 and is electrically connected to the second semiconductor layer 131.

Fig. 30 is a perspective view of the plan view of Fig. 25 taken along line C2-C3.

Referring to FIG. 30, the first semiconductor layer 113 of the third cell region 163 is electrically connected to the third upper electrode 183. The third upper electrode 183 shields the spaces between the third cell region 163 and the fourth cell region 164 and is electrically connected to the fourth lower electrode 154 of the fourth cell region 164. do. Also, the first pad 210 and the second pad 220 are spaced apart from each other and are formed on the second interlayer insulating film 190. Of course, as described above, the first pad 210 is electrically connected to the second semiconductor layer 131 of the first cell region 161, and the second pad 220 is electrically connected to the second semiconductor layer 131 of the fourth cell region 164 1 semiconductor layer 114, as shown in FIG.

Referring to the modeling of FIG. 19, the first semiconductor layers 111, 112, 113, and 114 of each cell region are modeled as n-type semiconductors, and the second semiconductor layers 131, 132, 133, Type semiconductor. The first lower electrode 151 formed on the second semiconductor layer 131 of the first cell region 161 is modeled as an anode electrode of the first light emitting diode D1. Accordingly, the first pad 210 may be modeled as a wiring connected to the anode electrode of the first light emitting diode D1. The fourth upper electrode 184 electrically connected to the first semiconductor layer 114 of the fourth cell region 164 is modeled as a cathode electrode of the fourth light emitting diode D4. Accordingly, the second pad 220 can be understood as a wiring connected to the cathode electrode of the fourth light emitting diode D4.

Through this, an array structure in which four light emitting diodes D1 to D4 are connected in series is formed, and electrical connection to the outside is achieved through two pads 210 and 220 formed on one substrate 100. [

In the present invention, four light emitting diodes are formed in a mutually separated form, and an anode terminal of one light emitting diode is electrically connected to a cathode terminal of another light emitting diode through a lower electrode and an upper electrode. However, according to the present embodiment, four light emitting diodes are only one embodiment, and various numbers of light emitting diodes can be formed according to the present invention.

31 is a circuit diagram modeling 10 LEDs connected in series according to an embodiment of the present invention.

Referring to FIG. 31, ten cell areas 301, 302, 303, 304, 305, 306, 307, 308, 309, 310 are defined using the process disclosed in FIG. The first semiconductor layer, the active layer, the second semiconductor layer and the lower electrode in the respective cell regions 301, 302, 303, 304, 305, 306, 307, 308, 309 and 310 are separated from other cell regions. Each lower electrode is formed on the second semiconductor layer to form an anode electrode of the light emitting diodes D1 to D10.

Subsequently, the first interlayer insulating film and the upper electrodes are formed using the processes shown in FIGS. However, the formed upper electrodes shield the spacing space between adjacent cell regions and function as wiring to achieve an electrical connection between the anode electrodes of the adjacent light emitting diodes.

In addition, a second interlayer insulating film is formed on the basis of the processes shown in FIGS. 20 to 29, the lower electrode of the first light emitting diode D1 connected to the positive power supply voltage V + in the current path is exposed, and the negative power supply voltage V The upper electrode of the tenth light emitting diode D10 is opened. Then, the first pad 320 is formed to connect the anode terminal of the first light emitting diode D1. Also, the second pad 330 is formed to connect the cathode terminal of the tenth light emitting diode D10.

In addition, the connection of the light emitting diodes may be composed of an array of a serial / parallel type.

32 is a circuit diagram modeling that light emitting diodes constitute an array in a linear / parallel form according to an embodiment of the present invention.

Referring to FIG. 32, the plurality of light emitting diodes D1 to D8 have a series connection and are connected in parallel with adjacent light emitting diodes. Each of the light emitting diodes D1 to D8 is formed independently of each other through the definition of the cell regions 401, 402, 403, 404, 405, 406, 407, As described above, the anode electrodes of the light emitting diodes D1 to D8 are formed through the lower electrode. Further, the wiring between the cathode electrode of the light emitting diodes D1 to D8 and the anode electrode of the adjacent light emitting diode is formed through formation of the upper electrode and proper wiring. However, the lower electrode is formed on the second semiconductor layer, and the upper electrode is formed to shield the spacing space between adjacent cell regions.

Finally, the first pad 410 to which the positive power supply voltage V + is supplied is electrically connected to the lower electrode formed on the second semiconductor layer of the first light emitting diode D1 or the third light emitting diode D3, and the negative power supply voltage V- The second pad 420 is electrically connected to the upper electrode, which is the cathode terminal of the sixth light emitting diode D6 or the eighth light emitting diode D8.

According to the present invention, the light generated in the active layer of each light emitting diode is reflected toward the substrate from the lower electrode and the upper electrode, and the flip chip type light emitting diodes are electrically connected to one substrate through the wiring of the upper electrode . The upper electrode is shielded from the outside through the second interlayer insulating film. The first pad to which the positive power supply voltage is supplied is electrically connected to the lower electrode of the light emitting diode which is connected closest to the positive power supply voltage. Also, a second pad to which a negative power supply voltage is supplied is electrically connected to an upper electrode of the light emitting diode connected closest to the negative power supply voltage.

Therefore, a complicated process of mounting two chips on an external power source through the wiring arranged on the submount substrate is achieved by mounting a plurality of chips on the submount substrate in the flip chip type. In addition, the spacing space between the cell areas can be shielded through the top electrode to maximize the reflection of light towards the substrate.

Further, the second interlayer insulating film protects a plurality of laminated structures disposed between the substrate and the second interlayer insulating film from external temperature, humidity, and the like. Therefore, a structure that can be directly mounted on the substrate without the intervention of another packaging means is realized.

In particular, since a plurality of light emitting diodes are implemented as a flip chip type on one substrate, there is an advantage that a commercial power supply can be directly used in a state in which a voltage drop, a level conversion, or a wave form conversion to a supplied commercial power supply is excluded .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, This is possible.

100: substrate
111, 112, 113, and 114: a first semiconductor layer
121, 122, 123, 124:
131, 132, 133, 134: a second semiconductor layer
140:
151: first lower electrode
152: second lower electrode
153: third lower electrode
154: fourth lower electrode
161: first cell region
162: Second cell area
163: Third cell region
164: fourth cell region
170: a first interlayer insulating film
181: first upper electrode
182: second upper electrode
183: third upper electrode
184: fourth upper electrode
190: a second interlayer insulating film
210: first pad
220: second pad

Claims (19)

Board;
A first light emitting diode to a fourth light emitting diode formed on the substrate, the first light emitting diode including a first semiconductor layer, the active layer, and the second semiconductor layer;
First to fourth upper electrodes formed on the first to fourth light emitting diodes;
The first to fourth light emitting diodes are arranged between the first to fourth upper electrodes to isolate the first to fourth upper electrodes from the side surfaces of the first to fourth light emitting diodes A first interlayer insulating film;
A first pad formed over the upper region of the first light emitting diode and the second light emitting diode and electrically connected to the first light emitting diode; And
A pad formed over an upper region of the third light emitting diode and the fourth light emitting diode and electrically connected to the fourth light emitting diode;
/ RTI >
The first light emitting diode and the second light emitting diode are arranged in one direction, the third light emitting diode and the fourth light emitting diode are arranged in a direction opposite to one direction,
The first upper electrode electrically connects the first semiconductor layer of the first light emitting diode and the second semiconductor layer of the second light emitting diode,
The second upper electrode is electrically connected to the first semiconductor layer of the second light emitting diode,
The third upper electrode electrically connects the first semiconductor layer of the third light emitting diode and the second semiconductor layer of the fourth light emitting diode,
The fourth upper electrode is electrically connected to the first semiconductor layer of the fourth light emitting diode,
Wherein the first pad and the second pad are spaced apart from each other. The method according to claim 1,
And the first upper electrode to the fourth upper electrode include an ohmic contact layer that makes an ohmic contact with the first semiconductor layer. The method of claim 2,
Wherein the ohmic contact layer comprises any one metal material selected from the group consisting of Cr, Ni, Ti, Rh, and Al. The method according to claim 1,
Wherein the first upper electrode extends from an upper portion of the first light emitting diode and covers a side surface of the fourth light emitting diode. The method according to claim 1,
Wherein the first interlayer insulating film covers an upper surface of the substrate located outside the first to fourth light emitting diodes. The method according to claim 1,
Further comprising lower electrodes aligned on a second semiconductor layer of the first to fourth light emitting diodes,
Wherein the first interlayer insulating layer exposes a part of the lower electrodes on the first light emitting diode to the second light emitting diode,
The first upper electrode is connected to the lower electrode of the second light emitting diode exposed by the first interlayer insulating film,
And the third upper electrode is connected to the lower electrode of the fourth light emitting diode exposed by the first interlayer insulating film. The method of claim 6,
And a second interlayer insulating film covering the first upper electrode to the fourth upper electrode,
Wherein the second interlayer insulating film exposes a lower electrode of the first light emitting diode exposed by the first upper electrode of the fourth light emitting diode and the first interlayer insulating film. The method of claim 7,
Wherein the first light emitting diode to the fourth light emitting diode are connected in series by the first upper electrode to the fourth upper electrode. The method of claim 7,
The first pad is connected to the lower electrode of the first light emitting diode exposed through the second interlayer insulating film and the second pad is connected to the first upper electrode of the fourth light emitting diode exposed through the second interlayer insulating film, To the light emitting diode array. The method according to claim 1,
The third light emitting diode is disposed in a direction perpendicular to the one direction of the second light emitting diode,
And the second upper electrode extends from an upper portion of the second light emitting diode to an upper portion of the third light emitting diode. The method of claim 10,
The second upper electrode includes a protruding region partially protruded from the upper portion of the third light emitting diode,
And the second upper electrode has the protruding region connected to the second semiconductor layer of the third light emitting diode and electrically connected to the second semiconductor layer of the third light emitting diode. The method of claim 11,
And the third upper electrode has a concave structure corresponding to the protruding region of the second upper electrode. The method according to claim 1,
The first light emitting diode to the fourth light emitting diode each have a via hole for exposing the first semiconductor layer through a second semiconductor layer and an active layer,
Wherein the first upper electrode to the fourth upper electrode are connected to the first semiconductor layer of the corresponding one of the first to fourth light emitting diodes through the via hole. The method according to claim 1,
Wherein the first upper electrode and the fourth upper electrode occupy an area of 30% or more and less than 100% of the total area of the light emitting diode array. The method according to claim 1,
Wherein the first upper electrode to the fourth upper electrode have a plate or sheet shape having a width-width ratio within a range of 1: 3 to 3: 1. The method according to claim 1,
Wherein at least one of the first to fourth upper electrodes has a greater width or width than a width or width of the corresponding light emitting diode. The method according to claim 1,
The first pad is formed to cover the side portions of the first light emitting diode and the second light emitting diode,
And the second pad covers the sides of the third light emitting diode and the fourth light emitting diode. 18. The method of claim 17,
Wherein one side of the first light emitting diode and one side of the second light emitting diode are opposed to each other. 18. The method of claim 17,
Wherein one side of the third light emitting diode and one side of the fourth light emitting diode face each other.

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