KR20180088798A - 얇은 솔더 정지 층을 갖는 전기 디바이스 및 제조를 위한 방법 - Google Patents

얇은 솔더 정지 층을 갖는 전기 디바이스 및 제조를 위한 방법 Download PDF

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Publication number
KR20180088798A
KR20180088798A KR1020187011776A KR20187011776A KR20180088798A KR 20180088798 A KR20180088798 A KR 20180088798A KR 1020187011776 A KR1020187011776 A KR 1020187011776A KR 20187011776 A KR20187011776 A KR 20187011776A KR 20180088798 A KR20180088798 A KR 20180088798A
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South Korea
Prior art keywords
stop layer
carrier
solder stop
lss
top surface
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KR1020187011776A
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English (en)
Korean (ko)
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알렉산더 슈마예브
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스냅트랙, 인코포레이티드
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Publication of KR20180088798A publication Critical patent/KR20180088798A/ko
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
KR1020187011776A 2015-11-27 2016-09-06 얇은 솔더 정지 층을 갖는 전기 디바이스 및 제조를 위한 방법 Ceased KR20180088798A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102015120647.1A DE102015120647B4 (de) 2015-11-27 2015-11-27 Elektrisches Bauelement mit dünner Lot-Stopp-Schicht und Verfahren zur Herstellung
DE102015120647.1 2015-11-27
PCT/EP2016/070973 WO2017088998A1 (de) 2015-11-27 2016-09-06 Elektrisches bauelement mit dünner lot-stopp-schicht und verfahren zu seiner herstellung

Publications (1)

Publication Number Publication Date
KR20180088798A true KR20180088798A (ko) 2018-08-07

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Country Status (8)

Country Link
US (1) US20180331062A1 (enExample)
EP (1) EP3381052A1 (enExample)
JP (1) JP2018536994A (enExample)
KR (1) KR20180088798A (enExample)
CN (1) CN108369935A (enExample)
BR (1) BR112018010666A8 (enExample)
DE (1) DE102015120647B4 (enExample)
WO (1) WO2017088998A1 (enExample)

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Publication number Priority date Publication date Assignee Title
FI130166B (en) 2019-03-08 2023-03-23 Picosun Oy Solder mask
DE102023116055A1 (de) * 2023-06-20 2024-12-24 Ams-Osram International Gmbh Anschlussträger, verfahren zur herstellung einer lotverbindung und bauelement

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WO2004027850A1 (en) * 2002-09-20 2004-04-01 Honeywell International, Inc. Interlayer adhesion promoter for low k materials
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Also Published As

Publication number Publication date
CN108369935A (zh) 2018-08-03
WO2017088998A1 (de) 2017-06-01
DE102015120647B4 (de) 2017-12-28
US20180331062A1 (en) 2018-11-15
BR112018010666A2 (pt) 2018-11-13
BR112018010666A8 (pt) 2019-02-26
EP3381052A1 (de) 2018-10-03
JP2018536994A (ja) 2018-12-13
DE102015120647A1 (de) 2017-06-01

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