BR112018010666A8 - dispositivo elétrico com camada de máscara de solda fina e método para produção - Google Patents
dispositivo elétrico com camada de máscara de solda fina e método para produçãoInfo
- Publication number
- BR112018010666A8 BR112018010666A8 BR112018010666A BR112018010666A BR112018010666A8 BR 112018010666 A8 BR112018010666 A8 BR 112018010666A8 BR 112018010666 A BR112018010666 A BR 112018010666A BR 112018010666 A BR112018010666 A BR 112018010666A BR 112018010666 A8 BR112018010666 A8 BR 112018010666A8
- Authority
- BR
- Brazil
- Prior art keywords
- mask layer
- fixture
- production method
- welding mask
- thin welding
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/384—Bump effects
- H01L2924/3841—Solder bridging
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102015120647.1A DE102015120647B4 (de) | 2015-11-27 | 2015-11-27 | Elektrisches Bauelement mit dünner Lot-Stopp-Schicht und Verfahren zur Herstellung |
| PCT/EP2016/070973 WO2017088998A1 (de) | 2015-11-27 | 2016-09-06 | Elektrisches bauelement mit dünner lot-stopp-schicht und verfahren zu seiner herstellung |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| BR112018010666A2 BR112018010666A2 (pt) | 2018-11-13 |
| BR112018010666A8 true BR112018010666A8 (pt) | 2019-02-26 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| BR112018010666A BR112018010666A8 (pt) | 2015-11-27 | 2016-09-06 | dispositivo elétrico com camada de máscara de solda fina e método para produção |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US20180331062A1 (enExample) |
| EP (1) | EP3381052A1 (enExample) |
| JP (1) | JP2018536994A (enExample) |
| KR (1) | KR20180088798A (enExample) |
| CN (1) | CN108369935A (enExample) |
| BR (1) | BR112018010666A8 (enExample) |
| DE (1) | DE102015120647B4 (enExample) |
| WO (1) | WO2017088998A1 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FI130166B (en) | 2019-03-08 | 2023-03-23 | Picosun Oy | Solder mask |
| DE102023116055A1 (de) * | 2023-06-20 | 2024-12-24 | Ams-Osram International Gmbh | Anschlussträger, verfahren zur herstellung einer lotverbindung und bauelement |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03218644A (ja) * | 1990-01-24 | 1991-09-26 | Sharp Corp | 回路基板の接続構造 |
| US5620131A (en) * | 1995-06-15 | 1997-04-15 | Lucent Technologies Inc. | Method of solder bonding |
| US6294840B1 (en) * | 1999-11-18 | 2001-09-25 | Lsi Logic Corporation | Dual-thickness solder mask in integrated circuit package |
| US6645791B2 (en) * | 2001-04-23 | 2003-11-11 | Fairchild Semiconductor | Semiconductor die package including carrier with mask |
| WO2004027850A1 (en) * | 2002-09-20 | 2004-04-01 | Honeywell International, Inc. | Interlayer adhesion promoter for low k materials |
| JP2006511938A (ja) * | 2002-12-20 | 2006-04-06 | アギア システムズ インコーポレーテッド | 銅相互接続構造に結合するための構造および方法 |
| US6790759B1 (en) * | 2003-07-31 | 2004-09-14 | Freescale Semiconductor, Inc. | Semiconductor device with strain relieving bump design |
| US7294451B2 (en) * | 2003-11-18 | 2007-11-13 | Texas Instruments Incorporated | Raised solder-mask-defined (SMD) solder ball pads for a laminate electronic circuit board |
| US7132303B2 (en) * | 2003-12-18 | 2006-11-07 | Freescale Semiconductor, Inc. | Stacked semiconductor device assembly and method for forming |
| KR100626617B1 (ko) * | 2004-12-07 | 2006-09-25 | 삼성전자주식회사 | 반도체 패키지용 배선 기판의 볼 랜드 구조 |
| JP4795112B2 (ja) * | 2006-05-17 | 2011-10-19 | 株式会社フジクラ | 接合基材の製造方法 |
| JP5031403B2 (ja) * | 2007-03-01 | 2012-09-19 | 京セラケミカル株式会社 | 封止用エポキシ樹脂組成物、樹脂封止型半導体装置及びその製造方法 |
| US7812460B2 (en) * | 2008-05-30 | 2010-10-12 | Unimicron Technology Corp. | Packaging substrate and method for fabricating the same |
| US9524945B2 (en) * | 2010-05-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with L-shaped non-metal sidewall protection structure |
| US8922004B2 (en) * | 2010-06-11 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper bump structures having sidewall protection layers |
| TWI575684B (zh) * | 2011-06-13 | 2017-03-21 | 矽品精密工業股份有限公司 | 晶片尺寸封裝件 |
| KR101307436B1 (ko) * | 2011-11-10 | 2013-09-12 | (주)유우일렉트로닉스 | Mems 센서 패키징 및 그 방법 |
| US10192804B2 (en) * | 2012-07-09 | 2019-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump-on-trace packaging structure and method for forming the same |
| GB2520952A (en) * | 2013-12-04 | 2015-06-10 | Ibm | Flip-chip electronic device with carrier having heat dissipation elements free of solder mask |
| CN104637967A (zh) * | 2015-02-13 | 2015-05-20 | 苏州晶方半导体科技股份有限公司 | 封装方法及封装结构 |
| US9859234B2 (en) * | 2015-08-06 | 2018-01-02 | Invensas Corporation | Methods and structures to repair device warpage |
-
2015
- 2015-11-27 DE DE102015120647.1A patent/DE102015120647B4/de active Active
-
2016
- 2016-09-06 EP EP16762778.5A patent/EP3381052A1/de not_active Withdrawn
- 2016-09-06 WO PCT/EP2016/070973 patent/WO2017088998A1/de not_active Ceased
- 2016-09-06 CN CN201680062169.7A patent/CN108369935A/zh active Pending
- 2016-09-06 KR KR1020187011776A patent/KR20180088798A/ko not_active Ceased
- 2016-09-06 BR BR112018010666A patent/BR112018010666A8/pt not_active Application Discontinuation
- 2016-09-06 US US15/776,019 patent/US20180331062A1/en not_active Abandoned
- 2016-09-06 JP JP2018527165A patent/JP2018536994A/ja not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| CN108369935A (zh) | 2018-08-03 |
| KR20180088798A (ko) | 2018-08-07 |
| WO2017088998A1 (de) | 2017-06-01 |
| DE102015120647B4 (de) | 2017-12-28 |
| US20180331062A1 (en) | 2018-11-15 |
| BR112018010666A2 (pt) | 2018-11-13 |
| EP3381052A1 (de) | 2018-10-03 |
| JP2018536994A (ja) | 2018-12-13 |
| DE102015120647A1 (de) | 2017-06-01 |
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| B11Y | Definitive dismissal - extension of time limit for request of examination expired [chapter 11.1.1 patent gazette] |