KR20180088124A - Semiconductor device, method of fabricating semiconductor device, semiconductor device package, and method of fabricating semiconductor device package - Google Patents

Abstract

An embodiment of the present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, a semiconductor device package, and a method for manufacturing the semiconductor device package. The semiconductor device according to an embodiment of the present invention includes a semiconductor layer, a metal layer disposed on the semiconductor layer, a porous metal layer disposed on the metal layer, and a bonding metal layer disposed on the porous metal layer. According to an embodiment of the present invention, the porous metal layer includes a plurality of pores. The porous metal layer includes the same material as the metal layer. The metal layer includes at least one selected from a group including Au, Ag, and Cu, and the bonding metal layer includes Sn. Accordingly, the present invention can perform stable bonding.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, a semiconductor device package, and a method of manufacturing a semiconductor device package. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

The present invention relates to a semiconductor device, a semiconductor device manufacturing method, a semiconductor device package, and a method of manufacturing a semiconductor device package.

Semiconductor devices including compounds such as GaN and AlGaN have many merits such as wide and easy bandgap energy, and can be used variously as light emitting devices, light receiving devices, and various diodes.

Particularly, a light emitting device such as a light emitting diode or a laser diode using a Group III-V or Group II-VI compound semiconductor material can be used for a variety of applications such as red, Blue and ultraviolet rays can be realized. In addition, a light emitting device such as a light emitting diode or a laser diode using a Group III-V or Group-VI-VI compound semiconductor material can realize a white light source having high efficiency by using a fluorescent material or combining colors. Such a light emitting device has advantages of low power consumption, semi-permanent lifetime, fast response speed, safety, and environment friendliness compared with conventional light sources such as fluorescent lamps and incandescent lamps.

In addition, when a light-receiving element such as a photodetector or a solar cell is manufactured using a Group III-V or Group-VI-VI compound semiconducting material, development of a device material absorbs light of various wavelength regions to generate a photocurrent , It is possible to use light in various wavelength ranges from the gamma ray to the radio wave region. Further, such a light receiving element has advantages of fast response speed, safety, environmental friendliness and easy control of element materials, and can be easily used for power control or microwave circuit or communication module.

Accordingly, the semiconductor device can be replaced with a transmission module of an optical communication means, a light emitting diode backlight replacing a cold cathode fluorescent lamp (CCFL) constituting a backlight of an LCD (Liquid Crystal Display) display device, White light emitting diode (LED) lighting devices, automotive headlights, traffic lights, and gas and fire sensors. In addition, semiconductor devices can be applied to high frequency application circuits, other power control devices, and communication modules.

The light emitting device can be provided as a pn junction diode having a characteristic in which electric energy is converted into light energy by using a group III-V element or a group II-VI element in the periodic table, Various wavelengths can be realized by adjusting the composition ratio.

On the other hand, semiconductor devices are required to have high output and high voltage driving as their application fields are diversified. The temperature is increased by the heat generated in the semiconductor device due to the high output and high voltage driving of the semiconductor device. However, when the heat emission from the semiconductor device is not smooth, the light output may decrease and the power conversion efficiency (PCE) may decrease due to the temperature rise. Accordingly, there is a demand for a technique for efficiently discharging heat generated from a semiconductor device and improving power conversion efficiency.

In addition, the semiconductor device may include an electrode capable of being supplied with power for driving from the outside. In addition, the semiconductor device may be electrically connected to a pad portion provided on an external submount or lead frame, for example, as a method of supplying power from the outside. At this time, the semiconductor device can be electrically connected to the pad portion by die bonding, flip chip bonding, wire bonding or the like.

On the other hand, a bonding pad may be used for electrical connection between the electrode of the semiconductor element and the pad portion. The bonding pad may be provided on at least one of the semiconductor element and the pad portion. At this time, there is a demand for a method of electrically connecting a semiconductor element and a pad portion by providing a small pressure at a low temperature and providing a stable bonding force.

Embodiments can provide a semiconductor device, a semiconductor device manufacturing method, a semiconductor device package, and a method of manufacturing a semiconductor device package, wherein stable bonding can be performed with provision of a small pressure at a low temperature.

A semiconductor device according to an embodiment includes: a semiconductor layer; A metal layer disposed on the semiconductor layer; A porous metal layer disposed on the metal layer and including a plurality of pores; A bonding metal layer disposed on the porous metal layer; . ≪ / RTI >

According to an embodiment, the porous metal layer may comprise the same material as the metal layer.

According to an embodiment of the present invention, the metal layer includes at least one selected from the group consisting of Au, Ag, and Cu, and the bonding metal layer may include Sn.

A semiconductor device package according to an embodiment includes: a pad portion; A bonding metal layer disposed on the pad portion; An alloy layer disposed on the bonding metal layer; A porous metal layer disposed on the alloy layer and including a plurality of pores; A metal layer disposed on the porous metal layer; A semiconductor layer disposed on the metal layer; And the alloy layer may include an alloy formed by bonding the material contained in the bonding metal layer and the material contained in the porous metal layer.

According to the embodiment, the melting point of the alloy layer can be provided higher than the melting point of the bonding metal layer.

A method of fabricating a semiconductor device according to an embodiment includes: forming a metal layer on a semiconductor layer; Forming an alloy layer in which a first metal and a second metal are bonded on the metal layer; Removing the second metal through a chemical treatment on the alloy layer and forming a porous metal layer of a first metal including a plurality of pores; Forming a bonding metal layer on the porous metal layer; . ≪ / RTI >

A method of manufacturing a semiconductor device package according to an embodiment includes: providing a pad portion; Providing the bonding metal layer of the semiconductor device to be in contact with the pad portion; Wherein the bonding metal layer is bonded to the bonding metal layer in the porous metal layer by providing at least one of heat or pressure to bond the bonding metal layer to the pad portion and diffusing the material contained in the bonding metal layer into a plurality of pores provided in the porous metal layer, Forming an alloy layer by bonding the material and the material contained in the porous metal layer; . ≪ / RTI >

According to the semiconductor device, the semiconductor device manufacturing method, the semiconductor device package, and the semiconductor device package manufacturing method according to the embodiments, stable bonding can be performed by providing a small pressure at a low temperature.

1 is a view showing a semiconductor device according to an embodiment of the present invention.
FIGS. 2 and 3 are views illustrating a process of forming a porous metal layer applied to a semiconductor device according to an embodiment of the present invention.
4 is a photograph showing a cross section of the porous metal layer shown in Fig.
5 is a photograph showing the surface of the porous metal layer shown in Fig.
6 is a diagram illustrating a semiconductor device package according to an embodiment of the present invention.
7 is a view showing another example of a semiconductor device package according to an embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the accompanying drawings. In the description of the embodiments, it is to be understood that each layer (film), area, pattern or structure may be referred to as being "on" or "under" the substrate, each layer Quot; on " and " under " are intended to include both "directly" or "indirectly" do. Further, the description of the upper, lower, or lower layers of each layer will be described with reference to the drawings.

Hereinafter, a semiconductor device, a semiconductor device manufacturing method, a semiconductor device package, and a semiconductor device package manufacturing method according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

A semiconductor device according to an embodiment of the present invention can be applied to a light emitting device including a light emitting diode device and a laser diode device. Further, the semiconductor device according to the embodiment of the present invention can be applied to a light receiving element. Further, the semiconductor device according to the embodiment of the present invention can be applied to a power device.

First, a semiconductor device according to an embodiment will be described with reference to FIG. 1 is a view showing a semiconductor device according to an embodiment of the present invention.

The semiconductor device 100 according to the embodiment may include a semiconductor layer 110, as shown in FIG. The semiconductor device 100 shown in FIG. 1 shows only a part of the semiconductor layer 110 in which power is supplied from the outside.

The semiconductor layer 110 may be formed of a compound semiconductor. For example, the semiconductor layer 110 may be formed of a Group 2-VI compound semiconductor or a Group 3B-5 compound semiconductor. For example, the semiconductor layer 110 may include at least two elements selected from aluminum (Al), gallium (Ga), indium (In), phosphorus (P), arsenic (As) .

The semiconductor layer 110 may be a semiconductor material having a composition formula of In _x Al _y Ga _{1 -x- y} N (0? X? 1, 0? _Y? 1, 0? _X + y? 1) Lt; / RTI > The semiconductor layer 110 may be selected from, for example, InAlGaN, InAlN, InGaN, AlGaN, and GaN.

Further, according to the embodiment, the semiconductor layer 110 _{(Al x Ga 1 -x) y} In 1 - be provided with a semiconductor material having a composition formula _y P (0≤x≤1, 0≤y≤1) . The semiconductor layer 110 may be selected from, for example, AlGaInP, AlInP, GaP, GaInP, and the like.

Also, according to the embodiment, the semiconductor layer 110 may include an n-type dopant. For example, the semiconductor layer 110 may include at least one dopant selected from the group including Si, Ge, Sn, Se, Te, and the like. In addition, the semiconductor layer 110 may include a p-type dopant. For example, the semiconductor layer 110 may include at least one dopant selected from the group consisting of Mg, Zn, Ca, Sr, and Ba.

The semiconductor device 110 according to the embodiment may include a metal layer 120, a porous metal layer 130, and a bonding metal layer 140, as shown in FIG. For example, the metal layer 120, the porous metal layer 130, and the bonding metal layer 140 may be collectively referred to as a bonding pad layer.

According to the semiconductor device 110 of the embodiment, a separate conductive material electrically connected to the semiconductor layer 110 may be further provided between the metal layer 120 and the semiconductor layer 110. According to another embodiment of the semiconductor device 110, the metal layer 120 may not be provided, and the porous metal layer 130 may be disposed in direct contact with the semiconductor layer 110.

According to an embodiment, the metal layer 120 may be disposed on the semiconductor layer 110, as shown in FIG. The porous metal layer 130 may be disposed on the metal layer 120. The porous metal layer 130 may include a plurality of pores. The bonding metal layer 140 may be disposed on the porous metal layer 130.

The porous metal layer 130 according to an embodiment may include the same material as the metal layer 120, for example. The metal layer 120 may include a material having excellent adhesion to the semiconductor layer 110. In addition, the metal layer 120 may include a material having excellent reflection characteristics. The metal layer 120 may include at least one selected from the group including, for example, Au, Ag, and Cu.

The porous metal layer 130 may be referred to as a metal sponge layer, which is a metal layer comprising a plurality of pores. As an example, the porous metal layer 130 may be provided in a thickness of a few micrometers. The method of forming the porous metal layer 120 will be described later.

The semiconductor device 100 according to the embodiment may be attached to a submount or attached to a lead frame or the like and supplied in the form of a semiconductor device package. At this time, the bonding metal layer 140 may be electrically connected to a pad portion provided on the submount or a pad portion provided on the lead frame. For example, the bonding metal layer 140 may be disposed in direct contact with a pad portion provided on the submount or a pad portion provided on the lead frame.

According to the embodiment, the bonding metal layer 130 may include a bonding material for connection with the pad portion. For example, the bonding metal layer 130 may include tin (Sn) for electrical connection with the pad portion.

A method of forming the porous metal layer 130 according to the embodiment will now be described with reference to FIGS. 2 and 3. FIG. FIGS. 2 and 3 are views illustrating a process of forming a porous metal layer applied to a semiconductor device according to an embodiment of the present invention.

According to the embodiment, as shown in FIG. 2, an alloy layer in which the first metal 131 and the second metal 133 are combined may be formed on the substrate 105. For example, the first metal 131 and the second metal 133 may be formed on the substrate 105 by an electron beam evaporator or the like. The first metal 131 and the second metal 133 may be selected from materials that satisfy the physical properties that can be combined with each other to form an alloy layer.

For example, the first metal 131 may be selected from the group including Au, Ag, and Cu. Also, the bimetal 133 may be selected from a bonding material containing Sn as an example.

Thereafter, the alloy layer may be chemically treated to remove the second metal 133 from the alloy layer. As the second metal 133 is removed from the alloy layer, a porous metal layer 130 including a plurality of pores p may be formed. For example, a plurality of pores p may be formed in a region where the second metal 133 is removed from the alloy layer in which the first metal 131 and the second metal 133 are combined. The plurality of pores p provided in the porous metal layer 130 may be provided in a nano-size, for example.

According to the embodiment, the porous metal layer 130 may be formed of an alloy layer having a plurality of pores, as shown in FIGS. FIG. 4 is a photograph showing a cross section of the porous metal layer shown in FIG. 3, and FIG. 5 is a photograph showing the surface of the porous metal layer shown in FIG.

As shown in FIGS. 4 and 5, it can be seen that the porous metal layer 130 according to the embodiment has a plurality of pores formed on its surface, and that a plurality of pores are formed also in the depth direction . The porous metal layer 130 according to an embodiment may be referred to as a kind of metal sponge layer including a plurality of pores. By way of example, the porous metal layer 130 may be referred to as a metal sponge layer having a plurality of nano-scale pores.

The chemical treatment for the alloy layer may be, for example, an etching solution. The second metal (133) may be removed from the alloy layer by selection of an appropriate etchant to form the porous metal layer (130) provided with a plurality of pores (p).

By way of example, the etchant may comprise a solution of strong acid or a solution of strong alkali. The etchant may be selected from at least one of strong acid solutions containing nitric acid (HNO ₃ ). Also, the etching solution may be selected from at least one of strong alkaline solutions containing sodium hydroxide (NaOH).

According to an embodiment, the porous metal layer 130, which may be applied to the semiconductor device 100, may be formed in a manner similar to that described with reference to FIGS.

According to the method for fabricating a semiconductor device according to the embodiment, the metal layer 120 may be formed on the semiconductor layer 110.

An alloy layer in which the first metal and the second metal are combined may be formed on the metal layer 120. Next, as described with reference to FIGS. 2 and 3, the second metal may be removed through chemical treatment of the alloy layer to form a porous metal layer 130 of a first metal comprising a plurality of pores have.

The bonding metal layer 140 may be formed on the porous metal layer 130.

According to the method of manufacturing a semiconductor device according to the embodiment, a bonding pad layer capable of supplying electricity to the semiconductor layer 110 can be formed through this process.

On the other hand, the semiconductor device 100 according to the embodiment may be attached to a submount or attached to a lead frame or the like and supplied in the form of a semiconductor device package. At this time, the bonding metal layer 140 may be electrically connected to a pad portion provided on the submount or a pad portion provided on the lead frame. For example, the bonding metal layer 140 may be disposed in direct contact with a pad portion provided on the submount or a pad portion provided on the lead frame.

For example, the bonding metal layer 140 may be connected to the pad portion by a die bonding method. In addition, the bonding metal layer 140 may be connected to the pad portion by a flip-chip bonding method.

The semiconductor device package according to the embodiment will now be described with reference to FIG. 6 is a diagram illustrating a semiconductor device package according to an embodiment of the present invention. In describing the semiconductor device package according to the embodiment with reference to FIG. 6, description overlapping with those described with reference to FIGS. 1 to 5 may be omitted.

The semiconductor device package 200 according to the embodiment may include a pad portion 210, as shown in FIG. The semiconductor device package 200 shown in FIG. 6 shows only a partial region around a pad portion 210 that supplies power to a semiconductor device.

For example, the pad portion 210 may be provided on the submount. Also, the pad portion 210 may be provided on the lead frame. Also, the pad unit 210 may be provided on a circuit board.

According to the method for fabricating a semiconductor device package according to the embodiment, the semiconductor element 100 described with reference to FIGS. 1 to 5 may be provided on the pad portion 210. At this time, the bonding metal layer 140 of the semiconductor device 100 may be provided to be in contact with the pad portion 210.

For example, the bonding metal layer 140 may be disposed in direct contact with the pad 210. According to another embodiment, a bonding material may be further provided between the pad portion 210 and the bonding metal layer 140 in addition to the bonding metal layer 140.

According to the method of manufacturing a semiconductor device package according to the embodiment, at least one of heat or pressure may be provided while the bonding metal layer 140 is disposed on the pad portion 210.

For example, heat can be supplied in a state where the bonding metal layer 140 and the pad portion 210 are in contact with each other. In addition, the bonding metal layer 140 and the pad 210 may be in contact with each other. In addition, heat and pressure may be supplied while the bonding metal layer 140 is in contact with the pad 210.

The bonding material included in the bonding metal layer 140 may be diffused into the porous metal layer 130 as heat or pressure is provided between the bonding metal layer 140 and the pad portion 210. [ have. An alloy layer 135 may be formed by bonding between a bonding material diffused from the bonding metal layer 140 and a material contained in the porous metal layer 130 in a plurality of pore regions provided in the porous metal layer 130 have. The alloy layer 135 may be formed between the bonding metal layer 140 and the porous metal layer 130.

Thus, according to the method of fabricating a semiconductor device package according to the embodiment, a kind of eutectic bonding can be performed between the semiconductor device 100 and the pad part 210. According to an embodiment, the bonding process can be performed at lower temperatures, lower pressures than commonly known eutectic bonding. A metal compound may be generated by chemical bonding at the interface between the porous metal layer 130 and the bonding material diffused from the bonding metal layer 140.

According to the embodiment, the metal compound generated at the interface between the porous metal layer 130 and the bonding material diffused from the bonding metal layer 140 may have a relatively high melting point. For example, the melting point of the alloy layer 135 formed by the bonding between the porous metal layer 130 and the bonding material diffused from the bonding metal layer 140 may be higher than the melting point of the bonding metal layer 140.

The semiconductor device package 200 according to the embodiment may include a pad portion 210 and a bonding metal layer 140 as shown in FIG. The bonding metal layer 140 may be disposed on the pad portion 210.

The semiconductor device package 200 according to the embodiment may further include an alloy layer 135, a porous metal layer 130, a metal layer 120, and a semiconductor layer 110.

The alloy layer 135 may be disposed on the bonding metal layer 130. The porous metal layer 130 may be disposed on the alloy layer 135. The porous metal layer 130 may include a plurality of pores.

The alloy layer 135 may be formed by a combination of a material included in the bonding metal layer 140 and a material included in the porous metal layer 130 as described above. For example, when the porous metal layer 130 includes Au and the bonding metal layer 140 includes Sn, the alloy layer 135 may include AuSn.

According to the embodiment, the melting point of the alloy layer 135 may be higher than the melting point of the bonding metal layer 140.

For example, the melting point of the bonding metal layer 140 may be between 220 and 250 degrees. In addition, the alloy layer 135 may have a higher melting point than 250 degrees. The melting point of the alloy layer 135 can be flexibly selected by adjusting the composition ratio of the material of the alloy layer 135.

The metal layer 120 may be disposed on the porous metal layer 130. The semiconductor layer 110 may be disposed on the metal layer 120.

Thus, according to the embodiment, power supplied through the pad 210 can be applied to the semiconductor layer 110.

The semiconductor device package 200 according to the embodiment may be additionally surface-mounted (SMT) to the main board supplying power according to the application product. At this time, as an example, the semiconductor device package 200 may be surface mounted (SMT) on the main board by soldering or the like.

Meanwhile, according to a conventional method of manufacturing a semiconductor device package, a method of bonding a semiconductor device to a pad portion through a soldering process has been applied. However, in the case where the bonding process is performed through the first soldering process in the process of manufacturing the semiconductor device package, in the reflow process for the second soldering process in which the surface mounting is further performed on the main substrate, The bonding material used in the process can be melted again. Accordingly, in the reflow process for the second soldering process, the stability of the electrical connection and the physical connection between the semiconductor device package and the pad portion can be weakened.

However, according to the method of manufacturing a semiconductor device package according to the embodiment, the melting point of the alloy layer 135, which provides a bonding force between the semiconductor element and the pad portion according to the embodiment, may be formed to be higher than the melting point of the general soldering material have. Therefore, even when the semiconductor device package 200 according to the embodiment is bonded to the main substrate through a reflow process, re-melting phenomenon does not occur and electrical connection and physical bonding force are not deteriorated There are advantages.

Meanwhile, according to the application example of the semiconductor device package 200 according to the embodiment, the pad portion 210 may be disposed on the resin, and the pad portion 210 may be disposed around the resin. Accordingly, when the pad unit 210 and the semiconductor device 100 are bonded at a high temperature, deformation of the resin may occur or discoloration may occur in the resin.

However, according to the semiconductor device package 200 according to the embodiment, as described above, the semiconductor device 100 can be bonded to the pad portion 210 in a low-temperature environment. Thus, according to the embodiment, the resin disposed around the pad portion can be prevented from being exposed to high temperature, so that the resin can be prevented from being damaged or discolored.

6, the bonding metal layer 140 is disposed on the pad portion 210, and the alloy layer 135 (not shown) is formed on the bonding metal layer 140. In the semiconductor device package 200 according to the embodiment, ) Were arranged on the basis of the following description.

According to another embodiment of the present invention, the thickness of the bonding metal layer 140 may be controlled so that the material forming the bonding metal layer 140 during the bonding of the semiconductor element 100 and the pad 210 may be porous The metal layer 130 may be formed of a metal. Accordingly, the alloy layer 135 may be disposed directly on the pad 210.

According to the method of manufacturing a semiconductor device package according to the embodiment, the bonding material contained in the bonding metal layer 140 can provide a bonding force with the pad portion 130. In addition, the bonding material contained in the bonding metal layer 140 may be diffused into a plurality of pores provided in the porous metal layer 130, so that eutectic bonding may be realized at the interface. Accordingly, according to the embodiment, a stable bonding force can be provided between the pad portion 210 and the alloy layer 135. [

7 is a view showing another example of a semiconductor device package according to an embodiment of the present invention. Referring to FIG. 7, in explaining the semiconductor device package according to the embodiment, descriptions overlapping with those described with reference to FIGS. 1 to 6 may be omitted.

7, the semiconductor device package 400 according to the embodiment includes a semiconductor device 100, a pad portion 210, a lead frame 220, a package body 230, a main substrate 300, . The semiconductor device 100 may be electrically connected to the pad 210 provided on the package body 230. The pad unit 210 may be electrically connected to the main substrate 300 disposed below. For example, the pad unit 210 may be electrically connected to the main board 300 through the lead frame 220 disposed at the bottom.

The semiconductor device 100 may be disposed on the pad portion 210 provided on the lead frame 220. The semiconductor device 100 may be disposed in a cavity provided by the package body 230. The molding part 240 may be disposed on the semiconductor device 100. For example, the molding unit 240 may include wavelength conversion particles that receive light provided from the semiconductor device 100 and emit wavelength-converted light.

7, the semiconductor device package 400 according to the embodiment includes a first bonding layer 115 disposed on the pad portion 210 and a second bonding portion 115 disposed below the lead frame 220. [ Layer < RTI ID = 0.0 > 310 < / RTI >

For example, the first bonding layer 115 may include the bonding metal layer 140, the alloy layer 135, and the porous metal layer 130 described with reference to FIG. In addition, the second bonding layer 310 may include a bonding material used in a soldering process.

According to the embodiment, as described with reference to FIGS. 1 to 6, the first bonding layer 115 may have a higher melting point than the second bonding layer 310. The first bonding layer 115 may be formed below the melting point of the second bonding layer 310.

According to the method of manufacturing a semiconductor device package 400 according to the embodiment, the bonding process between the semiconductor device 100 and the pad part 210 can be performed at a relatively low first temperature. Also, the bonding process between the semiconductor device 100 and the pad 210 may be performed while applying a relatively low first pressure.

The bonding process between the lead frame 220 and the main substrate 300 may be performed at a relatively high second temperature. In addition, the bonding process between the lead frame 220 and the main substrate 300 may be performed while applying a relatively high second pressure.

However, as described above, since the melting point of the first bonding layer 115 is higher than the second temperature, the reflow process for bonding between the lead frame 220 and the main substrate 300 the bonding force between the semiconductor element 100 and the pad portion 210 does not deteriorate during the reflow process.

Also, as described above, the bonding process between the semiconductor device 100 and the pad portion 210 can be performed at the relatively low first temperature. Therefore, according to the embodiment, it is possible to prevent the package body 230 from being damaged or discolored during the bonding process between the semiconductor device 100 and the pad unit 210.

According to the embodiment, since the bonding process between the semiconductor device 100 and the pad 210 can be performed at the relatively low temperature, the selection width of the material constituting the package body 230 is wide . According to the embodiment, the package body 230 may be provided using not only expensive materials such as ceramics but also relatively inexpensive resin materials.

Meanwhile, the semiconductor device 100 according to the embodiment may be connected to the pad unit 210 by a flip chip bonding method. The semiconductor device 100 may be top emission and side emission. Also, the semiconductor device 100 may emit light in a downward direction. As described above, the semiconductor device 100 according to the embodiment may be a flip-chip light emitting device that emits light in six directions.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments can be combined and modified by other persons having ordinary skill in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention.

100 semiconductor device
110 semiconductor layer
115 first bonding layer
120 metal layer
130 porous metal layer
135 alloy layer
140 bonding metal layer
200 semiconductor device package
210 pad portion
220 lead frame
230 package body
240 molding part
300 main board
310 second bonding layer
400 semiconductor device package

Claims (7)

A semiconductor layer;
A metal layer disposed on the semiconductor layer;
A porous metal layer disposed on the metal layer and including a plurality of pores;
A bonding metal layer disposed on the porous metal layer;
≪ / RTI > The method according to claim 1,
Wherein the porous metal layer comprises the same material as the metal layer. The method according to claim 1,
Wherein the metal layer includes at least one selected from the group consisting of Au, Ag, and Cu, and the bonding metal layer includes Sn. Pad portion;
A bonding metal layer disposed on the pad portion;
An alloy layer disposed on the bonding metal layer;
A porous metal layer disposed on the alloy layer and including a plurality of pores;
A metal layer disposed on the porous metal layer;
A semiconductor layer disposed on the metal layer;
/ RTI >
Wherein the alloy layer comprises an alloy formed by bonding a substance contained in the bonding metal layer and a substance contained in the porous metal layer. 5. The method of claim 4,
Wherein a melting point of the alloy layer is higher than a melting point of the bonding metal layer. Forming a metal layer on the semiconductor layer;
Forming an alloy layer in which a first metal and a second metal are bonded on the metal layer;
Removing the second metal through a chemical treatment on the alloy layer and forming a porous metal layer of a first metal including a plurality of pores;
Forming a bonding metal layer on the porous metal layer;
≪ / RTI > Providing a pad portion;
Providing the pad portion in contact with the bonding metal layer of the semiconductor device according to any one of claims 1 to 3;
Wherein the bonding metal layer is bonded to the bonding metal layer in the porous metal layer by providing at least one of heat or pressure to bond the bonding metal layer to the pad portion and diffusing the material contained in the bonding metal layer into a plurality of pores provided in the porous metal layer, Forming an alloy layer by bonding the material and the material contained in the porous metal layer;
≪ / RTI >

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