KR20170105173A - Liquid crystal display device having common voltage compensatiing circuit - Google Patents

Abstract

The present invention relates to a liquid crystal display device capable of preventing deterioration in image quality due to a reduction in the line width of a common voltage supply line, or reducing a bezel width. The liquid crystal display device of the present invention comprises a display panel, a data driving circuit, a gate driving circuit, and a common voltage compensation circuit. The display panel displays an input image, and includes a pixel array including a pixel electrode to which a data voltage is supplied and a common electrode to which a common voltage is supplied. The data driving circuit supplies the data voltage to data lines of the display panel. The gate driving circuit includes a level shifter and a shift register. The level shifter outputs shift clocks and a start pulse. The shift register receives a gate low voltage and a gate high voltage, shifts the start pulse in accordance with the shift clocks, and sequentially shifts the gate pulse to supply the gate pulse to the gate lines. The common voltage compensation circuit receives a gate sensing voltage for sensing the gate lines through a gate low voltage supply line to which the gate low voltage is supplied, extracts a ripple component included in the gate sensing voltage, and supplies a common voltage compensation voltage generated by inversion-amplifying the ripple component, to the common electrode.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device having a common voltage compensation circuit,

The present invention relates to a liquid crystal display device capable of compensating a common voltage supplied to a common electrode of a display panel.

A liquid crystal display includes a display panel in which liquid crystal molecules in an intermediate state between a liquid and a solid are positioned between two substrates. A liquid crystal display reproduces an image of an input image by changing the arrangement of liquid crystal molecules according to video data of the input image, thereby adjusting the amount of light passing through the display panel according to the gray value of the video data.

A liquid crystal display device of an active matrix driving type displays a moving picture by using a thin film transistor (Thin Film Transistor) as a switching element. The display panel of the liquid crystal display device includes pixels formed in pixel regions in the form of a matrix defined by data lines, gate lines (or scan lines) intersecting with the data lines, data lines and gate lines do.

The pixels of the liquid crystal display include a thin film transistor which is located adjacent to the intersection of the data line and the gate line. The thin film transistor supplies the data voltage supplied through the data line to the pixel electrode of the liquid crystal cell in response to the gate pulse from the gate line. The liquid crystal cell is rotated by an electric field generated according to the voltage difference between the voltage of the pixel electrode and the common voltage applied to the common electrode to control the amount of light passing through the polarizer. The storage capacitor is connected to the pixel electrode of the liquid crystal cell to maintain the voltage of the liquid crystal cell.

The common voltage applied to the common electrode is ripple due to electrical coupling with the pixel electrode. The ripple phenomenon of the common voltage is proportional to the variation of the data voltage with time. Therefore, in the inversion method in which the polarity of the data voltage is varied, the ripple phenomenon of the common voltage becomes severe at the moment when the polarity of the data voltage is changed, because the fluctuation range of the data voltage is large. As described above, the ripple phenomenon of the common voltage causes a line-dim phenomenon along the horizontal direction, thereby deteriorating the display quality.

Therefore, in order to prevent such a line-dim phenomenon, various common voltage compensating circuits have been developed which supply a compensating common voltage which can feed back the common voltage supplied to the common electrode and cancel the ripple voltage.

However, in order to apply a common voltage compensation circuit to a GIP (Gate In Panel) model in which a gate drive circuit is formed on a display panel, a common voltage supply line, a common voltage feedback line, a GIP circuit, and the like should be formed in a limited bezel area. Particularly, in order to sense the common voltage of the common electrode, the wiring width of the common voltage feedback line must be secured to some extent. In order to stably secure the wiring width of the common voltage feedback line in the same bezel region, The wiring width of the common voltage supply line has to be reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent a deterioration in image quality due to a decrease in the wiring width of a common voltage supply line by sensing a change in gate voltage supplied to gate lines of a display panel and compensating a common voltage supplied to the common electrode, And a liquid crystal display device.

According to an aspect of the present invention, there is provided a liquid crystal display device including a display panel, a data driving circuit, a gate driving circuit, and a common voltage compensation circuit. The display panel is provided with a pixel array in which an input image is displayed and includes a pixel electrode to which a data voltage is supplied and a common electrode to which a common voltage is supplied. The data driving circuit supplies a data voltage to the data lines of the display panel. The gate drive circuit includes a level shifter and a shift register. The level shifter outputs the shift clocks and the start pulse. The shift register receives a gate low voltage and a gate high voltage, and sequentially shifts the gate pulse by shifting the start pulse according to the shift clock to supply the gate line with the gate pulse. The common voltage compensation circuit receives a gate sensing voltage obtained by sensing the gate lines through a gate low voltage supply line to which the gate low voltage is supplied, extracts a ripple component included in the gate sensing voltage, And supplies the amplified common voltage compensation voltage to the common electrode.

In the above configuration, the shift register is composed of a plurality of stages each connected to the gate lines. Each stage includes a logic unit for controlling charging and discharging operations of a Q node and a QB node which are charged and discharged opposite to each other in response to the gate start signal, the gate high voltage and the gate low voltage, A first pull-up transistor for outputting a scan pulse at a turn-on level when charged, and a first pull-down transistor for outputting a scan pulse at a turn-off level when the QB node is charged to an activation level. The gate sensing voltage is supplied to the common voltage compensation circuit through the first pull-down transistor and the gate low voltage supply line.

Further, the first pull-up transistor includes a gate electrode connected to the Q node, a source electrode for receiving the clock signal, and a drain electrode connected to the first output node. The first pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the gate-low voltage supply wiring, and a drain electrode connected to the first output node. The scan pulse supplied through the first output node is supplied to the gate line connected to the stage of the current stage and the next stage.

The common voltage compensation circuit may further include an operational amplifier including an inverting input terminal to which the common voltage is supplied, an inverting input terminal, and an output terminal connected to the common voltage supply line, and an inverting input terminal connected to the gate- A capacitor and a first resistor connected in series between the lines, and a second resistor connected in parallel between the inverting input terminal and the output terminal.

The liquid crystal display according to the present invention may further include a third resistor disposed between an output terminal to which the gate-low voltage is supplied and a buffer of the common voltage compensation circuit.

The gate low voltage supply line includes a first gate low voltage supply line for supplying a first gate low voltage and a second gate low voltage supply line for supplying a second gate low voltage having a different level from the first gate low voltage. Line. ≪ / RTI > The shift register includes a plurality of stages each connected to the gate lines. Each stage includes a Q node that is charged and discharged inversely to each other in response to the gate start signal, the gate high voltage, the first and second gate low voltages, a logic unit that controls charge and discharge operations of the QB node, A first pull-up transistor and a second pull-up transistor for outputting a scan pulse at a turn-on level when the Q node is charged to an activation level; a first pull-up transistor and a second pull-up transistor for outputting a scan pulse at a turn- Down transistor and a second pull-down transistor. The gate sensing voltage is supplied to the common voltage compensation circuit through the first pull-down transistor and the first gate low voltage supply line.

Further, the first pull-up transistor includes a gate electrode connected to the Q node, a source electrode for receiving the clock signal, and a drain electrode connected to the first output node. The second pull-up transistor includes a gate electrode connected to the Q node, a source electrode for receiving the clock signal, and a drain electrode connected to the second output node. The first pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the first gate-low voltage supply line, and a drain electrode connected to the first output node. The second pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the second gate low voltage supply line, and a drain electrode connected to the second output node. The scan pulse supplied through the first output node is supplied to the gate line connected to the stage of the current stage, and the scan pulses supplied through the two output nodes are supplied to the next stage.

The common voltage compensation circuit may further include an operational amplifier including a non-inverting input terminal to which the common voltage is supplied, an inverting input terminal, and an output terminal connected to the common voltage supply line, an operational amplifier including the inverting input terminal and the first gate- A buffer and capacitor connected in series between the supply lines, a capacitor and a first resistor, and a second resistor connected in parallel between the inverting input terminal and the output terminal.

The liquid crystal display according to the present invention may further include a third resistor disposed between an output terminal to which the first gate low voltage is supplied and a buffer of the common voltage compensation circuit.

According to the touch sensor built-in display device according to the present invention, it is possible to supply the compensating common voltage for sensing the gate line change and removing the ripple component included in the feedback common voltage, so that it is possible to prevent the deterioration of the picture quality due to the parasitic capacitance The common voltage feedback line can be eliminated, so that the effect of reducing the bezel area can be obtained.

1 is a block diagram schematically showing a liquid crystal display according to an embodiment of the present invention;
2 schematically shows a partial area of a liquid crystal display according to an embodiment of the present invention,
3 is a plan view schematically showing wirings of a liquid crystal display device according to an embodiment of the present invention,
Fig. 4 is a circuit diagram showing an example of each stage of the shift register shown in Fig. 2,
Fig. 5 is a circuit diagram showing another example of each stage of the shift register shown in Fig. 2,
6 is a circuit diagram showing a common voltage compensating unit for compensating a common voltage by sensing a gate low voltage in a liquid crystal display according to an embodiment of the present invention.
FIG. 7 is a diagram for explaining the principle of removing the direct current component and amplifying and outputting the AC component of the common voltage compensator shown in FIG. 6;
8 is a waveform diagram showing a ripple voltage generated by sensing a gate line corresponding to a display pattern of a region where a gradation is changed in a liquid crystal display device according to an embodiment of the present invention,
FIG. 9 is a plan view schematically showing the effect that a liquid crystal display device according to an embodiment of the present invention can achieve with respect to a conventional liquid crystal display device having a feedback common voltage supply line. FIG.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

First, a liquid crystal display according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG.

1 is a block diagram schematically showing a liquid crystal display according to an embodiment of the present invention. FIG. 2 is a schematic view showing a partial area of a liquid crystal display according to an embodiment of the present invention, and FIG. 3 is a plan view schematically showing wirings of a liquid crystal display according to an embodiment of the present invention.

1, a liquid crystal display according to an embodiment of the present invention includes a display panel 10, a data driving circuit, a GIP (Gate In Panel) type gate driving circuit, a common voltage compensation circuit CVC, and a timing controller TC) and the like.

The display panel 10 includes an active area AA and a bezel area BA. The active area AA is an area where a pixel array is arranged in an area where an input image is displayed. The bezel area BA is a region in which a shift register and various signal lines and a common voltage supply line of a gate drive circuit are disposed.

The pixel array may include a thin film transistor (TFT) array formed on the first substrate, a color filter array formed on the second substrate, and liquid crystal cells Clc.

The TFT array includes data lines DL, gate lines (or scan lines) GL intersecting with the data lines DL, data lines GL formed at intersections of the data lines DL and gate lines GL, A thin film transistor TFT, a pixel electrode 1 connected to the thin film transistor TFT, a storage capacitor Cst, and the like. On the second substrate of the display panel 10, a color filter array including a black matrix and a color filter is formed. The common electrode 2 may be formed on the first substrate or the second substrate. The liquid crystal cells Clc are driven by the electric field between the pixel electrode 1 to which the data voltage is supplied and the common electrode 2 to which the common voltage Va is supplied.

The common voltage Va may be supplied from a separate power source (not shown) and supplied to the common electrode 2 through the common line CL. The common line CL includes a first common line CLa arranged in the bezel area BA and arranged in parallel with the data line, a second common line CLb branched from the first common line CLa, A plurality of second common lines CLb arranged in parallel with the data lines GL and arranged in parallel with the data lines DL extending in the vertical direction from the second common lines CLb, And a plurality of third common lines CLc connecting the plurality of second common lines CLb. In this case, the common line CL is configured as a matrix type in the active area AA by the second common lines CLb and the third common lines CLc.

In the embodiment of the present invention, the common line is composed of the first through third common lines. However, in the case of the small liquid crystal display device, the first common line may be directly connected to the common electrode, The common lines may be omitted, or both the second and third common lines may be omitted.

3, the common line CL includes a first common line arranged in the bezel area BA and arranged in parallel with the gate line, a first common line branched from the first common line, A plurality of second common lines arranged in parallel and a plurality of third common lines extending in the horizontal direction from the second common lines and arranged in parallel with the gate lines GL and connecting adjacent second common lines, . ≪ / RTI > In this case, the common line CL is configured as a matrix type in the active area AA by the second common lines and the third common lines. This modified embodiment may also connect the first common line directly to the common electrode in the case of a small liquid crystal display device, omit the second common lines or the third common lines, or omit both the second common line and the third common line .

In addition, the display panel 10 may be formed by a color filter on transistor (COT) method in which a color filter array is not formed on the second substrate but color filters are provided on the TFT array.

On the first substrate and the second substrate of the display panel 10, a polarizing plate orthogonal to the optical axis is attached, and an alignment film for setting the pretilt angle of the liquid crystal is formed at the interface with the liquid crystal layer. A spacer for maintaining a cell gap of the liquid crystal layer may be disposed between the first substrate and the second substrate of the display panel 10.

The data driver circuit includes a plurality of source driver ICs (SDa, SD) connected to the groups of data lines (DL), respectively. The source drive ICs SDa and SD receive digital video data RGB from the timing controller TC. The source drive ICs SDa and SD convert the digital video data RGB to a positive / negative analog data voltage in response to a source timing control signal from the timing controller TC, And supplies them to the data lines DL of the display panel 10 in synchronization with the pulses (or scan pulses). The source drive ICs SDa and SD may be connected to the data lines DL of the display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process. The source drive ICs SDa and SD shown in FIG. 1 are mounted on a TCP (Tape Carrier Package). Also, a printed circuit board (PCB) 20 is connected to the first substrate of the display panel 10 via TCP.

The GIP type gate driving circuit includes a level shifter LS mounted on the PCB 20 and a shift register SR formed on the first substrate of the display panel 10.

The level shifter LS receives signals such as a start pulse ST, gate shift clocks GLCK and flicker signal FLK from the timing controller TC and also outputs a gate high voltage VGH, (VGL) or the like. The start pulse ST, the gate shift clocks GCLK, and the flicker signal FLK are signals swinging between 0V and 3.3V. The gate shift clocks GLCK1-n are n-phase clock signals having a predetermined phase difference. The gate high voltage VGH is a voltage equal to or higher than the threshold voltage of the thin film transistor TFT formed in the thin film transistor array of the display panel 10 and is about 28 V. The gate low voltage VGL is applied to the thin film transistor Which is lower than the threshold voltage of the thin film transistor (TFT) formed in the transistor array, is approximately -5 V or so.

The level shifter LS shifts the start pulse ST input from the timing controller TC and the shift clock signal GCLK level-shifted to the gate high voltage VGH and the gate low voltage VGL, (CLK). Therefore, the start pulse VST and the shift clock signals CLK output from the level shifter LS swing between the gate high voltage VGH and the gate low voltage VGL, respectively. The level shifter LS can reduce the flicker by lowering the gate high voltage according to the flicker signal FLK to lower the kickback voltage Vp of the liquid crystal cell.

1, the output signals of the level shifter LS are connected to the wirings formed in the TCP of the first source driver IC (SDa) disposed at the upper left of the display panel 10, And may be supplied to the shift register SR through LOG (Line On Glass) lines LW formed on the first substrate. The shift register SR is formed directly on the first substrate of the display panel 10 by the GIP process.

The start pulse VST, the clock signals CLK1 to CLKn, the gate low voltage VGL and the gate high voltage VGH are input to the shift register SR as shown in FIG. The shift register SR includes a plurality of stages ST1 to STn to which the shift register SR is connected. The clock signals CLK1 to CLKn are n (n is a natural number of 2 or more) upper clock signals whose phases are sequentially delayed. The clock signals CLK1 to CLKn are supplied to the respective stages ST1 to STn through the clock signal supply lines SL1 to SLn.

The shift register SR shifts the start pulse VST input from the level shifter LS in accordance with the gate shift clock signals CLK1 to CLKn to generate a swing voltage VGH between the gate high voltage VGH and the gate low voltage VGL. Are sequentially shifted. The gate pulse output from the shift register SR is sequentially supplied to the gate lines GL.

Next, the shift register SR of the liquid crystal display according to the embodiment of the present invention will be described in more detail with reference to FIGS. 4 and 5. FIG.

Fig. 4 is a circuit diagram showing an example of each stage of the shift register shown in Fig. 2, and Fig. 5 is a circuit diagram showing another example of each stage of the shift register shown in Fig.

4, each of the stages ST1 to STn of the shift register SR is connected between the Q node and the QB node in response to the gate start signal VST, the gate high voltage VGH, and the gate low voltage VGL. A pull-up transistor (TU) for outputting a scan pulse at a turn-on level when the Q node is charged to an activation level; and a pull-up transistor And a pull-down transistor (TD) for outputting at a turn-off level.

The pull-up transistor TU includes a gate electrode connected to the Q node, a source electrode for receiving the clock signal GCLK, and a drain electrode connected to the output node N1.

The pull-down transistor TD includes a gate electrode connected to the QB node, a source electrode connected to the gate low voltage (VGL) supply wiring, and a drain electrode connected to the output node N1.

The Q node and the QB node are charged and discharged opposite to each other. That is, when the Q node is charged to the activation level, the QB node is discharged to the deactivation level, and conversely, when the Q node is discharged to the deactivation level, the QB node is charged to the activation level.

When the Q node is activated, the pull-down transistor TD is turned off, and the pull-up transistor TU outputs one of the gate shift clock signals GCLK1 to GCLKn as a scan pulse of the turn-on level. This scan pulse becomes the gate voltage Gout output to the corresponding gate line and is used as the carry signal Cout supplied to the next stage.

On the other hand, when the QB node is activated, the pull-up transistor TU is turned off and the pull-down transistor TD is turned on, so that the gate voltage of the gate line is sensed and supplied to the gate low voltage supply line VGL. Generally, since the gate lines GL have intersections with the data lines DL, the gate sensing voltage obtained by sensing the gate line GL when the QB node is activated is applied to the gate line GL, and the data line DL.

The gate sensing voltages of the gate lines GL including the noise components are supplied to the common voltage compensation circuit CVC (see FIGS. 2 and 4).

5, each of the stages ST1 to STn of the shift register SR is connected to the gate start signal VST, the gate high voltage VGH and the first and second gate low voltages VGL1 and VGL2 (LO) for controlling the charging and discharging operations of the Q node and the QB node in response to the first and second pull-up transistors (TUa, TUb) for outputting the scan pulse at the turn- And first and second pull-down transistors TDa and TDb for outputting a scan pulse at a turn-off level when the QB node is charged to an activation level.

The first pull-up transistor TUa includes a gate electrode connected to the Q node, a source electrode for receiving the clock signal GCLK, and a drain electrode connected to the first output node N1. The second pull-up transistor TUb includes a gate electrode connected to the Q node, a source electrode for receiving the clock signal GCLK, and a drain electrode connected to the second output node N2.

The first pull-down transistor TD includes a gate electrode connected to the QB node, a source electrode connected to the first gate low voltage (VGL1) supply line, and a drain electrode connected to the first output node N1. The second pull-down transistor TDb includes a gate electrode connected to the QB node, a source electrode connected to the second gate-low voltage (VGL2) supply line, and a drain electrode connected to the second output node N2. The levels of the first gate low voltage VGL1 and the second gate low voltage VGL2 may be different from each other and the first gate low voltage VGL1 may be set higher than the second gate low voltage VGL2.

The first node N1 to which the first pull-up transistor TUa and the first pull-down transistor TDa are connected functions as a gate voltage output terminal for supplying a gate voltage to the gate line, and the second pull-up transistor TUb and the second pull- The second node N2 to which the transistor TDb is connected functions as a carry stage for supplying a carry signal to the next stage. Therefore, the signals output to the first and second output terminals N1 and N2 are the same.

The stages ST1 to STn of the shift register SR of FIG. 5 are obtained by dividing the gate voltage output stage and the carry signal output stage into two stages ST1 to STn of the shift register SR shown in FIG. Its function and operation are the same. Therefore, further explanation is omitted in order to avoid redundant description.

In the embodiment of FIG. 5, the gate sensing voltage of each gate line including the noise component is supplied to the common voltage compensation circuit.

8 is a waveform diagram showing a ripple voltage generated by sensing a gate line corresponding to a display pattern of a region where a gradation is changed in a liquid crystal display according to an embodiment of the present invention. And a ripple component obtained by sensing a gate line corresponding to the gate line.

From the stages ST1 to STn of the shift register SR according to the embodiment of FIGS. 4 and 5, the gate sensing voltage of each gate line including the noise component is supplied through the gate low voltage (VGL, VGL1) supply line And is supplied to the common voltage compensation circuit (CVC).

Next, the common voltage compensation circuit (CVC) of the liquid crystal display according to the embodiment of the present invention will be described with reference to FIG.

The common voltage compensation circuit CVC has an input connected to a supply line of gate low voltages VGL and VGL1 to which a gate low voltage VGL is supplied and an output connected to a common line CL.

 The common voltage compensation circuit CVC includes an operational amplifier 12 including a non-inverting input terminal (+) to which the common voltage Va is supplied, an inverting input terminal (-), and an output terminal connected to the common voltage supply line CL A capacitor C and a first resistor R1, an inverting input terminal (-) and an output (-) connected in series between an inverting input terminal OP and an inverting input terminal (-) and a gate low voltage And a second resistor R2 connected in parallel between the terminals.

The buffer BUF of the common voltage compensation circuit CVC buffers the gate sensing voltage supplied from each stage of the shift register. As shown in Fig. 7, the capacitor C has a common voltage Va input to the non-inverting input terminal +. A buffer BUF is formed so that the DC level difference B of the gate sensing voltages VGL and VGL1 obtained by sensing the gate line is not amplified and the ripple component (AC component) A of the gate sensing voltage can be extracted. .

The first resistor R1 and the second resistor R2 and the operational amplifier OP amplify the common voltage compensation voltage Vb obtained by inverting and amplifying the ripple component of the gate sensing voltage at a ratio of R2 / R1 to the common line CL Output.

As described above, the common voltage compensation circuit of the liquid crystal display according to the embodiment of the present invention is provided with a common voltage compensation circuit (not shown) (Noise component) included in the gate sensing voltage, amplifies the noise component by inverting the amplified noise component, and supplies the amplified voltage of the opposite phase to the common electrode to generate a common voltage ripple .

Therefore, a feedback common line for sensing the common voltage is not required to compensate for the ripple component, which is the noise component included in the common voltage.

FIG. 9 is a plan view schematically showing an effect of a liquid crystal display device according to an embodiment of the present invention, with respect to a conventional liquid crystal display device having a feedback common voltage supply line.

9A is an example of a case where a feedback common line FB for sensing a common line CLa is formed in a bezel region of a conventional liquid crystal display device.

FIG. 9B is a diagram showing a common line for supplying a common voltage (for example, a first common line (CLa in FIG. 3) shown in an embodiment of the present invention) in the liquid crystal display according to the embodiment of the present invention, A common line having a wider width can be formed in the same bezel region as shown in Fig. 9 (b), so that the electrical resistance can be reduced So that the display quality can be improved.

FIG. 9C is a cross-sectional view of a liquid crystal display according to an embodiment of the present invention, showing a common line CL for supplying a common voltage (for example, a first common line shown in an embodiment of the present invention 9A and 9B. In the case of forming a common line as shown in FIG. 9C, the feedback common line FB formed in FIG. 9A can be removed So that the effect of reducing the bezel area can be obtained.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 20: PCB
CVC: Common voltage compensation circuit LS: Level shifter
SDa, SD: Source drive IC SR: Shift register
ST1 to STn: stage TC: timing controller

Claims (9)

A display panel having a pixel array in which an input image is displayed, the pixel array including a pixel electrode to which a data voltage is supplied and a common electrode to which a common voltage is supplied;
A data driving circuit for supplying a data voltage to the data lines of the display panel;
Shift clocks, a level shifter for outputting a start pulse, a gate low voltage and a gate high voltage are input, and the gate pulses are sequentially shifted by shifting the start pulse according to the shift clock to supply the gate pulses to the gate lines A gate drive circuit including a shift register; And
A gate sensing voltage obtained by sensing the gate lines through a gate low voltage supply line to which the gate low voltage is supplied, a ripple component included in the gate sensing voltage, and a common voltage compensation And a common voltage compensation circuit for supplying a voltage to the common electrode. The method according to claim 1,
Wherein the shift register includes a plurality of stages each connected to the gate lines,
In each stage,
A logic part for controlling charging and discharging operations of the Q node and the QB node which are charged and discharged opposite to each other in response to the gate start signal, the gate high voltage and the gate low voltage;
A first pull-up transistor for outputting a scan pulse at a turn-on level when the Q node is charged to an activation level; And
And a first pull-down transistor for outputting a scan pulse at a turn-off level when the QB node is charged to an activation level,
Wherein the gate sensing voltage is supplied to the common voltage compensation circuit through the first pull-down transistor and the gate low voltage supply line. 3. The method of claim 2,
Wherein the first pull-up transistor includes a gate electrode connected to the Q node, a source electrode for receiving the clock signal, and a drain electrode connected to the first output node,
Wherein the first pull-down transistor comprises a gate electrode connected to the QB node, a source electrode connected to the gate-low voltage supply wiring, and a drain electrode connected to the first output node,
Wherein the scan pulse supplied through the first output node is supplied to a gate line connected to a stage of a current stage and to a next stage. 4. The method according to any one of claims 1 to 3,
Wherein the common voltage compensation circuit comprises:
An operational amplifier including a non-inverting input terminal to which the common voltage is supplied, an inverting input terminal, and an output terminal connected to the common voltage supply line;
A buffer, a capacitor and a first resistor serially connected between the inverting input terminal and the gate-low voltage supply line;
And a second resistor connected in parallel between the inverting input terminal and the output terminal. 5. The method of claim 4,
And a third resistor is disposed between an output terminal to which the gate-low voltage is supplied and a buffer of the common voltage compensation circuit. The method according to claim 1,
Wherein the gate-low voltage supply line includes a first gate-low voltage supply line for supplying a first gate-low voltage and a second gate-low voltage supply line for supplying a second gate-low voltage having a different level from the first gate- / RTI >
Wherein the shift register includes a plurality of stages each connected to the gate lines,
In each stage,
A logic part for controlling charging and discharging operations of the Q node and the QB node which are charged and discharged opposite to each other in response to the gate start signal, the gate high voltage, the first and second gate low voltages;
A first pull-up transistor and a second pull-up transistor for outputting a scan pulse at a turn-on level when the Q node is charged to an activation level; And
A first pull-down transistor and a second pull-down transistor for outputting a scan pulse at a turn-off level when the QB node is charged to an activation level,
And the gate sensing voltage is supplied to the common voltage compensation circuit through the first pull-down transistor and the first gate low voltage supply line. The method according to claim 6,
Wherein the first pull-up transistor includes a gate electrode connected to the Q node, a source electrode for receiving the clock signal, and a drain electrode connected to the first output node,
The second pull-up transistor including a gate electrode connected to the Q node, a source electrode for receiving the clock signal, and a drain electrode connected to the second output node,
The first pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the first gate low voltage supply line, and a drain electrode connected to the first output node,
The second pull-down transistor includes a gate electrode connected to the QB node, a source electrode connected to the second gate low voltage supply line, and a drain electrode connected to the second output node,
Wherein a scan pulse supplied through the first output node is supplied to a gate line connected to a stage of a current stage and a scan pulse supplied through the two output nodes is supplied to a next stage. The method according to any one of claims 1, 6, and 7,
Wherein the common voltage compensation circuit comprises:
An operational amplifier including a non-inverting input terminal to which the common voltage is supplied, an inverting input terminal, and an output terminal connected to the common voltage supply line;
A buffer, a capacitor and a first resistor connected in series between the inverting input terminal and the first gate-low voltage supply line;
And a second resistor connected in parallel between the inverting input terminal and the output terminal. 9. The method of claim 8,
And a third resistor is disposed between an output terminal to which the first gate low voltage is supplied and a buffer of the common voltage compensation circuit.

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