KR100824420B1 - Liquid crystal dispaly apparatus of line on glass type - Google Patents

Abstract

The present invention relates to a line on glass type liquid crystal display device capable of improving image quality by reducing horizontal lines.

A line-on-glass type liquid crystal display device according to an embodiment of the present invention includes an image display part including a plurality of liquid crystal cells formed at each intersection of gate lines and data lines; A plurality of gate tape carrier packages each having a plurality of gate drive integrated circuits driving the gate lines; A plurality of data tape carrier packages each having a plurality of data drive integrated circuits driving data lines thereon; Line-on-glass signal lines formed in an outer region of an image display unit in a line-on-glass manner and supplying driving signals required by the gate drive integrated circuits; And a power supply unit supplying a switching gate low voltage for compensating a difference between the gate low voltage signals output to the respective gate lines through the line on glass type signal lines and the gate drive integrated circuits.

According to this configuration, as the same gate low voltage is supplied to each horizontal line block connected to each gate drive IC in the dot and two-dot inversion driving method, the horizontal line phenomenon due to the luminance difference between the horizontal line blocks can be prevented. .

Description

Line on glass type liquid crystal display device {LIQUID CRYSTAL DISPALY APPARATUS OF LINE ON GLASS TYPE}             

1 is a plan view schematically showing the configuration of a conventional line on glass type liquid crystal display device.

FIG. 2 shows details of the image display area shown in FIG. 1; FIG.

3A and 3B are diagrams illustrating data signal polarities supplied to liquid crystal cells of a liquid crystal panel divided into odd and even frames by a 2-dot inversion liquid crystal panel driving method.

4 is a diagram illustrating a data voltage in the even frame shown in FIG. 3B.

5 is a view showing a gate low voltage input and output to the gate drive IC of the liquid crystal display according to the prior art.

6 is a view for explaining the difference between the gate low voltage waveform according to the prior art.

FIG. 7 is a diagram illustrating separation between horizontal line blocks according to a gate low voltage difference illustrated in FIG. 6.

8 is a diagram schematically showing a configuration of a LOG type liquid crystal display device according to an embodiment of the present invention.

9 is a view showing in detail the power supply shown in FIG.

10 is a view showing a gate low voltage input and output from a gate drive integrated circuit of a liquid crystal display according to an exemplary embodiment of the present invention.

11 illustrates gate low voltage waveform differences according to an embodiment of the present invention.

12 illustrates a gate low voltage input to a gate drive integrated circuit of a liquid crystal display according to another exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

1,34 liquid crystal panel 2,36 lower substrate

4,38: Upper board 8,40: Data TCP

10,42: Data Drive IC 12,44: Data PCB

14,46: Gate TCP 16,48: Gate Drive IC

18: data line 20: gate line

21, 41: image display area 22: gate drive signal transmission group

24: input pad 25, 30: output pad

26: LOG type signal line group 28: gate driving signal transmission line group

32: horizontal line 54: power supply

60: power supply voltage signal (VCC) generation unit

62: data drive IC bias voltage generator                 

64: gate high voltage signal generation unit

66: switching gate low voltage signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a line on glass type liquid crystal display device capable of improving image quality by reducing a horizontal line phenomenon.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line.

The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying various driving voltages used in the liquid crystal display device. It has a supply part. The timing controller controls the driving timing of the gate driver and the data driver and supplies the pixel data signal to the data driver. The power supply unit generates driving voltages such as a common voltage VCOM, a gate high voltage VGH, and a gate low voltage VGL required for driving the liquid crystal display using the input power. The gate driver sequentially supplies the scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Among them, a data driver and a gate driver directly connected to the liquid crystal panel are integrated into a plurality of integrated circuits (ICs). Each of the integrated data drive IC and the gate drive IC is mounted on a tape carrier package (TCP) and connected to a liquid crystal panel by a tape automated bonding (TAB) method or mounted on a liquid crystal panel by a chip on glass (COG) method.

Here, the drive ICs connected to the liquid crystal panel in a TAB manner through TCP are interconnected with the control signals and DC voltages input from the outside through signal lines mounted on a printed circuit board (PCB) connected to the TCP. . In detail, the data drive ICs are connected in series through signal lines mounted on the data PCB, and are commonly supplied with control signals from the timing controller, pixel data signals, and driving voltages from the power supply unit. The gate drive ICs are connected in series through signal lines mounted on the gate PCB, and are commonly supplied with control signals from the timing controller and driving voltages from the power supply.

The drive ICs mounted on the liquid crystal panel in the COG method are interconnected in a line on glass (hereinafter referred to as "LOG") method in which signal lines are mounted on the liquid crystal panel, that is, the lower glass, as well as a timing controller and a power supply unit. Control signals and driving voltages are supplied.

Recently, even when the drive ICs are connected to the liquid crystal panel by the TAB method, the liquid crystal display device can be further thinned by adopting the LOG method and removing the PCB. In particular, the gate PCB is removed by forming a relatively small number of signal lines connected to the gate drive ICs on the liquid crystal panel in a LOG method. In other words, the TAB type gate drive ICs are connected in series through signal lines mounted on the lower glass of the liquid crystal panel, and are commonly supplied with control signals and driving voltage signals (hereinafter referred to as gate driving signals). do.

In practice, the liquid crystal display device in which the gate PCB is removed by using the LOG type signal wires has a plurality of data TCPs connected between the liquid crystal panel 1 and the liquid crystal panel 1 and the data PCB 12 as shown in FIG. 8, a plurality of gate TCPs 14 connected to the other side of the liquid crystal panel 1, data drive ICs 10 mounted on each of the data TCPs 8, and gate TCPs ( 14) and gate drive ICs 16 mounted on each.

The liquid crystal panel 1 is injected between the lower substrate 2 on which the thin film transistor array is formed, the upper substrate 4 on which the color filter array is formed, and the lower substrate 2 and the upper substrate 4 together with various signal lines. It consists of the liquid crystal material. The liquid crystal panel 1 is provided with an image display area 21 composed of liquid crystal cells provided at each intersection of the gate lines 20 and the data lines 18 to display an image. Data pads extended from the data line 18 and gate pads extended from the gate line 20 are positioned in the outer region of the lower substrate 2 positioned at the outer portion of the image display area 21. In addition, in the outer region of the lower substrate 2, a LOG type signal line group 26 for transmitting gate driving signals supplied to the gate drive IC 16 is positioned.

A data drive IC 10 is mounted on the data TCP 8, and input pads 24 and output pads 25 electrically connected to the data drive IC 10 are formed. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12, and the output pads 25 are electrically connected to the data pads on the lower substrate 2. In particular, the first data TCP 8 is further formed with a gate drive signal transmission group 22 electrically connected to the LOG type signal line group 26 on the lower substrate 2. The gate driving signal transmission group 22 supplies the gate driving signals supplied from the timing controller and the power supply unit to the LOG type signal line group 26 via the data PCB 12.

The data drive ICs 10 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 18 on the liquid crystal panel.

A gate drive IC 16 is mounted on the gate TCP 14, and a gate drive signal transmission line group 28 and output pads 30 electrically connected to the gate drive IC 16 are formed. The gate driving signal transmission line group 28 is electrically connected to the LOG signal line group 26 on the lower substrate 2, and the output pads 30 are electrically connected to the gate pads on the lower substrate 2. .

The gate drive ICs 16 sequentially supply the scanning signal, that is, the gate high voltage signal VGH, to the gate lines 20 in response to the input control signals. In addition, the gate drive ICs 16 supply the gate low voltage signal VGL to the gate lines in a period other than the period in which the gate high voltage signal VGH is supplied.

The LOG signal line group 26 typically includes a power supply unit such as a gate high voltage signal VGH, a gate low voltage signal VGL, a common voltage signal VCOM, a ground voltage signal GND, and a power supply voltage signal VCC. Signal lines for supplying each of the DC voltage signals supplied from the gate control signal supplied from the timing controller, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate output enable signal GOE. It is composed.

The LOG signal line group 26 is formed side by side in a fine pattern in a very limited narrow space such as a pad portion located in the outer region of the image display portion 21. The LOG signal line group 26 is formed of a gate metal layer similarly to the gate lines 20. As the gate metal, a metal having a relatively large resistivity value (0.046), such as AlNd, is usually used.                         

FIG. 2 is a diagram illustrating in detail the image display area shown in FIG. 1.

Referring to FIG. 2, the image display area is formed at the intersections of the liquid crystal cells Clc arranged in a matrix, and the n gate lines GL1 to GLn and the m data lines DL1 to DLm, respectively. A thin film transistor (TFT) is provided. The thin film transistor TFT supplies a data signal from the data lines DL1 to DLm to the liquid crystal cell in response to the gate high voltage VGH from the gate lines GL1 to GLn. The liquid crystal cell may be equivalently represented by a liquid crystal capacitor Clc including a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor TFT. Further, a storage capacitor Cst is further formed in the liquid crystal cell to hold the data signal charged in the liquid crystal capacitor Clc until the next data signal is charged, that is, while the gate low voltage VGL is applied. . The storage capacitor Cst is formed between the previous gate line and the pixel electrode. In addition, a cross capacitor Ccross is further formed between the gate lines GL1 to GLn and the data lines DL1 to DLm in the liquid crystal cell. The liquid crystal cell realizes gray scale by controlling light transmittance by varying an arrangement state of liquid crystal having dielectric anisotropy according to a data signal charged through a thin film transistor (TFT).

Such liquid crystal display devices are generally driven by a frame frequency of 60 Hz. However, in systems requiring low power consumption such as notebook computers, it is required to lower the frame frequency to 50 to 30 Hz. As the frame frequency is lowered, the flicker phenomenon occurs in the dot inversion method that provides excellent image quality among the inversion methods, so that the liquid crystal cell on the liquid crystal panel 2 in the liquid crystal display according to the related art in order to improve the flicker phenomenon In order to drive them, a two-dot inversion type liquid crystal panel driving method as shown in FIGS. 3A and 3B has been proposed.

3A and 3B illustrate data signal polarities supplied to liquid crystal cells of a liquid crystal panel divided into odd frames and even frames by a 2-dot inversion liquid crystal panel driving method. In the odd and even frames shown in FIGS. 3A and 3B, the two-dot inversion scheme changes the polarity of the data signal in the horizontal direction in the vertical direction while changing the liquid crystal cell, that is, in the unit of dots, like the dot inversion scheme. It can be seen that is driven to change in units of 2 dots. While the two-dot inversion method has the advantage that the flicker phenomenon is reduced compared to the dot inversion method in a commercial screen driven at a frame frequency of 50 Hz, the horizontal line is generated every two scanning lines depending on the luminance difference between the scanning lines. Have.

Referring to FIG. 3B, the polarities of the first and second data lines in the k−1 th gate line GLk−1 are “+ ″ →“ − ”and the first and second data in the k th gate line GLk. The polarity of the line is represented by "-" → "+". At this time, their data values are represented as 0 Gray / 8V and 63 Gray / 3V in the k-1th gate line GLk-1, respectively, and 0 Gray / 0.3V respectively in the kth gate line GLk. , 63Gray / 5V.

When the polarity is converted from the k-1 th gate line GLk-1 to the k th gate line GLk, the change of the data voltage signal according to these influences the cross capacitor Ccross in FIG. That is, the gate low voltage VGL of the k-1 th gate line GLk-1, which is turned off due to the change in the polarity of the data voltage signal during the gate line conversion, is affected.

5 is a view showing a gate low voltage input and output to the gate drive IC of the liquid crystal display according to the prior art.

Referring to FIG. 5, in a liquid crystal display according to the related art, a gate low voltage VGL input from an external source is converted at a power supply and input to a gate drive IC, as shown in FIG. 5A. It has a constant DC voltage.

However, in the liquid crystal display according to the related art, as described with reference to FIG. 4, the gate low voltage VGL of the gate line Glk-1, which is turned off due to the cross capacitor Ccross due to the line polarity change, is affected. An output terminal of the gate low voltage VGL is shown in FIG. 5 (b). Referring to FIG. 5B, the output waveform of the gate low voltage VGL is switched in a distorted form every 2H (horizontal synchronization time) according to the driving method of the liquid crystal display according to the related art.

The distortion of the gate low voltage waveform is amplified by the line resistances a, b and c of the gate low voltage transmission line between the gate drive ICs 16A to 16D as shown in FIG. For example, the gate low voltage supplied to the 256th gate line GL256 of the first gate drive IC 16A and the first gate line GL1 of the second gate drive IC 16B is changed. The same applies to the dot inversion driving method.

Thus, a difference occurs between the gate low voltages VGL256 and VGL1 supplied to the last gate line GL256 of the gate drive ICs 16A to 16C and the first gate line GL1 of the next gate drive ICs 16B to 16D. As a result, as shown in FIG. 7, the luminance difference is generated between the horizontal line blocks A to D connected to the different gate drive ICs 16A to 16D. The luminance difference between the horizontal line blocks A to D is caused by the horizontal line 32 phenomenon, and the screen is divided so that the image quality is reduced.

Accordingly, it is an object of the present invention to provide a LOG type liquid crystal display device which can prevent a horizontal line phenomenon due to a luminance difference between horizontal line blocks by reducing a resistance deviation due to a gate low voltage due to a polarity inversion of a gate line.

In order to achieve the above object, a LOG type liquid crystal display device according to the present invention includes an image display unit including a plurality of liquid crystal cells formed at each intersection of gate lines and data lines; A plurality of gate tape carrier packages each having a plurality of gate drive integrated circuits driving the gate lines; A plurality of data tape carrier packages each having a plurality of data drive integrated circuits driving the data lines; Line-on-glass signal lines formed in an outer region of the image display unit to supply driving signals required by the gate drive integrated circuits; And a power supply unit configured to supply a switching gate low voltage for compensating a difference between the gate low voltage signals output to the gate lines through the line on glass signal lines and the gate drive integrated circuits.

The power supply unit of the present invention is characterized in that it comprises a switching gate low voltage signal generator for turning off the thin film transistors of the liquid crystal cells and switching the switching gate low voltage every horizontal period.

In the present invention, the power supply unit turns on a power supply voltage signal generation unit for generating a power supply voltage signal, a data drive integrated circuit bias voltage generation unit for driving the data drive integrated circuits, and the thin film transistors of the liquid crystal cells. It characterized in that it further comprises a gate high voltage signal generator for.

The horizontal period in the present invention is characterized in that two horizontal periods.

The horizontal period period in the present invention is characterized in that one horizontal period period.

The switching gate low voltage in the present invention is characterized in that the phase shifted.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 8 to 12.                     

8 is a diagram schematically showing the configuration of a LOG type liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 8, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 34, a plurality of data TCPs 40 connected between the liquid crystal panel 34 and the data PCB 44, and a liquid crystal display. A plurality of gate TCPs 46A to 46D connected to the other side of the panel 34, data drive ICs 42 mounted on each of the data TCPs 40, and gate TCPs 46A to 46D, respectively. A power supply unit 54 for supplying driving power to the gate driver ICs 48A to 48D and the gate driver ICs 48A to 48D and the data drive ICs 42 through the data PCB 44. Equipped.

The liquid crystal panel 34 is injected between the lower substrate 36 on which the thin film transistor array is formed, the upper substrate 38 on which the color filter array is formed, and the lower substrate 36 and the upper substrate 38 together with various signal lines. Composed of liquid crystal materials. The liquid crystal panel 34 is provided with an image display area 41 composed of liquid crystal cells provided for each intersection area of the gate lines and the data lines to display an image. Data pads extended from a data line and gate pads extended from a gate line are positioned in an outer area of the lower substrate 36 positioned at an outer portion of the image display area 41. In addition, in the outer region of the lower substrate 36, a group of LOG signal lines for transmitting gate driving signals supplied to the gate drive ICs 48A to 48D is positioned.

A data drive IC 42 is mounted on the data TCP 40, and the data TCP 40 outputs the output pads and the lower substrate of the data PCB 44 through input / output pads connected to the data drive IC 42. 36) data pads. In particular, the first data TCP 40 further includes a gate drive signal transmission group connected to the LOG type signal line group on the lower substrate 36. The gate drive signal transmission group supplies the gate drive signals supplied from the timing controller and the power supply unit 54 to the LOG type signal line group via the data PCB 44.

The data drive ICs 42 convert a pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines on the liquid crystal panel.

Gate TCPs 46A to 46D are mounted with gate drive ICs 48A to 48D, and the gate TCPs 46A to 46D are connected to the lower substrate 36 through output pads connected to the gate drive ICs 48A to 48D. It is connected to the gate pads. The gate TCPs 46A to 46D further include a gate drive signal transmission line group connected between the LOG type signal line group of the lower substrate 36 and the gate drive ICs 48A to 48D.

The gate drive ICs 48A to 48D sequentially supply the scanning signal, that is, the gate high voltage signal VGH, to the gate lines in response to the input control signals. In addition, the gate drive ICs 48A to 48D supply the gate low voltage signal VGL to the gate lines in a period other than the period in which the gate high voltage signal VGH is supplied.

The LOG signal line group typically includes a power supply unit 54 such as a gate high voltage signal VGH, a gate low voltage signal VGL, a common voltage signal VCOM, a ground voltage signal GND, and a power supply voltage signal VCC. Signal lines for supplying each of the DC voltage signals supplied from the gate control signal supplied from the timing controller, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate output enable signal GOE. It is composed. The LOG signal line group is formed of the gate metal layer in the same manner as the gate lines.

The power supply unit 54 generates a driving voltage for driving the gate drive ICs 48A to 48D, the data drive IC 42, and the like using power input from the external power supply unit. As shown in FIG. 9, the power supply unit 54 includes a power supply voltage signal VCC generator 60, a data drive IC bias voltage generator 62, and a gate high voltage signal VGH for turning on the TFT. The switching gate low voltage for turning off the generation unit 64 and the TFT and switching the gate low voltage VGL every 2 horizontal periods 2H according to the 2-dot inversion driving method as described in FIG. 3. A signal generator 66 is provided.

FIG. 10 is a diagram illustrating a gate low voltage input and output from a gate drive IC of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 10, the liquid crystal display according to the exemplary embodiment of the present invention is driven according to the two-dot inversion frame illustrated in FIG. 3B. At this time, the change of the data voltage signal values during the conversion from the k-1 th gate line GLk-1 to the k th gate line GLk of the frame affects the cross capacitor Ccross. The influence of the cross capacitor Ccross affects the gate-low voltage VGL of the k-th gate line GLk-1 which is turned off. As a result, the gate low voltage VGL waveform applied to the gate line GL due to the influence of the gate low voltage VGL is distorted as shown in FIG.                     

Accordingly, in the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 6 of the related art, the gate drive ICs 48A to 48D are used to reduce the variation in the gate low voltage waveform of each gate drive IC. Supply the switched gate low voltage (VGL) as in. The gate low voltage VGL to be switched is generated by the switching gate low voltage signal generator 66 in the power supply 54 to the gate driving signal transmission group and the gate TCPs 46A to 46D formed on the data PCB 44. The gate drive ICs 48A to 48D are supplied via the formed gate drive signal transmission line group.

At this time, the gate low voltage VGL is switched in a direction opposite to the swing direction of the distorted gate low voltage waveform. That is, when the waveform of the gate low voltage VGL of the turned-off gate line is swinged to "-" → "+" → "-" → "+" based on -5V, the power supply unit 54 The gate low voltage VGL supplied to the gate drive ICs 48A to 48D is supplied to switch from " + " → "-" " "

Thus, by supplying the switching gate low voltage (VGL) to each gate drive IC (48A to 48D) through the power supply 54, the last gate line (GL256) and the next gate drive IC (48B) of the gate drive IC (48A to 48C) The gate low voltage VGL waveform is substantially the same as the first gate line GL1 of the second through the fourth gate lines.

Accordingly, the switching gate low voltage VGL is input to each of the gate drive ICs 48A to 48D so that the same gate low voltage VGL is supplied to the gate line as shown in FIG. 11 so that the luminance difference between the horizontal line blocks does not occur. do. In addition, in the line-on-glass type liquid crystal display according to the present invention, when the frame has the same frame as in FIG. 3A, the gate low voltage VGL is shifted in phase by two horizontal period periods 2H.

Through such a configuration, the LOG type liquid crystal display according to the dot inversion driving method inputs the gate low voltage VGL which is switched every one horizontal period 1H from the power supply 54 as shown in FIG. As in FIG. 11, the same gate low voltage VGL is supplied to the last gate line GL256 of the gate drive ICs 48A to 48C and the first gate line GL1 of the next gate drive ICs 48B to 48D. The luminance difference between the horizontal line blocks does not occur.

As described above, in the LOG type liquid crystal display according to the present invention, the resistance deviation of the gate low voltage according to the polarity conversion in the dot and two dot inversion driving methods is switched to the gate low voltage at each horizontal period period according to the corresponding driving method. By driving, the same gate low voltage can be supplied to the gate lines. As the same gate low voltage is supplied to each horizontal line block connected to each gate drive IC, the horizontal line phenomenon due to the luminance difference between the horizontal line blocks does not occur.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

An image display unit including a plurality of liquid crystal cells formed at intersections of gate lines and data lines; A plurality of gate tape carrier packages each having a plurality of gate drive integrated circuits driving the gate lines; A plurality of data tape carrier packages each having a plurality of data drive integrated circuits driving the data lines; Line-on-glass signal lines formed in an outer region of the image display unit to supply driving signals required by the gate drive integrated circuits; And a power supply unit configured to supply a switching gate low voltage for compensating a difference between the gate low voltage signals output to the gate lines through the line on glass signal lines and the gate drive integrated circuits. On glass type liquid crystal display device. The method of claim 1, The power supply unit And a switching gate low voltage signal generator for turning off the thin film transistors of the liquid crystal cells and switching the switching gate low voltage at every horizontal period. The method of claim 2, The power supply unit A power supply voltage signal generator for generating a power supply voltage signal; A data drive integrated circuit bias voltage generator driving the data drive integrated circuits; And a gate high voltage signal generator for turning on the thin film transistors of the liquid crystal cells. The method of claim 2, And the horizontal period is two horizontal periods. The method of claim 2, And the horizontal period is one horizontal period. The method according to any one of claims 4 and 5, And the switching gate low voltage is shifted in phase.

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