KR20050000644A - Driving apparatus and method of liquid crystal display device - Google Patents

Abstract

PURPOSE: A driver apparatus of a liquid crystal display device and its method are provided to improve vertical line and horizontal line generation due to panel resistance. CONSTITUTION: A liquid crystal panel(31) displays an image. A number of data driver integrated circuits supply a video signal to the liquid crystal panel. A timing controller(139) generates a polarity control signal to control the polarity of the video signal, and then supplies it to the data driver integrated circuits. The polarity control signal is inverted with an adjacent data driver integrated circuit in a unit of 1 horizontal line of the liquid crystal panel.

Description

DRIVING APPARATUS AND METHOD OF LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device and a driving method of a liquid crystal display device, and more particularly, to a driving device and a driving method of a liquid crystal display device so as to improve horizontal and vertical lines due to panel resistance.

Conventional liquid crystal displays (hereinafter referred to as "LCDs") display an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line.

The driving circuit supplies a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and various driving voltages used in the liquid crystal display device. It has a power supply. The timing controller controls the driving timing of the gate driver and the data driver and supplies the pixel data signal to the data driver. The power supply unit generates driving voltages such as the common voltage VCOM, the gate high voltage VGH, and the gate low voltage VGL required by the liquid crystal display using the input power. The gate driver sequentially supplies scanning signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a pixel voltage signal to each of the data lines whenever a scanning signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the pixel voltage signal for each liquid crystal cell.

Among them, a data driver and a gate driver directly connected to the liquid crystal panel are integrated into a plurality of integrated circuits (ICs). Each of the integrated data driver IC and the gate driver IC may be mounted on a tape carrier package (TCP) and connected to a liquid crystal panel using a tape automated bonding (TAB) method or mounted on a liquid crystal panel using a chip on glass (COG) method.

Here, the driver ICs connected to the liquid crystal panel in a TAB manner through TCP are interconnected with control signals and DC voltages input from the outside through signal lines mounted on a printed circuit board (PCB) connected to TCP. . In detail, the data driver ICs are connected in series through signal lines mounted on the data PCB and are commonly supplied with control signals from the timing controller, pixel data signals, and driving voltages from the power supply. The gate driver ICs are connected in series through signal lines mounted on the gate PCB, and are commonly supplied with control signals from the timing controller and driving voltages from the power supply.

The driver ICs mounted on the liquid crystal panel in the COG method are connected to each other in a line on glass (hereinafter referred to as "LOG") method in which signal lines are mounted on the liquid crystal panel, that is, the lower glass, and a timing controller and a power supply unit. Control signals and driving voltages are supplied.

Recently, even when the driver ICs are connected to the liquid crystal panel by the TAB method, the liquid crystal display device can be further thinned by adopting the LOG method and removing the PCB. In particular, the gate PCB is eliminated by forming the signal lines connected to the gate driver ICs requiring relatively few signal lines on the liquid crystal panel in a LOG method. In other words, the TAB type gate driver ICs are connected in series through signal lines mounted on the lower glass of the liquid crystal panel, and receive control signals and driving voltage signals (hereinafter, referred to as gate driving signals) in common. do.

In practice, a liquid crystal display device in which a gate PCB is removed using LOG type signal wires is connected to the liquid crystal panel 1 and the liquid crystal panel 1 and the data PCB 12 as shown in FIGS. 1 and 2. Data TCPs 8, a plurality of gate TCPs 14 connected to the other side of the liquid crystal panel 1, data driver ICs 10 mounted on each of the data TCPs 8, and a gate Each of the TCPs 14 has gate driver ICs 16 mounted thereon.

The liquid crystal panel 1 is injected between the lower substrate 2 on which the thin film transistor array is formed, the upper substrate 4 on which the color filter array is formed, and the lower substrate 2 and the upper substrate 4 together with various signal lines. Containing liquid crystals. The liquid crystal panel 1 is provided with an image display area 21 composed of liquid crystal cells provided at each intersection of the gate lines 20 and the data lines 18 to display an image. Data pads extended from the data line 18 and gate pads extended from the gate line 20 are positioned in the outer region of the lower substrate 2 positioned at the outer portion of the image display area 21. Also, in the outer region of the lower substrate 2, a LOG type signal line group 26 for transmitting gate driving signals supplied to the gate driver IC 16 is located.

A data driver IC 10 is mounted on the data TCP 8, and input pads 24 and output pads 25 electrically connected to the data driver IC 10 are formed. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12, and the output pads 25 are electrically connected to the data pads on the lower substrate 2. In particular, the first data TCP 8 is additionally formed with a gate drive signal transmission group 22 electrically connected to the LOG signal line group 26 on the lower substrate 2. The gate drive signal transfer group 22 supplies the gate drive signals supplied from the timing controller 9 and the power supply to the LOG signal line group 26 via the data PCB 12.

The data driver ICs 10 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 18 on the liquid crystal panel.

A gate driver IC 16 is mounted on the gate TCP 14, and a gate drive signal transmission line group 28 and output pads 30 electrically connected to the gate driver IC 16 are formed. The gate driving signal transmission line group 28 is electrically connected to the LOG signal line group 26 on the lower substrate 2, and the output pads 30 are electrically connected to the gate pads on the lower substrate 2. .

The gate driver ICs 16 sequentially supply the scanning signal, that is, the gate high voltage VGH, to the gate lines 20 in response to the input control signals. In addition, the gate driver ICs 16 supply the gate low voltage VGL to the gate lines in a period other than the period in which the gate high voltage VGH is supplied.

The LOG signal line group 26 typically includes a DC voltage supplied from a power supply such as a gate high voltage VGH, a gate low voltage VGH, a common voltage VCOM, a ground voltage GND, and a power supply voltage VCC. Signal lines and signal lines supplying gate control signals supplied from a timing controller, such as a gate start pulse GSP, a gate shift clock signal GSC, and a gate enable signal GOE, respectively.

In the LCD, three driving methods such as a frame inversion method, a line inversion method, and a dot inversion method are used to drive the liquid crystal cells LC on the liquid crystal panel. Mainly used. The liquid crystal panel driving method of the frame inversion method inverts the polarity of the data signal supplied to the liquid crystal cells whenever the frame is changed. In the line inversion type liquid crystal panel driving method, polarities of data signals supplied to liquid crystal cells are reversed according to a line on the liquid crystal panel, that is, a gate line. In addition, the dot inversion scheme allows the data signals of opposite polarities to be supplied to adjacent liquid crystal cells and inverts the polarities of the data signals supplied to the liquid crystal cells for each frame.

Among the three liquid crystal panel driving methods, the dot inversion method is configured to supply a liquid crystal cell by supplying a data signal having a polarity opposite to the data signals supplied to adjacent liquid crystal cells in the vertical and horizontal directions. Compared with the line inversion schemes, it provides an image of superior image quality. The dot inversion method is divided into a one-dot inversion method and a two-dot inversion method.

In the one-dot inversion scheme, the data output enable signal SOE input from the timing controller 9 to the data driver ICs 10 has a frequency twice that of the polarity pulse POL. The data driver ICs 10 receiving the polarity pulse POL and the data output enable signal SOE synchronize the video signal to the data line DL in synchronization with the falling edge (or rising edge) of the data output enable signal. Supply. At this time, the video signal supplied from the data driver ICs 10 to the data line DL alternates between positive and negative polarities according to the polarity pulse POL supplied from the timing controller 9. Will appear. In addition, the gate driver ICs 16 are supplied with a gate output enable signal having the same frequency as the data output enable signal, and the gate driver ICs 16 drive the gate using the gate output enable signal supplied thereto. The pulse is generated, and the generated gate driving pulse is sequentially supplied to the gate line GL.

As shown in FIG. 3, the 1-dot inversion driving method includes a liquid crystal cell LC positioned adjacent to each other with a gate line GL interposed therebetween and a data line DL positioned adjacent to each other. The opposite polarity data signals are supplied to all of the liquid crystal cells LC to display an image.

In the 1-dot inversion driving method of the conventional liquid crystal display device, since the gate low voltage VGL supplied between the gate driver ICs 16 shown in FIG. Because of the difference in luminance, the horizontal line 32 appears to cause the screen to be divided, resulting in deterioration of image quality.

In detail, in the conventional liquid crystal display, the LOG type gate low voltage transmission line VGLL for supplying the gate low voltage VGL may include the first data TCP 8 and the first to fourth data lines as shown in FIG. 2. And first to fourth LOG type gate low voltage transmission lines VGLL1 to VGLL4 connected between the gate TCPs 14A to 14D, respectively. The first to fourth LOG type gate low voltage transmission lines VGLL1 to VGLL4 have line resistance values a, b, c, and d proportional to their line lengths, and have first to fourth gate TCPs 14A to 14D. Connected in series via).

That is, the gate driver IC 16 mounted on the first gate TCP 14A includes the first gate low voltage (A) influenced by the first line resistance value a of the first LOG gate low voltage transmission line VGLL1. VGL1) is supplied. The first gate low voltage VGL1 is supplied to the gate lines of the first horizontal line block A through the first gate driver IC 16.

The second line resistance of the first LOG type gate low voltage transfer line VGLL1 and the second LOG type gate low voltage transfer line VGLL2 connected in series to the gate driver IC 16 mounted on the second gate TCP 14B. The second gate low voltage VGL2 affected by the value a + b is supplied. The second gate low voltage VGL2 is supplied to the gate lines of the second horizontal line block B through the second gate driver IC 16.

The third line resistance value of the first LOG type gate low voltage transmission line to the third LOG type gate low voltage transmission line VGLL1 to VGLL3 connected in series to the gate driver IC 16 mounted on the third gate TCP 14C. The third gate low voltage VGL3 affected by (a + b + c) is supplied. The third gate low voltage VGL3 is supplied to the gate lines of the third horizontal line block C through the third gate driver IC 16.

The fourth line resistance value (a + b + c +) of the first to fourth LOG type gate low voltage transmission lines VGLL1 to VGLL4 connected in series to the gate driver IC 16 mounted on the fourth gate TCP 14D. The fourth gate low voltage VGL4 affected by d) is supplied. The fourth gate low voltage VGL4 is supplied to the gate lines of the fourth horizontal line block D through the fourth gate driver IC 16.

As such, the first to fourth gate low voltages VGL1 to VGL4 supplied to the respective gate driver ICs 16 through the first to fourth LOG type gate low voltage transfer lines VGLL1 to VGLL4 may be gate lines GL. ) Is swinged toward the positive or negative polarity under the influence of the parasitic capacitor Cp.

The swing of the first to fourth gate low voltages VGL1 to VGL4 is described below in connection with the one-dot inversion scheme illustrated in FIGS. 4 and 5.

When the gate high voltage VGH is supplied to the n-1 th gate line GLn-1, a zero gray positive voltage close to black from the data driver ICs 10 is supplied to the n-1 th data line DLn-1. For example, a gamma voltage of 8V is supplied, and a 63-gray negative voltage close to white, for example, a gamma voltage of 3V, is supplied from the data driver ICs 10 to the nth data line DLn.

Subsequently, as the gate low voltage VGL is supplied to the n-1 th gate line GLn-1 and the gate high voltage VGH is supplied to the n th gate lines GLn, the n-1 th data line ( The DLn-1 is supplied with a zero gray negative voltage, for example, a gamma voltage of 0.3 V, from the data driver ICs 10, and the n-th data line DLn from the data driver ICs 10. A 63-degree positive polarity voltage close to white, for example a gamma voltage of 5V, is supplied.

As described above, when the gate high voltage VGH is supplied to the n-th gate lines GLn, a negative gray gamma voltage of 63 gray close to white supplied to the n-th data line DLn-1 is shown in FIG. 6. Supplied to the previous gate line GLn-1 due to the difference between the voltage charged in the parasitic capacitor Cp between the illustrated n-1 th data line DLn-1 and the previous gate line GLn-1 The gate low voltage VGL swings from the positive polarity to the negative polarity.

Accordingly, since the gate low voltage VGL is supplied to all the gate lines except for the gate lines to which the gate high voltage VGH is supplied, the swing voltage of the first gate low voltage VGL1 is changed to the first gate driver IC 14A. Is supplied to the second LOG type gate low voltage transmission line VGLL2. Accordingly, the swing voltage of the first gate low voltage VGL1 affects the second gate low voltage VGL2 through the second LOG gate low voltage transmission line VGLL2. That is, the line resistance value b of the second LOG type gate low voltage transmission line VGLL2 and the swing voltage of the first gate low voltage VGL1 are added to the second gate low voltage VGL2. Similarly, the line resistance value c of the third LOG type gate low voltage transmission line VGLL3 and the swing voltage of the second gate low voltage VGL2 are added to the third gate low voltage VGL3. In addition, the fourth gate low voltage VGL4 is added with the line resistance value d of the fourth LOG type gate low voltage transmission line VGLL4 and the swing voltage of the third gate low voltage VGL3.

Accordingly, the swing voltages of the first to fourth gate low voltages VGL2, VGL3, and VGL4 supplied to the first to second horizontal line blocks A, B, C, and D, and the first to fourth gate driver ICs ( The gate low voltage VGL supplied to each gate driver IC 16 is changed in proportion to the line resistance between 14A and 14D.

As a difference occurs in the gate low voltages VGL1 to VGL4 supplied to the gate lines for each gate driver IC 16, the luminance difference between the horizontal line blocks A to D connected to different gate driver ICs 16 is different. Will occur. The luminance difference between the horizontal line blocks A to D is caused by the horizontal line 32 phenomenon, and the screen is divided so that the image quality is reduced.

Meanwhile, in the liquid crystal display device driven by the 2-dot inversion method, as in the 1-dot inversion method described above, the n-1th gate is applied to the gate low voltage VGL supplied to the gate lines in the n-th gate driver IC. Since the swing voltage of the gate low voltage supplied to the gate lines in the driver IC and the panel resistance value between the gate driver IC are added, horizontal lines are generated on the liquid crystal panel. In other words, in the conventional liquid crystal display, the gate low voltage VGL as shown in FIG. 7A is distorted as shown in FIG. 7B due to the panel resistance between the gate driver ICs. Therefore, a block dim, that is, a horizontal line phenomenon, occurs between the gate driver ICs.

Accordingly, an object of the present invention is to provide a driving device and a driving method of a liquid crystal display device to improve the horizontal and vertical lines caused by panel resistance.

1 is a plan view schematically showing the configuration of a conventional liquid crystal display device.

FIG. 2 is a view for explaining separation between horizontal line blocks due to line resistance of the panel shown in FIG. 1; FIG.

3 is a diagram illustrating polar patterns of data signals supplied to liquid crystal cells of the liquid crystal panel of FIG. 2.

4 is a diagram illustrating a data voltage supplied to four adjacent liquid crystal cells in a polar pattern of data signals shown in FIG. 3.

FIG. 5 is a diagram illustrating a change in data voltage supplied to four adjacent liquid crystal cells shown in FIG. 3.

6 is a circuit diagram showing a parasitic capacitor Cp between data lines and gate lines.

7A is a waveform diagram showing a normal gate low voltage VGL.

Fig. 7B is a waveform diagram showing the swing of the gate low voltage VGL caused by the panel resistance.

8 is a view showing a driving device of a liquid crystal display according to a first embodiment of the present invention.

FIG. 9 is a block diagram illustrating different polarity control signals supplied to a plurality of data driver integrated circuits from the timing controller shown in FIG. 8. FIG.

FIG. 10 is a view showing video signal polarity displayed on a liquid crystal panel by the timing controller shown in FIG. 9; FIG.

11 is a waveform diagram showing that the swing of the gate low voltage VGL is canceled by the polarity control signal and the inverted polarity control signal.

12 is a view illustrating a vertical line phenomenon appearing on a liquid crystal panel according to a driving apparatus and a driving method of a liquid crystal display according to a first embodiment of the present invention.

13 is a view showing a driving device of a liquid crystal display according to a second embodiment of the present invention.

FIG. 14 is a diagram illustrating the video signal polarity displayed on the liquid crystal panel according to the polarity control signal and the inverted polarity control signal supplied from the timing controller shown in FIG. 13 to the data driver integrated circuit;

FIG. 15 is a view showing video signal polarity displayed on a liquid crystal panel according to a polarity control signal and an inverted polarity control signal supplied from a timing controller shown in FIG. 13 to a data driver integrated circuit;

<Description of Symbols for Main Parts of Drawings>

1,31 Liquid crystal panel 2,52 Lower substrate

4,34: Upper board 8,38: Data TCP

9, 39, 139: timing controller 12, 44: data PCB

14,44A, 44B, 44C, 44D: Gate TCP 16, 36: Gate Drive IC

18, 48: data line 20, 50: gate line

21, 51: image display section 22: gate drive signal transmission group

32: horizontal line 112: left region of liquid crystal panel

114: right region of the liquid crystal panel 150: random number generator

10, 40, 102A to 102D, 140a to 140h: data drive IC

In order to achieve the above object, a driving apparatus of a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel for displaying an image, a plurality of data driver integrated circuits for supplying a video signal to the liquid crystal panel, and the video. And a timing controller configured to generate a polarity control signal for controlling the polarity of the signal and to supply the polarity control signal to the plurality of data driver integrated circuits, wherein the polarity control signal is integrated into the plurality of data drivers in units of one horizontal line of the liquid crystal panel. And inverts the adjacent data driver integrated circuit among the circuits.

In the driving device, the polarity of the video signal may be inverted in the vertical line unit of the liquid crystal panel and in the horizontal line unit.

The polarity of the video signal in the driving device may be inverted in units of two vertical lines of the liquid crystal panel and in units of one horizontal line.

The driving device is characterized in that the rate at which the polarity control signal is supplied to the plurality of data driver integrated circuits is the same as the rate at which the inverted polarity control signal is supplied.

In the driving device, the inverted polarity control signal is supplied to at least two data driver integrated circuits in the one horizontal period.

The data driver integrated circuit to which the inverted polarity control signal is supplied by the driving device is different in units of one horizontal line of the liquid crystal panel.

In the driving device, the polarity control signal is repeated in a period of at least N horizontal line units within one frame.

In the driving device, the timing controller includes a random number generator for randomly inverting the polarity control signal.

In the driving device, the timing controller inverts and supplies the polarity control signal to at least one of the data driver integrated circuits by using the random number from the random number generator.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, the method including: providing a liquid crystal panel for displaying an image and a plurality of data driver integrated circuits for supplying a video signal to the liquid crystal panel; and controlling the polarity of the video signal. Generating a polarity control signal, generating an inverted polarity control signal inverted from the polarity control signal, and supplying the polarity control signal to the plurality of data driver integrated circuits, And supplying the inverted polarity control signal to the adjacent data driver integrated circuit among the driver integrated circuits.

In the driving method, the polarity of the video signal is inverted in the vertical line unit of the liquid crystal panel and in the horizontal line unit.

In the driving method, the polarity of the video signal may be inverted in units of two vertical lines of the liquid crystal panel and in units of one horizontal line.

In the driving method, the ratio of supplying the polarity control signal to the plurality of data driver integrated circuits is the same as the ratio of supplying the inverted polarity control signal.

In the driving method, the inverted polarity control signal is supplied to at least two data driver integrated circuits in the one horizontal period.

The data driver integrated circuit to which the inverted polarity control signal is supplied may differ in units of one horizontal line of the liquid crystal panel in the driving method.

In the driving method, the polarity control signal is repeated in a period of at least N horizontal line units within one frame.

The driving method may further include generating a random number for randomly inverting the polarity control signal using a random number generator.

In the driving method, the inverted polarity control signal is supplied to at least one of the data driver integrated circuits according to the random number.

Other objects and features of the present invention in addition to the above objects will be apparent from the description of the embodiments with reference to the accompanying drawings.

An embodiment of the present invention will be described with reference to FIGS. 8 to 15.

Referring to FIG. 8, the driving apparatus of the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal panel 31 and a plurality of data TCPs connected between the liquid crystal panel 31 and the data PCB 42. 38, a plurality of gate TCPs 44 connected to one side of the liquid crystal panel 31, data driver ICs 40 mounted on each of the data TCPs 38, and gate TCPs 44, respectively. The gate driver ICs 36 and the gate driver ICs 36 which supply polarity pulses POL to one half of the data driver ICs 40 and the inverted polarity pulses BPOL to the other half of the data driver ICs 40 are mounted on the gate driver ICs 36. ) Is provided with a timing controller 39 for supplying a gate driving signal.

The liquid crystal panel 31 is injected between the lower substrate 52 on which the TFT array is formed, the upper substrate 34 on which the color filter array is formed, and the lower substrate 52 and the upper substrate 34 together with various signal lines. A liquid crystal is comprised. The liquid crystal panel 31 is provided with an image display area 51 composed of liquid crystal cells provided at each intersection of the gate lines 50 and the data lines 48 to display an image. Data pads extended from the data line 48 and gate pads extended from the gate line 50 are positioned in the outer region of the lower substrate 52 positioned in the outer portion of the image display area 51. In addition, a gate signal line 56 for transmitting gate driving signals supplied to the gate driver IC 46 is positioned in an outer region of the lower substrate 52.

A data driver IC 40 is mounted on the data TCP 38, and input pads and output pads electrically connected to the data driver IC 40 are formed. The input pads of the data TCP 38 are electrically connected to the output pads of the data PCB 42, and the output pads are electrically connected to the data pads on the lower substrate 52. In particular, the first data TCP 38 further includes a gate driving signal line 56 electrically connected to the gate control signal line VGLL1 on the lower substrate 52. The gate driving signal line 56 supplies gate driving signals supplied from the timing controller 39 and the power supply unit to the gate control signal line VGLL1 via the data PCB 42.

The timing controller 39 has two output terminals for supplying the polarity pulse POL and the inverted polarity pulse BPOL to the data driver ICs 40. The polarity pulse POL from the timing controller 39 is supplied to the first through N / 2th data driver ICs 40 of the data driver ICs 40, and the inverted polarity pulse BPOL is The (N / 2) + 1st to Nth data driver ICs 40 of the data driver ICs 40 are supplied.

The data driver ICs 40 convert the pixel data signal, which is a digital signal, into a pixel voltage signal, which is an analog signal, and supply the same to the data lines 48 on the liquid crystal panel 31. At this time, the polarity of the pixel voltage signal is inverted according to the polarity pulse POL or the inverted polarity pulse BPOL supplied from the timing controller 39.

A gate driver IC 36 is mounted on the gate TCP 44, and input pads and output pads electrically connected to the gate driver IC 46 are formed. The input pads are electrically connected to the gate control signal line VGLL1 on the lower substrate 52, and the output pads are electrically connected to the gate pads on the lower substrate 52.

The gate driver ICs 36 sequentially supply the scanning signal, that is, the gate high voltage VGH, to the gate lines 50 in response to the input control signals. In addition, the gate driver ICs 46 supply the gate low voltage VGL to the gate lines in a period other than the period in which the gate high voltage VGH is supplied.

The gate control signal line VGLL1 is a DC voltage signal supplied from a power supply such as a gate high voltage VGH, a gate low voltage VGL, a common voltage VCOM, a ground voltage GND, and a power supply voltage VCC. And a signal line for supplying each of the gate control signals supplied from the timing controller 39, such as a gate start pulse GSP, a gate shift clock signal GSC, and a gate enable signal GOE. The gate control signal line VGLL1 is formed simultaneously with the gate lines 50 on the lower substrate 52.

In the LCD, three driving methods such as a frame inversion method, a line inversion method, and a dot inversion method are used to drive the liquid crystal cells LC on the liquid crystal panel. Mainly used. The liquid crystal panel driving method of the frame inversion method inverts the polarity of the data signal supplied to the liquid crystal cells whenever the frame is changed. In the line inversion type liquid crystal panel driving method, polarities of data signals supplied to liquid crystal cells are reversed according to a line on the liquid crystal panel, that is, a gate line. In addition, the dot inversion scheme allows the data signals of opposite polarities to be supplied to adjacent liquid crystal cells and inverts the polarities of the data signals supplied to the liquid crystal cells for each frame.

Among the three liquid crystal panel driving methods, the dot inversion method is configured to supply a liquid crystal cell by supplying a data signal having a polarity opposite to that of the data signals supplied to adjacent liquid crystal cells in the vertical and horizontal directions. Compared with the line inversion schemes, it provides an image of superior image quality. Due to these advantages, in recent years, a dot inversion type liquid crystal panel driving method is mainly used. The dot inversion method is divided into a 1 dot inversion method and a 2 dot inversion method.

Referring to FIG. 9, the driving method of the one-dot inversion type liquid crystal display device will be described. The image display area 51 is divided into left and right areas 82 and 84 so that the left area of the image display area 51 The polarity pulse POL is supplied from the timing controller 39 to each of the first to n / 2th data driver ICs 40 which supply a video signal to the data lines corresponding to the plurality of data lines 82. The video signal in the left region 82 of the signal starts from the positive polarity (+). At the same time, a timing controller 39 is provided to each of the (n / 2) +1 th to n th data driver ICs 40 which supply a video signal to the data lines corresponding to the right side area 84 of the image display area 51. By supplying the inverted polarity pulse BPOL, the video signal of the right region 84 of the image display region 51 starts from the negative polarity (-).

Accordingly, as illustrated in FIG. 10, in the left region 82 of the image display region 51 to which the polarity pulses POL are supplied, the video signals having the positive (+) and the negative (−) appear alternately. In the right region 84 of the image display region 51 to which the inverted polar pulses BPOL are supplied, video signals of negative polarity (-) and positive polarity (+) appear alternately.

Therefore, when one gate line is examined, the gate low voltage VGL in the left region 82 of the image display region 51 swings from the positive polarity (+) to the negative polarity (−). The gate low voltage VGL in the right region 84 of the image display region 51 swings from the negative polarity (-) to the positive polarity (+). Accordingly, as shown in FIG. 11, the gate low voltage VGL supplied to the gate line has a swing between the left region 82 of the image display region 51 and the right region 84 of the image display region 51. The opposites cancel each other out. In other words, the gate low voltage VGL is not affected by the polarity change of the video signal. Therefore, no horizontal line is generated on the image display area 51.

However, when the liquid crystal panel 31 is driven by dividing the image display area 51 into two and supplying polarized pulses POL and BPOL inverted to the divided areas, the divided areas 112, A vertical line phenomenon occurs at the boundary C of 114. That is, since the polarity pulses POL and BPOL supplied to the boundary C of the divided regions 112 and 114 are the same, a vertical line phenomenon occurs.

When the liquid crystal panel 31 is driven by supplying the polarity pulses POL and BPOL which are mutually inverted to the divided area by dividing the image display area 51 into two, the boundary C of the divided areas 112 and 114 is provided. As shown in FIG. 13, the driving device of the liquid crystal display according to the second exemplary embodiment of the present invention may include other components except for the timing controller 139. It has the same components as the driving device of the liquid crystal display according to the first embodiment of the present invention. Therefore, in the driving apparatus of the liquid crystal display according to the second exemplary embodiment of the present invention, descriptions of other components except for the timing controller 139 will be described with reference to FIG. 8. This will be replaced with the description of the driving device.

In the driving apparatus of the liquid crystal display according to the second exemplary embodiment of the present invention, the timing controller 139 drives the polarity of the video signal on the liquid crystal panel in a 1 dot inversion or 2 dot inversion manner as shown in FIG. 14. Let's go. At this time, the timing controller 139 supplies the respective polarity pulses POL and the inverted polarity pulses BPOL for each of the plurality of data driver ICs 140a through 140h, and each of the plurality of data driver ICs 140a through 140h. Inverting the polarity pulse output from the same ratio to one horizontal line of the liquid crystal panel is supplied to visually minimize the vertical line phenomenon.

In detail, the timing controller 139 inverts the polarity pulses POL and BPOL between two adjacent data driver ICs 140a to 140h among the plurality of data driver ICs 140a to 140h in units of one horizontal period. . That is, the timing controller 139 supplies the polarity pulse POL to the third data driver IC 140c and the inverted polarity pulse to the fourth data driver IC 140d during one horizontal period as shown in FIG. 14. The BPOL is supplied, the polarity pulse POL is supplied to the sixth data driver IC 140f, and the inverted polarity pulse BPOL is supplied to the seventh data driver IC 140g. Subsequently, the polarity pulse POL is supplied to the first data driver IC 140a and the inverted polarity pulse BLPOL is supplied to the second data driver IC 140b during the second horizontal period, and the fifth data driver IC is supplied. The polarity pulse POL is supplied to 140e, and the inverted polarity pulse BPOL is supplied to the sixth data driver IC 140f. Similarly, the timing controller 139 inverts the polarity pulses POL and BPOL supplied to two adjacent data driver ICs 140a to 140h in the third to Nth horizontal periods. Accordingly, the polarity of the video signal on the liquid crystal panel is driven in a 1 dot inversion or a 2 dot inversion manner and is supplied to adjacent data driver ICs 140a through 140h among the plurality of data driver ICs 140a through 140h. The polarity pulses POL and BPOL are inverted. Therefore, the vertical line phenomenon occurring on the liquid crystal panel is visually minimized. In other words, since the polarity pulse POL and the inverted polarity pulse BPOL are supplied at the same ratio in units of horizontal lines on the liquid crystal panel, the swing of the gate low voltage VGL is canceled as shown in FIG. Since the vertical line phenomenon generated at the boundary of the data driver ICs 140a to 140h supplying the inverted polarity pulses is generated at different positions for each horizontal line, the vertical line phenomenon is not visually felt.

Meanwhile, the timing controller 139 rotates the polarity pulses POL and BPOL supplied to the plurality of data driver ICs 140a to 140h by one horizontal period, field or frame unit. In addition, as illustrated in FIG. 15, the timing controller 139 uses the random number generator 150 to generate polarity pulses between the data driver ICs 140a to 140h among the plurality of data driver ICs 140a to 140h in units of one horizontal period. (POL, BPOL) can be supplied randomly.

As described above, the driving device and the driving method of the liquid crystal display according to the exemplary embodiment of the present invention provide a polarity pulse supplied to two adjacent data driver ICs among a plurality of data driver ICs in one horizontal line unit, field or Frames and randomly invert each other. Accordingly, the present invention can visually minimize the vertical line phenomenon generated on the liquid crystal panel.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (18)

A liquid crystal panel displaying an image, A plurality of data driver integrated circuits for supplying a video signal to the liquid crystal panel; A timing controller for generating a polarity control signal for controlling the polarity of the video signal and supplying the polarity control signal to the plurality of data driver integrated circuits; And wherein the polarity control signal is inverted with the adjacent data driver integrated circuit among the plurality of data driver integrated circuits in units of one horizontal line of the liquid crystal panel. The method of claim 1, The polarity of the video signal is inverted in units of vertical lines of the liquid crystal panel and inverted in units of horizontal lines. The method of claim 1, The polarity of the video signal is inverted in units of two vertical lines of the liquid crystal panel and inverted in units of one horizontal line. The method of claim 1, A driving apparatus of a liquid crystal display device, characterized in that the ratio of supplying the polarity control signal to the plurality of data driver integrated circuits is the same as the ratio of supplying the inverted polarity control signal. The method of claim 1, And said inverted polarity control signal is supplied to at least two data driver integrated circuits in said one horizontal period. The method of claim 5, wherein And the data driver integrated circuit to which the inverted polarity control signal is supplied differs in units of one horizontal line of the liquid crystal panel. The method of claim 6, And wherein the polarity control signal is repeated in at least N horizontal line units within one frame. The method of claim 1, And the timing controller comprises a random number generator for randomly inverting the polarity control signal. The method of claim 8, And the timing controller inverts and supplies the polarity control signal to at least one of the data driver integrated circuits by using the random number from the random number generator. Providing a liquid crystal panel displaying an image and a plurality of data driver integrated circuits for supplying a video signal to the liquid crystal panel; Generating a polarity control signal for controlling the polarity of the video signal; Generating an inverted polarity control signal inverted with the polarity control signal; Supplying the polarity control signal to the plurality of data driver integrated circuits and supplying the inverted polarity control signal to the adjacent data driver integrated circuit among the plurality of data driver integrated circuits. Driving method of liquid crystal display device. The method of claim 10, The polarity of the video signal is inverted in units of vertical lines of the liquid crystal panel and inverted in units of horizontal lines. The method of claim 10, The polarity of the video signal is inverted in units of two vertical lines of the liquid crystal panel and inverted in units of one horizontal line. The method of claim 10, A method of driving a liquid crystal display device, characterized in that the rate at which the polarity control signal is supplied to the plurality of data driver integrated circuits is the same as the rate at which the inverted polarity control signal is supplied. The method of claim 10, And the inverted polarity control signal is supplied to at least two data driver integrated circuits in the one horizontal period. The method of claim 14, And the data driver integrated circuit to which the inverted polarity control signal is supplied differs in units of one horizontal line of the liquid crystal panel. The method of claim 15, And wherein the polarity control signal is repeated in at least N horizontal line units within one frame. The method of claim 10, And generating a random number for randomly inverting the polarity control signal by using a random number generator. The method of claim 17, The inverted polarity control signal is supplied to at least one of the data driver integrated circuits according to the random number.