KR101362132B1 - Liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of displaying a normal screen and an inverted screen on an image display unit. The liquid crystal display device of the present invention includes a liquid crystal in which pixel cells are formed for each region defined by a plurality of gate lines and a plurality of data lines. A data driver for supplying a data signal to the data lines, a gate driver for supplying a gate signal to the gate lines, and a memory unit for storing one frame of data; And a timing controller configured to change an output order of data stored in the memory and output the data to the data driver to display a normal screen or an inverted screen on the liquid crystal panel, wherein the memory unit is supplied from an outside of the timing controller. Indicating the normal screen or the reverse screen Selecting an output order of the stored data in response to a selection signal directly; outputting the stored data in the same order as the input order when the selection signal indicates the normal screen; And outputting the stored data in an order opposite to the input order when indicating the inverted screen.

Cascade, COG, Normal, Reverse, SSP, GSP

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

1 is a view schematically showing a liquid crystal display device of a general COG method

2A and 2B illustrate a liquid crystal display device having a single FPC according to the related art.

3 illustrates a liquid crystal display device according to the present invention.

4 is a block diagram of the timing controller shown in FIG.

<Code Description of Main Parts of Drawing>

210: liquid crystal panel 250: control board

252: timing controller 254: power generation unit

50: signal generator 52: data processor

54: memory unit 220a, 220b, 220c, 220d: data IC

224: data LOG 240a, 240b: gate IC

244: gate LOG

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device for displaying a normal screen and a screen inverted up, down, left, and right in an image display unit.

Recently, various flat panel display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have emerged. Such flat panel displays include liquid crystal displays, field emission displays, plasma display panels, and light emitting displays.

Among flat panel displays, liquid crystal displays have been actively applied to notebooks, desktop monitors, and mobile terminals due to their excellent resolution, color display, and image quality.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the LCD includes a liquid crystal panel having a liquid crystal cell, a backlight unit for irradiating light to the liquid crystal panel, and a driving circuit for driving the liquid crystal cell.

Here, the driving circuit includes an integrated circuit (IC) for driving the liquid crystal cell. The tape carrier package and the chip on film are connected according to a method of connecting the IC to the liquid crystal panel. ) And chip on glass (hereinafter referred to as 'COG').

1 is a view schematically showing a liquid crystal display using a COG method according to the related art.

Referring to FIG. 1, the liquid crystal display device using the COG method according to the related art includes a liquid crystal panel 10 in which pixel cells P are formed in regions defined by a plurality of gate lines GL and data lines DL. And a data IC 20 mounted directly on the first side of the liquid crystal panel to supply a data signal to the data lines DL, and a first data supply signal to the data IC 20. A flexible printed circuit (FPC) 30, a gate IC 40 mounted directly on the second side of the liquid crystal panel to supply a gate pulse signal to the gate lines GL, and to each gate IC 40. And a second FPC 50 for supplying a gate driving signal.

The liquid crystal display using the COG method according to the related art has a disadvantage in that the cost of the liquid crystal display is increased by using expensive first and second FPCs to drive a plurality of data and gate ICs.

Accordingly, a liquid crystal display device having a reduced manufacturing cost by allowing one FPC to be connected to the first data IC and the first gate IC has been described.

2A and 2B, a liquid crystal display having a single FPC according to the related art has a liquid crystal in which pixel cells P are formed in regions defined by a plurality of gate lines GL and data lines DL. A panel 110, a control board 150 for driving the data ICs 120a to 120d and the gate ICs 140a and 140b, and an FPC connected between the liquid crystal panel 110 and the control board 150; 130 and a plurality of data ICs 120a to 120d mounted directly on the first side of the liquid crystal panel 110 and connected in a cascade manner to supply data signals to the data lines DL. And a plurality of gate ICs 140a and 140b mounted directly on the second side of the liquid crystal panel 110 and connected in a cascade manner to supply a gate pulse signal to the gate line GL.

The FPC 130 is connected to the first region provided on the first side of the lower substrate 110, connected to the second region provided on the second side of the lower substrate 110, and connected to the control board 150 through a connector. Connected.

The first region is a data COG region in which the plurality of data ICs 120a to 120d are mounted, and a plurality of data LOG (Line On Glass) for connecting the data ICs 120a to 120d to the FPC 130 in a cascade manner. ) 124 and a plurality of data pads connecting the data ICs 120a to 120d and the data lines DL.

The second region includes a gate COG region in which the plurality of gate ICs 140a to 140b are mounted, and a plurality of gate LOGs 144 for cascading the gate ICs 140a and 140b to the FPC 130. Include.

The control board 150 includes a timing controller 152 for controlling the data ICs 120a to 120d and the gate ICs 140a and 140b, a power generator 154 for generating driving power, and an FPC 130. And a connector connected with the.

The plurality of data ICs 120a to 120d are mounted in the data COG region and are connected in series with the FPC 130 through the data LOGs 124. The data ICs 120a to 120d sequentially latch digital data supplied in a cascade manner, convert the latched digital data into analog data signals, and supply the analog data signals to the data lines DL.

That is, the first data IC 120a supplies the data driving signal from the control board 150, that is, the data signal, the data control signal, and the data driving power through the first data LOGs 124 connected to the FPC 130. Receive. The second data IC 120b is a data drive signal from the control board 150, i.e., data, via the FPC 130, the first data LOGs 124, the first data IC 120a, and the second data LOG 124. Signal, data control signal and data driving power are supplied.

The gate ICs 140a and 140b receive the gate driving signal from the control board 150, that is, the gate control signal and the gate driving power through the gate LOGs 144 connected to the FPC 130. The gate ICs 140a and 140b supply gate pulses that sequentially drive the plurality of gate lines GL according to the gate control signal.

A liquid crystal display device in which one FPC as described above is connected to the data ICs 120a to 120d in a cascade manner and the gate ICs 140a to 140b are connected in a cascade manner is used to look at the screen in up, down, left, and right directions. Image quality characteristics may change according to the viewing angle.

For example, a liquid crystal display device applied to a notebook computer is determined by viewing direction from the upper direction by a predetermined angle based on a direction perpendicular to the screen, and on the contrary, in public places or public transportation (buses, trains and aircraft). The liquid crystal display device installed at a constant height) is determined in a direction viewed from below by a predetermined angle based on a direction perpendicular to the screen. In addition, the liquid crystal display device applied to the audio system or various information displays provided between the driver's seat and the passenger seat of the passenger car is determined in a direction in which the viewing angle is viewed from the left or right by a predetermined angle based on the direction perpendicular to the screen. .

Therefore, the liquid crystal display device is manufactured such that up, down, left, and right inversion of the screen is possible according to the use environment as described above.

As shown in FIG. 2A, the following driving method is performed to display the upper, lower, left, and right inverted screens as described above on the image display unit of the liquid crystal panel 110.

When the first data control signal, that is, the first source start pulse SSP1 is input to the fourth data IC 120d through the first data control signal line 126a connected to the last fourth data IC 120d, the data The first data signal among the data signals input to the LOG 124 is latched in the fourth data IC 120d in reverse order. Here, the first data control signal line 126a is substantially connected between the FPC 130 and the fourth data IC 120d via the data LOGs 124 and the first to third data ICs 120a to 120c. Connected.

Subsequently, when all data signals corresponding to the fourth data IC 120d are latched, the fourth data IC 120d generates a carry signal, and the carry signal is transmitted through the carry signal line 125. It is input to the third data IC 120c. Subsequently, the third data IC 120c is enabled in the carry signal and is reversed from the next data signal of the data signal latched to the fourth data IC 120d among the data signals input to the data LOG 124. To the third data IC 120c.

In this way, when all data for the horizontal line in the reverse direction from the fourth data IC 120a to the first data IC 120a are latched, the latched data are simultaneously converted into analog data signals and output to the data lines DL. do. The first to fourth data ICs 120a to 120d latch the data in the reverse direction and convert the latched data into an analog signal and output the data to the data lines DL in each horizontal period. Repeat.

At this time, the first gate start pulse GSP1 is input to the second gate driver IC 140b through the first gate control line 127a for upside down. Here, the first gate control signal line 127a is substantially connected between the FPC 130 and the second gate IC 140b via the gate LOGs 144 and the first data IC 140a. In response to the first gate start pulse GSP1, the second gate driver IC 140b and the first gate driver IC 140a are driven in reverse order. Accordingly, the plurality of gate lines GL are driven in reverse order from the last gate line to the first gate line.

As such, the data ICs 120a to 120d latch the data in the reverse direction to supply the data lines DL, and the gate ICs 140a and 140b drive the gate lines GL in the reverse direction. 110 displays a screen inverted up, down, left and right.

On the other hand, as shown in Figure 2b, in order to display the normal screen in contrast to the inverted screen on the image display unit of the liquid crystal panel 110, the following driving method is performed.

First, when the second data control signal, that is, the second source start pulse SSP2 is input to the first data IC 120a through the second data control signal line 126b, the data input to the data LOG 124. The first data IC 120a to the fourth data IC 120d are sequentially latched from the first data signal.

As such, when all data for the horizontal line in the forward direction are latched to the first to fourth data ICs 120a to 120d, the latched data are simultaneously converted into analog data signals and outputted to the data lines DL. As described above, the first to fourth data ICs 120a to 120d repeat the operation of latching data in the forward direction, converting the latched data into analog signals, and outputting the data to the data lines DL. do.

In response to the second gate start pulse GSP2 supplied to the first gate driving IC 140a through the second gate control line 127b, the gate ICs 140a and 140b sequentially move from the first gate line to the last gate line. To run.

As such, the data ICs 120a to 120d latch the data in the forward direction to supply the data lines DL, and the gate ICs 140a and 140b drive the gate lines GL in the forward direction. 110 displays a normal screen.

However, as shown in FIG. 2A, the second data control signal line 126a to which the data driving signal is input to display the inverted screen is inputted with the data control signal to display the normal screen as shown in FIG. 2B. Compared with the first data driving signal line 126b, the line resistance increases, resulting in a signal delay and a screen defect due to the signal delay of the line.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device for preventing a delay of an input signal to display an inverted screen when displaying a normal screen and a screen inverted up, down, left, and right on an image display unit. .

In order to achieve the above object, a liquid crystal display according to an aspect of the present invention is a liquid crystal panel in which pixel cells are formed for each region defined by a plurality of gate lines and a plurality of data lines, and a data signal to the data lines. A data driver for supplying a gate driver for supplying a gate signal to the gate lines, and a memory for storing data of one frame; controlling the data driver and the gate driver; And a timing controller for changing the output order of the data stored in the memory to output the data to the data driver.

The data driver includes a plurality of data integrated circuits disposed on a first side of the liquid crystal panel, and the plurality of data integrated circuits receive data from the timing controller in a cascade manner. The gate driver includes a plurality of gate integrated circuits disposed on a second side of the liquid crystal panel, and the plurality of gate integrated circuits receive gate driving signals from the timing controller in a cascade manner.

The memory selects the output order of the stored data in response to the selection signal. Specifically, the memory outputs the stored data in the same order as the input order when the selection signal indicates the normal screen, and outputs the stored data in the order opposite to the input order when the selection signal indicates the reverse screen.

The plurality of data integrated circuits and the plurality of gate integrated circuits are driven in the same direction regardless of the normal screen and the inverted screen.

The timing controller supplies a source start pulse to a first data integrated circuit of the plurality of data integrated circuits and a gate start pulse to a first gate integrated circuit of the plurality of gate integrated circuits regardless of the normal screen and the inverted screen.

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An embodiment of a liquid crystal display and a driving method according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

As shown in FIG. 3, a liquid crystal display device having a single FPC according to the present invention and cascade-connecting each data IC includes a pixel for each region defined by a plurality of gate lines GL and data lines DL. A liquid crystal panel 210 having a cell P, a control board 250 for generating data and gate driving signals for driving the plurality of data ICs 220a to 220d and the gate ICs 240a and 240b; In addition, the FPC 230 connected between the liquid crystal panel 210 and the control board 250 and the first side of the liquid crystal panel 210 may be directly mounted to supply a data signal to the data lines DL. A plurality of data ICs 220a to 220d connected to each other and a cascade method connected directly to the second side of the liquid crystal panel 210 to supply a gate pulse signal to the gate line GL. The gate ICs 240a and 240b, the FPC 230 and the first data IC 220a The data control line 260 and, FPC (230) and the first gate IC the gate control line-270 is connected between (240a) connected to include.

The liquid crystal panel 210 includes a lower substrate 202 and an upper substrate 204 bonded to each other. In this case, a liquid crystal layer is formed between the lower substrate 202 and the upper substrate 204, and a spacer is formed to keep the gap between the lower substrate 202 and the upper substrate 204 constant.

A color filter, a common electrode, a black matrix, and the like, which are not shown, are formed on the upper substrate 204, and the common electrode may be formed on the lower substrate 202.

The lower substrate 202 is connected to a plurality of data lines DL and a plurality of gate lines GL formed to intersect, a thin film transistor formed in a region defined by the plurality of data lines and a plurality of gate lines, and a thin film transistor. Pixel cells to be included.

The thin film transistor supplies the data driving signal from the data line DL to the pixel cell in response to the gate pulse signal from the gate line GL. The pixel cell may be equivalently represented as a liquid crystal capacitor because the pixel cell includes a common electrode facing the liquid crystal layer and a pixel electrode of the thin film transistor. The pixel cell includes a storage capacitor for maintaining a data signal charged in the liquid crystal capacitor until the next data signal is charged.

In addition, a data pad portion connected to each of the plurality of data lines DL is formed in the first region provided on the first side of the lower substrate 202, and a plurality of gates are provided in the region provided on the second side of the lower substrate 202. Gate pad portions connected to each of the lines GL are formed.

The first region includes a data COG region in which the plurality of data ICs 220a to 220d are mounted, a plurality of data LOGs 224 for cascading the data ICs 220a to 220d to the FPC 230, and an FPC. A data control line 260 connected between the 230 and the first data IC 220a to supply a source start pulse SSP, and to connect the data ICs 220a to 220d and the data lines DL. It includes a plurality of data pads. Here, a plurality of data LOGs 224 are formed between the FPC 230 and the first data IC 220a and between the second to fourth data ICs 220b to 220d, respectively. The plurality of data LOGs 224 include a plurality of data transmission lines for transmitting digital data, a plurality of control signal transmission lines for transmitting data control signals except for a source start pulse (SSP), and a plurality of power lines for transmitting data driving power. It includes.

The second region includes a gate COG region in which the plurality of gate ICs 240a and 240b are mounted, a plurality of gate LOGs 244 that connect the gate ICs 240a and 240b to the FPC 230 in a cascade manner, and an FPC. A plurality of gate lines 270 connected between the 230 and the first gate IC 220a to supply a gate start pulse GSP, and a plurality of gate ICs 240a and 240b connected to the gate lines GL. It includes a gate pad. Here, a plurality of gate LOGs 244 are formed between the FPC 230 and the first gate IC 240a and between the first and second gate ICs 240a and 240d. The plurality of gate LOGs 244 includes a plurality of control signal transmission lines for transmitting gate control signals except for a gate start pulse GSP, and a plurality of power lines for transmitting gate driving power.

The FPC 230 protrudes from one side and is connected to the connector 256 of the control board 250 and a plurality of data LOGs 224 and gate LOGs 244 formed on the liquid crystal panel 210. It includes output pads. The FPC 230 supplies the digital data and the data control signal and the data driving power from the control board 250 to the data LOGs 224 and the data control line 260, and supplies the gate control signal and the gate driving power. Supply to gate LOGs 244 and gate control line 270.

The control board 250 includes a timing controller 252 for driving the data ICs 220a to 220d and the gate ICs 240a and 240b and a power generation unit 254 for generating driving power. And a connector 256 connected to 230.

As illustrated in FIG. 4, the timing controller 252 may include a data processor 50 for inputting data RGB from the outside and aligning it with driving of the liquid crystal panel 210 to output a data signal RGB; A control signal generator for generating and supplying data control signals for controlling the data ICs 220a to 220d and gate control signals for controlling the gate ICs 240a and 240b using an external control signal ECS. 52). The data control signals include a source start pulse SSP, a source shift clock SSC, a source output enable SOE, a polarity control signal POL, and the like. The gate control signals include a gate start pulse GSP, a gate shift clock GSC, and a gate output enable GOE.

In addition, the timing controller 252 stores data signals of one frame arranged by the data processing unit 50 and displays data for displaying an inverted screen or a normal screen according to the inversion selection signal RI on the image display unit of the liquid crystal panel 210. A memory unit 54 is further provided for inverting or maintaining the output order of the signals. That is, the data signal output from the data processing unit 50 is stored in the memory unit 54, and the memory unit 54 outputs or inputs the stored data signals in an order opposite to the input order according to the inversion selection signal RI. Will be output in the correct order.

The power generator 254 generates driving power required for driving the liquid crystal panel 210, the data ICs 220a to 220d, and the gate ICs 240a and 240b.

The plurality of data ICs 220a to 220d are mounted in the first area data COG area, and the data ICs 220a to 220d are connected to the data LOGs 224. Each of the plurality of data ICs 220a to 220d converts the supplied digital data into an analog data signal according to a data control signal and supplies the converted digital data to the data lines DL. At this time, the liquid crystal display according to the embodiment of the present invention is composed of four data IC (220a to 220d).

That is, the first data IC 220a receives a data driving signal, that is, a data signal, a data control signal, and a data driving power from the control board 250 through the data LOGs 224 connected to the FPC 230. The first data IC 220a is supplied with a source start pulse SSP among data control signals through a data control line 260 connected to the FPC 230.

 The second data IC 220b is a data signal from the control board 250 via data LOGs 224 connected between the first data IC 220a and the first and second data ICs 220a and 220b, The data control signal and the data driving power are supplied. In the same manner, the third and fourth data ICs 220c and 220d are also supplied with the data signal, the data control signal and the data driving power through the data LOGs 224 connected to the front end data IC.

The plurality of gate ICs 240a and 240b are mounted in the gate COG region of the second region, and the gate driving signal from the control board 250 through the FPC 230 and the gate LOGs 244, that is, the gate control signal and The gate drive power is supplied. The gate ICs 240a and 240b sequentially generate gate pulses according to the gate control signal, and supply the gate pulses to the gate line GL. In this case, the liquid crystal display according to the exemplary embodiment of the present invention is composed of two gate ICs 240a and 240b.

The first gate IC 240a receives the gate control signal and the gate driving power from the control board 250 through the gate LOGs 244 connected to the FPC 230. The first gate IC 240a receives the gate start pulse GSP from the control board 250 through the gate control line 270 connected to the FPC 230. The second gate IC 240b receives a gate control signal and a gate driving power through the gate LOGs 244 connected to the first gate IC 220a.

As described above, in order to display the up, down, left, and right inverted screens on the liquid crystal display according to the present invention, the source start pulse SSP is input to the first data IC 220a and the gate start pulse GSP is input to the first gate IC 240a. ) Is entered. In addition, the timing controller 252 outputs data of one frame stored in the memory 54 in the order opposite to the data input order according to the up, down, left, right, and inverted selection signal RI for each horizontal period of the data ICs 220a to 220d. Allow forward input.

This will be described in more detail as follows.

In order to display the normal screen on the screen display unit of the liquid crystal display device, source data RGB input from the outside is sorted by the data processing unit 52 and stored in the memory unit 54. If the up, down, left, right reverse selection signal RI is not input to the memory unit 54, the data stored in order to display the normal screen is output in the input order, that is, the first, second, third and fourth data signals. do.

When the source start pulse SSP is input to the first data IC 220a through the data control line 260, the first data signals input through the data LOG 224 are latched in the forward direction.

Subsequently, when all of the first data signals are latched to the first data IC 220a, the first data IC 220a generates a carry signal, and the carry signal is transferred to the second data IC through the carry signal line 225. Input to 220b. Accordingly, the second data IC 220b is enabled in the carry signal, and forwardly latches the second data signals supplied after the first data signals through the data LOGs 224. The third and fourth data driver ICs 220c and 220d also latch the third data signals and the fourth data signals supplied through the data LOGs 224 in response to the carry signals generated in the forward direction. .

As such, when all data of a horizontal line forward in the first to fourth data ICs 220a to 220d are latched, the latched data is simultaneously converted into an analog data signal and output to the data lines DL. As described above, the first to fourth data ICs 220a to 220d repeat the operation of latching data in the forward direction, converting the latched data into analog signals, and outputting the data to the data lines DL. do.

In response to the gate start pulse GSP supplied to the first gate driver IC 240a through the gate control line 270, the gate ICs 140a and 140b are driven in the forward direction, thereby sequentially from the first gate line to the last gate line. To run.

As such, the memory unit 54 of the timing controller 252 outputs the stored data in the order of input so that the data ICs 220a to 220d latch the data in the forward direction and supply the data to the data lines DL. In addition, the liquid crystal panel 110 displays a normal screen by the gate ICs 140a and 140b driving the gate lines GL in the forward direction.

On the other hand, in order to display an inverted screen on the screen display unit of the liquid crystal display, source data RGB input from the outside is aligned in the data processing unit 52 and stored in the memory unit 54. When the up, down, left, right inversion selection signal RI is input to the memory unit 54, the memory unit 54 outputs the stored data in an order opposite to the input order to display the reversed screen. In other words, the memory unit 54 stores data of one frame as shown in Table 1 below.

Referring to Table 1, R10 corresponding to the [1,1] pixel of the liquid crystal panel 210 is input to the memory unit 54 by R10, G10 and B10 data and R11, G11 and B11 data. And Rnm, Gnm, and Bnm data corresponding to the [n, m] th pixel are sequentially input and stored. When the up, down, left, and right inversion selection signals RI are input to the memory unit 54, Rnm, Gnm, and Bnm data are output in the opposite order to the input order, and Rn (m-1), Gn (m-1), and Bn (m -1) The data is output in reverse order from the Rnm, Gnm, and Bnm data corresponding to the [n, m] -th pixel to the R10, G10 and B10 data corresponding to the [1,1] th pixel. In other words, the memory unit 54 outputs data in the order from the last n-th horizontal line to the first horizontal line, and in the order from the last m-th pixel to the first pixel in each horizontal line.

As described above, the data output in the reverse order from the memory unit 54 are first to fourth data driving ICs 220a to 220d in response to the source start pulse SSP supplied to the first data IC 220a every horizontal period. Are sequentially latched forward). The first to fourth data driver ICs 220a to 220d convert the latched data into analog data every horizontal period and output the analog data to the data lines DL. In other words, the data output in reverse order from the data of the nth horizontal line in the memory unit 54 are latched in the forward direction to the first to fourth data ICs 220a to 220d in every horizontal period, and the data lines DL. Is supplied.

In addition, the first and second gate ICs 240a and 240b are driven in the forward direction in response to the gate start pulse GSP supplied to the first gate IC 240a to sequentially drive the gate lines GL.

Accordingly, the data for the nth horizontal line, which is supplied in reverse order to the first to fourth data driving ICs 220a to 220d and latched in the forward direction, of the liquid crystal panel 210 when the first gate line GL is driven. It is filled in the first horizontal line. The first horizontal line data, which is supplied in reverse order to the first to fourth data driving ICs 220a to 220d and is latched in the forward direction, is applied to the liquid crystal panel 210 when the last n th gate line GL is driven. It is charged to the nth horizontal line. As a result, the screen inverted up, down, left, and right is displayed on the liquid crystal panel 210.

As described above, the memory unit 54 of the timing controller 252 outputs the stored data in an order opposite to the input order, and the data ICs 220a to 220d latch the data in the forward direction to the data lines. And the gate ICs 240a and 240b drive the gate lines GL in a forward direction, the liquid crystal panel 110 displays a screen inverted up, down, left, and right. In other words, the liquid crystal display according to the present invention outputs the data driving ICs 220a to 220b and the gate driving ICs 240a and 240b by reversing the output order of the data in the memory unit to display an inverted screen. There is no need to drive in the reverse direction. Therefore, the normal screen and the inverted screen may be displayed on the liquid crystal panel 210 using only one source start pulse SSP and one gate start pulse GSP.

According to the liquid crystal display of the present invention, since the output order of the data signals for displaying the inverted screen or the normal screen is changed in accordance with the input of the inversion selection signal in the timing controller, the data ICs and the gate ICs need to be driven in both directions. It is only driven forward. As a result, the liquid crystal panel needs only one source start pulse supplied to the first data IC and one gate start pulse supplied to the first gate IC, and thus a screen failure due to a signal delay of the start pulse supplied to the last data IC and the gate IC. Can be prevented.

Claims (13)

A liquid crystal panel in which pixel cells are formed in respective regions defined by a plurality of gate lines and a plurality of data lines; A data driver for supplying a data signal to the data lines; A gate driver for supplying a gate signal to the gate lines; And a memory unit for storing one frame of data, controlling the data driver and the gate driver, and changing an output order of data stored in the memory unit to display a normal screen or an inverted screen on the liquid crystal panel. Includes a timing controller to output The memory unit Supplied from an outside of the timing controller, the output order of the stored data is changed in response to a selection signal indicating the normal screen or the reverse screen; Outputting the stored data in the same order as the input order when the selection signal indicates the normal screen; Outputting the stored data in an order opposite to the input order when the selection signal indicates the inverted screen inverted up, down, left, and right relative to the normal screen; The data driver includes data integrated circuits (ICs) disposed on a first side of the liquid crystal panel, wherein the data ICs receive data from the timing controller in a cascade manner. The timing controller supplies a source start pulse to the first data IC close to the timing controller irrespective of the normal screen and the reversed screen so that the data ICs latch data in the same direction regardless of the normal screen and the reversed screen, The gate driver includes gate ICs disposed on a second side of the liquid crystal panel, wherein the gate ICs receive gate driving signals from the timing controller in a cascade manner. The timing controller supplies a gate start pulse to the first gate IC close to the timing controller irrespective of the normal screen and the inverted screen so that the gate ICs are driven in the same direction regardless of the normal screen and the inverted screen, The source start pulse supplied from the timing controller to the first data IC and the gate start pulse supplied from the timing controller to the first gate IC are electrically connected between the control board on which the timing controller is mounted and the liquid crystal panel. And a liquid crystal panel supplied from the control board to the liquid crystal panel via a single flexible printed circuit connected thereto. delete delete delete delete delete delete delete delete delete delete delete delete

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