KR20170029291A - Method for removing stub in multilayer pcb by forming outer layer circuit - Google Patents

Method for removing stub in multilayer pcb by forming outer layer circuit Download PDF

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Publication number
KR20170029291A
KR20170029291A KR1020150126446A KR20150126446A KR20170029291A KR 20170029291 A KR20170029291 A KR 20170029291A KR 1020150126446 A KR1020150126446 A KR 1020150126446A KR 20150126446 A KR20150126446 A KR 20150126446A KR 20170029291 A KR20170029291 A KR 20170029291A
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KR
South Korea
Prior art keywords
outer layer
etching
forming
hole
stub
Prior art date
Application number
KR1020150126446A
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Korean (ko)
Inventor
최광종
Original Assignee
주식회사 티엘비
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Priority to KR1020150126446A priority Critical patent/KR20170029291A/en
Publication of KR20170029291A publication Critical patent/KR20170029291A/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061Etching masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/067Etchants
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention relates to a method for removing a stub of a multilayer printed circuit board by forming an outer layer circuit. The method for removing a stub of a multilayer printed circuit board by forming an outer layer circuit includes: a step of forming a plurality of substrates including a circuit formed with a copper film; a step of stacking substrates for forming an outer layer including a copper film on outer layers of the substrates; a step of forming a through hole passing through the inner substrates and the substrates forming the outer layers; a step of plating an inner wall of the through hole by copper-plating; a step of filling the through hole with an insulation material; a step of attaching a dry film to the outer layer; a step of exposing and developing the dry film; a step of forming a circuit on the outer layer and removing the copper plating from the through hole by etching a copper film on the outer layer; a step of peeling a remaining dry film from the outer layer; and a step of filling the through hole with the solder-resist. In the step of etching the copper film on the outer layer, etching is performed at an etching rate of 0.1-0.7 m/s. Therefore, the method of removing a stub of a multilayer printed circuit board by forming an outer layer circuit can increase a multilayer printed circuit board manufacturing yield by not requiring a separate drilling process required to remove unnecessary stub, can reduce a circuit board manufacturing defect rate by not affecting an adjacent circuit when the unnecessary stub is removed, and can prevent layer signal interference or disturbance in a high frequency working area.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a stub removal method for a multilayer printed circuit board,

The present invention relates to a method for removing a stub on a multilayer printed circuit board, and more particularly, to a stub removal method for removing a stub from a multilayer printed circuit board by an etching process for forming an outer layer of a multilayer printed circuit board Layer printed circuit board through the formation of an outer layer circuit.

Recently, electronic technology related technology has been progressing in multi-function and high-speed. In order to cope with this trend, semiconductor chip manufacturing technology is also rapidly developing.

In particular, the thickness of printed circuit boards has also been reduced in order to reduce the thickness of finished electronic products. In recent years, technologies related to multilayer printed circuit boards that constitute more circuit layers in the same thickness printed circuit board have been researched and developed.

 The multilayer printed circuit board is usually formed by heat pressing a plurality of printed circuit boards including a prepreg formed by impregnating an epoxy resin with glass fiber and a copper foil circuit formed on the surface thereof.

For the interlayer connection between the multilayer circuits, as shown in FIGS. 1 and 2, the inner walls of the holes 130 are plated with the holes 130 formed through the entire substrate after the substrates are stacked The insulating material 150 is filled to achieve an interlayer electrical connection.

Then, the copper foils 115 and 122 of the outer layers 110 and 120 are etched to form a copper foil circuit of the outer layer.

However, if electrical connection is not required from the upper outer layer 110 to the substrate of the intermediate layer, the copper plating layer 140 having a predetermined depth is removed using a conventional drill.

This is because when the copper plating layer 140 (which is referred to as a stub) is unnecessarily present on the inner wall of the hole 130 in the layer where electrical connection is not required, the copper plating layer 140 This is because crosstalk or interference occurs.

Therefore, in a highly integrated printed circuit board, it is necessary to remove the copper plating layer that is unnecessarily left on the inner wall of the hole 130. The method of removing the stub using the drill as described above is called a back drilling method.

The copper plating layer 140 formed on the inner wall of the hole 130 as well as the insulator 150 filled in the hole 130 are also removed by the back drilling method.

However, as the thickness of the printed circuit board becomes thin and thin, the length of the stub is shortened to about one hundred micrometers. Therefore, it is not easy to control the drill so as to remove the stub with a predetermined depth.

In order to remove the stub, it is very difficult to drill three-dimensionally accurately along the height direction of the stub on the multilayer printed circuit board. In such a drilling process, .

As described above, when the peripheral circuit is penetrated and drilled, the manufacturing of the entire multilayer printed circuit board eventually becomes defective.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a multilayer printed circuit board (PCB), which is capable of removing an unnecessary stub at the time of forming an outer layer circuit, And a method for removing a stub of the stub.

It is another object of the present invention to provide a method for removing a stub on a multilayer printed circuit board through formation of an outer layer circuit which is configured so that a circuit line width finally formed can be a design dimension without affecting a peripheral circuit upon removal of a stub.

According to another aspect of the present invention, there is provided a method for removing a stub on a multilayer printed circuit board by forming an outer layer circuit, the method comprising: forming a plurality of substrates including a circuit formed of a copper foil; Forming a through-hole through the substrate for forming the outer layer and the plurality of substrates; plating the inner wall of the through-hole through copper plating; Forming a circuit on the outer layer by etching the copper foil of the outer layer, and forming a copper plating layer on the inside of the through hole by etching the copper foil of the outer layer, Removing the remaining dry film from the outer layer, filling the through hole with a solder resist, Comprises a step, etching the copper foil of the outer layer is characterized in that the etching in an etching rate of 0.1 to 0.7 ㎛ / s.

Preferably, in the step of removing the copper foil inside the through-hole by etching the copper foil of the outer layer, the inside of the through-hole is etched to a depth of 100 mu m or less.

Here, the exposed portion for circuit formation formed by the exposure and development of the dry film in the outer layer may be protruded by 20% to 70% from the edge of the circuit finally formed by etching.

Preferably, the step of etching the copper foil of the outer layer is etched with hydrochloric acid at a concentration of 3 normal hydrochloric acid and a water-based etching solution.

According to the present invention, a separate drilling process required for unnecessary stub removal is not required, and thus the yield of multilayer printed circuit board manufacturing can be improved.

In addition, when the stub is removed, the line width of the finally formed circuit is made to be the design dimension without affecting the peripheral circuit, and the manufacturing defect rate of the circuit board can be reduced.

Further, inter-layer signal interference or disturbance in the high-frequency operation region can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
1 is a cross-sectional view of a conventional multilayer printed circuit board in a state in which a through hole is formed for interlayer connection,
2 is a cross-sectional view illustrating a drilling method for removing an unnecessary stub in a conventional multilayer printed circuit board,
Fig. 3 is a cross-sectional view of a state in which a substrate for forming an outer layer is laminated on the plurality of inner layer substrate outer layers,
4 is a cross-sectional view of a state in which a through-hole penetrating the substrate for forming the outer layer and the inner-layer substrate is formed,
5 is a cross-sectional view of a state in which the inner wall of the through hole is plated,
6 is a cross-sectional view of the through-hole filled with an insulating material and the dry film adhered to the outer layer substrate,
7 is a cross-sectional view of a state in which a circuit is formed on an outer layer substrate and a copper foil in the through hole is removed,
8 is a cross-sectional view showing a state in which the remaining dry film is removed from the surface of the outer layer substrate,
FIG. 9 is a cross-sectional view of a surface of the outer layer substrate and a solder resist applied to the through hole. FIG.

Hereinafter, the configuration of the present invention will be described in detail with reference to the accompanying drawings.

Prior to this, the terms used in the specification and claims should not be construed in a dictionary sense, and the inventor may, on the principle that the concept of a term can be properly defined in order to explain its invention in the best way And should be construed in light of the meanings and concepts consistent with the technical idea of the present invention.

Therefore, the embodiments shown in the present specification and the drawings are only exemplary embodiments of the present invention, and not all of the technical ideas of the present invention are presented. Therefore, various equivalents It should be understood that water and variations may exist.

FIG. 3 is a cross-sectional view showing a state in which a substrate for forming an outer layer is laminated on the plurality of inner layer substrate outer layers, FIG. 4 is a cross-sectional view of a state in which a through hole penetrating the outer layer- FIG. 6 is a cross-sectional view of a state in which the inside of the through hole is filled with an insulating material and the dry film adheres to the outer layer substrate, FIG. 7 is a cross- FIG. 8 is a cross-sectional view of a state in which the remaining dry film is removed from the surface of the outer layer substrate, and FIG. 9 is a cross-sectional view of the outer layer substrate in a state where the solder resist is coated on the surface and the through- Sectional view.

3 to 9, a method of removing a stub on a multilayer printed circuit board by forming an outer layer circuit according to the present invention includes the steps of: forming a plurality of substrates 100 including a circuit formed of a copper foil; A step of laminating a substrate 10 for forming an outer layer including a copper foil 15 on an outer layer of a substrate 100 and a through hole 30 penetrating through the substrate 10 for forming an outer layer and the plurality of substrates 100 Filling the inside of the through hole (30) with an insulating material (50), forming a copper foil (15) on the outer layer, ) Of the dry film (60), exposing and developing the dry film (60), etching the copper foil (15) of the outer layer to form a circuit (12) Removing the copper plating (40) inside the hole (30), removing residual plating Wherein the step of etching the copper foil (15) in the outer layer comprises: etching the copper foil (15) in the outer layer with an etching rate of 0.1 to 0.7 m / s .

The plurality of substrates 100 may include a plurality of individual substrates including a circuit formed by closely adhering a dry film to the surface of the copper foil and subjecting it to exposure, development, and etching in a state where a copper foil is disposed on the surface of the prepreg Laminated, and applying heat and pressure.

A substrate 10 for forming an outer layer disposed outside the plurality of substrates 100 is also formed by disposing a copper foil 15 on the surface of the prepreg.

The prepreg is formed by impregnating a reinforcing base material such as glass fiber with a polymer resin. As the reinforcing base material, a glass fiber fabric, a glass fiber nonwoven fabric, a carbon fiber fabric, or an organic polymer fiber fabric is used.

The polymer resin for forming the prepreg is mixed with an additive such as a hardening agent for adjusting the dielectric constant, thermal expansion rate, and time required for curing.

As the additives to be mixed into the polymer resin for the above-mentioned property control, inorganic fillers such as silica, aluminum hydroxide, calcium carbonate, and organic fillers such as cured epoxy and crosslinked acryl are available.

A through hole 30 is formed through the substrates 100 and 10 in a state where the substrate 10 for forming an outer layer is loaded on the inner substrate 100 composed of a plurality of substrates as described above.

The through-holes 30 are plated on the inner walls of the stacked substrates 10, 20 and 100 for electrical connection.

Thus, a copper plating layer 40 is formed on the inner wall of the through hole 30, and then the inside of the through hole 30 is filled with an insulating material 50 such as epoxy.

Thereafter, the dry film 60 is brought into close contact with the surface of the copper foil 15 of the outer layer substrate.

The circuit film 12 is formed on the surface of the outer layer 10 by exposing and developing the dry film 60 and etching the copper foil 15 of the outer layer.

During the etching process for forming the circuit 12 on the surface of the outer layer 10, the copper plating layer 40 in the through hole 30 is removed to a certain depth d.

The depth d at which the copper plating layer is removed in the through hole 30 while etching the copper foil 15 of the outer layer substrate 10 is preferably 100 μm or less.

If the depth of the copper plating layer inside the through hole 30 to be removed as described above exceeds 100 탆, it becomes very difficult to control the depth of etching the copper plating layer 40 by etching, , The etching solution may penetrate under the dry film (60) during the removal process of the copper plating layer (40) to etch the peripheral circuit, thereby undesirably affecting the formation of a predetermined design dimension circuit.

 Here, it is preferable that the step of etching the copper foil 15 in the outer layer is etched at an etching rate of 0.1 to 0.7 탆 / s.

Specifically, when the etching is performed by spraying an etching solution of sulfuric acid-fruit type, the etching is preferably performed at an etching rate of 0.1 to 0.12 mu m / sec. In the case of spraying a Cucl2 etching solution of sodium chloride-sodium chloride type having a normal concentration of hydrochloric acid of 0.7 Is etched at an etching rate of 0.2 to 0.4 mu m / sec.

In addition, in the case of spraying a hydrochloric acid-hydrofluoric acid type Cucl2 etchant having a normal concentration of 3 hydrochloric acid, it is preferable that the etch rate is 0.5 to 0.7 占 퐉 / sec.

The etching rate is adjustable by controlling the relative jetting speed of the etching liquid to the copper foil 15 and the stub 40, and the amount and concentration of the etchant.

If the etching rate for removing the stub 40 is less than 0.1 占 퐉 / sec, the etching rate becomes too small to reduce the process yield. As the etching time becomes longer, the etching liquid permeates into the peripheral circuits, The copper foil is etched.

That is, when the etching time becomes too long, the etching liquid does not penetrate only in the vertical direction of the substrate through the opening portion of the dry film, but the etching liquid flowing into the opening portion of the dry film flows laterally of the substrate, Etched.

This eventually has an undesirable effect on the formation of the circuit line width of the design dimension or the width of the component connection pad.

If the etching rate is larger than 0.7 μm / sec, the etching rate becomes too large, and it becomes very difficult to control the depth of removal of the stub 40 through etching. When the depth d of removal of the stub 40 is deeper than necessary Or shallow.

The etch for removing the stub 40 may be performed using a 3N hydrochloric acid-hydrochloric acid-hydrochloric acid-type It is preferable to etch with a Cucl2 etchant.

7, the circuit-forming dry film residue 64 formed by the exposure and development of the dry film 60 on the surface of the outer layer substrate 10 is preferably the dry film residue 64 Circuit, that is, 20% to 70% protruding outward from the edge of the circuit 12 of the design dimension.

That is, when the width W of the circuit 12 to be finally formed is W, the dry film 64 for forming the circuit 12 is formed by W + S by the exposure and development processes.

As described above, while the etching process is performed to remove the stub 40 by a predetermined depth d, the etchant penetrates in the vertical direction of the substrate, that is, in the depth d direction of the stub 40, And flows between the dry film 64 and the insulator of the outer layer substrate 10 in the horizontal direction.

Therefore, in consideration of the influence of the etching liquid flowing in the horizontal direction of the substrate as described above to reduce the circuit line width, the width of the remaining dry film for forming the circuit 12 is formed to be W + S instead of the design circuit line width W .

When the stub 40 is removed by etching as described above, the portion of the through hole 35 of the outer layer substrate 10 in which the stub 40 is present is a space free of the copper layer.

Thereafter, the remaining dry film 60 is removed from the circuit surface formed on the external substrate 10.

Then, the solder resist 70 is filled in the space of the through hole 35 from which the stub is removed, thereby functioning as a plugging step using an insulator.

While the present invention has been described with reference to the exemplary embodiments and the drawings, it is to be understood that the technical scope of the present invention is not limited to these embodiments and that various changes and modifications will be apparent to those skilled in the art. Various modifications and variations may be made without departing from the scope of the appended claims.

10: outer layer substrate
12: Copper
20: outer layer substrate
22: Copper foil
30: Through hole
40: Plated layer
50: Insulator
60: Dry film
70: Solder resist
100: Inner layer substrate

Claims (4)

CLAIMS 1. A method for removing a stub in a multilayer printed circuit board comprising a plurality of layers of copper-
Forming a plurality of substrates including a circuit formed of a copper foil;
Stacking a substrate for forming an outer layer including a copper foil on the plurality of substrate outer layers;
Forming a through-hole through the substrate for forming the outer layer and the plurality of substrates;
Plating the inner wall of the through hole through copper plating;
Filling the inside of the through hole with an insulating material;
Adhering a dry film to the outer layer;
Exposing and developing the dry film;
Etching the copper foil of the outer layer to form a circuit in the outer layer and removing copper plating inside the through hole;
Peeling the remaining dry film from the outer layer;
Filling the through hole with a solder resist,
Wherein the step of etching the copper foil of the outer layer is etched at an etching rate of 0.1 to 0.7 mu m / s.
The method according to claim 1,
Wherein the step of removing the copper foil in the through hole by etching the copper foil of the outer layer comprises etching the inside of the through hole to a depth of 100 mu m or less.
3. The method of claim 2,
Wherein the remaining portion for circuit formation formed by the exposure and development of the dry film in the outer layer is formed to protrude from the edge of the circuit finally formed by etching by 20% to 70% of the circuit width Gt; a < / RTI > stub of a multilayer printed circuit board.
The method of claim 3,
Wherein the step of etching the copper foil of the outer layer is performed by etching with hydrochloric acid having a normal concentration of 3N hydrochloric acid and a water-based etchant.
KR1020150126446A 2015-09-07 2015-09-07 Method for removing stub in multilayer pcb by forming outer layer circuit KR20170029291A (en)

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Application Number Priority Date Filing Date Title
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109803481A (en) * 2017-11-17 2019-05-24 英业达科技有限公司 Multilayer board and the method for making multilayer board
KR20190097550A (en) * 2018-02-12 2019-08-21 주식회사 티엘비 Method for multilayer pcb of embedded trace pcb type
CN111650771A (en) * 2020-06-16 2020-09-11 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
CN113225917A (en) * 2020-01-21 2021-08-06 宏恒胜电子科技(淮安)有限公司 Method for manufacturing circuit board with back drilling hole
CN114007345A (en) * 2021-09-18 2022-02-01 宏华胜精密电子(烟台)有限公司 Preparation method of circuit board
KR102357005B1 (en) * 2021-05-25 2022-02-08 주식회사 스마트코리아피씨비 Back drill stub residue removal method
WO2022174021A1 (en) * 2021-02-11 2022-08-18 R&D Circuits, Inc. System and method for detecting defective back drills in printed circuit boards

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109803481A (en) * 2017-11-17 2019-05-24 英业达科技有限公司 Multilayer board and the method for making multilayer board
CN109803481B (en) * 2017-11-17 2021-07-06 英业达科技有限公司 Multilayer printed circuit board and method for manufacturing multilayer printed circuit board
KR20190097550A (en) * 2018-02-12 2019-08-21 주식회사 티엘비 Method for multilayer pcb of embedded trace pcb type
CN113225917A (en) * 2020-01-21 2021-08-06 宏恒胜电子科技(淮安)有限公司 Method for manufacturing circuit board with back drilling hole
CN111650771A (en) * 2020-06-16 2020-09-11 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
CN111650771B (en) * 2020-06-16 2023-01-10 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
WO2022174021A1 (en) * 2021-02-11 2022-08-18 R&D Circuits, Inc. System and method for detecting defective back drills in printed circuit boards
KR102357005B1 (en) * 2021-05-25 2022-02-08 주식회사 스마트코리아피씨비 Back drill stub residue removal method
CN114007345A (en) * 2021-09-18 2022-02-01 宏华胜精密电子(烟台)有限公司 Preparation method of circuit board

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