KR20170029291A - Method for removing stub in multilayer pcb by forming outer layer circuit - Google Patents
Method for removing stub in multilayer pcb by forming outer layer circuit Download PDFInfo
- Publication number
- KR20170029291A KR20170029291A KR1020150126446A KR20150126446A KR20170029291A KR 20170029291 A KR20170029291 A KR 20170029291A KR 1020150126446 A KR1020150126446 A KR 1020150126446A KR 20150126446 A KR20150126446 A KR 20150126446A KR 20170029291 A KR20170029291 A KR 20170029291A
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- KR
- South Korea
- Prior art keywords
- outer layer
- etching
- forming
- hole
- stub
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/067—Etchants
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
The present invention relates to a method for removing a stub on a multilayer printed circuit board, and more particularly, to a stub removal method for removing a stub from a multilayer printed circuit board by an etching process for forming an outer layer of a multilayer printed circuit board Layer printed circuit board through the formation of an outer layer circuit.
Recently, electronic technology related technology has been progressing in multi-function and high-speed. In order to cope with this trend, semiconductor chip manufacturing technology is also rapidly developing.
In particular, the thickness of printed circuit boards has also been reduced in order to reduce the thickness of finished electronic products. In recent years, technologies related to multilayer printed circuit boards that constitute more circuit layers in the same thickness printed circuit board have been researched and developed.
The multilayer printed circuit board is usually formed by heat pressing a plurality of printed circuit boards including a prepreg formed by impregnating an epoxy resin with glass fiber and a copper foil circuit formed on the surface thereof.
For the interlayer connection between the multilayer circuits, as shown in FIGS. 1 and 2, the inner walls of the
Then, the
However, if electrical connection is not required from the upper
This is because when the copper plating layer 140 (which is referred to as a stub) is unnecessarily present on the inner wall of the
Therefore, in a highly integrated printed circuit board, it is necessary to remove the copper plating layer that is unnecessarily left on the inner wall of the
The
However, as the thickness of the printed circuit board becomes thin and thin, the length of the stub is shortened to about one hundred micrometers. Therefore, it is not easy to control the drill so as to remove the stub with a predetermined depth.
In order to remove the stub, it is very difficult to drill three-dimensionally accurately along the height direction of the stub on the multilayer printed circuit board. In such a drilling process, .
As described above, when the peripheral circuit is penetrated and drilled, the manufacturing of the entire multilayer printed circuit board eventually becomes defective.
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a multilayer printed circuit board (PCB), which is capable of removing an unnecessary stub at the time of forming an outer layer circuit, And a method for removing a stub of the stub.
It is another object of the present invention to provide a method for removing a stub on a multilayer printed circuit board through formation of an outer layer circuit which is configured so that a circuit line width finally formed can be a design dimension without affecting a peripheral circuit upon removal of a stub.
According to another aspect of the present invention, there is provided a method for removing a stub on a multilayer printed circuit board by forming an outer layer circuit, the method comprising: forming a plurality of substrates including a circuit formed of a copper foil; Forming a through-hole through the substrate for forming the outer layer and the plurality of substrates; plating the inner wall of the through-hole through copper plating; Forming a circuit on the outer layer by etching the copper foil of the outer layer, and forming a copper plating layer on the inside of the through hole by etching the copper foil of the outer layer, Removing the remaining dry film from the outer layer, filling the through hole with a solder resist, Comprises a step, etching the copper foil of the outer layer is characterized in that the etching in an etching rate of 0.1 to 0.7 ㎛ / s.
Preferably, in the step of removing the copper foil inside the through-hole by etching the copper foil of the outer layer, the inside of the through-hole is etched to a depth of 100 mu m or less.
Here, the exposed portion for circuit formation formed by the exposure and development of the dry film in the outer layer may be protruded by 20% to 70% from the edge of the circuit finally formed by etching.
Preferably, the step of etching the copper foil of the outer layer is etched with hydrochloric acid at a concentration of 3 normal hydrochloric acid and a water-based etching solution.
According to the present invention, a separate drilling process required for unnecessary stub removal is not required, and thus the yield of multilayer printed circuit board manufacturing can be improved.
In addition, when the stub is removed, the line width of the finally formed circuit is made to be the design dimension without affecting the peripheral circuit, and the manufacturing defect rate of the circuit board can be reduced.
Further, inter-layer signal interference or disturbance in the high-frequency operation region can be prevented.
BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
1 is a cross-sectional view of a conventional multilayer printed circuit board in a state in which a through hole is formed for interlayer connection,
2 is a cross-sectional view illustrating a drilling method for removing an unnecessary stub in a conventional multilayer printed circuit board,
Fig. 3 is a cross-sectional view of a state in which a substrate for forming an outer layer is laminated on the plurality of inner layer substrate outer layers,
4 is a cross-sectional view of a state in which a through-hole penetrating the substrate for forming the outer layer and the inner-layer substrate is formed,
5 is a cross-sectional view of a state in which the inner wall of the through hole is plated,
6 is a cross-sectional view of the through-hole filled with an insulating material and the dry film adhered to the outer layer substrate,
7 is a cross-sectional view of a state in which a circuit is formed on an outer layer substrate and a copper foil in the through hole is removed,
8 is a cross-sectional view showing a state in which the remaining dry film is removed from the surface of the outer layer substrate,
FIG. 9 is a cross-sectional view of a surface of the outer layer substrate and a solder resist applied to the through hole. FIG.
Hereinafter, the configuration of the present invention will be described in detail with reference to the accompanying drawings.
Prior to this, the terms used in the specification and claims should not be construed in a dictionary sense, and the inventor may, on the principle that the concept of a term can be properly defined in order to explain its invention in the best way And should be construed in light of the meanings and concepts consistent with the technical idea of the present invention.
Therefore, the embodiments shown in the present specification and the drawings are only exemplary embodiments of the present invention, and not all of the technical ideas of the present invention are presented. Therefore, various equivalents It should be understood that water and variations may exist.
FIG. 3 is a cross-sectional view showing a state in which a substrate for forming an outer layer is laminated on the plurality of inner layer substrate outer layers, FIG. 4 is a cross-sectional view of a state in which a through hole penetrating the outer layer- FIG. 6 is a cross-sectional view of a state in which the inside of the through hole is filled with an insulating material and the dry film adheres to the outer layer substrate, FIG. 7 is a cross- FIG. 8 is a cross-sectional view of a state in which the remaining dry film is removed from the surface of the outer layer substrate, and FIG. 9 is a cross-sectional view of the outer layer substrate in a state where the solder resist is coated on the surface and the through- Sectional view.
3 to 9, a method of removing a stub on a multilayer printed circuit board by forming an outer layer circuit according to the present invention includes the steps of: forming a plurality of
The plurality of
A
The prepreg is formed by impregnating a reinforcing base material such as glass fiber with a polymer resin. As the reinforcing base material, a glass fiber fabric, a glass fiber nonwoven fabric, a carbon fiber fabric, or an organic polymer fiber fabric is used.
The polymer resin for forming the prepreg is mixed with an additive such as a hardening agent for adjusting the dielectric constant, thermal expansion rate, and time required for curing.
As the additives to be mixed into the polymer resin for the above-mentioned property control, inorganic fillers such as silica, aluminum hydroxide, calcium carbonate, and organic fillers such as cured epoxy and crosslinked acryl are available.
A through
The through-
Thus, a
Thereafter, the
The
During the etching process for forming the
The depth d at which the copper plating layer is removed in the through
If the depth of the copper plating layer inside the through
Here, it is preferable that the step of etching the
Specifically, when the etching is performed by spraying an etching solution of sulfuric acid-fruit type, the etching is preferably performed at an etching rate of 0.1 to 0.12 mu m / sec. In the case of spraying a Cucl2 etching solution of sodium chloride-sodium chloride type having a normal concentration of hydrochloric acid of 0.7 Is etched at an etching rate of 0.2 to 0.4 mu m / sec.
In addition, in the case of spraying a hydrochloric acid-hydrofluoric acid type Cucl2 etchant having a normal concentration of 3 hydrochloric acid, it is preferable that the etch rate is 0.5 to 0.7 占 퐉 / sec.
The etching rate is adjustable by controlling the relative jetting speed of the etching liquid to the
If the etching rate for removing the
That is, when the etching time becomes too long, the etching liquid does not penetrate only in the vertical direction of the substrate through the opening portion of the dry film, but the etching liquid flowing into the opening portion of the dry film flows laterally of the substrate, Etched.
This eventually has an undesirable effect on the formation of the circuit line width of the design dimension or the width of the component connection pad.
If the etching rate is larger than 0.7 μm / sec, the etching rate becomes too large, and it becomes very difficult to control the depth of removal of the
The etch for removing the
7, the circuit-forming
That is, when the width W of the
As described above, while the etching process is performed to remove the
Therefore, in consideration of the influence of the etching liquid flowing in the horizontal direction of the substrate as described above to reduce the circuit line width, the width of the remaining dry film for forming the
When the
Thereafter, the remaining
Then, the solder resist 70 is filled in the space of the through
While the present invention has been described with reference to the exemplary embodiments and the drawings, it is to be understood that the technical scope of the present invention is not limited to these embodiments and that various changes and modifications will be apparent to those skilled in the art. Various modifications and variations may be made without departing from the scope of the appended claims.
10: outer layer substrate
12: Copper
20: outer layer substrate
22: Copper foil
30: Through hole
40: Plated layer
50: Insulator
60: Dry film
70: Solder resist
100: Inner layer substrate
Claims (4)
Forming a plurality of substrates including a circuit formed of a copper foil;
Stacking a substrate for forming an outer layer including a copper foil on the plurality of substrate outer layers;
Forming a through-hole through the substrate for forming the outer layer and the plurality of substrates;
Plating the inner wall of the through hole through copper plating;
Filling the inside of the through hole with an insulating material;
Adhering a dry film to the outer layer;
Exposing and developing the dry film;
Etching the copper foil of the outer layer to form a circuit in the outer layer and removing copper plating inside the through hole;
Peeling the remaining dry film from the outer layer;
Filling the through hole with a solder resist,
Wherein the step of etching the copper foil of the outer layer is etched at an etching rate of 0.1 to 0.7 mu m / s.
Wherein the step of removing the copper foil in the through hole by etching the copper foil of the outer layer comprises etching the inside of the through hole to a depth of 100 mu m or less.
Wherein the remaining portion for circuit formation formed by the exposure and development of the dry film in the outer layer is formed to protrude from the edge of the circuit finally formed by etching by 20% to 70% of the circuit width Gt; a < / RTI > stub of a multilayer printed circuit board.
Wherein the step of etching the copper foil of the outer layer is performed by etching with hydrochloric acid having a normal concentration of 3N hydrochloric acid and a water-based etchant.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020150126446A KR20170029291A (en) | 2015-09-07 | 2015-09-07 | Method for removing stub in multilayer pcb by forming outer layer circuit |
Applications Claiming Priority (1)
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KR1020150126446A KR20170029291A (en) | 2015-09-07 | 2015-09-07 | Method for removing stub in multilayer pcb by forming outer layer circuit |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109803481A (en) * | 2017-11-17 | 2019-05-24 | 英业达科技有限公司 | Multilayer board and the method for making multilayer board |
KR20190097550A (en) * | 2018-02-12 | 2019-08-21 | 주식회사 티엘비 | Method for multilayer pcb of embedded trace pcb type |
CN111650771A (en) * | 2020-06-16 | 2020-09-11 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
CN113225917A (en) * | 2020-01-21 | 2021-08-06 | 宏恒胜电子科技(淮安)有限公司 | Method for manufacturing circuit board with back drilling hole |
CN114007345A (en) * | 2021-09-18 | 2022-02-01 | 宏华胜精密电子(烟台)有限公司 | Preparation method of circuit board |
KR102357005B1 (en) * | 2021-05-25 | 2022-02-08 | 주식회사 스마트코리아피씨비 | Back drill stub residue removal method |
WO2022174021A1 (en) * | 2021-02-11 | 2022-08-18 | R&D Circuits, Inc. | System and method for detecting defective back drills in printed circuit boards |
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2015
- 2015-09-07 KR KR1020150126446A patent/KR20170029291A/en active Search and Examination
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109803481A (en) * | 2017-11-17 | 2019-05-24 | 英业达科技有限公司 | Multilayer board and the method for making multilayer board |
CN109803481B (en) * | 2017-11-17 | 2021-07-06 | 英业达科技有限公司 | Multilayer printed circuit board and method for manufacturing multilayer printed circuit board |
KR20190097550A (en) * | 2018-02-12 | 2019-08-21 | 주식회사 티엘비 | Method for multilayer pcb of embedded trace pcb type |
CN113225917A (en) * | 2020-01-21 | 2021-08-06 | 宏恒胜电子科技(淮安)有限公司 | Method for manufacturing circuit board with back drilling hole |
CN111650771A (en) * | 2020-06-16 | 2020-09-11 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
CN111650771B (en) * | 2020-06-16 | 2023-01-10 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
WO2022174021A1 (en) * | 2021-02-11 | 2022-08-18 | R&D Circuits, Inc. | System and method for detecting defective back drills in printed circuit boards |
KR102357005B1 (en) * | 2021-05-25 | 2022-02-08 | 주식회사 스마트코리아피씨비 | Back drill stub residue removal method |
CN114007345A (en) * | 2021-09-18 | 2022-02-01 | 宏华胜精密电子(烟台)有限公司 | Preparation method of circuit board |
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