KR20160093133A - Gate drive integrated circuit and display device comprising thereof - Google Patents

Abstract

The present invention relates to a gate drive integrated circuit and a display device comprising the same. Provided is a gate drive integrated circuit which includes a first input/output control part and a second input/output control part electrically connected to a line to which a gate start signal and a gate signal including a gate clock are applied, and a logic circuit part which applies a gate signal received from the first input/output control part and the second input/output control part to the gate line of the display panel. So, the slew of the gate signal can be reduced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a gate drive integrated circuit and a display device including the gate drive integrated circuit.

The present invention relates to a gate drive integrated circuit and a display device including the gate drive integrated circuit.

The conventional display device includes a panel formed by intersecting gate lines and data lines, a gate driver for driving gate lines formed on the panel, a data driver for driving data lines formed on the panel, And a timing controller for controlling the driving timing of the driving signal.

A display panel constituting a liquid crystal display (LCD) or an organic light-emitting diode (OLED) or the like includes a gate driving circuit for supplying a scan signal to gate lines, The image is displayed using the data driving circuit for supplying the voltage.

On the other hand, in the conventional display device, on the other hand, in such a conventional display device, the gate driver is configured to sequentially supply the scan signals to the gate lines and to transfer signals between the gate drive circuits. There is a problem that the signal is not outputted accurately at the gate driving circuit due to the physical characteristics inside the driving circuit during the transferring process, which may affect the operation of the entire scan line.

In view of the above, it is an object of the present invention to reduce the slew of the gate signal applied to the display device.

It is also an object of the present invention to improve the timing accuracy of the gate signal.

It is also an object of the present invention to reduce the phenomenon of being dropped by a resistor in the process of applying a power line.

In order to achieve the above object, in one aspect, the present invention provides a semiconductor memory device including a first input / output control unit, a second input / output control unit electrically connected to a wiring to which a gate signal including a gate start signal and a gate clock is applied, And a logic circuit for applying the gate signal applied from the second input / output control unit to the gate line of the display panel.

Also, the present invention provides a gate drive integrated circuit including a first input / output control unit and a second input / output control unit for applying a gate signal in a first direction or a second direction.

The present invention also includes a gate driver including a plurality of gate drive integrated circuits for applying a signal to a gate line of a display panel, a data driver for applying a signal to the data line, and a timing controller for controlling the gate driver and the data driver A first input / output control unit and a second input / output control unit electrically connected to a wiring to which a gate signal including a gate start signal and a gate clock are applied, and a second input / output control unit electrically connected to the first input / output control unit or the second input / And a logic circuit portion for applying the gate signal to the gate line of the display panel.

As described above, according to the present invention, there is an effect that the input / output control unit is coupled to the gate drive integrated circuit to control the application direction of the gate signal.

According to the present invention, since the gate signal is amplified in the input / output control section, there is an effect of reducing distortion such as slew of the gate signal.

Further, according to the present invention, there is an effect of reducing the resistance of power by disposing a parallel resistor at the gate COF to which the gate drive integrated circuit is coupled.

1 is a schematic system configuration diagram of a display device 100 for applying embodiments.
2 is a diagram illustrating clock signal generation according to one embodiment.
3 is a view showing a part of a display panel to which a plurality of gate drive ICs to which an embodiment of the present invention is applied is connected.
4 is a view showing a detailed configuration of the gate drive IC.
FIG. 5 is a view showing a configuration of a gate COF to which the gate drive IC of FIG. 4 is coupled.
6 is a diagram showing an output dip phenomenon of VGH / VGL.
7 is a diagram showing an input signal applied between gate drive ICs.
8 is a view showing an internal configuration of a gate drive IC according to an embodiment of the present invention.
FIG. 9 is a diagram illustrating a detailed configuration of the input / output control units 810 and 820 according to an embodiment of the present invention.
10 is a view showing a configuration of a gate COF according to an embodiment of the present invention.
11 is a view showing a configuration of a gate drive IC corresponding to the gate COF of FIG.
12 is a view showing a configuration of a gate COF according to another embodiment of the present invention.
13 is a view showing a configuration of a gate drive IC according to another embodiment of the present invention.
FIG. 14 is a diagram comparing a case where resistors are arranged on a gate COF according to an embodiment of the present invention and a case where a resistor is not disposed on the gate COF.
FIG. 15 is a graph showing a reduction in slew of an input signal in a gate drive IC when the present invention is applied.
16 is a view showing a state in which the output dip is improved when the present invention is applied.
17 is a diagram showing timing accuracy due to slew improvement when the present invention is applied.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a schematic system configuration diagram of a display device 100 for applying embodiments.

1, a display device 100 according to an embodiment of the present invention includes a panel 110 formed by intersecting gate lines GL1 through GLn and data lines DL1 through DLm, A data driver 130 for driving the data lines formed on the panel 110 and a gate driver 120 for driving the gate drivers 120 and the data driver 130. [ A timing controller 140, and the like.

Each pixel (P) is defined in the panel 110 by intersecting the gate lines GL1 to GLn and the data lines DL1 to DLm.

The gate driver 120 drives the gate lines GL1 to GLn by sequentially supplying a scan signal to the gate lines GL1 to GLn. To this end, x (x is a natural number of 2 or more) clock signals And sequentially supplies the scan signals to the gate lines GL1 to GLn based on the received signals.

The above-mentioned x clock signals can be generated in a level shifter. The generation of the clock signal of this level shifter will be described with reference to FIG.

The display device 100 of FIG. 1 may be, for example, a liquid crystal display device or an organic light emitting display device, but is not limited thereto. For example, the panel 110, the gate driver 120, the data driver 130, A timing controller 140 and the like and may be any type of display device as long as the gate driver 120 uses a clock signal to drive the gate lines GL1 to GLn. In addition, the display device 100 of FIG. 1 may be a display device of a mobile terminal, for example, a narrow bezel as an important factor.

An embodiment of the gate drive circuit control signal for controlling the gate drive circuit may include a gate start signal VST, a gate clock, and the like. These signals are generated in the timing controller 140 and supplied to a plurality of gate drive integrated circuits (ICs) included in the gate drive circuit.

The timing controller 140 may be formed in a source printed circuit board (PCB), and a gate drive IC (hereinafter referred to as a gate drive IC) may be connected to a display panel by a TAB (Tape Automated Bonding) Or may be formed on a display panel by a COG (Chip On Glass) method or may be electrically connected to a display panel by a COF (Chip On Film) method.

The timing controller 140 supplies the gate start pulse through the gate start pulse line GSPL formed on the substrate of the display panel, supplies the gate shift clock through the gate shift clock line GSCL, And supplies the gate output enable signal through the gate signal GOEL.

2 is a diagram illustrating clock signal generation according to one embodiment.

2, the level shifter 200 generates a level shifter 200 based on the clock information CLOCK input from the timing controller 140 and the high level voltage VGH and the low level voltage VGL supplied from the power supply unit 210 Thereby generating x clock signals CLK 1, CLK 2, CKL 3, CLK 4, ..., CLK x.

The level shifter 200 outputs the generated x clock signals (CLK 1 to CLK x) to the gate driver 120 that drives the x-phase. The level shifter 200 may be included in the data driver 130 or may be formed on a printed circuit board (PCB) connected through the panel 110 and the data driver 130, But may be formed or positioned anywhere other than the gate driver 120, without limitation.

The gate driver 120 may include a plurality of gate drive ICs directly formed on the panel 110 to sequentially supply scan signals to the gate lines. An embodiment in which the gate drive IC is connected to the display panel with the COF will be described

3 is a view showing a part of a display panel to which a plurality of gate drive ICs to which an embodiment of the present invention is applied is connected. The timing controller 140 and the data driver 130 are not shown in Fig. The gate drive IC 320 is coupled to the film 310 for COF. Hereinafter, the film in which the gate drive IC 320 is disposed is referred to as a gate COF.

4 is a view showing a detailed configuration of the gate drive IC. The gate drive IC 320 includes input signal pads 327a and 327b to which external loads are applied and a logic circuit portion 325 for performing logic control using signals of the pads.

The gate drive IC may optionally include dummy pads 321a and 321b formed for the function of transferring and receiving signals to and powering the gate COF in which adjacent gate drive ICs are disposed. The dummy pads 321a and 321b may be optionally included.

As shown in FIG. 4, the input signal pads 327a and 327b of the gate drive IC 320 are connected to the pads of the other gate drive ICs located on the left and right sides, so there is no distinction of input / output.

FIG. 5 is a view showing a configuration of a gate COF to which the gate drive IC of FIG. 4 is coupled. The gate COF is applied with a power line (VGH / VGL) and an input signal, and the applied signal is applied to the gate drive IC 320. [ The region 315 of the gate COF is the portion to which the gate drive IC of FIG. 4 is coupled.

The pads 327a and 327b of the gate drive IC 320 of FIG. 4 are coupled to 317a and 317b of the gate COF 310 to receive a signal. As shown in FIG. 5, the routing in the gate COF is a form in which an input signal line surrounds a power line. As shown in FIG. 3, a plurality of gate COFs are bonded to the display panel, and input signals and power sources generated by the timing controller are applied to the ICs along the LOG.

4 and 5, conventional input signal pads are symmetrically symmetrical with respect to the center, and are connected between the left and right pads not only inside the gate drive IC but also on the gate COF, It is used as an input pad.

This structure affects the slew because the resistance component of the LOG (Line Of Glass) becomes larger as the input signal (Input Signal) goes farther (Far). In addition, an IC output Dip phenomenon also occurs. The IC's internal power routing resistance affects the LOG resistance component as well as the output dip.

6 is a diagram showing an output dip phenomenon of VGH / VGL. VGH / VGL is applied to the gate drive IC side, and one embodiment of VGH is 24V. The VGL for turn-off may be applied from -5V to -6V, and -10V may be applied in one embodiment. In FIG. 6, when VGH is applied, a voltage drop such as 610 may occur due to a resistance component, a capacitance load, or the like. And the resulting output dip may cause a slew to occur in the output signal, such as 620. That is, due to the output dip of the VGH, the signal that should be output as 625 is output as the signal of 620 is generated.

7 is a diagram showing an input signal applied between gate drive ICs. 7, reference numeral 725 denotes a signal generated by the timing controller of the control printed circuit board. On the other hand, although the first signal having a waveform such as 725 is applied to the plurality of gate COFs from the timing controller, the signal applied to the gate COF located farthest from the timing controller is slew like 729. The reason why the signals applied to the gate drive IC are different depending on the position of the gate drive IC is due to the resistance component or the capacitance, and the timing corresponding to the specific signal level may vary due to the slew.

For example, when the point at which the desired signal level is reached due to slew is the point indicated at 750, there is a difference between 750 and the high point 755 of the signal applied at the timing controller, The output signal of the gate drive IC is different from the signal to be output originally and the gate drive transistor can not be controlled so that the video data of the display panel is outputted properly. As a result, a wrong video signal may be output on the corresponding scan line.

Therefore, in this specification, the gate COF combined with the gate drive IC and the gate drive IC reinforcing the output of the weakened or distorted signal due to the resistance due to the LOG (Line on Glass), the resistance due to wiring, and the capacitance load see. To this end, a configuration in which the pad of the gate drive IC can input and output is proposed.

For this purpose, in this specification, an input signal pad of a gate driving circuit (Gate D-IC) is converted into I / O to improve a slew, an IC side (high side) ) Portion of the VGH / VGL pad to improve the output dip.

Further, when the embodiment of the present invention is applied, the LOG resistance component is lowered to prevent slewing as the input signal goes farther to the far side (far side). In addition, to improve the output dipping phenomenon, the input pad can be made I / O and the IC side dummy pad can be composed of the VGH / VGL power pad.

8 is a view showing an internal configuration of a gate drive IC according to an embodiment of the present invention. The gate drive IC 800 includes a logic circuit portion 325 for providing a logic circuit for applying a gate signal to the display panel, input / output control portions 810 and 820, and input / output pads 815 and 825 for input / output . Power line pads 830a and 830b, which are selectively connected to the VGH / VGL, may be disposed in the gate drive IC 800. [ When power is not applied to the power line pads 830a and 830b, it can operate as a dummy pad. In addition, the logic circuit portion 325 is applied with SHL (Signal High / Low) for controlling the signal direction of the input / output pads 815 and 825. SHL is an example of a shift direction control signal, and determines which input / output pads 815 and 825 become input terminals or output terminals.

For example, when SHL is HIGH, the first input / output pad 815 becomes the input pad and the second input / output pad 825 becomes the output pad. On the other hand, when SHL is Low, the second input / output pad 825 becomes the input pad and the first input / output pad 815 becomes the output pad.

The input and output directions of the signals are determined according to SHL, and signals applied from other gate drive ICs adjacent to the gate drive IC 800 can be buffered by the input / output control units 810 and 820. The input / output control units 810 and 820 may be configured as a combination circuit. A detailed embodiment will be described with reference to FIG.

On the other hand, the power line pads 830a and 830b selectively disposed on the side of the gate drive IC and connected to the VGH / VGL may be disposed at the same positions as the dummy pads 321a and 321b in the configuration of FIG. Also, although not shown in the figure, the logic circuit portion 325 of the gate drive IC may be connected to the VGH / VGL power line applied at the gate COF. In another embodiment, the power applied from the power line pads 830a and 830b may be connected to the logic circuit portion 325. Wirings are arranged between the power line pads 830a and 830b of the gate drive IC or the power line terminals 1150a and 1150b of the logic circuit of the gate drive IC of FIG. 11 to be described later and power is supplied from the gate COF, And the gate drive IC can be constituted by parallel resistors, thereby reducing power output dip phenomenon.

The electrical connection between the power line and the logic circuit portion 325 may be variously configured, and the present invention is not limited thereto.

In the configuration of FIG. 8, the two input / output control units are capable of controlling the direction of a signal to be input / output, and also have the effect of buffering and amplifying input / output signals. Therefore, even in the case of the gate drive IC located far from the timing controller, the gate signal is applied in a sufficiently amplified state, so that the slew of the gate signal can be eliminated or the degree of slewing thereof can be reduced. This can reduce an error between the timing of the gate drive IC to which the gate signal is applied first and the timing of the gate drive IC to which the gate signal is applied at the latest, thereby precisely controlling the operation of the display panel.

FIG. 9 is a diagram illustrating a detailed configuration of the input / output control units 810 and 820 according to an embodiment of the present invention. When High is applied to SHL, the first input / output pad 815 becomes the input pad and the second input / output pad 825 becomes the output pad. 801, and the direction of the signal is the same as 891. When Low is applied to SHL, the first input / output pad 815 becomes the output pad and the second input / output pad 825 becomes the input pad. 802, and the direction of the signal is equal to 892.

In FIG. 9, the input / output control units 810 and 820 may include a buffer composed of an N-MOS transistor and a P-MOS transistor. The N-MOS transistor and the P-MOS transistor are coupled to the SHL so that one input / output control unit inputs a signal and the other input / output control unit outputs a signal. When the N-MOS transistor and the P-MOS transistor are used, amplification of the signal is possible, so that the slew of the input signal, that is, the gate signal, can be improved. The configuration of the transistor of FIG. 9 is an embodiment, and the present invention is not limited thereto.

8 and 9 are summarized as follows. The timing controller may control the gate driver to apply a gate signal, i.e., a scan signal, to the gate line, and the gate driver may include a plurality of gate drive ICs and a gate COF. In yet another embodiment, the gate driver includes a plurality of gate drive ICs, but may be electrically connected to the gate COFs. Each gate drive IC may include an input / output control unit for controlling the direction of a signal and eliminating a signal slew in the process of applying a gate signal and power between gate drive ICs.

The gate drive IC receives a gate signal including a gate start signal and a gate clock from a timing controller or another external gate drive IC. Of course, this signal can be received through the gate COF, which is electrically coupled to the gate drive IC. The first input / output control unit 810 and the second input / output control unit 810 of the gate drive IC are electrically connected to the wiring to which the gate signal is applied. The wiring is electrically connected to the input / output pads 815, 825 or includes input / output pads 815, 825.

The logic circuit portion 325 of the gate drive IC applies the gate signal applied from the first input / output control portion 810 or the second input / output control portion 810 to the gate line of the display panel. 8 and 9, the logic circuit unit 325 can control the application direction of the gate signals of the first input / output control unit 810 and the second input / output control unit 810 in the first direction or the second direction have.

9, the first input / output control unit 810 receives a signal and provides the signal to the logic circuit unit 325, and the second input / output control unit 820 controls the logic And receives a signal from the circuit unit 325 and outputs it to the outside. In the embodiment of the second direction 802, it can be seen that the term " 801 " The logic circuit unit 325 may include an input terminal to which a control signal SHL for controlling the application direction of the gate signal is inputted. The SHL in FIG. 9 indicates an input control signal and also indicates an input terminal to which a control signal is applied to the logic circuit unit 325.

8 and 9, the input / output direction of the input / output control unit is determined by an input control signal SHL. Therefore, all of the gate drive ICs disposed on one side of the display device can be equally applied with the control signal. On the other hand, the gate drive ICs disposed on both sides of the display device receive the control signal in a divided state. The control signal of the gate drive IC may be set during the process of coupling the god driver IC to the display device so as to be semi-permanently set in the display device.

The above-described control signal allows the gaudy drive IC to have the same configuration regardless of the side of the display device, and only the value of the control signal can be set differently, so that the circuit of the gaudy drive IC can be designed in the same manner. In addition, when the gate drive IC is mass-produced, the production cost can be reduced according to the same circuit configuration.

10 is a view showing a configuration of a gate COF according to an embodiment of the present invention. In FIG. 10, the signal input / output pads 1015 and 1025 may be arranged so that the signal lines are connected to the input / output pads 815 and 825 of the gate drive IC. Meanwhile, the power line may be applied to the logic circuit portion 325 of FIG. 8 or 8 described above, and the power line terminals 1050a and 1050b may be electrically connected to the logic circuit portion 325 of the gate drive IC . The power line of FIG. 10 may be comprised of one or more power lines. The COF pads 1030a and 1030b of the gate COF may be selectively arranged.

11 is a view showing a configuration of a gate drive IC corresponding to the gate COF of FIG. The power line terminals 1150a and 1150b of the logic circuit portion 325 are arranged in the configuration of Fig. 8 or Fig. Power line terminals 1150a and 1150b of the logic circuit portion of FIG. 11 are connected to the power line terminals 1050a and 1050b of the gate COF of FIG. 10 to apply VGH or VGL.

12 is a view showing a configuration of a gate COF according to another embodiment of the present invention. In FIG. 6, the VGH / VGL drops during the operation of the gate drive IC due to the resistance component and the LOG resistance component of each channel in the power routing, thereby causing an output dip. To prevent this, the power line can be extended like 1210 to reduce the resistance.

The power lines may be connected to the COF pads 1030a and 1030b to reduce the output dip by arranging the resistors in parallel to the power lines. Since the VGH / VGL is applied to the COF pad in the same configuration as the gate COF of FIG. 12, it can be used as a power line terminal.

13 is a view showing a configuration of a gate drive IC according to another embodiment of the present invention. The configuration of the gate drive IC in Fig. 13 is an embodiment in which power is applied to the logic circuit portion 325 through the COF pads 1030a and 1030b in the same configuration as the gate COF in Fig. The power line pads 830a and 830b of the gate drive IC may be electrically connected to the logic circuit portion 325 as shown at 1310 to apply power such as VGH or VGL.

12 and 13 are summarized as follows. The VGH and VGL applied to the gate COF are formed such that a signal line to which VGH and VGL are applied between the COF pads 1030a and 1030b so as to constitute a parallel resistor in order to eliminate an output dip phenomenon due to film resistance and chip resistance, Can be extended. The COF pads 1030a and 1030b of the gate COF are in electrical contact with the power line pads of the gate drive IC and can apply power to the gate drive IC. In another embodiment, the VGH and VGL applied to the COF pads 1030a and 1030b may only supply power to other adjacent gate COFs and the role of supplying VGH and VGL to the gate drive IC may be controlled by power line terminals 1050a, 1050b. This can be variously configured depending on the implementation method and the configuration of the parallel resistance of the power line.

FIG. 14 is a diagram comparing a case where resistors are arranged on a gate COF according to an embodiment of the present invention and a case where a resistor is not disposed on the gate COF. 1401 shows the relationship of the resistance between the gate COF 1491 and the gate COF 1491 in a conventional configuration in which no resistance is placed on the gate COF 1491. 1402 shows the relationship of the resistance in the gate COF 1492 or between the gate COF 1492. The embodiment in which the resistors 1420a and 1420b are disposed on the gate COF 1492 reflects the configuration of FIG. 12 according to the present invention. 14, PAD_L and PAD_R indicate power line terminals on the gate COF 1492, respectively. The power line terminals 1450a and 1450b of 1402 correspond to the power line terminals 1050a and 1050b of FIG.

In FIG. 14, since the pattern resistances on the respective gate COFs and the resistances of ch1-30 and ch432-403 are parallel to each other, the internal total resistance value decreases (pattern resistance <ch1-30, ch432-403 resistance). Therefore, as the internal resistance value of the gate drive IC decreases, the resistance of the LOG plus the IC resistance decreases, thereby reducing the output dip.

FIG. 15 is a graph showing a decrease in slew of an input signal in a gate drive IC when the present invention is applied. The timing controller 140 transfers the input signal to the IC # 1 800n through the IC # n (800a), IC # n-1 (800b), etc. which are gate drive ICs. The configuration of the gate drive IC has been described above with reference to FIG. Each signal is applied to the gate drive IC and passes through the input / output control units 810 and 820 in the gate drive IC. In this process, since the input signal is buffered through the input / output control units 810 and 820, the slew phenomenon disappears. Therefore, even if the LOG resistance is generated as in 1501, the LOG resistance is not accumulated.

That is, since the input signal is buffered and amplified in the gate drive IC through the input / output control units 810 and 820, the resistance exists only in the LOG resistance between the gate and the COF, and since this resistance also eliminates slew through buffering and amplification, Is maintained until the last gate drive IC 800n.

16 is a view showing a state in which the output dip is improved when the present invention is applied. Conventionally, as shown in FIG. 6, VGH applied as in 1601 drops as 610 due to LOG resistance and chip resistance. As a result, the signal generated by the timing controller is 625, but due to the drop of VGH, the actual signal is slewed like 620. However, when the present invention is applied, the drop range of VGH becomes as small as 1610, and as a result, it is confirmed that the slew is improved as in 1620.

17 is a diagram showing timing accuracy due to slew improvement when the present invention is applied. In FIG. 17, reference numeral 1701 denotes the conventional slew state shown in FIG. There is a large difference between the timing 755 of the timing controller and the timing 750 when the actual input signal rises to a certain level. On the other hand, when the present invention is applied, since the input signal is amplified by the gate drive IC, the difference between the timing 1755 of the timing controller 1720 and the timing 1750 when the actual input signal rises to a certain level, such as 1720 of 1702, Rise.

In the case of applying the present invention, the signal input from the gate drive integrated circuit is amplified to suppress slew occurrence. In addition, it is possible to improve the output dipping phenomenon and control the timing of the input signal to operate correctly. To this end, the gate drive integrated circuit of the present invention allows input / output control of a wiring to which a gate signal is applied so as to amplify a signal and control the directionality of the signal. Also, the wiring can be extended to reduce the resistance of VGH and VGL to the gate drive IC and gate COF. To this end, the gate drive IC may further include a power line pad, and the gate COF at the corresponding location may further include a COF pad to which VGH and VGL are applied.

In an embodiment of the present invention, the power line terminal for applying power to the gate drive IC and the power line pad described above may be configured separately or may be constituted by one. This can be applied variously in relation to the gate drive IC and the gate COF.

Further, the gate drive IC can receive a control signal for controlling the direction of the above-mentioned signal from the timing controller, and the above-mentioned SHL becomes one embodiment of the control signal.

When the present invention is applied, the gate driver IC or gate drive ICs constituting the gate driver and the gate COF and the LOG resistance inherent in the gate COF and the output slew of the signal due to the wiring resistance or the output dip of the signal are removed, can do.

In particular, the input / output control unit of the gate drive IC can perform both a role of receiving a signal and a function of outputting a signal according to the control. Therefore, when the gate drive IC is positioned on both sides of the display panel, . In this case, one type of gate drive IC can be connected to the display panels on both sides, thereby reducing the design and production cost of the gate drive IC and enabling the production of a general purpose gate drive IC.

Also, if power line pads are provided separately at the gate COF, power is connected in parallel at the gate drive IC and the gate COF, power is connected at the gate drive IC even when power is lost in the gate COF. . In addition, since the power is connected in parallel, the resistance can be reduced and the output dip phenomenon can be reduced.

When the embodiment of the present invention is applied, the input signal pad of the gate drive IC can be converted to I / O. In addition, the side dummy pad on the side of the gate drive IC can be configured as a high voltage VGH / VGL power line pad to improve the input signal slew and improve the output dip .

When the present invention is applied, unlike a conventional input signal pad, even when an input signal is applied to a gate drive IC located far away from the timing controller, the signal is amplified so as to overcome the LOG resistance component, have.

In addition, when the present invention is applied, the power routing resistance inside the gate drive IC and the LOG resistance component can be reduced by the COF pad disposed at the gate COF. That is, when the above-mentioned COF pad is disposed in the gate COF and used as a VGH / VGL power pad, the power routing resistance in the gate drive IC can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: display device
110: Panel
120: gate driver
130: Data driver
140: Timing controller
800: Gate drive integrated circuit
810 and 820: Input /

Claims (12)

A first input / output control unit and a second input / output control unit electrically connected to a wiring to which a gate signal including a gate start signal and a gate clock is applied; And
And a logic circuit section for applying a gate signal applied from the first input / output control section or the second input / output control section to a gate line of the display panel.
The method according to claim 1,
Wherein the first input / output control unit and the second input / output control unit apply the gate signal in a first direction or a second direction.
3. The method of claim 2,
Wherein the logic circuit section further comprises an input terminal to which a control signal for controlling the application direction of the gate signal is inputted.
The method according to claim 1,
Wherein the input / output control section includes an N-MOS transistor and a P-MOS transistor.
The method according to claim 1,
Wherein the gate drive integrated circuit further comprises at least one of a power line pad or a power line terminal receiving VGH and VGL.
6. The method of claim 5,
The gate COF coupled to the gate drive integrated circuit has a signal line to which VGH and VGL are applied, extended to the COF pad,
Wherein the power line pad of the gate drive integrated circuit is in electrical contact with the COF pad.
A display panel in which gate lines and data lines cross each other; And
A gate driver including a plurality of gate drive integrated circuits for applying a signal to the gate line, a data driver for applying a signal to the data line, and a timing controller for controlling the gate driver and the data driver As a result,
The gate drive integrated circuit
A first input / output control unit and a second input / output control unit electrically connected to a wiring to which a gate signal including a gate start signal and a gate clock is applied; And
And a logic circuit section for applying a gate signal applied from the first input / output control section or the second input / output control section to a gate line of the display panel.
8. The method of claim 7,
Wherein the first input / output control unit and the second input / output control unit apply the gate signal in a first direction or a second direction.
9. The method of claim 8,
Wherein the logic circuit section further comprises an input terminal to which a control signal for controlling the application direction of the gate signal is input.
8. The method of claim 7,
Wherein the input / output control section includes an N-MOS transistor and a P-MOS transistor.
8. The method of claim 7,
Wherein the gate drive integrated circuit further comprises at least one of a power line pad or a power line terminal to which VGH and VGL are applied.
12. The method of claim 11,
A gate COF coupled to the gate drive integrated circuit is coupled to the display panel,
In the gate COF, signal lines to which VGH and VGL are applied extend to the COF pad,
Wherein the power line pad of the gate drive integrated circuit is in electrical contact with the COF pad.

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