KR100973805B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, comprising: a plurality of gate lines, a plurality of data lines, and a liquid crystal panel assembly including a plurality of pixels connected to the gate line and the data line and arranged in a matrix form, the gate line A gate driver for turning on / off a switching device included in the pixel by applying a gate on / off voltage, and receiving a common voltage and a first voltage fed back from the liquid crystal panel assembly as an input and inverting and amplifying the feedback common voltage. And a power compensation circuit for generating a second voltage and applying the same to the gate driver, wherein the gate driver receives the second voltage and operates the second voltage. According to the present invention, a stable power supply voltage can be applied to the gate driver.

Liquid crystal display, gate driver IC, operational amplifier, common voltage, gate driver IC power supply voltage, coupling

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 illustrates a liquid crystal display according to another exemplary embodiment of the present invention.

4 is a waveform diagram illustrating a conventional gate driving IC power supply voltage and a gate driving IC power supply voltage of a liquid crystal display according to another exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly to a liquid crystal display including a circuit for stabilizing a power supply voltage of a gate drive integrated circuit (IC).

A general liquid crystal display device includes two display panels and a liquid crystal layer having dielectric anisotropy interposed therebetween. The desired image is obtained by applying an electric field to the liquid crystal layer and adjusting the intensity of the electric field to adjust the transmittance of light passing through the liquid crystal layer. Such liquid crystal displays are typical among portable flat panel displays (FPDs) that are easy to carry. Among them, TFT-LCDs using thin film transistors (TFTs) as switching elements are mainly used.

In general, a plurality of display signal lines, that is, gate lines and data lines, are formed on a display panel on which thin film transistors are formed, and a plurality of thin film transistors and pixel electrodes are formed on a matrix pixel area defined by intersections of gate lines and data lines. have. The thin film transistor controls the data signal transmitted by the data driver integrated circuit through the data line and transmits the data signal to the pixel electrode according to the gate signal transmitted by the gate driver integrated circuit through the gate line.

A technology for mounting the gate driving integrated circuit and the data driving integrated circuit in a liquid crystal display device includes a tape automated bonding (TAB) mounting method, which is used for gates in which electrical signals are transmitted from the outside to the upper and left sides of the thin film transistor array substrate. Printed circuit board (PCB) and printed circuit board for data are arranged, and each PCB board is equipped with a drive IC that converts electrical signals into scan signals and data signals and outputs them to pads and wiring, respectively. The liquid crystal panel assembly is connected to the liquid crystal panel assembly by a tape carrier package (TCP).

Meanwhile, another method may be a chip on glass (COG) mounting method, in which a driving IC in the form of a semiconductor package is directly mounted on a liquid crystal panel assembly to transmit an electrical signal to the liquid crystal panel assembly.

In the above manner, when the gate driver IC is connected to the liquid crystal panel by TCP or directly mounted on the liquid crystal panel assembly without the PCB for the gate, the wiring for the power voltage and the control signals transmitted to the gate driver IC is connected to the liquid crystal panel. Via the assembly. The wiring via the liquid crystal panel assembly has a resistance component. When a power supply and a control signal are applied to the gate driving IC through the wiring, the gate power supply voltage is affected to reduce the screen quality of the liquid crystal display.

In particular, in driving a liquid crystal panel assembly having such a structure, the gate-off voltage V _off is distorted due to coupling by the slew rate of the gate driving IC in a pattern where white / black intersects between adjacent pixels. causing the coupling to the power supply voltage of the gate drive IC _(dd GV) is causing a drop of the gate drive IC power supply voltage (GV _dd). The drop of the gate driving IC power supply voltage GV _dd causes a malfunction of the gate driving IC, resulting in a defective block-type noise of the gate driving IC.

Accordingly, an aspect of the present invention is to provide a liquid crystal display device which stabilizes a power supply voltage of a gate driving IC by returning a common voltage to the power supply voltage of the gate driving IC and applying the same to the gate driving IC.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines and arranged in a matrix form. A liquid crystal panel assembly; a gate driver configured to apply a gate on / off voltage to the gate line to turn on / off a switching element included in the pixel; and a common voltage and a first voltage fed back from the liquid crystal panel assembly. And a power compensation circuit for inverting and amplifying the feedback common voltage to generate a second voltage added to the first voltage and applying the same to the gate driver, wherein the gate driver operates by receiving the second voltage.

The power compensation circuit may include a capacitor having one terminal connected to the feedback common voltage input, a first resistor having one terminal connected to the other terminal of the capacitor, and an inverting terminal connected to the other terminal of the first resistor. An operational amplifier having a non-inverting terminal connected to the first voltage and outputting the second voltage through an output terminal, and a second resistor connected between the other terminal of the first resistor and an output terminal of the operational amplifier. It is desirable to.

A wiring between an output terminal of the power compensation circuit and a power input terminal of the gate driver may pass through the liquid crystal panel assembly.

The gate driver may include a plurality of integrated circuits, and the integrated circuits may be directly mounted on the liquid crystal panel assembly.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel of a liquid crystal display device according to an embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 includes a plurality of display signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels connected to the plurality of display signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. .

The display signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a data signal line or data for transmitting a data signal. Line D ₁ -D _m . The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel includes a switching element Q connected to a display signal line G ₁ -G _n , D ₁ -D _m , and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected thereto. It includes. The holding capacitor C _ST can be omitted as necessary.

The switching element Q is provided on the lower panel 100, and the control terminal and the input terminal are connected to the gate line G ₁ -G _n and the data line D ₁ -D _m, respectively. The output terminal is connected to the liquid crystal capacitor C _LC and the storage capacitor C _ST .

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives a common voltage V _com . Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be linear or rod-shaped.

The storage capacitor C _ST is formed by overlapping a separate signal line (not shown) and the pixel electrode 190 provided on the lower panel 100, and a predetermined voltage such as a common voltage V _com is applied to the separate signal line. Is approved. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

Meanwhile, in order to implement color display, each pixel must display color, which is possible by providing a red, green, or blue color filter 230 in a region corresponding to the pixel electrode 190. In FIG. 2, the color filter 230 is formed in a corresponding region of the upper panel 200. Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the liquid crystal panel assembly 300.

The gray voltage generator 800 generates two sets of gray voltages related to the transmittance of the pixel. One of the two sets has a positive value for the common voltage (V _com ) and the other set has a negative value.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the liquid crystal panel assembly 300 to receive a gate signal formed by a combination of a gate on voltage V _on and a gate off voltage V _off from the outside. It is applied to the gate lines G ₁ -G _n and usually consists of a plurality of integrated circuits.

The data driver 500 is connected to the data lines D ₁ -Dm of the liquid crystal panel assembly 300 to select the gray voltage from the gray voltage generator 800 and apply the gray voltage to the pixel as a data signal. It consists of a circuit.

A plurality of gate drive integrated circuits or data drive integrated circuits may be mounted in a tape carrier package (TCP) (not shown) to attach TCP to the liquid crystal panel assembly 300, or to integrate these onto a glass substrate without using TCP. Circuits may be directly attached (chip on glass, COG mounting method), and circuits performing the same functions as those integrated circuits may be directly mounted on the liquid crystal panel assembly 300.

The signal controller 600 generates control signals for controlling operations of the gate driver 400 and the data driver 500, and provides the corresponding control signals to the gate driver 400 and the data driver 500.

Next, the display operation of the liquid crystal display will be described in more detail.

The signal controller 600 inputs an input control signal for controlling the RGB image signals R, G, and B and their display from an external graphic controller (not shown), for example, a vertical sync signal V _sync and a horizontal sync signal. (H _sync ), a main clock (MCLK), a data enable signal (DE) is provided. The signal controller 600 properly processes the image signals R, G, and B according to the operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate control signal. After generating the CONT1 and the data control signal CONT2 and the like, the gate control signal CONT1 is sent to the gate driver 400 and the data control signal CONT2 and the processed image signals R ', G', and B 'are processed. ) Is sent to the data driver 500.

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal), a gate clock signal CPV for controlling the output timing of the gate-on pulse, and a gate-on pulse. And an output enable signal OE that defines the width of the signal.

The data control signal CONT2 is a load for applying a corresponding data voltage to the horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B 'and the data lines D ₁ -D _m . Signal LOAD, inverted signal RVS and data that inverts the polarity of the data voltage with respect to common voltage V _com (hereinafter referred to as " polarity of data voltage " by reducing " polarity of data voltage with respect to common voltage "). Clock signal HCLK and the like.

The data driver 500 sequentially receives image data R ′, G ′, and B ′ corresponding to one row of pixels according to the data control signal CONT2 from the signal controller 600, and generates a gray voltage generator ( The image data R ', G', B 'is converted into the corresponding data voltage by selecting the gray voltage corresponding to each of the image data R', G ', and B' among the gray voltages from the 800.

The gate driver 400 applies the gate-on voltage V _on to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n. Turn on the switching element (Q) connected to.

The gate-on voltage V _on is applied to one gate line G ₁ -G _n so that a row of switching elements Q connected thereto is turned on (this period is "1H" or "1 horizontal period). (horizontal period) "and equal to one period of the horizontal sync signal Hsync, the data enable signal DE, and the gate clock CPV], and the data driver 500 converts each data voltage to a corresponding data line D. ₁ -D _m ). The data voltage supplied to the data lines D ₁ -D _m is applied to the corresponding pixel through the turned-on switching element Q.

In this manner, the gate-on voltages V _{on are} sequentially applied to all the gate lines G ₁ -G _n during one frame to apply data voltages to all the pixels. At the end of one frame, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel is opposite to that of the previous frame ("frame inversion). "). In this case, the polarity of the data voltage flowing through one data line may be changed (“line inversion”) within one frame or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS ( "Dot reversal").

Next, the structure of the liquid crystal display according to the present invention will be described in detail with reference to FIG. 3.

3 illustrates a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIG. 3, the gate driver 400 of the liquid crystal display according to the exemplary embodiment of the present invention is a plurality of gate driver ICs 440, and the data driver 500 is a plurality of data driver ICs 540. Is made of.                     

As described above, the liquid crystal display according to the present invention does not have a PCB for the gate, so that the wiring for the power voltage and the control signals transmitted to the gate driving IC 440 is passed through the liquid crystal panel assembly 300 and the liquid crystal panel assembly 300. The wiring via) has a resistance component R _L. When the power supply voltage and the control signal are applied to the gate driving IC 440 through the wiring, the gate power supply voltage is affected by the resistance component R _L.

In the liquid crystal display according to the present exemplary embodiment, the common voltage FV _com fed back from the liquid crystal panel assembly 300 and the power supply voltage GV _{dd to} be applied to the gate driving IC 440 are inputted, inverted and amplified, and then the output voltage GV. _dd ′) to the gate driving IC 440.

The power compensation circuit 40 includes a capacitor C, two resistors R1 and R2, and an operational amplifier 50. One terminal of the capacitor C is connected to the common voltage FV _com fed back from the liquid crystal panel assembly 300, and the other terminal is connected to one terminal of the first resistor R1. The inverting terminal of the operational amplifier 50 is connected to the other terminal of the first resistor R1, the non-inverting terminal is connected to the gate driving IC power supply voltage GV _dd , and the output terminal is the power supply of the gate driving IC 440. It is connected to the input terminal. The second resistor is connected between the other terminal of the first resistor and the output terminal of the operational amplifier.

Wiring between the output terminal of the operational amplifier 50 and the power input terminal of the gate driving IC 440 is via the liquid crystal panel assembly 300. The gate driving IC 440 operates by applying the output voltage GV _dd ′ from the operational amplifier 50 through the wiring via the liquid crystal panel assembly 300.

The fed back common voltage FV _com is inverted and amplified by the operational amplifier 50 and added to the gate driving IC power supply voltage GV _dd . Since the common voltage (V _com ), the gate off voltage (V _off ), and the gate driving IC power supply voltage (GV _dd ) all swing in the same phase, the waveform obtained by inverting and amplifying the fed back common voltage (FV _com ) is gate driven. The waveform of the IC power supply voltage GV _dd becomes a symmetrical waveform with respect to the time axis. Therefore, it is a sense of distortion of the waveform of gate drive IC power supply voltage (GV _dd), the common voltage (FV _com) an inverting amplifier adding a wave gate drive IC power supply voltage (GV _dd) fed back to the waveform of.

4 is a waveform diagram illustrating a conventional gate driving IC power supply voltage GV _dd and a gate driving IC power supply voltage GV _dd 'of a liquid crystal display according to another exemplary embodiment of the present invention. The waveform at the top of FIG. 4 is the waveform of the conventional gate driving IC power supply voltage GV _dd , and the waveform at the bottom of FIG. 4 is the gate driving IC power supply voltage GV _dd 'of the liquid crystal display according to another exemplary embodiment of the present invention. ) Waveform.

As shown in FIG. 4 and Table 1 below, the difference ΔV between the maximum value and the minimum value of the gate driving IC power supply voltage GV _dd in the conventional liquid crystal display device is 4.28V, and the minimum value V (min) is 0.9V. to be. In contrast, as shown in FIG. 4B, the difference ΔV between the maximum value and the minimum value of the gate driving IC power supply voltage GV _dd 'in the liquid crystal display according to the present invention is 3.60V, and the minimum value V (min) is 1.1V. .

Conventional GV _dd GV _dd 'according to the present invention ΔV 4.28 V 3.60V V (min) 0.9 V 1.1 V

The power supply voltage (GV _dd ') applied to the gate driving IC according to the present invention has a smaller ΔV and a larger V (min) than the conventional gate driving IC power supply voltage, thereby improving voltage drop and slew rate, and margin for power. This will increase.

Therefore, according to the present invention, a more stable gate driving IC power supply voltage can be applied as compared with the conventional gate driving IC power supply voltage, thereby further improving the screen quality of the liquid crystal display.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

In this way, the common voltage fed back from the liquid crystal panel assembly is inverted and amplified to the power source voltage to be applied to the gate driving IC, and the voltage added to the gate driving IC is applied to drop the gate driving IC power supply voltage by the wiring via the liquid crystal panel assembly. It is possible to reduce, thereby improving the screen quality of the liquid crystal display.

Claims (4)

A liquid crystal panel assembly comprising a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the gate lines and the data lines, respectively, and arranged in a matrix form; A gate driver to turn on / off a switching device included in the pixel by applying a gate on / off voltage to the gate line; The feedback common voltage and the power supply voltage for the first gate driving IC are input from the liquid crystal panel assembly to invert and amplify the feedback common voltage to generate a power supply voltage for the second gate driving IC in addition to the power supply voltage for the first gate driving IC. Power compensation circuit applied to the gate driver Including; And the gate driver is configured to receive a power supply voltage for the second gate driver IC. In claim 1, The power compensation circuit may include a capacitor having one terminal connected to the feedback common voltage input, a first resistor having one terminal connected to the other terminal of the capacitor, and an inverting terminal connected to the other terminal of the first resistor. An operational amplifier having a non-inverting terminal connected to the power supply voltage for the first gate driving IC and outputting a power supply voltage for the second gate driving IC through an output terminal, and an output terminal of the first resistor other terminal and the operational amplifier; A liquid crystal display device comprising a second resistor connected therebetween. The method of claim 1 or 2, And a wire between an output terminal of the power compensation circuit and a power input terminal of the gate driver is via the liquid crystal panel assembly. The method of claim 1 or 2, The gate driver includes a plurality of integrated circuits, and the integrated circuits are mounted directly on the liquid crystal panel assembly.

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