KR20080049371A - Scan drive chip and liquid crystal display device including the same - Google Patents

Abstract

A scan drive IC and an LCD(Liquid Crystal Display) module including the same are provided to prevent the damage of the scan drive IC and an LCD panel by controlling individually driving voltages and control signals. A scan drive IC(Integrated Circuit) includes a scan circuit, signal inputting pins(SIP1-SIP7), signal delivering pins(STP1-STP7), control switches, and a delivery option pin(TOP). The scan circuit outputs plural scan signals having enable pulses through plural outputting pins. The signal inputting pins receive driving voltages and control signals required for the scan circuit from outside. The signal delivering pins deliver the driving voltages and control signals from the signal inputting pins and signals from the scan circuit to outside. The control switches switch the driving voltages, the control signals, and the scan signals to be supplied to the signal delivering pins. The delivery option pin receives a delivery control signal to be supplied to a control terminal of the control switches.

Description

Scan Drive Chip and Liquid Crystal Display Device Including the same}

1 is a diagram schematically showing a liquid crystal display module of a typical LOG type.

2 is a circuit diagram schematically illustrating a scan drive chip according to an embodiment of the present invention.

3 is a block diagram schematically illustrating a LOG type liquid crystal display module according to an embodiment of the present invention.

4 is a detailed circuit diagram illustrating an example of the chip output controllers illustrated in FIG. 3.

5A and 5B are detailed circuit diagrams illustrating another example of the signal transfer controller illustrated in FIG. 3.

≪A brief description of the main parts of the drawings≫

10,30: liquid crystal panel

12A ~ 12C, 32A ~ 32C: Gate Drive Chip

14A ~ 14C, 34A ~ 34C: Data Drive Chip

16,36: Timing Controller

18,38: TCP

20: shift register

22: buffer array

40A to 40C: first to third signal transmission controllers

SIP1 to SIP7: first to seventh signal input pins

STP1 to STP7: first to seventh signal transmission pins

SW1 to SW7: first to eighth control switches

SSW: Selector Switch

TOP: Delivery Option Pin

The present invention relates to a drive chip for driving pixels on a flat panel display panel, and more particularly, to a scan drive chip mounted on a flat panel display panel. In addition, the present invention relates to a liquid crystal display module having a scan driver chip mounted on a liquid crystal panel.

A flat display panel such as a liquid crystal panel, a plasma display panel, an electroluminescent display panel, and the like includes pixels formed in unit areas separated by scan lines and data lines, respectively. Accordingly, the flat panel display panel can increase the size of the screen beyond the limit while maintaining a thin thickness. In fact, flat panel displays provide a large screen with a significantly thinner thickness than a cathode ray tube, which is a conventional display device. In other words, the flat panel display panel enables a slim and light weight display module.

The flat panel display module drives (or enables) the pixels on the flat panel display panel by line by using scan driver chips. In addition, the flat panel display module includes source driver chips that supply pixel data signals on data lines whenever pixels of any one line on the flat panel display panel are enabled. These scan drive chips and source drive chips were mounted on a wiring film or printed circuit board called a Tape Carrage Package (hereinafter referred to as "TCP") rather than a flat panel display panel. For this reason, in the existing flat panel display module, not only the driving circuit board to be connected to the flat panel display panel but also the connection wiring therebetween are complicated and the manufacturing process is complicated.

In order to solve this disadvantage, the wiring for the driving circuit is further formed on the flat panel display panel. The wiring for the drive circuit allows the scan drive chips and the source drive chips to be mounted on the flat panel display panel, thereby simplifying the connection wiring to the drive circuit board and the flat panel display panel therefrom.

In fact, the liquid crystal display module as shown in FIG. 1 includes first to third scan drive chips 12A to 12C mounted on the left edge of the liquid crystal panel 10. The first to third scan drive chips 12A to 12C are serially connected to the TCP 18 by the first to third scan wires SCW1 to SCW3. The first scan drive chip 12A receives the driving voltages and the scan control signals supplied from the driving circuit board 16 via the TCP 16 and the first scan wiring SCW1 to the second scan wiring SCW2. Through the second scan drive chip 12B. In addition, the first scan driver 12A sequentially sequentially scans the j scan lines GL1 to GLj allocated to each other by the driving voltages and the scan control signals (for example, the period of the horizontal synchronization signal). Enable. Further, the first scan drive chip 12A supplies the carry signal as the shifted start pulse to the second scan drive chip 12B via the second scan wiring SCW2.

The second scan drive chip 12B receives the driving voltages and the scan control signals supplied from the first scan drive chip 12A via the second scan wire SCW2 through the third scan wire SCW3. 3 Scan drive chip 12C. According to the driving voltages and the scan control signals from the first scan driver chip 12A, the second scan driver chip 12B selects j scan lines GL (j + 1) to GL2j allocated thereto. It is enabled sequentially by a certain period (for example, the period of a horizontal synchronizing signal). In addition, the second scan drive chip 12B supplies the carry signal to the third scan drive chip 12C via the third scan wiring SCW3 as a shifted start pulse.

The third scan driver chip 12C also has j scan lines GL (2j + 1) to GL3j allocated to itself by driving voltages and scan control signals from the second scan drive chip 12B. Is sequentially enabled by a predetermined period (for example, a period of a horizontal synchronization signal). In addition, the third scan drive chip 12C outputs the drive voltage and scan control signals from the second scan drive chip 12B through its output terminals together with a carry signal that can be used as a shifted start pulse. do.

In addition, the flat panel display module includes first to third source drive chips 14A to 14C arranged at an upper edge of the liquid crystal panel 10. The first to third source drive chips 14A to 14C are serially connected to the TCP 18 by the first to third source wirings SOW1 to SOW3. Each of the first to third source drive chips 14A to 14C sequentially inputs 3k pixel data supplied in a stream form from the driving circuit board 16 via the TCP 18 by TCP, and then k in analog form. To pixel data signals. In addition, each of the first to third source drive chips 14A to 14C simultaneously supplies the converted k pixel data signals to k data lines allocated to the same. To this end, the first source drive chip 14A removes the pixel data stream, the driving voltages and the source control signals inputted from the driving circuit board 16 via the TCP 18 and the first source wiring SOW1. 2 is supplied to the second source drive chip 14B via the source wiring SOW2. The second source drive chip 14B receives the pixel data stream, driving voltages, and source control signals inputted from the first source drive chip 14A via the second source wiring SOW2. ) To the third source drive chip 14B. The third source drive chip 14C also sends the pixel data stream, driving voltages and source control signals inputted from the second source drive chip 14B via the third source wiring SOW3 through its output terminals. do.

As described above, the scan and source drive chips 12A to 12C and 14A to 14C mounted on the liquid crystal panel 10 are wires for driving circuits (ie, scan and source wires SCW on the liquid crystal panel 10). (SOW)) in series form, driving voltage and control signals are transferred to the transfer output terminals of the last drive chip (i.e., the third scan drive chip 12C and the third source drive chip 14C). It must be. As a result, a shortage between the transfer output terminals of the last drive chip or a defect of the liquid crystal display module (or, flat panel display module) due to the inflow of EOS / ESD into the transfer output terminals of the last drive chip is frequently generated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan drive chip capable of controlling the transfer of driving voltages and control signals.

It is an object of the present invention to provide a liquid crystal display module suitable for minimizing short circuits and defects caused by EOS / ESD.

In accordance with another aspect of the present invention, a scan drive chip includes: a scan circuit unit configured to output a plurality of scan signals having an enable pulse of a predetermined width sequentially shifted through a plurality of output pins; Signal input pins for inputting driving voltages and control signals necessary for the scan circuit unit from an external device; Signal transmission pins for transmitting the driving voltages and control signals from the signal input pins and a signal from the scan circuit unit to the outside; Control switches for switching the drive voltages, the control signals, and the scan signal to be supplied from the signal input pins and the scan circuit portion to the signal transfer pins; And a transmission option pin for inputting a transmission control signal to be supplied to a control terminal of the control switches.

The signal input pins may include: a first signal input pin for inputting a scan start pulse indicating the start of generation of the scan signal; A second signal input pin for inputting a scan clock specifying a shift period of an enable pulse of the scan signal; And third and fourth signal input pins for respectively supplying a supply voltage and a base voltage for operating the scan circuit. The signal transmission pins may include: a first signal transmission pin configured to receive a last scan signal from the scan circuit unit through a corresponding control switch; And second to fourth signal transmission pins respectively connected to corresponding second to fourth signal input pins through corresponding control switches.

A gate start pulse first signal input pin, said signal input pins indicating the start of generation of said scan signal; A second signal input pin for inputting a gate clock specifying a shift period of an enable pulse of the scan signal; Third and fourth signal input pins for supplying a supply voltage and a base voltage for operating the scan circuit unit may be provided. In this case, the signal transfer pins may also include: a first signal transfer pin supplied with the last scan signal via a corresponding control switch from the scan circuit unit; And second to fourth signal transmission pins respectively connected to corresponding second to fourth signal input pins through corresponding control switches.

The signal input pins may further include fifth and sixth signal input pins for respectively inputting a gate high voltage and a gate low voltage for buffering the scan signal by the scan circuit unit, and the signal transfer pins may include the fifth and sixth signal input pins. And fifth and sixth signal transmission pins connected via a control switch corresponding to the sixth signal input pin.

The scan drive chip may further include an option output pin for supplying a common voltage to the pixels to which the plurality of scan signals are supplied. In this case, the signal input pins further include a seventh signal input pin for inputting the common voltage to be supplied to the option output pin from the outside, and the signal transfer pins are connected to the seventh signal input pin through a control switch. And a seventh signaling pin connected thereto.

According to another exemplary embodiment, a liquid crystal display module includes: a liquid crystal panel in which a plurality of gate lines and a plurality of data lines are formed; A data driver for driving the data lines; The gate lines are mounted on the panel to sequentially drive the gate lines for a predetermined period of time, and j scan signals having an enable pulse of a constant width connected to j of the gate lines and sequentially shifted. Signal input pins for inputting j output pins, driving voltages, and control signals for outputting to j of the plurality of output lines; A transmission pin for transmitting the driving voltages and gate control signals and the last scan signal to the outside from the signal input pins, and a transmission for inputting a transfer control signal for controlling a transfer operation of the driving voltages and the control signal; At least two scan drive chips each having an option pin; A printed circuit board controlling the data driver and supplying the driving voltages and the gate control signals required for the gate drive chips to a wiring film electrically contacting the liquid crystal panel; The signal transmission pins of each of the wiring film and at least one scan drive chip on the wiring film side to the adjacent at least two scan drive chips to connect the at least two scan drive chips in series to the wiring film. At least two wiring patterns in electrical connection with the signal input chips; And at least two transfer controllers each generating the transfer control signal to be supplied to the transfer option pin of the corresponding scan drive chip using the drive voltages from the corresponding wiring pattern.

The transfer control unit includes a select switch for supplying a supply voltage and a base voltage on a corresponding wiring pattern to the transfer option pin of a corresponding scan drive chip.

The transfer control unit may include a signal line for transferring any one of a supply voltage and a base voltage on a corresponding wiring pattern to the transfer option pin of a corresponding scan drive chip.

Other objects, other features, and other advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments associated with the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram schematically illustrating a scan drive chip according to an embodiment of the present invention. The scan drive chip illustrated in FIG. 2 is assumed to drive gate lines on the liquid crystal panel for convenience of description. Although the scan drive chip for driving the gate line on the liquid crystal panel is described, those skilled in the art can recognize that the present invention can be modified or changed in various forms without departing from the spirit and scope of the present invention. Could be.

Referring to FIG. 2, the scan drive chip includes signal input pins SIP1 to SIP7 for inputting driving voltages and control signals required for driving the shift register 20 and the buffer array 22, and these signal input pins SIP1. Signal transfer pins STP1 to STP7 respectively corresponding to ˜SIP7 are provided. One of the signal input pins SIP1 to SIP7 (for example, the first signal input pin SIP1 to which a start pulse is input) is connected only to the shift register 20. Similarly, any one of the signal transfer pins STP1 to STP7 (eg, the first signal transfer pin STP1 for transferring a shifted start pulse (ie, a carry signal) to be used as a start pulse) is also used in the shift register 20. Only). Some of the signal input pins SIP1 to SIP7 (for example, the second signal input pin SIP2 for inputting the gate clock GSC for controlling the operation timing of the circuit element) may be connected to the shift register 20 and itself. It is connected to a corresponding signal transfer pin (eg, the second signal transfer pin STP2 for the transfer of the gate clock GSC). The other part of the signal input pins SIP1 to SIP7 (eg, the gate line). The third and fourth signal input pins (SIP3 and SIP4) for inputting the gate high voltage VGH and the gate low voltage VGL for enabling or disabling the VGLs may be buffer arrays 22. ) Is also connected to the corresponding signal transmission pins (e.g., the third and fourth signal transmission pins STP3 and STP4), and another part of the signal input pins SIP1 to SIP7 (e.g., Fifth and sixth signal inputs for supplying a supply voltage Vcc and a ground voltage GND necessary for the operation of a circuit element, respectively. (SIP5, SIP6) are also connected to the shift register 20 and the buffer array 22, and the signal transfer pins STP5 and STP6 corresponding to them, respectively, and further to the signal input pins SIP1 to SIP7. A signal input pin (eg, a seventh signal input pin (SIP7) for inputting a common voltage Vcom used as a reference voltage of the liquid crystal cell) for inputting a voltage of a purpose may be included. ) Additional signal input pin SIP7 corresponds to itself as well as a separate output terminal (e.g., common voltage output terminal VCOP) for outputting common voltage Vcom to the liquid crystal cells on the liquid crystal panel (not shown). Is connected to an additional seventh signal transfer pin STP7, in addition to the seventh signal input pin SIP7 and the seventh signal transfer pin STP7 for the common voltage Vcom; At least one signal input for transmission Pins and signal transfer pins may be provided.

The shift register 20 includes j shift stages driven by the supply voltage Vcc and the ground voltage GND from the fifth and sixth signal input pins SIP5 and SIP6. The shift stages included in the shift register 20 have a gate start pulse, which is another control signal from the first signal input pin SIP1, in response to a gate clock that is one of the control signals from the second signal input pin SIP2. It is shifted from the first shift stage toward the j th shift stage. Accordingly, in each of the j shift stages of the shift register 20, j scanning signals having exclusively enable pulses corresponding to the period of the gate clock are generated. The scanning signal generated in the j-th shift stage of the shift register 20 is also supplied to the first signal transfer pin STP1 as a shifted gate start pulse (ie, a carry signal).

The buffer array 22 includes j buffers corresponding to each of the j shift stages of the shift register 20. All of the j buffers included in the buffer array 22 are driven by the supply voltage Vcc and the ground voltage GND from the fifth and sixth signal input pins SIP5 and SIP6. In addition, all of the j buffers included in the buffer array 22 have corresponding shifts using the gate high voltage VGH and the gate low voltage VGL from the third and fourth signal input pins SIP5 and SIP6. The scanning signal from the shift stage of the register 20 is buffered. The j scanning signals buffered by this buffer array 22 have an enable pulse swinging between the gate high voltage VGH and the gate low voltage VGL. Further, the buffer array 22 carries j buffered scanning signals through j output pins SOP1 to SOPj on j scanning lines on a flat panel (not shown) (ie, j gate lines on a liquid crystal panel not shown). To feed. By the buffered j scanning signals, j scanning lines on the flat panel (ie, j gate lines on a liquid crystal panel not shown) are sequentially enabled for a certain period (ie, horizontal scanning period). do.

According to an exemplary embodiment of the present invention, a scan drive chip includes a first control switch SW1 and second to seventh signal input pins connected between a j-th shift stage of a shift register 20 and a first signal transfer pin STP1. Further provided are second to seventh control switches SW2 to SW7 connected between (SIP2 to SIP7) and the second to seventh signal transmission pins STP2 to STP7. All of the first to seventh control switches SW1 to SW7 are simultaneously switched by the transfer control signal TCS from the transfer option pin TOP. In detail, when the transfer control signal TCS has an enable logic value (eg, high or low logic), all of the first to seventh control switches SW1 to SW7 are turned on. The first signal transfer pin STP1 is connected to the j-th shift stage of the shift register 20 and the second to seventh signal transfer pins STP2 to STP7 correspond to the second to seventh signal input pins SIP2 respectively. To SIP7). Accordingly, the j th scanning signal from the j th shift stage of the shift register 20 is sent out through the first signal transfer pin STP1 as the shifted gate start pulse. In addition, the gate pulse on the second to seventh signal input pins SIP2 to SIP7, the gate high voltage VGH, the gate low voltage VGL, the supply voltage Vcc, the base voltage GND, and the common voltage Vcom. Also transmitted through the corresponding second to seventh signal transmission pin (STP2 ~ STP7). On the contrary, when the transmission control signal TCS has a disable logic value (for example, low or high logic), all of the first to seventh control switches SW1 to SW7 are turned off to be turned off. The first signal transfer pin STP1 is at the jth shift stage of the shift register 20 and the second to seventh signal transfer pins STP2 to STP7 correspond to the second to seventh signal input pins SIP2 to SIP7 respectively. Electrical separation). Accordingly, the j th scanning signal from the j th shift stage of the shift register 20 and the gate pulse on the second to seventh signal input pins SIP2 to SIP7, the gate high voltage VGH, the gate low voltage VGL, The supply voltage Vcc, the base voltage GND, and the common voltage Vcom are not transmitted to the first to seventh signal transfer pins STP2 to STP7.

As such, the driving voltages and the control signals to be transferred toward the signal transfer pins STP1 to STP7 are selectively blocked by the control switches SW1 to SW7 in response to the transfer control signal TCS on the transfer offset pin TOP. Can be. When the signal transfer pins STP1 to STP7 are not used, the signal transfer pins STP1 to STP7 are electrically disconnected so that circuitry (ie, the shift register 20 and the buffer array 22) in the scan drive chip is external. It is not affected by the EOD / ESD from the outside through the poor contact and the signal transmission pins STP1 to STP7. As a result, the scan drive chip according to the embodiment of the present invention can perform a stable operation irrespective of the influence of EOD / ESD through poor contact between the unused signal transmission pins and the unused signal transmission pins.

FIG. 3 is a block diagram schematically illustrating a liquid crystal display module according to an exemplary embodiment of the present invention including the scan drive chip illustrated in FIG. 2. Referring to FIG. 3, a liquid crystal display module according to an exemplary embodiment of the present invention may include first to third scan drive chips 32A to 32C mounted on the left edge of the liquid crystal panel 30, and these first to third scan drives. First to third signal transfer control units 40A to 40C connected to each of the chips 32A to 32C are provided. The first to third scan drive chips 32A to 32C are serially connected to the TCP 38 by the first to third scan wirings SCW1 to SCW3. Each of the first to third scan wirings SCW1 to SCW3 includes signal lines for transmitting driving voltages and scan control signals required for driving the first to third gate drive chips 32A to 32C. The first to third scan wirings SCW1 to SCW3 have a supply voltage Vcc, a base voltage GND, a gate high voltage VGH, a gate low voltage VGL, a gate start pulse GSP, and a gate clock. Signal lines for transmitting (GSC) are included. In addition, when the liquid crystal panel 10 includes liquid crystal cells driven in a lateral electric field method, a signal line for transmitting the common voltage Vcom is additionally included in each of the first to third scan wirings SCW1 to SCW3. Can be. Furthermore, when the first to third scan drive chips 32A to 32C respond to at least two or more clocks, each of the first to third scan wires SCW1 to SCW3 transmits at least one additional gate clock. At least one additional clock signal line may be added.

In the first scan drive chip 32A, drive voltages and scan control from the driver circuit board 36 toward its signal input pins SIP1 to SIP7 via the TCP 38 and the first scan wiring SCW1. Signals are input. In response to the driving voltages and the scan control signals, the first scan drive chip 32A sequentially processes the j gate lines GL1 to GLj allocated thereto sequentially for a predetermined period (for example, one horizontal synchronization signal). Enable period). In addition, the first scan drive chip 32A supplies a common voltage Vcom to liquid crystal cells (not shown) on the j gate lines GL1 to GLj. In addition, the first scan drive chip 32A controls first transfer of an enable logic value (for example, high logic) supplied from the first signal transfer control unit 40A to its transfer option pin TOP. In response to the signal TCS1, the driving voltages and the scan control signals supplied from the first scan wiring SCW1 are connected to the signal transfer pins STP1 to STP7 through the second scan wiring SCW2. Supply to the second scan drive chip 32B. In this case, the gate start pulse GSP supplied from the first scan drive chip 32A to the second scan drive chip 32B through the second scan wire SCW2 is generated in the first scan drive chip 32A. It becomes a carry signal (that is, a j-th scan signal).

The second scan drive chip 32B inputs driving voltages and scan control signals from the first scan drive chip 32A toward its signal input pins SIP1 to SIP7 via the second scan wire SCW2. . According to the driving voltages and the scan control signals, the second scan drive chip 32B sequentially processes the j gate lines GL (j + 1) to GL2j allocated to the second gate drive chip 32B sequentially for a predetermined period (for example, Enable periods of one horizontal synchronization signal). The j + 1 to 2j th gate lines GL (j + 1) to GL2j are sequentially enabled by a period of one horizontal sync signal from the time point at which the j th gate line GLj is disabled. In addition, the second scan drive chip 32B supplies the common voltage Vcom to liquid crystal cells (not shown) on the j gate lines GL (j + 1) to GL2j. In addition, the second scan drive chip 32B has a second transfer control signal of an enable logic value (for example, high logic) supplied from the second signal transfer control unit 40B to its transfer option pin TOP. In response to the TCS2, the driving voltages and the scan control signals supplied from the second scan wiring SCW2 are first connected through the third scan wiring SCW3 connected to the signal transfer pins STP1 to STP7. 3 Scan drive chip 32C. At this time, the gate start pulse GSP supplied from the second scan drive chip 32B to the third scan drive chip 32C through the third scan wiring SCW3 is generated in the second scan drive chip 32C. It becomes a carry signal (that is, a 2j th scan signal).

The third scan drive chip 32C inputs driving voltages and scan control signals from the second scan drive chip 32B toward its signal input pins SIP1 to SIP7 via the third scan wiring SCW3. . According to the driving voltages and the scan control signals, the third scan drive chip 32C sequentially processes the j gate lines GL (2j + 1) to GL3j allocated to the third gate drive chip 32C sequentially for a predetermined period (for example, Enable periods of one horizontal synchronization signal). The 2j + 1 to 3j th gate lines GL (2j + 1) to GL3j are sequentially enabled by a period of one horizontal synchronization signal from the time point at which the 2j th gate line GL2j is disabled. The third scan drive chip 32C supplies the common voltage Vcom to liquid crystal cells (not shown) on the j gate lines GL (2j + 1) to GL3j. In addition, the third scan drive chip 32C controls the third transfer of the disable logic value (for example, low logic) supplied from the third signal transfer control unit 40C to its transfer option pin TOP. In response to the signal TCS3, the driving voltages and the scan control signals supplied from the second scan wiring SCW2 are blocked from appearing on their signal transfer pins STP1 to STP7. In other words, the third scan drive chip 32C causes its signal transfer pins STP1 to STP7 to have a high impedance corresponding to the floating state. Accordingly, the signal transfer pins STP1 to STP7 of the third scan drive chip 32C may be shorted to each other due to external influences, or EOS may be transmitted through the signal transfer pins STP1 to STP7 of the third scan drive chip 32C. Alternatively, even when ESD is introduced, the first and second scan drive chips 32A and 32B as well as the third scan drive chip 32C may operate correctly. As a result, the liquid crystal display module according to the embodiment of the present invention can prevent damage to the scan drive chip and the liquid crystal panel due to poor connection at the signal transmission pin of the last scan drive chip and EOS / EDS.

In addition, the liquid crystal display module according to the embodiment of the present invention includes first to third source drive chips 34A to 34C arranged at an upper edge of the liquid crystal panel 30. The first to third source drive chips 34A to 34C are serially connected to the TCP 38 by the first to third source wirings SOW1 to SOW3. Each of the first to third source drive chips 34A to 34C sequentially inputs 3k pixel data, which are supplied in stream form from the driving circuit board 36 via the TCP 38, by k, in the form of analog. To pixel data signals. In addition, each of the first to third source drive chips 34A to 34C may be configured to allocate the converted k pixel data signals to each of one of the 3j gate lines GL1 to GL3j. Supply to k data lines simultaneously. To this end, the first source drive chip 34A removes the pixel data stream, the driving voltages and the source control signals inputted from the driving circuit board 36 via the TCP 38 and the first source wiring SOW1. It supplies to the 2nd source drive chip 34B via the 2 source wiring SOW2. The second source drive chip 34B receives the pixel data stream, the driving voltages, and the source control signals inputted from the first source drive chip 34A via the second source wiring SOW2. The third source drive chip 34C is supplied via SOW3). The driving circuit board 36 includes a power supply circuit portion for generating driving voltages necessary for the liquid crystal panel 30, the scan drive chips 32A to 32C, and the source drive chips 34A to 34C. In addition, the driving circuit board 36 includes a timing controller for generating control signals for controlling the driving timing of the scan drive chips 32A to 32C and the source drive chips 34A to 34C.

The first to third signal transfer controllers 40A to 40C may be set or reset according to the manufacturer's selection, so that the first to third signal transfer control units 40A to 40C may be configured to be enabled or disabled (ie, high logic) or disabled (ie, low logic). The third transfer control signals TCS1 to TCS3 are generated. The first and second transfer control signals TCS1 and TCS2 may include driving voltages and scan control signals to which the first and second scan drive chips 32A and 32B are input, and the second and third scan drive chips, 32B, 32C), enable logic value. On the other hand, the third transfer control signal TCS3 sets the third scan drive chip 32C such that drive voltages and scan control signals inputted to the signal input pins SIP1 to SIP7 of the third scan driver chip 32C do not appear. To control, it has a disable logic value (eg, low logic).

FIG. 4 is a detailed circuit diagram illustrating an example of the signal transmission controller 40 shown in FIG. 3 in detail. Referring to FIG. 4, the signal transfer controller 40 may include first and second signal lines SL1 and SL2 included in the signal wire SCW of FIG. 3 and a transfer option pin TOP of the scan drive chip 32. And a selector switch (SSW) connected therebetween. The first signal line SL1 is used to transmit the supply voltage Vcc, and the second signal line SL2 is used to transmit the base voltage GND. The selection switch SSW includes a movable contact selectively contacting the first and second selection contacts connected to the first and second signal lines SL1 and SL2, respectively. The movable contact of the selection switch SSW is in contact with the first selection contact connected to the first signal line SL1 or the second selection contact connected to the second signal line SL2 by the manufacturer, thereby providing a high logic or low logic. The transfer control signal TCS is supplied to the transfer option pin TOP of the scan drive chip 32.

5A and 5B are detailed circuit diagrams illustrating another embodiment of the signal transfer control unit 40 of FIG. 3 in detail. 5A illustrates in detail a signal transfer control unit for generating a high logic transfer control signal TCS that can be used as an enable logic value or a disable logic value. On the other hand, FIG. 5B illustrates in detail a signal transfer control unit for generating a transfer logic control signal TCS of a low logic that can be used as a disable logic value or an enable logic value.

Referring to FIG. 5A, the signal transfer control unit 40 may include a first signal line SL of a first signal line SL1 transmitting a supply voltage Vcc and a second signal line SL2 transmitting a base voltage GND. And a transmission control line TCL branched from SL1. The transfer control line TCL branched from the first signal line SL1 transfers the supply voltage Vcc on the first signal line SL1 toward the transfer option pin TOP of the scan drive chip 32, thereby Causes a high logic transfer control signal (TCS) to be generated that can be used as an enable logic value or a disable logic value.

The signal transfer control unit 40 of FIG. 5B includes a first signal line SL1 for transmitting the supply voltage Vcc and a second signal line SL2 among the second signal line SL2 for transmitting the base voltage GND. It has a branched transmission control line (TCL). The transfer control line TCL branched from the second signal line SL1 transfers the base voltage GND on the second signal line SL1 toward the transfer option pin TOP of the scan drive chip 32. Causes a transfer control signal TCS of low logic to be generated that can be used as an enable logic value or an enable logic value.

The signal transfer control unit 40 shown in FIGS. 5A and 5B includes only a signal line branching the supply voltage Vcc or the ground voltage GND, and is simplified in comparison with the signal transfer control unit 40 of FIG. 4. Has

As described above, the scan drive chip according to the present invention selectively blocks the driving voltages and the control signals to be transmitted toward the signal transmission pins by control switches in response to the transmission control signal on the transmission offset pin. If no signaling pins are used, the signaling pins are electrically isolated so that external circuitry connected to the circuitry and output pins in the scan drive chip causes external contact failures and the effects of EOD / ESD from the outside via the signaling pins. Will not receive. As a result, the scan drive chip can perform a stable operation irrespective of a bad contact between unused signal transmission pins and an effect of EOD / ESD through unused signal transmission pins.

In the liquid crystal display module according to an exemplary embodiment of the present disclosure, whether driving voltages and control signals are transmitted to signal transmission pins of each of the scan drive chips connected in series on the liquid crystal panel is provided to the signal transmission controllers corresponding to the scan drive chips. Are controlled individually. Even if the signaling pins of the last scan drive chip are shorted to each other due to external influences or EOS or ESD is introduced through the signaling pins of the last scan drive chip, the last scan drive chip as well as the preceding scan drive chips may operate correctly. Can be. As a result, the liquid crystal display module according to the embodiment of the present invention can prevent damage to the scan drive chip and the liquid crystal panel due to poor connection at the signal transmission pin of the last scan drive chip and EOS / EDS.

As described above, the present invention has been limited to the embodiments shown in the accompanying drawings, which are merely exemplary, and those skilled in the art to which the present invention pertains may have the spirit and scope of the present invention. It will be apparent that various modifications, changes and equivalent other embodiments are possible without departing from the scope of the present invention. For example, in the scan drive chip of the present invention, control switches responsive to a signal on a transfer option pin may also be applied to a source drive chip that needs to selectively switch voltages and signals to be transferred from the signal input pins to the signal transfer pins. It will be appreciated by those of ordinary skill in the art that the present invention pertains. Therefore, the spirit and scope of the present invention to be protected will be defined by the appended claims.

Claims (11)

A scan circuit unit configured to output a plurality of scan signals having an enable pulse of a constant width shifted sequentially through a plurality of output pins; Signal input pins for inputting driving voltages and control signals necessary for the scan circuit unit from an external device; Signal transmission pins for transmitting the driving voltages and control signals from the signal input pins and a signal from the scan circuit unit to the outside; Control switches for switching the drive voltages, the control signals, and the scan signal to be supplied from the signal input pins and the scan circuit portion to the signal transfer pins; And And a transmission option pin for inputting a transmission control signal to be supplied to a control terminal of the control switches. The method of claim 1, Signal input pins: a first signal input pin for inputting a scan start pulse indicative of the onset of generation of the scan signal; A second signal input pin for inputting a scan clock specifying a shift period of an enable pulse of the scan signal; Third and fourth signal input pins for respectively supplying a supply voltage and a base voltage for operating the scan circuit unit; Signal transfer pins include: a first signal transfer pin receiving a last scan signal from the scan circuit via a corresponding control switch; And second to fourth signal transfer pins connected to corresponding second to fourth signal input pins through corresponding control switches, respectively. The method of claim 1, The signal input pins: a gate start pulse first signal input pin indicating the start of generation of the scan signal; A second signal input pin for inputting a gate clock specifying a shift period of an enable pulse of the scan signal; Third and fourth signal input pins for inputting a supply voltage and a base voltage for operating the scan circuit unit, respectively; The signal transmission pins may include: a first signal transmission pin configured to receive a last scan signal from the scan circuit unit through a corresponding control switch; And second to fourth signal transfer pins connected to corresponding second to fourth signal input pins through corresponding control switches, respectively. The method of claim 3, wherein The signal input pins further include fifth and sixth signal input pins for respectively inputting a gate high voltage and a gate low voltage for buffering the scan signal by the scan circuit unit, And the fifth and sixth signal transfer pins, wherein the signal transfer pins are connected via a control switch corresponding to the fifth and sixth signal input pins. The method of claim 4, wherein And an optional output pin for supplying a common voltage to the pixels supplied with the plurality of scan signals, The signal input pins further include a seventh signal input pin for inputting the common voltage to be supplied to the option output pin from the outside, And the seventh signal transfer pin is connected to the seventh signal input pin through a control switch. A liquid crystal panel in which a plurality of gate lines and a plurality of data lines are formed; A data driver for driving the data lines; The gate lines are mounted on the panel to sequentially drive the gate lines for a predetermined period of time, and j scan signals having an enable pulse of a constant width connected to j of the gate lines and sequentially shifted. Signal input pins for inputting j output pins, driving voltages, and control signals for outputting to j of the plurality of output lines; Signal transmission pins for transmitting the driving voltages and gate control signals and the last scan signal to the outside from the signal input pins, and transmission for inputting a transmission control signal for controlling a transfer operation of the driving voltages and the control signal. At least two scan drive chips each having an option pin; A printed circuit board controlling the data driver and supplying the driving voltages and the gate control signals required for the gate drive chips to a wiring film electrically contacting the liquid crystal panel; The signal transmission pins of each of the wiring film and at least one scan drive chip on the wiring film side to the adjacent at least two scan drive chips to connect the at least two scan drive chips in series to the wiring film. At least two wiring patterns in electrical connection with the signal input chips; And And at least two transfer control units each generating the transfer control signal to be supplied to the transfer option pin of the corresponding scan drive chip using the drive voltages from the corresponding wiring pattern. 7. The liquid crystal display module as claimed in claim 6, wherein the transfer control unit includes a selection switch for selectively supplying a supply voltage and a base voltage on a corresponding wiring pattern to the transfer option pin of a corresponding scan drive chip. 7. The liquid crystal display module of claim 6, wherein the transfer control unit comprises a signal line for transmitting any one of a supply voltage and a base voltage on a corresponding wiring pattern to the transfer option pin of a corresponding scan drive chip. The method of claim 6, The signal input pins: a gate start pulse first signal input pin indicating the start of generation of the scan signal; A second signal input pin for inputting a gate clock specifying a shift period of an enable pulse of the scan signal; Third and fourth signal input pins for inputting a supply voltage and a base voltage for operating the scan circuit unit, respectively; The signal transmission pins may include: a first signal transmission pin configured to receive a last scan signal from the scan circuit unit through a corresponding control switch; And second to fourth signal transmission pins connected to corresponding second to fourth signal input pins through corresponding control switches, respectively. The method of claim 9, The signal input pins further include fifth and sixth signal input pins for respectively inputting a gate high voltage and a gate low voltage for buffering the scan signal by the scan circuit unit, And the fifth and sixth signal transfer pins, wherein the signal transfer pins are connected via a control switch corresponding to the fifth and sixth signal input pins. The method of claim 10, Each of the at least two or more scan drive chips further comprises an optional output pin for supplying a common voltage to the pixels to which the j scan signals are to be supplied; The signal input pins further include a seventh signal input pin for inputting the common voltage to be supplied to the option output pin from the outside, And a seventh signal transmission pin, wherein the signal transmission pins are connected to the seventh signal input pin through a control switch.

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