KR102290117B1 - Gate drive integrated circuit and display device comprising thereof - Google Patents

Abstract

The present invention relates to a gate drive integrated circuit and a display device including the same, and to a first input/output controller and a second input/output controller electrically connected to wirings to which a gate signal including a gate start signal and a gate clock is applied, and a first input/output Provided is a gate drive integrated circuit including a logic circuit unit for applying a gate signal applied from a control unit or a second input/output control unit to a gate line of a display panel.

Description

GATE DRIVE INTEGRATED CIRCUIT AND DISPLAY DEVICE COMPRISING THEREOF

The present invention relates to a gate drive integrated circuit and a display device including the same.

A conventional display device includes a panel formed by crossing gate lines and data lines, a gate driver for driving gate lines formed on the panel, a data driver for driving data lines formed on the panel, a gate driver and a data driver and a timing controller for controlling the driving timing of the .

A display panel constituting a liquid crystal display (LCD) or an organic light-emitting diode (OLED) includes a gate driving circuit for supplying scan signals to gate lines and data to data lines. An image is displayed using a data driving circuit that supplies voltage.

On the other hand, in the conventional display device, the gate driver, on the other hand, in the conventional display device, the gate driver sequentially supplies a scan signal to the gate lines and transmits a signal between the gate driving circuits. There is a problem in that a signal is not accurately output from the gate driving circuit due to the physical characteristics inside the driving circuit during the transfer process, which may affect the operation of the entire scan line.

Against this background, it is an object of the present invention to reduce the slew of a gate signal applied to a display device.

Another object of the present invention is to increase the timing accuracy of a gate signal.

In addition, an object of the present invention is to reduce a phenomenon in which a power line is dropped due to a resistance in the process of being applied thereto.

In order to achieve the above object, in one aspect, the present invention provides a first input/output control unit and a second input/output control unit electrically connected to a wiring to which a gate signal including a gate start signal and a gate clock is applied, and a first input/output control unit Alternatively, the present invention provides a gate drive integrated circuit including a logic circuit unit for applying a gate signal applied from the second input/output control unit to a gate line of a display panel.

In addition, the present invention provides a gate drive integrated circuit including a first input/output controller and a second input/output controller for applying a gate signal in a first direction or a second direction.

In addition, the present invention includes a gate driver including a plurality of gate drive integrated circuits for applying a signal to a gate line of a display panel, a data driver for applying a signal to the data line, and a timing controller for controlling the gate driver and the data driver In particular, a first input/output controller and a second input/output controller electrically connected to a wiring to which a gate signal including a gate start signal and a gate clock is applied, and the first input/output controller or the second input/output controller Provided is a display device coupled with a gate drive integrated circuit including a logic circuit unit for applying a gate signal to a gate line of a display panel.

As described above, according to the present invention, there is an effect of controlling the application direction of the gate signal by coupling the input/output controller to the gate drive integrated circuit.

In addition, according to the present invention, since the gate signal is amplified by the input/output controller, there is an effect of reducing distortion such as slew of the gate signal.

In addition, according to the present invention, there is an effect of reducing the resistance of power by arranging a parallel resistor in the gate COF to which the gate drive integrated circuit is coupled.

1 is a schematic system configuration diagram of a display device 100 to which embodiments are applied.
2 is a diagram illustrating generation of a clock signal according to an exemplary embodiment.
3 is a view showing a portion of a display panel to which a plurality of gate drive ICs are connected to which an embodiment of the present invention is applied.
4 is a diagram showing a detailed configuration of a gate drive IC.
FIG. 5 is a diagram showing the configuration of a gate COF coupled to the gate drive IC of FIG. 4 .
6 is a diagram illustrating an output dip phenomenon of VGH/VGL.
7 is a diagram illustrating an input signal applied between gate drive ICs.
8 is a diagram illustrating an internal configuration of a gate drive IC according to an embodiment of the present invention.
9 is a diagram showing a detailed configuration of the input/output control units 810 and 820 according to an embodiment of the present invention.
10 is a view showing the configuration of a gate COF according to an embodiment of the present invention.
11 is a diagram illustrating a configuration of a gate drive IC corresponding to the gate COF of FIG. 10 .
12 is a view showing the configuration of a gate COF according to another embodiment of the present invention.
13 is a diagram showing the configuration of a gate drive IC according to another embodiment of the present invention.
14 is a view comparing a case in which a resistor is disposed on a gate COF according to an embodiment of the present invention and a case in which it is not.
15 is a diagram illustrating a decrease in slew of an input signal in a gate drive IC when the present invention is applied.
16 is a view showing an improved state of the output dip when the present invention is applied.
17 is a diagram showing timing accuracy due to slew improvement when the present invention is applied.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms. When it is described that a component is “connected”, “coupled” or “connected” to another component, the component may be directly connected or connected to the other component, but other components may be interposed between each component. It will be understood that each component may be “interposed” or “connected”, “coupled” or “connected” through another component.

1 is a schematic system configuration diagram of a display device 100 to which embodiments are applied.

Referring to FIG. 1 , a display device 100 to which embodiments are applied includes a panel 110 formed by crossing gate lines GL1 to GLn and data lines DL1 to DLm, and a panel 110 . The gate driver 120 for driving the gate lines formed on the panel 110 , the data driver 130 for driving the data lines formed on the panel 110 , and driving timings of the gate driver 120 and the data driver 130 are controlled and a timing controller 140 and the like.

In the panel 110 , each pixel P is defined by crossing the gate lines GL1 to GLn and the data lines DL1 to DLm.

The gate driver 120 drives the gate lines GL1 to GLn by sequentially supplying scan signals to the gate lines GL1 to GLn. For this purpose, x (x is a natural number greater than or equal to 2) clock signals A scan signal is sequentially supplied to the gate lines GL1 to GLn based on the received input.

The above-mentioned x number of clock signals may be generated by a level shifter. A clock signal generation of such a level shifter will be described with reference to FIG. 2 .

The display device 100 of FIG. 1 may be, for example, a liquid crystal display device or an organic light emitting display device, but is not limited thereto, and includes a panel 110 , a gate driver 120 , a data driver 130 , It may be any type of display device including the timing controller 140 and the like, as long as the gate driver 120 uses a clock signal to drive the gate lines GL1 to GLn. Also, the display device 100 of FIG. 1 may be, for example, a display device of a mobile terminal in which a narrow bezel is the most important factor.

Examples of the gate driving circuit control signal for controlling the gate driving circuit may include a gate start signal VST and a gate clock. These signals are generated by the timing controller 140 and supplied to a plurality of gate drive integrated circuits (ICs) included in the gate driving circuit.

The timing controller 140 may be configured on a source printed circuit board (PCB), and the gate drive integrated circuit (hereinafter, referred to as 'gate drive IC') is connected to the display panel using a tape automated bonding (TAB) method. Alternatively, it may be configured on the display panel in a Chip On Glass (COG) method or may be electrically connected to the display panel in a Chip On Film (COF) method.

The timing controller 140 supplies a gate start pulse through a gate start pulse line GSPL formed on the substrate of the display panel, supplies a gate shift clock through a gate shift clock line GSCL, and a gate output enable signal line Supply the gate output enable signal through (GOEL).

2 is a diagram illustrating generation of a clock signal according to an exemplary embodiment.

Referring to FIG. 2 , the level shifter 200 is based on the clock information CLOCK input from the timing controller 140 and the high level voltage VGH and the low level voltage VGL supplied from the power supply unit 210 . Thus, x number of clock signals CLK 1, CLK 2, CKL 3, CLK 4, ... , CLK x are generated.

The level shifter 200 outputs the x generated clock signals CLK 1 to CLK x to the gate driver 120 driving the x-phase. The level shifter 200, for example, may be included in the data driver 130 or formed on a printed circuit board (PCB) connected through the panel 110 and the data driver 130, It is not limited, and may be formed or located anywhere other than the gate driver 120 .

Meanwhile, the gate driver 120 may include a plurality of gate drive ICs that are formed directly on the panel 110 and sequentially supply scan signals to the gate lines. An embodiment in which the gate drive IC is connected to the display panel through COF will be described.

3 is a view showing a portion of a display panel to which a plurality of gate drive ICs are connected to which an embodiment of the present invention is applied. In FIG. 1 , the timing controller 140 and the data driver 130 are not shown. The gate drive IC 320 is coupled to the film 310 for the COF. Hereinafter, a film on which the gate drive IC 320 is disposed is referred to as a gate COF.

4 is a diagram showing a detailed configuration of a gate drive IC. The gate drive IC 320 includes input signal pads 327a and 327b to which signals are applied from the outside, and a logic circuit unit 325 that performs logic control using the signals of the pads.

The gate drive IC may optionally include dummy pads 321a and 321b, which are formed for functions such as transmitting and receiving signals or applying power to a gate COF on which other adjacent gate drive ICs are disposed. The dummy pads 321a and 321b may be selectively included.

As shown in FIG. 4 , the input signal pads 327a and 327b of the gate drive IC 320 are connected to the pads of other gate drive ICs positioned on the left and right sides, so there is no distinction between input and output.

FIG. 5 is a diagram showing the configuration of a gate COF coupled to the gate drive IC of FIG. 4 . In the gate COF, power lines (VGH/VGL) and an input signal are applied, and the applied signal is applied to the gate drive IC 320 . Area 315 of the gate COF is a portion to which the gate drive IC of FIG. 4 is coupled.

The pads 327a and 327b of the gate drive IC 320 of FIG. 4 are coupled to 317a and 317b of the gate COF 310 to apply a signal. As shown in FIG. 5 , in the routing in the gate COF, an input signal line surrounds a power line as an embodiment. In addition, as shown in FIG. 3 , a plurality of gate COFs are bonded to the display panel, and input signals and power generated by the timing controller are applied to each IC along LOG.

On the other hand, referring to FIGS. 4 and 5, the conventional input signal pad is symmetrical left/right with respect to the center, and is connected between the left and right pads not only inside the gate drive IC but also on the gate COF. It is used as an input pad.

This structure affects the slew because the resistance component of the LOG (Line Of Glass) increases as the input signal goes to the far side. In addition, the IC output output dip phenomenon occurs. The IC internal power routing resistance affects the output dip phenomenon along with the LOG resistance component.

6 is a diagram illustrating an output dip phenomenon of VGH/VGL. VGH/VGL is applied to the gate drive IC side, and one embodiment of VGH is 24V. As for the VGL for turn-off, in an embodiment, -5V to -6V may be applied, and -10V may be applied. When VGH is applied in FIG. 6 , a voltage drop may occur as shown in 610 due to a resistance component or a capacitive load. In addition, an output dip may occur due to this, and a slew may occur in the output signal as shown in 620 . That is, due to the output dip of VGH, a signal that should be output as shown in 625 and a signal in which a slew occurs as shown in 620 are output.

7 is a diagram illustrating an input signal applied between gate drive ICs. In FIG. 7, reference numeral 725 is a signal generated by the timing controller of the control printed circuit board. On the other hand, although an initial signal having a waveform like 725 is applied to a plurality of gate COFs from the timing controller, a signal applied to a gate COF located farthest from the timing controller has a slew as shown in 729 . The reason that the signal applied to the gate drive IC is different depending on the location of the gate drive IC is due to a resistance component or capacitance, and a timing corresponding to a specific signal level may vary due to a slew.

For example, if the time point at which the desired signal level is reached due to the slew is the time point indicated by 750, there is a difference between 750 and the high point 755 of the signal applied from the timing controller, and there are two points (750 and 755). If the difference is out of the error range, the signal output from the gate drive IC is different from the signal originally intended to be output, and thus the gate driving transistor cannot be controlled to properly output the video data of the display panel. As a result, an incorrect video signal may be output from the corresponding scan line.

Therefore, in this specification, a gate drive IC that reinforces the output of a signal that is weakened or distorted due to resistance due to line on glass (LOG), resistance due to wiring, and capacitance load, etc. and gate COF combined with gate drive IC will be examined. see. To this end, we propose a configuration in which the pad of the gate drive IC can perform input/output.

To this end, in this specification, the input signal pad of the gate driving circuit (Gate D-IC) is converted into I/O to improve slew, and to reinforce the high voltage, the IC side (Side) ) to improve the output dip by adding the VGH/VGL pad.

In addition, when the embodiment of the present invention is applied, the LOG resistance component is lowered as the conventional input signal goes to the far side (far side) to prevent slew from occurring. In addition, in order to improve the output dip phenomenon, the input pad can be converted into I/O and the IC side dummy pad can be configured as a VGH/VGL power pad.

8 is a diagram illustrating an internal configuration of a gate drive IC according to an embodiment of the present invention. The gate drive IC 800 includes a logic circuit unit 325 providing a logic circuit for applying a gate signal to the display panel, input/output control units 810 and 820 , and input/output pads 815 and 825 for input/output. . Optionally, power line pads 830a and 830b connected to VGH/VGL may be disposed on the gate drive IC 800 . When power is not applied to the power line pads 830a and 830b, they may operate as dummy pads. In addition, a signal high/low (SHL) for controlling the signal direction of the input/output pads 815 and 825 is applied to the logic circuit unit 325 . SHL uses a shift direction control signal as an embodiment, and determines which input/output pads 815 and 825 serve as input terminals or output terminals.

For example, when SHL is high, the first input/output pad 815 becomes an input pad and the second input/output pad 825 becomes an output pad. Conversely, when SHL is low, the second input/output pad 825 becomes an input pad and the first input/output pad 815 becomes an output pad.

The signal input and output directions are determined according to the SHL, and the input/output controllers 810 and 820 may buffer signals applied from other gate drive ICs adjacent to the gate drive IC 800 . The input/output controllers 810 and 820 may be configured as a combination circuit. A detailed embodiment will be seen in FIG. 9 .

Meanwhile, the power line pads 830a and 830b selectively disposed on the side surface of the gate drive IC and connected to VGH/VGL may be disposed at the same location as the dummy pads 321a and 321b in the configuration of FIG. 4 described above. Also, although not shown in the drawing, the logic circuit unit 325 of the gate drive IC may be connected to the VGH/VGL power line applied from the gate COF. In another embodiment, the power applied from the power line pads 830a and 830b may be connected to the logic circuit unit 325 . A wiring is disposed between the power line pads 830a and 830b of the gate drive IC or the power line terminals 1150a and 1150b of the logic circuit of the gate drive IC of FIG. 11 to be described later to receive power from the gate COF, and at the same time the gate COF And it is possible to configure a parallel resistor in the gate drive IC to reduce the output dip of the power.

The electrical connection between the power line and the logic circuit unit 325 may be configured in various ways, but the present invention is not limited thereto.

In the configuration of FIG. 8 , the two input/output controllers can control the direction of the input/output signal, and have the effect of buffering and amplifying the input/output signal. Therefore, even in the case of a gate drive IC located far from the timing controller, since the gate signal is applied in a sufficiently amplified state, the slew of the gate signal can be eliminated or the degree of slew can be reduced. As a result, an error between the timing between the gate drive IC to which the gate signal is first applied and the gate drive IC to which the gate signal is applied last can be reduced, so that the operation of the display panel can be accurately controlled.

9 is a diagram showing a detailed configuration of the input/output control units 810 and 820 according to an embodiment of the present invention. When High is applied to SHL, the first input/output pad 815 becomes an input pad and the second input/output pad 825 becomes an output pad. Same as 801, and the direction of signal is the same as 891. When Low is applied to SHL, the first input/output pad 815 becomes an output pad and the second input/output pad 825 becomes an input pad. Same as 802, and the direction of the signal is the same as 892.

In FIG. 9 , the input/output controllers 810 and 820 may include buffers composed of N-MOS transistors and P-MOS transistors. The N-MOS transistor and the P-MOS transistor are combined with the SHL so that one input/output control unit inputs a signal and the other input/output control unit outputs a signal. When the N-MOS transistor and the P-MOS transistor are used, signal amplification is also possible, so that the slew of the input signal, that is, the gate signal can be improved. The configuration of the transistor of FIG. 9 is an example, and the present invention is not limited thereto.

8 and 9 are summarized as follows. In order to apply a gate signal, ie, a scan signal, to the gate line, the timing controller may control the gate driver, and the gate driver may include a plurality of gate drive ICs and gate COFs. In another embodiment, the gate driver includes a plurality of gate drive ICs, which may be electrically coupled to the gate COF. According to the present invention, each gate drive IC may include an input/output controller to control the signal direction and eliminate signal slew in a process in which a gate signal and power are applied between the gate drive ICs.

The gate drive IC receives a gate signal including a gate start signal and a gate clock from a timing controller or another external gate drive IC. Of course, this signal can be received through the gate COF to which the gate drive IC is electrically coupled. The first input/output control unit 810 and the second input/output control unit 810 of the gate drive IC are electrically connected to the wiring to which the aforementioned gate signal is applied. The wiring is electrically connected to the input/output pads 815 and 825 or includes the input/output pads 815 and 825 .

In addition, the logic circuit unit 325 of the gate drive IC applies the gate signal applied from the first input/output control unit 810 or the second input/output control unit 810 to the gate line of the display panel. 8 and 9, the logic circuit unit 325 may control the application direction of the gate signal of the first input/output control unit 810 and the second input/output control unit 810 in the first direction or the second direction. there is.

For example, referring to 801 of FIG. 9 as an embodiment in the first direction, the first input/output control unit 810 receives a signal and provides it to the logic circuit unit 325 , and the second input/output control unit 820 receives a signal. It serves to receive a signal from the circuit unit 325 and output it to the outside. Looking at 802 of FIG. 9 as an embodiment in the second direction, it can be seen that 801 and the “‡ term are opposite to each other. The logic circuit unit 325 may include an input terminal to which the control signal SHL for controlling the application direction of the gate signal is input. SHL of FIG. 9 indicates an input control signal and also indicates an input terminal to which the control signal is applied to the logic circuit unit 325 .

8 and 9 , the input/output direction of the input/output controller is determined by the input control signal SHL. Accordingly, the same control signal may be applied to all gate drive ICs disposed on one side of the display device. On the other hand, the gate drive ICs disposed on both sides of the display device are applied with the control signal halved. The control signal of the gate drive IC may be set in a process of coupling the gate drive IC to the display device to be semi-permanently set in the display device.

By the above-described control signal, the gate drive IC may have the same configuration no matter where it is disposed on any side of the display device, and only the value of the control signal may be set differently, so that the circuit of the gate drive IC may be designed identically. In addition, when mass-producing gate drive ICs, production costs can be reduced according to the same circuit configuration.

10 is a view showing the configuration of a gate COF according to an embodiment of the present invention. In FIG. 10 , signal input/output pads 1015 and 1025 may be disposed so that the signal lines are connected to the input/output pads 815 and 825 of the gate drive IC. Meanwhile, the power line may be applied to the logic circuit unit 325 of FIG. 8 or FIG. 8 , and for this purpose, the power line terminals 1050a and 1050b may be electrically connected to the logic circuit unit 325 of the gate drive IC. . The power line of FIG. 10 may be composed of one or more power lines. The COF pads 1030a and 1030b of the gate COF may be selectively disposed.

11 is a diagram illustrating a configuration of a gate drive IC corresponding to the gate COF of FIG. 10 . In the configuration of FIG. 8 or 9 , the power line terminals 1150a and 1150b of the logic circuit unit 325 are disposed. The power line terminals 1150a and 1150b of the logic circuit of FIG. 11 are connected to the power line terminals 1050a and 1050b of the gate COF of FIG. 10 to apply VGH or VGL.

12 is a view showing the configuration of a gate COF according to another embodiment of the present invention. In power routing, the output dip caused by VGH/VGL drop while the gate drive IC is operated by the resistance component for each channel and the LOG resistance component in power routing was described in FIG. 6 . To prevent this, in order to reduce the resistance, the power line is extended like 1210, so that the resistance component can be dropped.

The power line is connected to the COF pads 1030a and 1030b so that a resistor is disposed in parallel with the power line to reduce the output dip. Since VGH/VGL is also applied to the COF pad in the same configuration as the gate COF of FIG. 12 , it can be used as a power line terminal.

13 is a diagram showing the configuration of a gate drive IC according to another embodiment of the present invention. The configuration of the gate drive IC of FIG. 13 is an embodiment in which power is applied to the logic circuit unit 325 through the COF pads 1030a and 1030b in the same configuration as the gate COF of FIG. 12 . The power line pads 830a and 830b of the gate drive IC may be electrically connected to the logic circuit unit 325 as shown in 1310 to apply power such as VGH or VGL.

12 and 13 are summarized as follows. The VGH and VGL applied to the gate COF are the signal lines applied with VGH and VGL between the COF pads 1030a and 1030b so that a parallel resistance can be configured to eliminate the output dip phenomenon caused by the film resistance and the chip resistance, as shown in 1210. can be extended In addition, the COF pads 1030a and 1030b of the gate COF may electrically contact the power line pad of the gate drive IC to apply power to the gate drive IC. In another embodiment, VGH and VGL extended and applied to the COF pads 1030a and 1030b only transmit power to the other adjacent gate COFs, and the role of supplying VGH and VGL to the gate drive IC is the power line terminal 1050a, 1050b) can. This may be variously configured according to the implementation method and the configuration of the parallel resistance of the power line.

14 is a view comparing a case in which a resistor is disposed on a gate COF according to an embodiment of the present invention and a case in which it is not. 1401 shows the relationship of resistance within or between gate COFs 1491 in a conventional configuration where no resistors are placed on gate COFs 1491 . 1402 shows the relationship of resistance within or between gate COFs 1492 . As an embodiment in which resistors 1420a and 1420b are disposed on the gate COF 1492, the configuration of FIG. 12 according to the present invention is reflected. In FIG. 14 , PAD_L and PAD_R denote power line terminals on the gate COF 1492 , respectively. The power line terminals 1450a and 1450b of 1402 correspond to the power line terminals 1050a and 1050b of FIG. 12 .

In FIG. 14 , since the pattern resistance on each gate COF and the ch1-30 and ch432-403 resistors are in parallel with each other, the internal total resistance decreases (pattern resistance < ch1-30, ch432-403 resistance). Therefore, as the internal resistance of the gate drive IC decreases, the combined resistance of the LOG phase and the IC resistance also decreases, reducing the output dip.

15 is a diagram illustrating a decrease in slew of an input signal in a gate drive IC when the present invention is applied. An input signal from the timing controller 140 is transmitted to the IC#1 (800n) through the gate drive ICs IC#n (800a), IC#n-1 (800b), and the like. The configuration of the gate drive IC was previously described in FIG. 8 and the like. Each signal is applied to the gate drive IC and passes through the input/output control units 810 and 820 in the gate drive IC. In this process, since the input signal is buffered through the input/output controllers 810 and 820, the slew phenomenon disappears. Therefore, even if a LOG resistance occurs as in 1501, the LOG resistance does not accumulate.

That is, since the input signal is buffered and amplified through the input/output controllers 810 and 820 in the gate drive IC, only the LOG resistance between the gate COFs exists, and this resistance also eliminates the slew through buffering and amplification, so the input signal is maintained until the last gate drive IC 800n.

16 is a view showing an improved state of the output dip when the present invention is applied. Conventionally, as shown in FIG. 6, VGH applied as 1601 drops as 610 due to LOG resistance and chip resistance. As a result, the signal generated by the timing controller is 625, but due to the drop in VGH, the actual signal slew like 620. However, when the present invention is applied, the drop range of VGH becomes as small as 1610, and as a result, it can be confirmed that the slew is improved as in 1620.

17 is a diagram showing timing accuracy due to slew improvement when the present invention is applied. 1701 of FIG. 17 shows the conventional slew state shown in FIG. 7 . There is a large difference between the timing 755 of the timing controller and the timing 750 at which the actual input signal rises to a predetermined level. On the other hand, when the present invention is applied, since the input signal is amplified in the gate drive IC, as in 1720 of 1702, the difference between the timing 1755 of the timing controller and the timing 1750 at which the actual input signal rises to a certain level is small, so that the timing accuracy is reduced. rises

When the present invention is applied, the slew occurrence is suppressed by amplifying the signal input from the gate drive integrated circuit. In addition, by improving the output dip phenomenon, it is possible to control the timing of the input signal to operate accurately. To this end, the gate drive integrated circuit of the present invention allows the wiring to which the gate signal is applied to be input/output control, thereby amplifying the signal and controlling the directionality of the signal. In addition, it is possible to extend the wiring to reduce the resistance of VGH and VGL in the gate drive IC and gate COF. To this end, the gate drive IC may further include a power line pad, and the gate COF corresponding thereto may further include a COF pad to which VGH and VGL are applied.

In an embodiment of the present invention, the power line terminal for applying power to the gate drive IC and the aforementioned power line pad may be configured separately or may be configured as one. This can be variously applied in relation to the gate drive IC and the gate COF.

In addition, the gate drive IC may receive a control signal for controlling the direction of the above-described signal from the timing controller, and the aforementioned SHL is an example of the control signal.

When the present invention is applied, the slew or output dip of the signal due to the LOG resistance and wiring resistance inherent in the gate driver arranged for driving the gate or the gate drive IC and the gate COF constituting the same is eliminated and the signal output is reinforced. can do.

In particular, the input/output control unit of the gate drive IC can play both the role of receiving and outputting signals according to the control, so when the gate drive IC is placed on both sides of the display panel, the direction of input and output can be distinguished according to each position. can In this case, since only one type of gate drive IC can be connected to both display panels, it lowers the design and production cost of the gate drive IC and enables the production of general-purpose gate drive ICs.

In addition, if the gate COF provides a separate power line pad so that power is connected in parallel between the gate drive IC and the gate COF, power is connected from the gate drive IC even if the power is cut off within the gate COF, so VGH or VGL can be operated without error. is authorized In addition, since the power is connected in parallel, the resistance is reduced, thereby reducing the output dip phenomenon.

When the embodiment of the present invention is applied, an input signal pad of the gate drive IC may be converted into I/O. In addition, by configuring the side dummy pad on the side of the gate drive IC with a high voltage VGH/VGL power line pad, it is possible not only to improve the slew of the input signal, but also to improve the output dip phenomenon. can

When the present invention is applied, unlike the conventional input signal pad, even when the input signal is applied to the gate drive IC located far from the timing controller, the signal is amplified to reduce the slew by maximizing the LOG resistance component. there is.

In addition, when the present invention is applied, it is possible to reduce the output dip phenomenon by the COF pad disposed on the gate COF for the power routing resistance and the LOG resistance component inside the gate drive IC. That is, when the aforementioned COF pad is disposed on the gate COF and used as a VGH/VGL power pad, the power routing resistance in the gate drive IC can be reduced.

The above description and the accompanying drawings are merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains can combine the configuration within a range that does not depart from the essential characteristics of the present invention. , various modifications and variations such as separation, substitution and alteration will be possible. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the equivalent range should be construed as being included in the scope of the present invention.

100: display device
110: panel
120: gate driver
130: data driver
140: timing controller
800: gate drive integrated circuit
810, 820: input/output control unit

Claims (12)

a first input/output controller and a second input/output controller electrically connected to a line to which a gate signal including a gate start signal and a gate clock is applied; and
is electrically connected between the first input/output control unit and the second input/output control unit, and applies a gate signal applied from the first input/output control unit or the second input/output control unit to a gate line of the display panel in a first direction; and a logic circuit unit applied along a second direction opposite to the first direction.
delete According to claim 1,
The logic circuit unit further includes an input terminal to which a control signal for controlling an application direction of the gate signal is input.
According to claim 1,
and the first input/output control unit and the second input/output control unit include an N-MOS transistor and a P-MOS transistor.
According to claim 1,
The gate drive integrated circuit further includes any one or more of a power line pad or a power line terminal to which VGH and VGL are applied.
6. The method of claim 5,
In the gate COF to which the gate drive integrated circuit is coupled, signal lines to which VGH and VGL are applied extend to the COF pad,
a power line pad of the gate drive integrated circuit electrically contacts the COF pad through a resistor.
a display panel in which gate lines and data lines cross each other; and
A display device comprising: a gate driver including a plurality of gate drive integrated circuits for applying a signal to the gate line; a data driver for applying a signal to the data line; and a timing controller for controlling the gate driver and the data driver. in,
The gate drive integrated circuit
a first input/output controller and a second input/output controller electrically connected to a line to which a gate signal including a gate start signal and a gate clock is applied; and
is electrically connected between the first input/output control unit and the second input/output control unit, and applies a gate signal applied from the first input/output control unit or the second input/output control unit to a gate line of the display panel in a first direction; and a logic circuit unit applied along a second direction opposite to the first direction.
delete 8. The method of claim 7,
The logic circuit unit further includes an input terminal to which a control signal for controlling an application direction of the gate signal is input.
8. The method of claim 7,
and the first input/output controller and the second input/output controller include an N-MOS transistor and a P-MOS transistor.
8. The method of claim 7,
The gate drive integrated circuit further includes at least one of a power line pad or a power line terminal to which VGH and VGL are applied.
12. The method of claim 11,
A gate COF to which the gate drive integrated circuit is coupled is coupled to the display panel;
In the gate COF, signal lines to which VGH and VGL are applied extend to the COF pad,
A display device in which a power line pad of the gate drive integrated circuit electrically contacts the COF pad through a resistor.

Images